PTHVD1400DRLR

THVD1400_V01 TI | Alldatasheet

Document overview

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Technical content

THVD1400, THVD1420 3.3-V to 5-V RS-485 Transceivers in Small Package with ±8-kV IEC ESD Protection

1 Features

• Meets or exceeds the requirements of the TIA/ EIA-485A standard
• 3-V to 5.5-V Supply voltage
• Half-duplex RS-422/RS-485
• Data rates – THVD1400: 500 kbps – THVD1420: 12 Mbps
• Bus I/O protection – ±16-kV HBM ESD – ±8-kV IEC 61000-4-2 Contact discharge – ±15-kV IEC 61000-4-2 Air gap discharge – ±4-kV IEC 61000-4-4 Fast transient burst – ±16-V bus fault protection (absolute max voltage on bus pins)
• Small, space-saving 8-pin SOT package option (2.1 mm x 1.2 mm) – See the layout example for co-layout with standard SOIC-8 package
• Extended industrial temperature range: -40°C to 125°C
• Large receiver hysteresis for noise rejection
• Low power consumption – Low standby supply current: < 1 µA – Quiescent current during operation: 1.5 mA (typ)
• Glitch-free power-up/down for hot plug-in capability
• Open, short, and idle bus failsafe
• 1/8 Unit load (Up to 256 bus nodes)

2 Applications

• Factory Automation & Control
• Building Automation
• Grid Infrastructure
• Motor Drives
• Power Delivery
• Industrial Transport
• HVAC Systems
• Video Surveillance
• Smart Meters

Description

THVD1400 and THVD1420 are robust half-duplex RS-485 transceivers for industrial applications. The bus pins are immune to high levels of IEC Contact Discharge ESD events, eliminating the need for additional system level protection components. The devices operate from a single 3 to 5.5-V supply. The wide common-mode voltage range and low input leakage on bus pins make the devices suitable for multi-point applications over long cable runs. THVD1400 and THVD1420 are available in industry standard, 8-pin SOIC package for drop-in compatibility as well as in the industry-leading, small SOT package. The devices are characterized for ambient temperatures from –40°C to 125°C. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) THVD1400 THVD1420 SOT (8) 2.1 mm x 1.2 mm SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. A B R D RE DE Simplified Schematic www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: THVD1400 THVD1420 THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.2 Receiving Notification of Documentation Updates..22

12 Mechanical, Packaging, and Orderable

3 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (December 2020) to Revision A (April 2021) Page

• Changed the test condition description for the last row of I CC (3.6V) from 'Both driver and receiver enabled' to THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. SOIC-8 (D), SOT-8 (DRL) Package, Top View Table 4-1. Pin Functions PIN I/O DESCRIPTION NAME NO. R 1 Digital output Receive data output RE 2 Digital input Receiver enable, active low (internal 2-MΩ pull-up) DE 3 Digital input Driver enable, active high (internal 2-MΩ pull-down) D 4 Digital input Driver data input GND 5 Ground Device ground A 6 Bus input/output Bus I/O port, A (complementary to B) B 7 Bus input/output Bus I/O port, B (complementary to A) VCC 8 Power 3.3-V to 5-V supply www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: THVD1400 THVD1420

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted (see (1)) MIN MAX UNIT VCC Supply voltage –0.5 7 V VL Input voltage at any logic pin (D, DE or RE) –0.3 5.7 V VA, VB Voltage at A or B inputs –16 16 V IO Receiver output current –24 24 mA TJ Junction temperature 170 °C TSTG Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only and functional operation of the device at these or any other conditionsbeyond those indicated under Section 5.4 is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Bus terminals (A, B) and GND ±16,000 V V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All other pins ±1,000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1,500 (1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

5.3 ESD Ratings [IEC]

V(ESD) Electrostatic discharge IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND ±8,000 VElectrostatic discharge IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND ±15,000 Electrostatic discharge IEC 61000-4-4 EFT (Fast transient or burst), bus terminals and GND ±4,000 THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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5.4 Recommended Operating Conditions

VCC Supply voltage 3 5 5.5 V VID Differential input voltage –12 12 V VI Input voltage at any bus terminal(1) –7 12 V VIH High-level input voltage (driver, driver-enable, and receiver-enable inputs) 2 VCC V VIL Low-level input voltage (driver, driver-enable, and receiver-enable inputs) 0 0.8 V IO Output current Driver –60 60 mA Receiver –8 8 RL Differential load resistance 54 60 Ω 1/tUI Signaling rate: THVD1400 500 kbps 1/tUI Signaling rate: THVD1420 12 Mbps TJ Junction temperature –40 150 °C TA (2) Operating ambient temperature –40 125 °C TSHDN Thermal shutdown threshold (temperature rising) 150 170 °C THYS Thermal shutdown hysteresis 15 °C (1) The algebraic convention in which the least positive (mostnegative) limit is designated as minimum is used in this data sheet. (2) Operation is specified for internal (junction) temperatures upto 150°C. Self-heating due to internal power dissipation should be considered for each application.Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit whichdisables the driver outputs when the junction temperature reaches 170°C.

5.5 Thermal Information

THERMAL METRIC(1) THVD1400, THVD1420 UNITDRL (SOT) D (SOIC)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 112.2 126.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.4 66.2 °C/W RθJB Junction-to-board thermal resistance 22.1 69.4 °C/W ψJT Junction-to-top characterization parameter 1.2 18.7 °C/W ψJB Junction-to-board characterization parameter 22.0 68.7 °C/W (1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application report.

5.6 Power Dissipation Characteristics

PARAMETER TEST CONDITIONS VALUE UNIT PD Power dissipation, driver and receiver enabled, VCC = 5.5 V, TA = 125°C, 50% duty cycle square-wave signal at maximum signaling rate (THVD1400) Unterminated RL = 300 Ω, CL = 50 pF 145 mWRS-422 load RL = 100 Ω, CL = 50 pF 175 RS-485 load RL = 54 Ω, CL = 50 pF 235 Power dissipation, driver and receiver enabled, VCC = 5.5 V, TA = 125°C, 50% duty cycle square-wave signal at maximum signaling rate (THVD1420) Unterminated RL = 300 Ω, CL = 50 pF 175 mWRS-422 load RL = 100 Ω, CL = 50 pF 200 RS-485 load RL = 54 Ω, CL = 50 pF 250 www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: THVD1400 THVD1420

5.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver │VOD│ Driver differential-output voltage magnitude RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V See Figure 6-1 1.5 2 V RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3 RL = 100 Ω, CL = 50 pF See Figure 6-2 2 2.5 RL = 54 Ω, CL = 50 pF 1.5 2 RL = 54 Ω, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3 Δ│VOD│ Change in magnitude of driver differential-output voltage RL = 54 Ω or 100 Ω, CL = 50 pF See Figure 6-2 –50 50 mV VOC(SS) Steady-state common-mode output voltage 1 VCC / 2 3 V ΔVOC Change in differential driver common-mode output voltage –50 50 mV VOC(PP) Peak-to-peak driver common- mode output voltage RL = 54 Ω, CL = 50 pF, VCC = 5 V See Figure 6-2 520 mV VOC(PP) Peak-to-peak driver common- mode output voltage RL = 54 Ω, CL = 50 pF, VCC = 3.3 V See Figure 6-2 250 mV │IOS│ Driver short-circuit output current DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin -250 250 mA Receiver II Bus input current (driver disabled) DE = 0 V, VCC = 0 V or 5.5 V VI = 12 V 75 100 µA VI = –7 V –97 –70 VIT+ Positive-going receiver differential-input voltage threshold -7 V ≤ VCM ≤ 12 V –70 –45 mV VIT– Negative-going receiver differential-input voltage threshold –200 –150 mV VHYS (1) Receiver differential-input voltage threshold hysteresis (VIT+ – VIT– ) 30 50 mV VOH Receiver high-level output voltage IOH = –4 mA VCC – 0.4 VCC – 0.2 V VOL Receiver low-level output voltage IOL = 4 mA 0.2 0.4 V IOZ Receiver high-impedance output current VO = 0 V or VCC, RE = VCC –1 1 µA Logic IIN Input current (D, DE, RE) –5 5 µA THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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5.7 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply ICC Supply current (quiescent) VCC = 3.6 V Both driver and receiver enabled DE = VCC, RE = 0, no load 1500 1800 µA Driver enabled and receiver disabled DE = VCC, RE = VCC, no load 1000 1500 Driver disabled and receiver enabled DE = 0, RE = 0, no load 700 900 Both driver and receiver disabled DE = 0 , RE = VCC, no load 0.1 1 VCC = 5.5 V Driver and receiver enabled DE = VCC, RE = 0, no load 1700 3000 µA Driver enabled, receiver disabled DE = VCC, RE = VCC, no load 1300 2500 Driver disabled, receiver enabled DE = 0, RE = 0, no load 800 1000 Driver and receiver disabled DE = 0, RE = VCC, no load 0.1 1 (1) Under any specific conditions, V IT+ is specified to be at least VHYS higher thanVIT–.

5.8 Switching Characteristics (THVD1400)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver tr, tf Driver differential output rise and fall times See Figure 6-3 200 400 600 ns tPHL, tPLH Driver propagation delay 250 500 ns tSK(P) Driver pulse skew, |tPHL – tPLH| 15 ns tPHZ, tPLZ Driver disable time See Figure 6-4 and Figure 6-5 80 200 ns tPZH, tPZL Driver enable time Receiver enabled 200 650 ns Receiver disabled 4 10 µs Receiver tr, tf Receiver output rise and fall times See Figure 6-6 13 20 ns tPHL, tPLH Receiver propagation delay time 60 110 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 7 ns tPHZ, tPLZ Receiver disable time See Figure 6-7 30 60 ns tPZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time Driver enabled 60 150 ns Driver disabled See Figure 6-8 4 10 µs

5.9 Switching Characteristics (THVD1420)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver tr, tf Driver differential output rise and fall times See Figure 6-3 15 25 ns tPHL, tPLH Driver propagation delay 20 38 ns tSK(P) Driver pulse skew, |tPHL – tPLH| 3.5 ns tPHZ, tPLZ Driver disable time See Figure 6-4 and Figure 6-5 15 38 ns tPZH, tPZL Driver enable time Receiver enabled 15 70 ns Receiver disabled 4 10 µs Receiver www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: THVD1400 THVD1420

5.9 Switching Characteristics (THVD1420) (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr, tf Receiver output rise and fall times See Figure 6-6 10 16 ns tPHL, tPLH Receiver propagation delay time 40 75 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 5 ns tPHZ, tPLZ Receiver disable time See Figure 6-7 15 25 ns tPZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time Driver enabled 25 170 ns Driver disabled See Figure 6-8 4 10 µs THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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5.10 Typical Characteristics

D001_driver_vout_iout.grf Driver Output Current (mA) Driver Output Voltage (V) 0 10 20 30 40 50 60 70 80 0.5 1.5 2.5 3.5 4.5 5.5 D001 VOH (VCC=5V) VOL (VCC=5V) DE = VCC TA = 25°C Figure 5-1. Driver Output voltage vs Driver Output Current D002_driver_vdiff.grf Driver Output Current (mA) Driver Differential Output Voltage (V) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 2.4 2.6 2.8 3.2 3.4 3.6 3.8 4.2 4.4 4.6 4.8 D002 VCC = 5 V DE = VCC D = 0 V TA = 25°C Figure 5-2. Driver Differential Output voltage vs Driver Output Current D003_Iout_vcc.grf Vcc (V) Driver Output Current (mA) D003 RL = 54 Ω DE = VCC D = VCC TA = 25°C Figure 5-3. Driver Output Current vs Supply Voltage D004_rise_fall.grf Temperature (qC) Driver Rise and Fall Time (ns) -40 -20 0 20 40 60 80 100 120 140 310 315 320 325 330 335 340 345 350 D004 Fall time (VCC=5V) Rise time (VCC=5V) RL = 54 Ω CL = 50 pF spacer Figure 5-4. Driver Rise or Fall Time vs Temperature (THVD1400) D005_prop_delay.grf Temperature (qC) Propgation Delay (ns) -40 -20 0 20 40 60 80 100 120 140 280 285 290 295 300 305 310 315 320 D005 tPHL (ns) VCC=5V tPLH (ns) VCC=5V RL = 54 Ω CL = 50 pF Figure 5-5. Driver Propagation Delay vs Temperature (THVD1400) D006_Icc_datarate.grf Signaling Rate (kbps) Supply Current (mA) 0 50 100 150 200 250 300 350 400 450 500 D006 VCC=5V RL = 54 Ω TA = 25 °C Figure 5-6. Supply Current vs Signal Rate (THVD1400) www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: THVD1400 THVD1420

5.10 Typical Characteristics (continued)

Temperature (C) Driver Rise Fall Time (ns) -40 -20 0 20 40 60 80 100 120 140 6.5 7.5 8.5 9.5 10.5 Rise Time (VCC = 5 V ) Fall Time (VCC = 5 V) RL = 54 Ω CL = 50 pF Figure 5-7. Driver Rise and Fall Time vs Temperature (THVD1420) Temperature (C) Propagation Delay (ns) -40 -20 0 20 40 60 80 100 120 140 tPHL (VCC = 5 V) tPLH (VCC = 5 V) RL = 54 Ω CL = 50 pF Figure 5-8. Driver Propagation Delay vs Temperature (THVD1420) Signaling Rate (kbps) Supply Current (mA) 0 2000 4000 6000 8000 10000 12000 VCC = 5 V RL = 54 Ω TA = 25 °C Figure 5-9. Supply Current vs Signal Rate (THVD1420) THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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6 Parameter Measurement Information

A B DE Vcc Vtest VOD D 375 Ÿ RL 375 Ÿ Figure 6-1. Measurement of Driver Differential Output Voltage With Common-Mode Load A B VOC VOC(PP) ûVOC(SS) VA VB0V or Vcc A B D RL/2 CL VOC VOD RL/2 Figure 6-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load VOD VI tPLH tPHL tr tf 90% 50% 10% 50% Vcc ± 2 V 0 V Input Generator A B Vcc VOD D RL= 54 Ÿ VI 50 Ÿ DE CL= 50 pF ~~2 V Figure 6-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays VO VI tPZH tPHZ 50% 50% Vcc ~ 0V 0 V VOH90%Input Generator A B VOD RL = 110 Ÿ VI 50 Ÿ DE CL = 50 pF Figure 6-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load VO VI tPZL tPLZ 50% 50 % Vcc Vcc 0 V VOL 10%Input Generator A B VOD RL= 110 Ÿ VI 50 Ÿ DE CL= 50 pF Vcc Figure 6-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: THVD1400 THVD1420

90% 50 % 10 % 50% 3 V VOH VOL 0 V Input Generator VO VI 50 Ÿ RE A B R 1.5V 0 V CL=15 pF Figure 6-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays VO VI tPHZ 50 % 50 % Vcc VOH90 % 50 % 10 % VOL VCC tPLZ tPZL(1) VO tPZH(1) D at Vcc S1 to GND Input Generator VO VI 50 Ÿ A B R CL=15 pF RE 0V or Vcc DE Vcc D Vcc 1 kŸ D at 0V S1 to Vcc Figure 6-7. Measurement of Receiver Enable/Disable Times With Driver Enabled VO VI 50% Vcc §0V VOH 50% VOL VCC tPZL(2) VO tPZH(2) 50% Input Generator VO VI 50 Ÿ A B R CL=15 pF RE V or 1.5V Vcc 1 NŸ

1.5 V or 0V

A at 1.5V B at 0V A at 0V B at 1.5V S1 to VCC Figure 6-8. Measurement of Receiver Enable Times With Driver Disabled THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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7 Detailed Description

7.1 Overview

The THVD1400 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 500 kbps. The THVD1420 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 12 Mbps.

7.2 Functional Block Diagrams

R D DE RE B A GND VCC

7.3 Feature Description

Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to IEC 61000-4-2 of up to ±8 kV (Contact Discharge), ±15 kV (Air Gap Discharge) and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV.

7.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and V OD is negative. When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground; thus, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to V CC, thus, when left open while the driver is enabled, output A turns high and B turns low. Table 7-1. Driver Function Table INPUT ENABLE OUTPUTS FUNCTION D DE A B H H H L Actively drive bus high L H L H Actively drive bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus high by default When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as V ID = V A – V B is positive and higher than the positive input threshold, V IT+, the receiver output, R, turns high. When V ID is negative and lower than the negative input threshold, V IT-, the receiver output, R, turns low. If VID is between VIT+ and VIT- the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of V ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus). www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: THVD1400 THVD1420

Table 7-2. Receiver Function Table DIFFERENTIAL INPUT ENABLE OUTPUT FUNCTION VID = VA – VB RE R VIT+ < VID L H Receive valid bus high VIT- < VID < VIT+ L ? Indeterminate bus state VID < VIT- L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Fail-safe high output Short-circuit bus L H Fail-safe high output Idle (terminated) bus L H Fail-safe high output THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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8 Application Information Disclaimer

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The THVD1400 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.

8.2 Typical Application

An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, R T, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length. RT RT R A B R RE DE D D R A B R RE DE D D R D R RE DE D A B R D R RE DE D A B Figure 8-1. Typical RS-485 Network With Half-Duplex Transceivers

8.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of applications with varying requirements, such as distance, data rate, and number of nodes.

8.2.1.1 Data Rate and Bus Length

There is an inverse relationship between data rate and cable length, which means the higher the data rate, the shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 300 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%. www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: THVD1400 THVD1420

8.2.1.2 Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as shown in Equation 1. L(STUB) ≤ 0.1 × tr × v × c (1) where

• t r is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c

8.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit load represents a load impedance of approximately 12 k Ω. Because the THVD1400 consists of 1/8 UL transceivers, connecting up to 256 receivers to the bus is possible.

8.2.1.4 Receiver Failsafe

The differential receivers of the THVD1400 are failsafe to invalid bus states caused by the following:

• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver is not indeterminate. Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input V ID is more positive than 200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are V IT+, VIT–, and V HYS (the separation between V IT+ and V IT–). As shown in the Receiver Function Table , differential signals more negative than –200 mV always causes a low receiver output, and differential signals more positive than 200 mV always causes a high receiver output. When the differential input signal is close to zero, it is still above the V IT+ threshold, and the receiver output is high. Only when the differential input is more than V HYS below V IT+ does the receiver output transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver hysteresis value, VHYS, as well as the value of VIT+. THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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8.2.1.5 Transient Protection

The bus pins of the THVD1400 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8-kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more severe than the HBM ESD test. The 50% higher charge capacitance, C (S), and 78% lower discharge resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model. R(C) R(D) C(S) High-Voltage Pulse Generator Device Under Test Current (A) Time (ns) 0 50 100 150 200 250 300 10-kV IEC 10-kV HBM 330 Ω (1.5 kΩ) 150 pF (100 pF) 50 M (1 M) Figure 8-2. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis) The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common discharge events occur because of human contact with connectors and cables. Designers may choose to implement protection against longer duration transients, typically referred to as surge transients. EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the switching of power systems, including load changes and short circuit switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems. Figure 8-3 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are representative of events that may occur in factory environments in industrial and process automation. The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems. Pulse Power (kW) Time (µs) 0 5 10 15 20 25 30 35 40 0.5-kV Surge 10-kV ESD 4-kV EFT Pulse Power (MW) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Time (µs) 0 5 10 15 20 25 30 35 40 0.5-kV Surge 6-kV Surge 3.0 2.8 2.6 2.4 Figure 8-3. Power Comparison of ESD, EFT, and Surge Transients www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: THVD1400 THVD1420

In the event of surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver. Figure 8-4 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse train that is commonly applied during compliance testing. 100 0.1 0.01 10-3 10-4 10-5 10-6 Pulse Energy (J) 0.5 1 2 4 6 8 10 Peak Pulse Voltage (kV) 1000 ESD EFT Surge EFT Pulse Train Figure 8-4. Comparison of Transient Energies THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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Product Folder Links: THVD1400 THVD1420

8.2.2 Detailed Design Procedure

In order to protect bus nodes against high-energy transients, the implementation of external transient protection devices is necessary. Figure 8-5 suggests a protection circuit against 1 kV surge (IEC 61000-4-5) transients. Table 8-1 shows the associated bill of materials. VCC GND D DE R RE B A RxD TxD DIR MCU/ UART 10k 10k TVS 100nF100nF Figure 8-5. Transient Protection Against Surge Transients for Half-Duplex Devices Table 8-1. Bill of Materials DEVICE FUNCTION ORDER NUMBER MANUFACTURER XCVR RS-485 transceiver THVD1400 TI 10-Ω, pulse-proof thick-film resistor CRCW0603010RJNEAHP Vishay TVS Bidirectional 400-W transient suppressor CDSOT23-SM712 Bourns

8.2.3 Application Curves

Figure 8-6. THVD1400 waveforms at 500 kbps, VCC = 5V

9 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100 nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB power planes. www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: THVD1400 THVD1420

10 Layout

10.1 Layout Guidelines

Robust and reliable bus node design often requires the use of external transient protection devices in order to protect against surge transients that may occur in industrial environments. Since these transients have a wide frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be applied during PCB design. 1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across the board. 2. Use V CC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the path of least impedance and not the path of least resistance. 3. Design the protection components into the direction of the signal path. Do not force the transient currents to divert from the signal path to reach the protection device. 4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the V CC pins of transceiver, UART and/or controller ICs on the board. 5. Use at least two vias for V CC and ground connections of decoupling capacitors and protection devices to minimize effective via inductance. 6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines during transient events. 7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up. 8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to less than 1 mA.

10.2 Layout Example

R R Via to ground JMPR R R C Via to VCC TVS Figure 10-1. Layout Example for SOIC package THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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Figure 10-2. Layout Example for Co-layout of SOIC (D) and SOT (DRL) www.ti.com THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: THVD1400 THVD1420

11 Device and Documentation Support

11.1 Device Support

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. THVD1400, THVD1420 SLLSF78A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com

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Product Folder Links: THVD1400 THVD1420

www.ti.com 27-May-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTHVD1400DRLR ACTIVE SOT-5X3 DRL 8 4000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 THVD1400DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1400 THVD1420DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1420 THVD1420DRLR PREVIEW SOT-5X3 DRL 8 4000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 27-May-2021 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2021 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THVD1400DR SOIC D 8 2500 853.0 449.0 35.0 THVD1420DR SOIC D 8 2500 853.0 449.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2021 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 1.7 1.5 6X 0.5 2X 1.5

0.6 MAX

0.18 0.08 8X 0.4 0.2 0.05 0.00 8X 0.27 0.17 B 1.3 1.1 A 2.2 2.0 NOTE 3 SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE 4224486/B 03/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration TO-236, except minimum foot length. 1 8 ID AREA PIN 1 SEATING PLANE 0.05 C SCALE 8.000

0.1 C A B

0.05 SYMM SYMM

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (0.67) 8X (0.3) (1.48) 6X (0.5) (R0.05) TYP 4224486/B 03/2021 SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:30X SYMM 4 5 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 6X (0.5) 8X (0.67) 8X (0.3) (R0.05) TYP SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE 4224486/B 03/2021 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM

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