THS2630_V01 TI | Alldatasheet
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THS2630 High-Speed, Low-Noise, Fully-Differential I/O Amplifier
1 Features
- High performance – Bandwidth: 187MHz (VCC = ±15 V, G = 1 V/V) – Slew rate: 75 V/µs – Gain bandwidth product: 245 MHz – Distortion: –108 dBc THD at 2 VPP, 250 kHz
- Voltage noise – 1/f voltage noise corner: 85 Hz – 1.1 nV/√Hz input-referred noise
- Single supply operating range: 5 V to 35 V
- Quiescent current (shutdown): 770 µA (THS2630S)
2 Applications
- Single-ended to differential conversion
- Differential ADC driver
- Differential antialiasing
- Differential transmitter and receiver
- Output level shifter
- Medical ultrasound
3 Description
The THS2630 device is one in a family of fully- differential input/differential output devices fabricated using Texas Instruments state-of-the-art high voltage complementary bipolar process. The THS2630 is made of a true fully-differential signal path from input to output and high supply capability of up to ±17.5 V. This design leads to an excellent common-mode noise rejection performance (95 dB at 800 kHz) and total harmonic distortion ( −108 dBc at 2 V PP, 250 kHz). The wide supply range allows high-voltage differential signal chains to benefit from its improved headroom and dynamic range without adding separate amplifiers for each polarity of the differential signal. The THS2630 is characterized for operation over the wide temperature range of –40°C to +85°C. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) THS2630 D (SOIC, 8) 4.90 mm × 3.91 mm DGN (HVSSOP, 8) 3.00 mm × 3.00 mm DGK (VSSOP, 8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DAC8802 CH_A CH_B THS4032 +5 V ± 15 V Low-Noise Current to Voltage Converter THS2630 ± 15 V Filtering and Attenuation AFE58JD18 To TGC VCNTL Time Gain Control DAC Reference for Ultrasound Frequency (Hz) THD - Total Harmonic Distortion (dBc) -120 -110 -100 -90 -80 -70 -60 -50 100k 1M 10M VCC = 2.5 V VCC = 5 V VCC = 15 V VOUT = 2 VPP Total Harmonic Distortion vs Frequency ADVANCE INFORMATION THS2630 SLOSE96 – JANUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
10 Mechanical, Packaging, and Orderable
4 Revision History
January 2023 * Initial Release THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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5 Pin Configuration and Functions
Figure 5-1. THS2630S D, DGN, or DGK Package 8-Pin SOIC, HVSSOP, or VSSOP (Top View) V I N+ NC V CC - V O UT - V I N - V O C M V CC+ V O UT+ Figure 5-2. THS2630 D, DGN, or DGK Package 8-Pin SOIC, HVSSOP, or VSSOP (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME THS2630S THS2630 NC — 7 — No connect PD 7 — I Active low power-down pin VCC+ 3 3 I/O Positive supply voltage pin VCC– 6 6 I/O Negative supply voltage pin VIN– 1 1 I Negative input pin VOCM 2 2 I Common mode input pin VOUT+ 4 4 O Positive output pin VOUT– 5 5 O Negative output pin VIN+ 8 8 I Positive input pin (1) I = input, O = output www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: THS2630
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VI Input voltage –VCC +VCC V VCC– to VCC+ Supply voltage 37 V Supply turn-on/off dV/dT(2) 1.7 V/µs IO (3) Output current 150 mA VID Differential input voltage -1.5 1.5 V IIN Continuous Input Current 10 mA TJ (4) Maximum junction temperature 150 °C TJ (5) Maximum junction temperature, continuous operation, long-term reliability 125 °C TA Operating free-air temperature 0 85 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off. (3) The THS2630 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD thermally-enhanced package. (4) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (5) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.
6.2 ESD Ratings
THS2630: D, DGK, OR DGN PACKAGES V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3500 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc+ to Vcc– Dual supply ±2.5 ±17.5 V Single supply 5 35 TA Operating free-air temperature –40 85 °C THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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6.4 Thermal Information
THERMAL METRIC(1) THS2630 UNITD (SOIC) DGN (HVSSOP) DGK (VSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 126.3 57.3 147.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.3 82.9 37.9 °C/W RθJB Junction-to-board thermal resistance 69.8 29.7 83.2 °C/W ψJT Junction-to-top characterization parameter 19.5 6.3 0.9 °C/W ψJB Junction-to-board characterization parameter 69.0 29.7 81.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 13.9 n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE BW Small-signal bandwidth (–3 dB), single-ended input, differential output, VI = 63 mVPP VCC = 5 V Gain = 1, RF = 390 Ω 181 MHz VCC = ±5 V 183 VCC = ±15 V 187 VCC = 5 V Gain = 2, RF = 750 Ω 108 VCC = ±5 V 108 VCC = ±15 V 111 Gain-bandwidth product VO = 200 mVPP, Gain = 20, RF = 750Ω 245 MHz VOCM small-signal bandwidth VI = 63 mVPP 100 SR Slew rate(1) 75 V/µs ts Settling time to 0.1% Step voltage = 2 V, gain = 1 ns Settling time to 0.01% 52 DISTORTION PERFORMANCE THD Total harmonic distortion, differential input, differential output, VO = 2 VPP VCC = 5 V f = 250 kHz –106 dBc f = 1 MHz –93 VCC = ±5 V f = 250 kHz –106 f = 1 MHz –93 VCC = ±15 V f = 250 kHz –108 f = 1 MHz –94 VO = 4 VPP VCC = ±5 V f = 250 kHz –99 f = 1 MHz –84 VCC = ±15 V f = 250 kHz –100 f = 1 MHz –86 SFDR Spurious-free dynamic range, differential input, differential output, f = 250 kHz VO= 2 VPP VCC = ±2.5 109 dBc VCC = ±5 112 VCC = ±15 116 VO = 4 VPP VCC = ±5 104 VCC = ±15 106 IMD3 Third intermodulation distortion VI(PP) = 4 V, F1 = 3 MHz, F2 = 3.5 MHz –53 dBc OIP3 Third-order intercept 41.5 dB NOISE PERFORMANCE www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: THS2630
6.5 Electrical Characteristics (continued)
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vn Input voltage noise f = 10 kHz 1.1 nV/√Hz In Input current noise f = 10 kHz 1.3 pA/√Hz DC PERFORMANCE Open-loop gain TA = +25°C 91 95 dB TA = full range 87 VOS Input offset voltage TA = +25°C -1.3 ±0.1 1.3 mV VOS Input offset voltage TA = full range 1.5 Input offset voltage drift TA = full range 0.8 3.2 µV/°C IIB Input bias current TA = 25℃ TA = 25℃ 4.8 9.8 IIB Input bias current TA = full range TA = full range 4.8 15.1 µA IOS Input offset current TA = 25℃ TA = 25℃ -250 22 350 nA IOS Input offset current TA = full range TA = full range 400 nA Input offset current drift 0.13 nA/°C INPUT CHARACTERISTICS CMRR Common-mode rejection ratio TA = 25℃ TA = 25℃ 81 95 dB VICR Common-mode input voltage range –3.77 to 4.3 –4 to 4.5 V RI Common-mode input resistance Measured into each input terminal 320 MΩ RI Differential input resistance 12 kΩ CI_CM Common- mode input capacitance, closed loop Measured into each input terminal 1.3 pF CI_DIFF Differential input capacitance, closed loop 2.3 pF ro Output resistance Open loop Open loop 26 Ω OUTPUT CHARACTERISTICS Output voltage swing VCC = ±15 V, RL = 1kΩ TA = full range ±12.9 V IO Output current VCC = 5 V, RL = 7 Ω TA = +25°C 25 45 mA TA = full range 20 VCC = ±5 V, RL = 7 Ω TA = +25°C 30 55 TA = full range 28 VCC = ±15 V, RL = 7 Ω TA = +25°C 65 85 TA = full range 60 POWER SUPPLY ICC Quiescent current VCC = ±5 V TA = +25°C 8.9 10.5 mA Quiescent current VCC = ±5 V TA = full range 12.4 mA Quiescent current VCC = ±15 V TA = +25°C 11 13.2 mA Quiescent current VCC = ±17.5 V TA = +25°C 11 13.2 mA ICC(SD) Quiescent current (shutdown) (THS2630S only)(2) PD = –5 V TA = +25°C 0.77 0.92 mA PSRR Power-supply rejection ratio (dc) TA = +25°C 76 98 dB OUTPUT COMMON-MODE (VOCM) CONTROL VOCM specs VOCM offset voltage VOCM driven to midsupply -2.7 0.2 2.7 mV THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOCM specs Default VOCM offset Relative to midsupply, VOCM pin floating -10 0.65 10 mV VOCM input range low VS = ±15 V –14 –13.8 V VOCM input range high 13.3 13.7 V VOCM input range low –4.1 –4 V VOCM input range high 3.5 3.8 V VOCM input noise Flat-band, Vocm driven 13 nV/√Hz VOCM input resistance 15 kΩ (1) Slew rate is measured from an output level range of 25% to 75%. (2) For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section. www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: THS2630
6.6 Typical Characteristics: THS2630D
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise noted) Frequency (Hz) Output (dB) -10 100k 1M 10M 100M 1G G = 1, R F = 390 G = 2, R F = 750 G = 5, R F = 2 k G = 10, R F = 4 k VI = 63 mVPP Figure 6-1. Small-Signal Frequency Response Frequency (Hz) Output (dB) 100k 1M 10M 100M 1G R F = 390 R F = 620 VI = 63 mVPP Figure 6-2. Small-Signal Frequency Response Frequency (Hz) Output (dB) 100k 1M 10M 100M 1G V CC = 5 V V CC = 15 V VI = 63 mVPP Figure 6-3. Small-Signal Frequency Response VI = 63 mVPP Figure 6-4. Small-Signal Frequency Response VI = 63 mVPP Figure 6-5. Small-Signal Frequency Response Time ( s) Large Signal Transient Response (V) -0.5 0.5 -0.5 0.5 VoutP VoutN V I (Diff) Figure 6-6. Large-Signal Transient Response (Differential In/ Single Out) THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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6.6 Typical Characteristics: THS2630D (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise noted) Frequency (Hz) Output (dB) -25 -20 -15 -10 100k 1M 10M 100M 1G V CC = 2.5 V V CC = 5 V V CC = 15 V VI = 0.2 VRMS Figure 6-7. Large-Signal Frequency Response Frequency (Hz) CMRR - Common Mode Rejection Ratio (dB)-120 -100 -80 -60 -40 -20 100k 1M 10M 100M RF = 1 kΩ Figure 6-8. Common-Mode Rejection Ratio vs Frequency T A - Free-Air Temperature ( C) ICC - Supply Current (mA) -40 -20 0 20 40 60 80 100 V CC = 15 V V CC = 5 V Figure 6-9. Supply Current vs Free-Air Temperature T A - Free-Air Temperature ( C) ICC - Supply Current ( A) -40 -20 0 20 40 60 80 100 650 700 750 800 850 900 Figure 6-10. Supply Current vs Free-Air Temperature (Shutdown State) T A - Free-Air Temperature - C IIB - Input Bias Current ( A) -50 -25 0 25 50 75 100 IB- IB+ Figure 6-11. Input Bias Current vs Free-Air Temperature Time (ns) V O - Output Voltage (V) 0 25 50 75 100 125 150 1.9 1.92 1.94 1.96 1.98 2.02 2.04 RF = 510 Ω, CF= 1 pF, VCC= 5 V, VO = 4 VPP Figure 6-12. Settling Time www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: THS2630
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise noted) Frequency (Hz) PSRR - Power Supply Rejection Ratio (dB)-100 -90 -80 -70 -60 -50 -40 -30 10k 100k 1M 10M 100M V CC = +5 V V EE = -5 V RF = 330 Ω, RL = 400 Ω Figure 6-13. Power-Supply Rejection Ratio vs Frequency (Differential Out) Time (ns) V O - Output Voltage (V) 0 40 80 120 160 200 -2.5 -1.5 -0.5 0.5 1.5 2.5 V O V O VI_Peak = 2 V, CL = 10 pF, VCC = ±15 V Figure 6-14. Large-Signal Transient Response Frequency (Hz) THD - Total Harmonic Distortion (dBc) -120 -110 -100 -90 -80 -70 -60 -50 100k 1M 10M V CC = 2.5 V V CC = 5 V V CC = 15 V VOUT = 2 VPP Figure 6-15. Total Harmonic Distortion vs Frequency Frequency (Hz) HD2 - Second Harmonic Distortion (dB) -120 -110 -100 -90 -80 -70 -60 -50 100k 1M 10M V CC = 2.5 V V CC = 5 V V CC = 15 V VOUT = 2 VPP, Single-ended Input, Differential Output Figure 6-16. Second-Harmonic Distortion vs Frequency Frequency (Hz) HD2 - Second Harmonic Distortion (dBc) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 100k 1M 10M V CC = 5 V V CC = 15 V VOUT = 4 VPP, Single-ended Input, Differential Output Figure 6-17. Second-Harmonic Distortion vs Frequency V O - Output Voltage (V) HD2 - Second Harmonic Distortion (dBc) 0 1 2 3 4 5 6 7 -122 -120 -118 -116 -114 -112 -110 -108 -106 -104 V CC = 2.5 V V CC = 5 V V CC = 15 V f = 250 kHz, Single-ended Input, Differential Output Figure 6-18. Second-Harmonic Distortion vs Output Voltage THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise noted) V OUT - Output Voltage (V) HD2 - Second Harmonic Distortion (dBc) 0 1 2 3 4 5 6 7 -118 -116 -114 -112 -110 -108 -106 -104 -102 -100 V CC = 2.5 V V CC = 5 V V CC = 15 V f = 500 kHz, Single-ended Input, Differential Output Figure 6-19. Second-Harmonic Distortion vs Output Voltage Frequency (Hz) HD3 - Third Harmonic Distortion (dB) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 100k 1M 10M V CC = 2.5 V V CC = 5 V VOUT = 4 VPP, Single-ended Input, Differential Output Figure 6-20. Third-Harmonic Distortion vs Frequency Frequency (Hz) HD3 - Third Harmonic Distortion (dB) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 100k 1M 10M V CC = 2.5 V V CC = 5 V V CC = 15 V VOUT = 2 VPP, Single-ended Input, Differential Output Figure 6-21. Third-Harmonic Distortion vs Frequency V O - Output Voltage (V) HD3 - Second Harmonic Distortion (dBc) 0 1 2 3 4 5 6 7 -134 -130 -126 -122 -118 -114 -110 -106 -102 -98 -94 -90 V CC = 2.5 V V CC = 5 V V CC = 15 V f = 500 kHz, Single-ended Input, Differential Output Figure 6-22. Third-Harmonic Distortion vs Output Voltage V OUT - Output Voltage (V) HD3 - Second Harmonic Distortion (dBc) 0 1 2 3 4 5 6 7 -130 -125 -120 -115 -110 -105 -100 V CC = 2.5 V V CC = 5 V V CC = 15 V f = 250 kHz, Single-ended Input, Differential Output Figure 6-23. Third-Harmonic Distortion vs Output Voltage Frequency (Hz) V n - Voltage Noise (nV/ Hz) 10 100 1k 10k 100k Figure 6-24. Voltage Noise vs Frequency www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: THS2630
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise noted) Frequency (Hz) In (pA/ Hz) 10 100 1k 10k 100k Figure 6-25. Current Noise vs Frequency RF = 1 kΩ Figure 6-26. Input Offset Voltage vs Common-Mode Output Voltage R L ( ) V O - Output Voltage (V) -15 -10 100 1k 10k 100k V cc = 5 V V cc = 15 V RF = 1 kΩ, G = 2 V/V Figure 6-27. Output Voltage vs Differential Load Resistance Frequency (Hz) Output Impedance ( ) 0.1 100 100k 1M 10M 100M 1G Figure 6-28. Output Impedance vs Frequency THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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7 Detailed Description
7.1 Overview
7.1.1 Fully-Differential Amplifiers
The THS2630 is a fully differential amplifier (FDA). Differential signal processing offers a number of performance advantages in high-speed analog signal processing systems, including immunity to external common-mode noise, suppression of even-order non-linearities, and increased dynamic range. FDAs not only serve as the primary means of providing gain to a differential signal chain, but also provide a monolithic solution for converting single-ended signals into differential signals allowing for easy, high-performance processing. For more information on the basic theory of operation for FDAs, refer to the Fully Differential Amplifiers application note.
7.2 Functional Block Diagram
Amplifier C R C R Output Buffer VOUT+ VOUT− VCC+ VCC− VIN− VIN+ 30 k/c87 30 k/c87 VCC+ VCC− VOCM www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: THS2630
7.3 Feature Description
Figure 7-1 and Figure 7-2 shows the differences between the operation of the THS2630 in two different modes. FDAs can work with either differential or single-ended inputs. RFRG RG VOCM RF VCC+ VCC- VSource VOUT+ VOUT- Figure 7-1. Amplifying Differential Input Signals RFRG RG VOCM RF VCC+ VCC- VOUT+ VOUT- VSource Figure 7-2. Amplifying Single-ended Input Signals
7.4 Device Functional Modes
7.4.1 Power-Down Mode
The power-down mode is used when power saving is required. The power-down terminal ( PD) found on the THS2630S is an active low input. If left unconnected, an internal 250 kΩ resistor to VCC+ keeps the device turned on. The threshold voltage for the power-down function is approximately 1.4 V above V CC–. This means that if the PD terminal is 1.4 V above V CC–, the device is active. If the PD terminal is less than 1.4 V above V CC–, the device is off. It is recommended to pull the terminal to VCC– to turn the device off. Figure 7-3 shows the simplified version of the power-down circuit. While in the power-down state, the amplifier goes into a high-impedance state. The amplifier's output impedance is typically greater than 1 MΩ in the power-down state. V CC PD V CC To Internal Bias Circuitry Control 250 k Ω Figure 7-3. Simplified Power-Down Circuit Similar to an opamp in an inverting configuration, the output impedance of an FDA is determined by its feedback network configuration. In addition, the THS2630S has an internal 10 k Ω resistor at each output that is tied to the VCM error amplifier (see Section 7.2). The differential output impedance is equal to [(2*R F + 2*RG) || 20 k Ω]. Figure 7-4 shows the closed loop output impedance of the THS2630S when in power-down. THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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Frequency (Hz) Differential Output Impedance ( ) 500 1000 1500 2000 2500 3000 3500 100k 1M 10M 100M 1G VCC = ±5 V, G = 1 V/V, RF = 1kΩ, PD = VCC- Figure 7-4. Output Impedance (in Power-Down) vs Frequency www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: THS2630
8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Output Common-Mode Voltage
The output common-mode voltage pin sets the dc output voltage of the THS2630. A voltage applied to the VOCM pin from a low-impedance source can be used to directly set the output common-mode voltage. If the V OCM pin is left floating it defaults to the mid-rail voltage, defined as: V C C + + V C C − 2 (1) To minimize common-mode noise, connect a 0.1-µF bypass capacitor to the V OCM pin. Output common-mode voltage causes additional current to flow in the feedback resistor network. Since this current is supplied by the output stage of the amplifier, this creates additional power dissipation. For commonly-used feedback resistance values, this current is easily supplied by the amplifier. The additional internal power dissipation created by this current may be significant in some applications and may dictate use of the MSOP PowerPAD package to effectively control self-heating.
8.1.1.1 Resistor Matching
Resistor matching is important in FDAs to maintain good output balance. An ideal differential output signal implies the two outputs of the FDA should be exactly equal in amplitude and shifted 180° in phase. Any imbalance in amplitude or phase between the two output signals results in an undesirable common-mode signal at the output. The output balance error is a measure of how well the outputs are balanced and is defined as the ratio of the output common-mode voltage to the output differential signal. Ou t pu t Bal an c e E rr or = V OU T + − V OU T − V OU T + − V OU T − (2) At low frequencies, resistor mismatch is the primary contributor to output balance errors. Additionally CMRR, PSRR, and HD2 performance diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to optimize performance. See Table 8-1 for recommended resistor values to use for a particular gain. Table 8-1. Recommended Resistor Values Gain (V/V) RG (Ω) RF (Ω) 1 390 390 2 374 750 5 402 2010 10 402 4020 THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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8.1.2 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The THS2630 has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 8-1. A minimum value of 20 Ω should work well for most applications. For example, in 50- Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. RFRG RG VOCM RF VCC+ VCC- VOUT+ VOUT- 20 Ω 20 Ω Figure 8-1. Driving a Capacitive Load
8.1.3 Data Converters
Driving data converters are one of the most popular applications for fully-differential amplifiers. Figure 8-2 shows a typical configuration of an FDA attached to a differential analog-to-digital converter (ADC). RFRG RG VOCM RF VCC+ = 5 V AIN1 RCB THS1206 VIN 0.1 μF AIN2 AVDD DVDD VDD AVSS VREF RCB CCB VCC- = -5 V Figure 8-2. Fully-Differential Amplifier Attached to a Differential ADC FDAs can operate with a single supply. V OCM defaults to the mid-rail voltage, V CC/2. The differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the V OCM of the amplifier using a bypass capacitor to reduce broadband common-mode noise. RFRG RG VOCM RF VCC = 5 V AIN1 RCB THS1206 VIN 0.1 μF AIN2 AVDD DVDD VDD AVSS VREF RCB CCB Figure 8-3. Fully-Differential Amplifier Using a Single Supply www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: THS2630
8.1.4 Single-Supply Applications
For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed the common-mode input voltage range. However, some single-supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the circuit configuration of Figure 8-4 is suggested to bring the common-mode input voltage within the specifications of the amplifier. RFRG RG VOCM RF VCC = 5 V AIN1 RCB THS1206 VIN VCC RPU VCC RPU 0.1 μF AIN2 AVDD DVDD VDD AVSS VREF RCB CCB VP VOUT VOUT Figure 8-4. Circuit With Improved Common-Mode Input Voltage Equation 3 is used to calculate RPU: R PU = V P − V CC V I N − V P 1 R G + V OU T − V P 1 R F (3)
8.2 Typical Application
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 8-5 shows a method by which the noise may be filtered in the THS2630. Figure 8-5 shows a typical application design example for the THS2630 device in active low-pass filter topology driving and ADC. VIN− VIN+ + − + VOCM VOCMVIN− VIN+ VCC− THS1050THS2630 R(t) VCC C1R2 Vs VIC Figure 8-5. Antialias Filtering THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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8.2.1 Design Requirements
Table 8-2 provides example design parameters and values for the typical application design example in Figure 8-5. Table 8-2. Design Parameters DESIGN PARAMETERS VALUE Supply voltage ±2.5 V to ±17.5 V Amplifier topology Voltage feedback Output control DC coupled with output common mode control capability Filter requirement 500 kHz, Multiple feedback low pass filter
8.2.2 Detailed Design Procedure
8.2.2.1 Active Antialias Filtering
Figure 8-5 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is: H d f = K − f FS F × fc + 1 Q j f F SF × f c + 1 Rt
2 R 4 + Rt
1 + j 2 π fR 4 R tC 3 W ℎ e re K = R 2 R 1 (4) F SF × fc = 1 2 π 2 × R 2 R 3 C 1 C 2 an d Q = 2 × R 2 R 3 C 1 C 2 R 3 C 1 + R 2 C 1 + K R 3 C 1 (5) K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the quality factor. F SF = Re 2 + I m 2 an d Q = Re 2 + I m 2
2 Re (6)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C, and C2 = nC results in: F SF × f c = 1 2 πR c 2 × mn an d Q = 2 × m n 1 + m 1 + K (7) Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select C and calculate R for the desired fc. www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: THS2630
8.2.3 Application Curve
Frequency (Hz) Output (dB) -25 -20 -15 -10 100k 1M 10M 100M 1G V CC = 2.5 V V CC = 5 V V CC = 15 V Figure 8-6. Large-Signal Frequency Response
8.3 Power Supply Recommendations
The THS2630 device was designed to be operated on power supplies ranging from ±2.5 V to ±17.5 V (single- ended supplies of 5 V to 35 V). TI recommends using a power-supply accuracy of 5% or better. When operated on a board with high-speed digital signals, it is important to provide isolation between digital signal noise and the analog input pins. The THS2630 is connected to power supplies through pin 3 (V CC+) and pin 6 (VCC-). Each supply pin should be decoupled to GND as close to the device as possible with a low-inductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method of reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are advised. To avoid undesirable signal transients, the THS2630 device should not be powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs when an ADC is used in the application.
8.4 Layout
8.4.1 Layout Guidelines
To achieve the levels of high-frequency performance of the THS2630 device, follow proper printed-circuit board (PCB) high-frequency design techniques. A general set of guidelines is given below. In addition, a THS2630 device evaluation board is available to use as a guide for layout or for evaluating the device performance.
- Ground planes—It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance.
- Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
- Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inputs of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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8.4.2 Layout Example
RF+RG– RG+ RT– VOCM RF– VCC+ VCC+ FDA PD VCC- RT+RS+ RO+ RO– CL CBYP CBYP VIN Figure 8-7. Representative Schematic for Layout Ground and power plane removed from inner layers. Ground fill on outer layers also removed. Ground and power plane exist on inner layers. RF+ Place the feedback resistors, RF±, gain resistors, RG±, and the isolation resistors, RO±, as close to the device pins as possible to minimize parasitics RF– RO+ RO– RG– RG+ IN– VOCM VCC+ IN+ VCC– OUT– CL RT+ RS+ RT– VIN PD2 7 Vias to connect supply pins to CBYP. Place CBYP capacitors on the other side of the PCB as close to the vias as possible. OUT+ Remove GND and Power plane under output and inverting pins to minimize stray PCB capacitance Figure 8-8. Layout Recommendations www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: THS2630
8.4.3 General PowerPAD Design Considerations
The THS2630 is available in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted (see Figure 8-9 a and Figure 8-9 b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see Figure 8-9 c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the previously awkward mechanical methods of heatsinking. More complete details of the PowerPAD installation process and thermal management techniques can be found in PowerPAD Thermally-Enhanced Package technical brief. This document can be found on the TI website (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to SLMA002 when ordering. DIE Side View (a) End View (b) Bottom View (c) DIE Thermal Pad A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from VCC– to VCC+. Typically, the thermal pad is connected to the ground plane because this plane tends to physically be the largest and is able to dissipate the most amount of heat. Figure 8-9. Views of Thermally-Enhanced DGN Package THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, Design Guide for 2.3 nV/√Hz, Differential, Time Gain Control (TGC) DAC Reference Design for Ultrasound design guide
- Texas Instruments, EVM User's Guide for High-Speed Fully-Differential Amplifier user's guide
- Texas Instruments, Fully Differential Amplifiers application note
- Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application note
- Texas Instruments, PowerPAD Thermally-Enhanced Package technical brief
- Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: THS2630
10.1 Mechanical Data
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:8X SYMM 4 5 SEE DETAILS SYMM www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: THS2630
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5 THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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10.2 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PTHS2630SDR SOIC D 8 2500 330 12.4 6.40 5.20 2.10 8 12 Q1 PTHS2630SDGKR VSSOP DGK 8 2500 330 12.4 6.40 5.20 2.10 8 12 Q1 THS2630 SLOSE96 – JANUARY 2023 www.ti.com ADVANCE INFORMATION
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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTHS2630SDR SOIC D 8 2500 367 367 35 PTHS2630SDGKR VSSOP DGK 8 2500 366 364 50 www.ti.com THS2630 SLOSE96 – JANUARY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: THS2630
www.ti.com 16-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTHS2630SDGKR ACTIVE VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 85 Samples PTHS2630SDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 85 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 16-Mar-2023 Addendum-Page 2
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