PTH12010WAH

PTH12010W TI | Alldatasheet

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www.ti.com 12-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT FEATURES APPLICATIONS Nominal Size = 1.37 in x 0.62 in (34,8 mm x 15,75 mm)

DESCRIPTION

PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 ADJUST POWER MODULE

• Complex Multivoltage, Multiprocessor• Up to 12-A Output Current Systems• 12-V Input Voltage
• Wide-Output Voltage Adjust
• Efficiencies up to 94%
• 200 W/in3 Power Density
• On/Off Inhibit
• Output Voltage Sense
• Prebias Startup
• Undervoltage Lockout
• Auto-Track™ Sequencing
• Margin Up/Down Controls
• Output Overcurrent Protection (Nonlatching, Auto-Reset)
• Operating Temperature: –40°Ct o8 5°C
• Safety Agency Approvals: UL /cUL 60950, EN60950 VDE
• Point of Load Alliance (POLA™) Compatible The PTH12010 series of non-isolated power modules that are small in size but big on performance and flexibility. The high output current, compact footprint, and industry-leading features offers system designers a versatile module for powering complex multi-processor digital systems. The series employs double-sided surface mount construction and provides high-performance step-down power conversion for up to 12 A of output current. The output voltage of the W-suffix parts can be set to any value over set using a single external resistor. This series includes Auto-Track™ sequencing. Auto-Track simplifies the task of supply voltage sequencing in a power system by enabling modules to track each other, or any external voltage, during power up and power down. Other operating features include an on/off inhibit, output voltage adjust (trim), margin up/down controls, and the ability to start up into an existing output voltage or prebias. For improved load regulation, an output voltage sense is also provided. A nonlatching overcurrent trip serves as load fault protection. Target applications include complex multivoltage, multiprocessor systems that incorporate the industry’s high-speed TMS320™ DSP family, microprocessors, and bus drivers. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Auto-Track, TMS320, POLA are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com PT H 12010x (Top View) 543 Margin Up Margin Down VI L O A DC 560 F (Required) I /c109 R ,1% (Required) SET + C 330 F (Optional) O /c109 Inhibit GND GND VO VOSense Track ABSOLUTE MAXIMUM RATINGS PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. STANDARD APPLICATION A. RSET = Required to set the output voltage to a value higher than the lowest value (see the electrical characteristics table for values).

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. Voltages are with respect to GND MIN TYP MAX UNIT Vtrack Track Input Voltage –0.3 V I +0 . 3 V TA Operating Temperature Over V in Range –40 (1) 85 °C Range Twave Wave solder Surface temperature of module body or pins PTH12010WAH 260 (2) temperature (5 seconds) °CPTH12010WAS 235 (2)Solder reflowTreflow Surface temperature of module body or pinstemperature PTH12010WAZ 260 (2) Tstg Storage Temperature –40 125 °C Mechanical Shock Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 Sine, mounted 500 G Mechanical Vibration Mil-STD-883D, Method 2007.2 20 G 20-2000 Hz Weight 5 grams Flammability Meets UL 94V-O (1) For operation below 0 °C the external capacitors must have stable characteristics. Use either a low-ESR tantalum, Os-Con, or ceramic capacitor. (2) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated maximum.

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ELECTRICAL CHARACTERISTICS

PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 TA =2 5°C, Vi =1 2V ,V O = 3.3 V, Ci = 560 µF, CO =0 µF, and IO =I O max (Unless otherwise stated) PTH12010W CHARACTERISTICS CONDITIONS MIN TYP MAX UNIT 60 °C, 200 LFM airflow 0 12 (3) Io Output current 1.2 V ≤ Vo≤ 5.5 V A 25 °C, natural convection 0 12 (1) VI Input voltage range Over I o range 10.8 13.2 V Vo tol Set-point voltage tolerance ±2(4) %Vo ¨Regtemp Temperature variation –40 °C < T A <8 5 °C± 0 . 5 % V o ¨Regline Line regulation Over V I range ±10 mV ¨Regload Load regulation Over I o range ±12 mV ¨Regtot Total output variation Includes set-point, line, load, ±3 (2) %Vo ¨Vadj Output voltage adjust range Over V I range 1.2 5.5 V RSET = 280 Ω,V o =5V 9 4 RSET =2 . 0kΩ,V o =3 . 3V 9 3 RSET =4 . 3 2kΩ,V o =2 . 5V 9 1 η Efficiency I O =8A % RSET = 11.5 kΩ,V o =1 . 8V 8 9 RSET = 24.3 kΩ,V o =1 . 5V 8 8 RSET = OPEN, Vo =1 . 2V 8 6 Vo ≤ 2.5 V 25 mVpp Vr VO ripple (peak-to-peak) 20-MHz bandwidth Vo ≤ 2.5 V 1 % V O Io trip Overcurrent threshold Reset, followed by auto-recovery 20 A

1 A/µs load step, 50 to 100 % I omax,

CO = 330 µF Transient responsettr Recovery Time 70 µSec ¨Vtr Vo over/undershoot 100 mV Vo adj Margin up/down adjust ±5 % IIL –8(5) µAMargin input current (pins 9 /10) Pin to GNDmargin IIL track Track input current (pin 8) Pin to GND –0.13 (6) mA dVtrack/dt Track slew rate capability C O≤ CO(max) 1 V/ms Vi increasing 9.5 10.4 UVLO Undervoltage lockout V Vi decreasing 8.8 9 Inhibit control (pin3) VIH Input high voltage Referenced to GND V I– 0.5 Open (4) V VIL Input low voltage –0.2 0.5 IIL inhibit Input low current Pin to GND 0.24 mA Iin inh Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA fs Switching frequency Over V i and Io ranges 300 350 400 kHz Ci External input capacitance 560 (7) µF (3) See SOA curves or consult factory for appropriate derating. (4) The set-point voltage tolerance is affected by the tolerance and stability of R SET. The stated limit is unconditionally met if R SET has a tolerance of 1%, with 100 ppm/°C (or better) temperature stability. (5) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 V dc. (6) This control pin has an internal pull-up to the input voltage V I (7.5 V for pin 8). If it is left open-circuit the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external pull-up on this pin. For further information, see the related application section. (7) A 560 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple current. 3Submit Documentation Feedback

www.ti.com PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) TA =2 5°C, Vi =1 2V ,V O = 3.3 V, Ci = 560 µF, CO =0 µF, and IO =I O max (Unless otherwise stated) PTH12010W CHARACTERISTICS CONDITIONS MIN TYP MAX UNIT nonceramic 0 (8) 330(9) 6,600(10) Capacitance value µF CO External output capacitance ceramic 0 300 Equivalent series resistance (nonceramic) 4 (11) mΩ Per Bellcore TR-332 MTBF Reliability 6.4 10 6 Hr 50% stress, Ta =4 0 °C, ground benign (8) When operating at an output voltage ≥ 3.3 V, 47-µF of external output capacitance is required for proper operation. (9) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the transient response. (10) This is the calculated maximum. The minimum ESR limitation often results in a lower value. When controlling the Track pin using a voltage supervisor, CO(max) is reduced to 3300 µF. See the application notes for further guidance. (11) This is the typical ESR for all the electrolytic (nonceramic) ouput capacitance. Use 7 m Ω as the minimum when using max-ESR values to calculate. TA =2 5°C, Vi =1 2V ,V O = 1.8 V, Ci = 560 µF, CO =0 µF, and IO =I Omax (Unless otherwise stated) PTH12010L CHARACTERISTICS CONDITIONS MIN TYP MAX UNIT 60 °C, 200 LFM airflow 0 - 12 (12) Io Output current 0.8 V ≤ VO≤ 1.8 V A 25 °C, natural convection 0 12 (1) VI Input voltage range Over I O range 10.8 13.2 V Vo tol Set-point voltage tolerance ±2(13) %Vo ∆Regtemp Temperature variation –40 °C <T A <8 5 °C ±0.5 %V o ∆Regline Line regulation Over V i range ±10 mV ∆Regload Load regulation Over I O range ±12 mV ∆Regtot Total output variation Includes set-point, line, load, ±3(2) %Vo –4 0°C ≤ TA≤ 85 °C ¨Vadj Output voltage adjust range Over V i range 0.8 1.8 V RSET = 130 Ω,V o =1 . 8V 8 9 RSET =3 . 5 7kΩ,V o =1 . 5 8 8 V η Efficiency I O=8A R SET = 12.1 kΩ,V o =1 . 2 8 6 % V RSET = 32.4 kΩ,V o =1V 8 4 RSET = OPEN, Vo =0 . 8V 8 2 Vo≤ 1 V 25 mVpp Vr VO ripple (peak-to-peak) 20 MHz bandwidth Vo≤ 1V 1 % V O Io trip Overcurrent threshold Reset, followed by auto-recovery 20 A

1 A/µs load step, 50 to 100 % I omax, CO = 330

µF Transient responsettr Recovery Time 70 µSec ∆Vtr VO over/undershoot 100 mV VO adj Margin up/down adjust ±5% IIL margin Margin input current (pins 9 /10) Pin to GND –8 (14) µA (12) See SOA curves or consult factory for appropriate derating. (13) The set-point voltage tolerance is affected by the tolerance and stability of R SET. The stated limit is unconditionally met if R SET has a tolerance of 1%, with 100 ppm/°C (or better) temperature stability. (14) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 V dc.

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www.ti.com PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) TA =2 5°C, Vi =1 2V ,V O = 1.8 V, Ci = 560 µF, CO =0 µF, and IO =I Omax (Unless otherwise stated) PTH12010L CHARACTERISTICS CONDITIONS MIN TYP MAX UNIT IIL track Track input current (pin 8) Pin to GND –0.13 (15) mA dVtrack/dt Track slew rate capability C O≤ CO(max) 1 V/ms Vi increasing 9.5 10.4 UVLO Undervoltage lockout V Vi decreasing 8.8 9 Inhibit control (pin3) VIH Input high voltage Referenced to GND V I– 0.5 Open (4) V VIL Input low voltage –0.2 0.5 IIL Input low current Pin to GND 0.24 mA Ii inh Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA fs Switching frequency Over V i and Io ranges 200 250 300 kHz CI External input capacitance 560 (16) µF nonceramic 0 330 (17) 6,600(18) Capacitance value µF CO External output capacitance ceramic 0 300 Equivalent series resistance (nonceramic) 4 (19) mΩ Per Bellcore TR-332 MTBF Reliability 6.4 10 6 Hrs 50% stress, Ta =4 0°C, ground benign (15) This control pin has an internal pull-up to the input voltage V I (7.5 V for pin 8). If it is left open-circuit the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external pull-up on this pin. For further information, see the related application section. (16) A 560 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple current. (17) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the transient response. (18) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a voltage supervisor, C O(max) is reduced to 3300 µF. See the application notes for further guidance. (19) This is the typical ESR for all the electrolytic (nonceramic) ouput capacitance. Use 7 m Ω as the minimum when using max-ESR values to calculate. 5Submit Documentation Feedback

www.ti.com DEVICE INFORMATION PTHXX010 (Top View) 10 9 8 543 PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 TERMINAL FUNCTIONS TERMINAL NAME NO. This is the common ground connection for the V I and VO power connections. It is also the 0 V dcGND 1,7 reference for the control inputs. VI 2 The positive input voltage power node to the module, which is referenced to common GND. The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level ground signal to this input disables the module’s output and turns off the output voltage. Inhibit(20) 3 When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the inhibit feature is not used, the control pin should be left open-circuit. The module then produces an output whenever a valid input source is applied. A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of the module higher than its lowest value. The temperature stability of the resistor should be 100 ppm/ °C V O Adjust 4 devices. The resistor value required for a given output voltage may be calculated using a formula. If left open circuit, the output voltage defaults to its lowest value. For further information on output voltage adjustment, see the related application section. The specification table gives the preferred resistor values for a number of standard output voltages. The sense input allows the regulation circuit to compensate for voltage drop between the module and V O Sense 5 the load. For optimal voltage accuracy, VO Sense should be connected to VO. It can also be left disconnected. VO 6 The regulated positive power output with respect to the GND node. This is an analog control input that enables the output voltage to follow an external voltage. This pin becomes active typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage from 0 V up to the nominal set-point voltage. Within this range the output will follow the voltage at the Track pin on a volt-for-volt basis. When the control voltage is raised above thisTrack 8 range, the module regulates at its set-point voltage. The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus. If unused, this input should be connected to V i. Note: Due to the undervoltage lockout feature, the output of the module cannot follow its own input voltage during power up. When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The input requires an open-collector (open-drain) interface. It is not TTL compatible. A lower percentMargin Down(1) 9 change can be accomodated with a series resistor. For further information, see the related application section. When this input is asserted to GND, the output voltage is increased by 5%. The input requires an Margin Up(1) 10 open-collector (open-drain) interface. It is not TTL compatible. The percent change can be reduced with a series resistor. For further information, see the related application section. (20) Denotes negative logic: Open = Normal operation Ground = Function active

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400 LFM

200 LFM

100 LFM

Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. converter. Applies to Figure 1, Figure 2, and Figure 3. pins. Please refer to the mechanical specification for more information. Applies to Figure 4, Figure 5,a n dFigure 6.

Figure 7. Figure 8. Figure 9. converter. Applies to Figure 7, Figure 8, and Figure 9. pins. Please refer to the mechanical specification for more information. Applies to Figure 10.

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APPLICATION INFORMATION

CAPACITOR RECOMMENDATIONS FOR THE PTH12010 SERIES OF POWER MODULES INPUT CAPACITOR OUTPUT CAPACITORS (OPTIONAL) CERAMIC CAPACITORS TANTALUM CAPACITORS CAPACITOR TABLE PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 The recommended input capacitance is determined by the 560 µF minimum capacitance and 800 mArms minimum ripple current rating. A 10 µF X5R/X7R ceramic capacitor may also be added to reduce the reflected input ripple current. The ceramic capacitor should be located between the input electrolytic and the module. Ripple current, less than 100 m Ω equivalent series resistance (ESR) and temperature are major considerations when selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have a recommended minimum voltage rating of 2 × (max dc voltage + ac ripple). This is standard practice to ensure reliability. No tantalum capacitors were found with sufficient voltage rating to meet this requirement. At temperatures below 0°C, the ESR of aluminum electrolytic capacitors increases. For these applications, Os-Con, polymer-tantalum, and polymer-aluminum types should be considered. For applications with load transients (sudden changes in load current), regulator response benefits from external output capacitance. The value of 330 µF is used to define the transient response specification (see data sheet). For most applications, a high quality computer-grade aluminum electrolytic capacitor is adequate. These capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient temperatures above 0 °C. Below 0 °C, tantalum, ceramic or Os-Con type capacitors are recommended. When using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 m Ω (7 mΩ using the manufacturer’s maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified in Table 1. In addition to electrolytic capacitance, adding a 10 µF X5R/X7R ceramic capacitor to the output reduces the output ripple voltage and improve the regulator’s transient response. The measurement of both the output ripple and transient response is also best achieved across a 10 µF ceramic capacitor. Above 150 kHz the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramic capacitors have very low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output. When used on the output, their combined ESR is not critical as long as the total value of ceramic capacitance does not exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than five identical ceramic capacitors in parallel with values of 10 µF or greater. Tantalum type capacitors are most suited for use on the output bus, and are recommended for applications where the ambient operating temperature can be less than 0 °C. The AVX TPS, Sprague 593D/594/595 and Kemet T495/T510 capacitor series are suggested over other tantalum types due to their higher rated surge, power dissipation, and ripple current capability. As a caution, many general purpose tantalum capacitors have considerably higher ESR, reduced power dissipation and lower ripple current capability. These capacitors are also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not have a stated ESR or surge current rating are not recommended for power applications. When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit are encountered well before the maximum capacitance value is reached. Table 1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are critical parameters necessary to insure both optimum regulator performance and long capacitor life. 9Submit Documentation Feedback

capacitance is above 3000 µF, the selection of output capacitors becomes more important. Table 1. Input/Output Capacitors consideration for obsolescence. (30) N/R –Not recommended. The capacitor voltage rating does not meet the minimum derated operating limits. (31) The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V.

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Table 1. Input/Output Capacitors (continued)

16 V 47 3225 mm 1 (5) ≤5 GRM32ER61CJ476K

16 V 22 1 (5) ≤5 GRM32ER61C226K

16 V 10 1 (5) ≤5 GRM32DR61C106K

6.3 V 47 3225 mm N/R (34) ≤5 C3225X5R0J476MT

16 V 22 1 (35) ≤5 C3225X5R1C226MT

16 V 10 1 (7) ≤5 C3225X5R1C106MT

(32) A total capacitance of 540 µF is acceptable based on the combined ripple current rating. (33) A ceramic capacitor may be used to complement electrolytic types at the input to further reduce high-frequency ripple current. (34) N/R –Not recommended. The capacitor voltage rating does not meet the minimum derated operating limits. (35) A ceramic capacitor may be used to complement electrolytic types at the input to further reduce high-frequency ripple current.

actual output voltage that this resistance value provides. Figure 11 shows the placement of the required resistor. Table 2. Preferred Values of Rset for Standard Output Voltages range of values given in Table 4. The following formula may be used for calculating the adjust resistor value. Select the appropriate value for the parameters, R S and Vmin, from Table 3. Table 3. Adjust Formula Parameters Figure 11. Vo Adjust Resistor Placement

1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with temperature stability of 100 ppm/ °C

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pins 4 and 7 using dedicated PCB traces.

1. Never connect capacitors from VO Adjust to either GND or VO. Any capacitance added to the VO Adjust pin

affects the stability of the regulator. Table 4. Output Voltage Set-Point Resistor Values

require a flexible, high performance module that is small in size. Each of these products are POLA™ compatible. thereby providing customers with second-source availability. provides a quick reference to the features by product series and input bus voltage. Table 5. Operating Features by Series and Input Bus Voltage A) and PTH12030 (26 A) products incorporate overtemperature shutdown protection.

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0.1 W, 1 %

Figure 12. Power-Up Application Circuit under soft-start control, the output voltage rises to the set-point at a quicker and more linear rate. Figure 13. Power-Up Waveforms removed, the module automatically recovers and returns to normal operation.

from the regulator to be turned off. whenever a valid source voltage is connected to V I with respect to GND. Figure 14. Inhibit Control Circuit 25 ms Figure 15 shows the typical rise in both the output voltage and input current, following the turn-off of Q1. Figure 15. Power-Up from Inhibit Control

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1. The Track pin voltage must be allowed to rise above the module set-point voltage before the module

regulates at its adjusted set-point voltage.

1. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with ramp
2. The absolute maximum voltage that may be applied to the Track pin is the input voltage VI.
3. The module cannot follow a voltage at its Track control input until it has completed its soft-start initialization.

is recommended that the Track pin be held at ground potential.

1. The Auto-Track function is disabled by connecting the Track pin to the input voltage (V

is disabled, the output voltage rises at a quicker and more linear rate after input power has been applied. Figure 16. Sequenced Power Up and Power Down Using Auto-Track

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0.1 W, 1%

Table 6. Margin Up/Down Resistor Values Figure 19. Margin Up/Down Application Schematic under the control of the module’s internal soft-start mechanism; see Figure 20. signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track disabled. either the set-point voltage, or the voltage applied at the module’s Track control pin, whichever is lowest.

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330 F/c109

0.68 F/c109

0.1 F/c109

Figure 22. Application Circuit Demonstrating Prebias Startup between the pin and and the output node, ensures the output remains in regulation. pins, and that measured from VO Sense to GND, is the amount of IR drop being compensated by the regulator. This should be limited to a maximum of 0.3 V.

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www.ti.com TAPE AND REEL SPECIFICATIONS TRAY SPECIFICATIONS PTH12010W, PTH12010L SLTS205E–JUNE 2003–REVISED APRIL 2006 23Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTH12010LAH ACTIVE DIP MOD ULE EUH 10 25 Pb-Free (RoHS) Call TI N / A for Pkg Type PTH12010LAS ACTIVE DIP MOD ULE EUJ 10 25 TBD Call TI Level-1-235C-UNLIM PTH12010LAST ACTIVE DIP MOD ULE EUJ 10 250 TBD Call TI Level-1-235C-UNLIM PTH12010LAZ ACTIVE DIP MOD ULE EUJ 10 25 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTH12010LAZT ACTIVE DIP MOD ULE EUJ 10 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTH12010WAH ACTIVE DIP MOD ULE EUH 10 25 Pb-Free (RoHS) Call TI N / A for Pkg Type PTH12010WAS ACTIVE DIP MOD ULE EUJ 10 25 TBD Call TI Level-1-235C-UNLIM PTH12010WAST ACTIVE DIP MOD ULE EUJ 10 250 TBD Call TI Level-1-235C-UNLIM PTH12010WAZ ACTIVE DIP MOD ULE EUJ 10 25 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTH12010WAZT ACTIVE DIP MOD ULE EUJ 10 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Addendum-Page 1

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