PTCAN1473ADRQ1.A

TCAN1473A-Q1 TI | Alldatasheet

Document overview

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Technical content

TCAN1473A-Q1 Automotive Signal Improvement Capable CAN FD Transceiver With Sleep Mode

1 Features

• AEC-Q100 Qualified for automotive applications
• Functional Safety-Capable – Documentation available to aid in functional safety system design
• Implements Signal Improvement Capability (SIC) as defined in ISO 11898-2:2024 – Actively improves bus signal by eliminating ringing and enhancing bit symmetry – Backward compatible for use in classic CAN networks
• Wide input operational voltage range
• Supports classic CAN and CAN FD up to 8Mbps
• VIO level shifting supports: 1.7V to 5.5V
• Operating modes: – Normal mode – Silent mode – Standby mode – Low-power sleep mode supporting remote and local wake-up
• High-voltage INH output for system power control
• INH_MASK pin to keep INH disabled during spurious wake-up events
• Local wake-up support via the WAKE pin
• Sleep Wake Error (SWE) timer enables safe transition from standby mode to sleep mode in the event of a system power failure or software fault – Allows for extended power-up time
• Defined behavior when unpowered – Bus and IO terminals are high impedance
• Protection features: – ±58V CAN bus fault tolerant – Load dump support on VSUP – IEC ESD protection – Undervoltage protection – Thermal shutdown protection – TXD dominant state timeout (TXD DTO)
• Available in 14-pin leaded (SOT and SOIC) packages and leadless (VSON) package with wettable flanks for improved automated optical inspection (AOI) capability

2 Applications

• Body electronics and lighting
• Automotive gateway
• Advanced driver assistance systems (ADAS)
• Infotainment and cluster
• Hybrid, electric & powertrain systems
• Personal transport vehicles - Electric bike
• Industrial transportation

3 Description

The TCAN1473A-Q1 is a Controller Area Network (CAN) transceiver that meets the physical layer requirements of the ISO 11898-2:2024 CAN specification with Signal Improvement Capability (SIC) functionality. The device reduces signal ringing at dominant-to-recessive edges and enables higher throughput in complex network topologies. SIC allows applications to extract the real benefit of CAN Flexible Datarate (CAN FD) by operating at 2Mbps, 5Mbps, and 8Mbps, even in large networks with multiple unterminated stubs. The TCAN1473A-Q1 allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a system via the INH output pin. This allows a low-current sleep state in which power is gated to all system components except for the TCAN1473A-Q1, while monitoring the CAN bus. When a wake-up event is detected, the TCAN1473A- Q1 initiates system start-up by driving INH high. The TCAN1473A-Q1 features an SWE timer that enables a safe transition to Sleep mode after 4 minutes (tINACTIVE) of inactivity in Standby mode. This makes sure the device is transitioned to low-power Sleep mode if the MCU fails to transition the device to Normal mode. The device is pin compatible with classical CAN FD transceivers, such as TCAN1043A-Q1 or TCAN1043H-Q1 when INH_MASK feature is not used (INH_MASK pin is left floating or connected to GND). TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TCAN1473AC-Q1 SOT (DYY) 4.2mm × 3.26mm SOIC (D) 8.65mm × 6mm VSON (DMT) 4.5mm × 3mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TCAN1473A-Q1 MCU VDD Optional: Terminating Node Optional: Filtering, Transient and ESD VIN VIO VBAT 3 k EN CANH TXD RXD VIO WAKEVSUP CANL EN nSTB 100 nF VCC 100 nF CAN FD Controller 7 9 10

5 V VOUT INH

INH_MASK (leave floating or connect to GND) VREG Simplified Schematic TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

4RXD 11 INH_MASK 5VIO 10 VSUP 6EN 9 WAKE 7INH 8 nFAULT Not to scale Figure 4-1. D and DYY Packages, 14 Pin (SOIC) and (SOT) (Top View) 1TXD 14 nSTB 2GND 13 CANH 3VCC 12 CANL 4RXD 11 INH_MASK 5VIO 10 VSUP 6EN 9 WAKE 7INH 8 nFAULT Not to scale Thermal Pad Figure 4-2. DMT Package, 14 Pin (VSON) (Top View) Table 4-1. Pin Functions PINS TYPE (1) DESCRIPTION NAME NO. TXD 1 I CAN transmit data input, integrated pull-up GND 2 GND Ground connection VCC 3 P 5V transceiver supply RXD 4 O CAN receive data output, tri-state when VIO < UVIO VIO 5 P I/O supply voltage EN 6 I Enable input for mode control, integrated pull-down INH 7 O Inhibit pin to control system voltage regulators and supplies, high-voltage nFAULT 8 O Fault output, inverted logic WAKE 9 I Local WAKE input terminal, high voltage VSUP 10 P High-voltage supply from battery INH_MASK 11 I INH_MASK pin used to activate/deactivate INH functionality. Internal pull-down to GND. Can be left floating or connected to GND if INH_MASK functionality is not needed. Do not connect to power supply. CANL 12 I/O Low-level CAN bus input/output line CANH 13 I/O High-level CAN bus input/output line nSTB 14 I Standby mode control input, integrated pull-down Thermal Pad — Connect the thermal pad to the printed circuit board (PCB) ground plane for thermal relief (1) I = input, O = output, P = power, GND = ground TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VSUP Supply voltage(2) –0.3 45 V VCC Supply voltage –0.3 6 V VIO Supply voltage I/O level shifter –0.3 6 V VBUS CAN bus I/O voltage (CANH, CANL) –58 58 V VDIFF CAN bus differential voltage (VDIFF = VCANH - VCANL) –58 58 V VWAKE WAKE input voltage –45 45 and VI ≤ VSUP+0.3 V VINH INH pin voltage –0.3 45 and VO ≤ VSUP+0.3 V VLOGIC Logic pin voltage –0.3 6 V IO(LOGIC) Logic pin output current 8 mA IO(INH) Inhibit pin output current 6 mA IO(WAKE) WAKE pin output current 3 mA TJ Junction temperature –40 165 °C TSTG Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Able to support load dumps of up to 45 V for 300ms

5.2 ESD Ratings

VESD Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) VSUP, CANH, CANL, and WAKE with respect to ground ±8000 V All pins except VSUP, CANH, CANL, and WAKE. ±4000 V Charged device model (CDM), per AEC Q100-011 All pins ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 ESD Ratings - IEC Specifications

VESD Electrostatic discharge CANH, CANL, VSUP, and WAKE terminal to GND Unpowered Contact Discharge per ISO 10605 (1) ±8000 V VESD Electrostatic discharge CANH and CANL terminal to GND SAE J2962-2 per ISO 10605 Powered Contact Discharge (2) ±8000 V VESD Electrostatic discharge CANH and CANL terminal to GND SAE J2962-2 per ISO 10605 Powered Air discharge (2) ±15000 V www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCAN1473A-Q1

5.3 ESD Ratings - IEC Specifications (continued)

ISO-7637-2 (1) CAN, VSUP, WAKE terminal to GND Pulse 1 –100 V Pulse 2 75 V Pulse 3a –150 V Pulse 3b 100 V Transient voltage per ISO-7637-3 (2) CAN terminal to GND Direct coupling capacitor "slow transient pulse" with 100 nF coupling capacitor - powered ±30 V (1) Results given here are specific to the IEC 62228-3 Integrated circuits – EMC evaluation of transceivers – Part 3: CAN transceivers. Testing performed by IBEE Zwickau, EMC report available upon request. (2) Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed by OEM-approved independent 3rd party, EMC report available upon request.

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VSUP Supply voltage 4.5 40 V VIO I/O supply voltage 1.7 5.5 V VCC CAN transceiver supply voltage 4.5 5.5 V IOH(DO) Digital output high-level current –2 mA IOL(DO) Digital output low-level current 2 mA IO(INH) Inhibit output current 4 mA TJ Operating junction temperature –40 150 °C TSDR Thermal shutdown 175 °C TSDF Thermal shutdown release 160 °C TSD(HYS) Thermal shutdown hysteresis 10 °C

5.5 Thermal Information

THERMAL METRIC(1) TCAN1473A-Q1 UNIT D (SOIC) DMT (VSON) DYY (SOT) RθJA Junction-to-ambient thermal resistance 87.1 39.7 91.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 41.8 41.1 41.7 °C/W RθJB Junction-to-board thermal resistance 43.7 15.9 25.6 °C/W ΨJT Junction-to-top characterization parameter 8.5 0.9 25.4 °C/W ΨJB Junction-to-board characterization parameter 43.3 15.9 1.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 6.6 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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5.6 Power Dissipation Ratings

PARAMETER TEST CONDITIONS POWER DISSIPATION UNIT PD Average power dissipation VSUP = 14 V, VCC = 5 V, VIO = 5 V, TJ = 27°C, RL = 60 Ω, nSTB = 5 V, EN = 5 V, CL_RXD = 15 pF. Typical CAN operating conditions at 500 kbps with 25% transmission (dominant) rate. 62 mW VSUP = 14 V, VCC = 5.5 V, VIO = 5.5 V, TJ = 150°C, RL = 50 Ω, nSTB = 5.5 V, EN = 5.5 V, CL_RXD = 15 pF. Typical high load CAN operating conditions at 1 Mbps with 50% transmission (dominant) rate and loaded network. 135 mW

5.7 Power Supply Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Voltage and Current Characteristics ISUP_NORMAL Supply current CAN active Normal mode, silent mode, and go-to-sleep mode 140 µA ISUP_STBY Supply current, Standby mode CAN autonomous: inactive Standby mode(2) 65 µA ISUP_SLEEP Supply current CAN autonomous: inactive Sleep mode 18 33 µA ISUP_BIAS Supply current Additional current when in CAN autonomous: active

5.5 V < VSUP ≤ 28 V (1) 50 µA

UVSUP(R) Undervoltage VSUP threshold rising Ramp up 3.85 4.4 V UVSUP(F) Undervoltage VSUP threshold falling Ramp down 3.5 4.25 V ICC_NORMAL Supply current CAN active: dominant Normal mode TXD = 0 V, RL = 60 Ω, CL = open See Supply Test Circuit 60 mA Supply current CAN active: dominant Normal mode TXD = 0 V, RL = 50 Ω, CL = open 70 mA VCC supply current normal mode Dominant with bus fault Normal mode TXD = 0 V, RL = open, CL = open, CANH = -25 V 110 mA ICC_NORMAL Supply current CAN active: recessive Normal mode TXD = VIO, RL = 50 Ω, CL = open 5 mA ICC_STBY Supply current CAN autonomous: inactive Standby mode, TJ = -40 °C to 85 °C EN = nSTB = 0 V 2 µA ICC_STBY Supply current CAN autonomous: inactive Standby mode EN = nSTB = 0 V 5 µA ICC_SILENT Supply current Silent and go-to-sleep mode TXD = nSTB = VIO, RL = 50 Ω, CL = open 3 mA ICC_SLEEP Supply current CAN autonomous: inactive Sleep mode, TJ = -40 °C to 85 °C EN = 0 V or VIO, nSTB = 0 V 2 µA Supply current CAN autonomous: inactive Sleep mode EN = 0 V or VIO, nSTB = 0 V 5 µA UVCC(R) Undervoltage VCC threshold rising Ramp up 4.1 4.4 V UVCC(F) Undervoltage VCC threshold falling Ramp down 3.5 3.9 V VHYS(UVCC) Hysteresis voltage on UVCC 50 250 320 mV IIO_NORMAL I/O supply current Normal mode RXD floating, TXD = 0 V 350 µA I/O supply current Normal mode, standby mode, or go-to-sleep mode RXD floating, TXD = VIO 5 µA www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCAN1473A-Q1

5.7 Power Supply Characteristics (continued)

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIO_SLEEP I/O supply current Sleep mode, TJ = -40 °C to 85 °C nSTB = 0 V 2.5 µA I/O supply current Sleep mode nSTB = 0 V 5 µA UVIO(R) Under voltage VIO threshold rising Ramp up 1.4 1.65 V UVIO(F) Under voltage VIO threshold falling Ramp down 1 1.25 V VHYS(UVIO) Hysteresis voltage on UVIO 30 60 160 mV (1) ISUP(BIAS) is calculated by subtracting the supply current in CAN autonomous inactive mode from the total supply current in CAN autonomous active mode (2) After a valid wake-up, the CAN transceiver switches to CAN autonomous active mode and the ISUP(BIAS) current needs to be added to the specified ISUP current in CAN autonomous inactive mode.

5.8 Electrical Characteristics

Over recommended operating conditions with TJ = –40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CAN Driver Characteristics VCANH(D) Bus output voltage (dominant) CANH TXD = 0 V, 45 ≤ RL ≤ 65 Ω, CL = open, RCM = open See Figure 6-1 and Figure 6-4 3 4.26 V VCANL(D) Bus output voltage (dominant) CANL 0.75 2.01 V VCANH(R) VCANL(R) Recessive output voltage Bus biasing active TXD = VIO, RL = open (no load), RCM = open See Figure 6-1 and Figure 6-4 2 3 V VCANH(R) VCANL(R) Recessive output voltage Bus biasing active Recessive output voltage Bus biasing active TXD = VIO, 45 ≤ RL ≤ 65 Ω, CL = open, CSPLIT = 4.7 nF See Figure 6-1 and Figure 6-4 2.256 2.756 V VSYM Driver symmetry Bus biasing active (VO(CANH) + VO(CANL) ) / VREC where VREC = VCANH(R) + VCANL(R) nSTB= VIO, RL = 45 ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = Open, RCM = Open, TXD = 250 kHz, 1 MHz, 2.5 MHz See Figure 6-1 and Figure 6-4 0.95 1.05 V/V VSYM_DC DC Driver symmetry Bus biasing active VCC – VO(CANH) – VO(CANL) nSTB= VIO, RL = 45 ≤ RL ≤ 65 Ω, CL = open See Figure 6-1 and Figure 6-4 –300 300 mV VDIFF(D) Differential output voltage Bus biasing active Dominant CANH - CANL nSTB = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = open See Figure 6-1 and Figure 6-4 1.5 3 V CANH - CANL nSTB = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open See Figure 6-1 and Figure 6-4 1.5 3.3 V CANH - CANL nSTB = VIO, TXD = 0 V, RL = 2240 Ω, CL = open See Figure 6-1 and Figure 6-4 1.5 5 V VDIFF(R) Differential output voltage Bus biasing active Recessive CANH - CANL nSTB = VIO, TXD = VIO, 45 ≤ RL ≤ 65 Ω, CL = open, CSPLIT = 4.7 nF See Figure 6-1 and Figure 6-4 –50 50 mV VDIFF(R) Differential output voltage Bus biasing active Recessive CANH - CANL nSTB = VIO, TXD = VIO, RL = open Ω, CL = open See Figure 6-1 and Figure 6-4 –50 50 mV VCANH(INACT) Bus output voltage on CANH with bus biasing inactive nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open See Figure 6-1 and Figure 6-4 -0.1 0.1 V VCANL(INACT) Bus output voltage on CANL with bus biasing inactive nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open See Figure 6-1 and Figure 6-4 -0.1 0.1 V VDIFF(INACT) Bus output voltage on CANH - CANL (recessive) with bus biasing inactive nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open See Figure 6-1 and Figure 6-4 -0.2 0.2 V TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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5.8 Electrical Characteristics (continued)

Over recommended operating conditions with TJ = –40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICANH(OS) Short-circuit steady-state output current, dominant, CANH nSTB = VIO, TXD = 0 V -15 V ≤ V(CANH) ≤ 40 V See Figure 6-1 and Figure 6-8 –100 mA ICANL(OS) Short-circuit steady-state output current, dominant, CANL nSTB = VIO, TXD = 0 V -15 V ≤ V(CANL) ≤ 40 V See Figure 6-1 and Figure 6-8 100 mA IOS(REC) Short-circuit steady-state output current Bus biasing active Recessive nSTB = VIO, VBUS = CANH = CANL -27 V ≤ VBUS ≤ 42 V See Figure 6-1 and Figure 6-8 –3 3 mA RSE_ACT_REC Single ended SIC impedance (CANH to common mode bias and CANL to common mode bias) during active recessive drive phase

2 V ≤ VCANH,CANL ≤ VCC - 2 V if

–12 V ≤ VO(D) ≤ 12 V See Figure 6-13 37.5 66.5 Ω RDIFF_ACT_RE C Differential input resistance in active recessive drive phase (CANH to CANL)

2 V ≤ VCANH,CANL ≤ VCC - 2 V

See Figure 6-13 75 133 Ω CAN Receiver Characteristics VIT(DOM) Receiver dominant state input voltage range Bus biasing active nSTB = VIO, -12 V ≤ VCM ≤ 12 V See Figure 6-5 and Table 7-6 0.9 8 V VIT(REC) Receiver recessive state input voltage range Bus biasing active -3 0.5 V VHYS Hysteresis voltage for input threshold Bus biasing active nSTB = VIO See Figure 6-5 and Table 7-6 135 mV VDIFF(DOM) Receiver dominant state input voltage range Bus biasing inactive nSTB = 0 V, -12 V ≤ VCM ≤ 12 V See Figure 6-5 and Table 7-6 1.150 8 V VDIFF(REC) Receiver recessive state input voltage range Bus biasing inactive -3 0.4 V VCM Common mode range nSTB = VIO See Figure 6-5 and Table 7-6 –12 12 V IOFF(LKG) Power-off (unpowered) bus input leakage current VSUP = 0 V, CANH = CANL = 5 V 4.5 µA CI Input capacitance to ground (CANH or CANL) (1) TXD = VCC = VIO 40 pF CID Differential input capacitance (1) TXD = VCC = VIO 20 pF RDIFF_PAS_RE C Differential input resistance in passive recessive phase TXD = VCC = VIO = 5 V, nSTB = 5 V -12 V ≤ VCM ≤ 12 V 30 100 kΩ RSE_PAS_REC Single ended input resistance (CANH or CANL) in passive recessive phase 15 50 kΩ RIN(M) Input resistance matching: [1 – RIN(CANH) / RIN(CANL)] × 100% V(CANH) = V(CANL) = 5 V –3 3 % RCBF Valid differential load impedance range for bus fault circuitry RCM = RL, CL = open 45 70 Ω TXD Characteristics VIH High-level input voltage 0.7 VIO VIL Low-level input voltage 0.3 VIO IIH High-level input leakage current TXD = VIO = 5.5 V –2.5 1 µA IIL Low-level input leakage current TXD = 0 V, VIO = 5.5 V –137 –2.5 µA ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VSUP = VIO = 0 V –1 1 µA RPU Pull-up resistance to VIO 40 60 80 kΩ CI Input Capacitance VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V 5 pF RXD Characteristics VOH High-level output voltage IO = – 1.5mA, VIO =1.7V 0.8 VIO VOH High-level output voltage IO = –2 mA, VIO ≥ 2.5V 0.8 VIO VOL Low-level output voltage IO = 2 mA 0.2 VIO ILKG(OFF) Unpowered leakage current RXD = 5.5 V, VSUP = VIO = 0 V -1 1 µA www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCAN1473A-Q1

Over recommended operating conditions with TJ = –40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT nSTB Characteristics VIH High-level input voltage 0.7 VIO VIL Low-level input voltage 0.3 VIO IIH High-level input leakage current nSTB = VIO = 5.5 V 0.5 137 µA IIL Low-level input leakage current nSTB = 0 V, VIO = 5.5 V –1 1 µA ILKG(OFF) Unpowered leakage current nSTB = 5.5 V, VIO = 0 V –1 1 µA RPD Pull-down resistance to GND 40 60 80 kΩ nFAULT Characteristics VOH High-level output voltage IO = -2 mA 0.8 VIO VOL Low-level output voltage IO = 2 mA 0.2 VIO ILKG(OFF) Unpowered leakage current nFAULT = 5.5 V, VIO = 0 V –1 1 µA INH_MASK Characteristics VIH High-level input voltage 0.7 VIO VIL Low-level input voltage 0.3 VIO IIH High-level input leakage current INH_MASK = VCC = VIO = 5.5 V 0.5 137 µA IIL Low-level input leakage current INH_MASK = 0 V, VCC = VIO = 5.5 V -1 1 µA ILKG(OFF) Unpowered leakage current INH_MASK = 5.5 V, VCC = VIO = 0 V -1 1 µA RPD Pull-down resistance to GND (1) 40 60 80 kΩ EN Characteristics VIH High-level input voltage 0.7 VIO VIL Low-level input voltage 0.3 VIO IIH High-level input leakage current EN = VCC = VIO = 5.5 V 0.5 137 µA IIL Low-level input leakage current EN = 0 V, VCC = VIO = 5.5 V -1 1 µA ILKG(OFF) Unpowered leakage current EN = 5.5 V, VCC = VIO = 0 V -1 1 µA RPD Pull-down resistance to GND 40 60 80 kΩ WAKE Characteristics VIH High-level input voltage Sleep mode VSUP - 2 V VIL Low-level input voltage VSUP - 3.5 V IIH High-level input leakage current WAKE = VSUP – 1 V -3 µA IIL Low-level input leakage current WAKE = 1 V 3 µA INH Characteristics ΔVH High-level voltage drop from VSUP to INH (VSUP - VINH) IINH = –6 mA 0.5 1 V ILKG(INH) Sleep mode leakage current INH = 0 V –0.5 0.5 µA RPD Pull-down resistance Sleep mode 2.5 4 6 MΩ (1) Specified by design and verified using bench characterization

5.9 Timing Requirements

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Characteristics tPWRUP Time required for INH active after VSUP ≥ UVSUP(R) See Figure 6-12 500 µs tUV Undervoltage filter time VCC and VIO (1) VCC ≤ UVCC or VIO ≤ UVIO 100 350 ms tUV(RE-ENABLE) Re-enable time after undervoltage event (1) Time for device to return to normal operation from a UVCC or UVIO undervoltage event 200 µs Device Characteristics TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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5.9 Timing Requirements (continued)

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD) Recessive to dominant RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 6-6 100 190 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD) Dominant to recessive RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 6-6 110 190 ns tWK(TIMEOUT) Bus wake-up timeout value (1) 0.8 2 ms tWK(FILTER) Bus time to meet filtered bus requirements for wake-up request (1) 0.5 0.95 µs tSILENCE Timeout for bus inactivity (1) Timer is reset and restarted, when bus changes from dominant to recessive or from recessive to dominant 0.6 1.2 s tINACTIVE Standby mode hardware timer for power-up inactivity 3 4 5 min tBIAS Bus bias reaction time (1) Measured from the start of a dominant-recessive-dominant sequence (each phase 6 μs) until VSYM ≥ 0.1 nSTB = EN = 0 V, RL = 60 Ω, CSPLIT = 4.7 nF See Figure 6-9 and Figure 8-3 200 µs tCBF Bus fault-detection time 45 ≤ RCM ≤ 70 Ω CL = open 2.5 µs tWAKE_HT Hold time for which WAKE pin voltage is typically stable after the rising or falling edge on WAKE pin to recognize LWU 5 50 µs Mode Change Characteristics tINH_SLP_STB Time after WUP or LWU event until INH asserted (1) 100 µs tINH_MASK Hold time for which INH_MASK should be stable after the rising or falling edge to enable/disable INH_MASK function See Figure 6-10 and Figure 6-11 50 µs tMODE1 Mode change time from leaving the Sleep mode to entering Normal or Silent mode (1) Time measured from VCC and VIO crossing UV thresholds to entering normal or silent mode. 20 µs tMODE2 Mode change time between normal, silent and standby mode and from sleep to standby mode (1) Mode change time between normal, silent and standby mode and from sleep to standby mode 10 µs tGOTOSLEEP Minimum hold time for transition to sleep mode (1) EN = H and nSTB = L 20 50 µs (1) Specified by design and verified using bench characterization

5.10 Switching Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver Characteristics tprop(TxD- busdom) Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant) RL = 60Ω, CL = 100pF, RCM = open See Figure 6-4 80 ns tprop(TxD- busrec) Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive) 80 ns tsk(p) Pulse skew (|tprop(TxD-busdom) - tprop(TxD-busrec)|) RL = 60Ω, CL = 100pF, RCM = open See Figure 6-4 3 ns tR Differential output signal rise time 25 ns tF Differential output signal fall time 25 ns tTXDDTO Dominant timeout TXD = 0V, RL = 60Ω, CL = open See Figure 6-7 1.2 3.8 ms Receiver Characteristics tprop(busdom- RxD) Propagation delay time, bus dominant input to RxD low output CL(RXD) = 15pF See Figure 6-5 110 ns tprop(busrec- RxD) Propagation delay time, bus to recessive input to RXD high output 110 ns www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCAN1473A-Q1

5.10 Switching Characteristics (continued)

Over recommended operating conditions with TJ = -40°C to 150°C and VCC = 4.75V to 5.25V, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR Output signal rise time (RXD) See Figure 6-5 3 ns tF Output signal fall time (RXD) 3 ns tBUSDOM Dominant time out RL = 60Ω, CL = open See Figure 6-7 1.4 3.8 ms CAN FD Signal Improvement Characteristics tPAS_REC_STA RT Start time of passive recessive phase RL = 45Ω to 65Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF Measured from rising TXD edge with < 5ns slope at 50% threshold, to the end of the signal improvement phase; RDIFF_PAS_REC ≥ MIN RDIFF_ACT_REC; RSE_CANH/L ≥ MIN RSE_SIC_REC 365 530 ns tSIC_START Start time of active signal improvement phase RL = 45Ω to 65Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF Measured from rising TXD edge with < 5ns slope at 50% threshold to the start of active signal improvement phase 120 ns tSIC_END End time of active signal improvement phase RL = 45Ω to 65Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF Measured from rising TXD edge with < 5ns slope at 50% threshold to the end of active signal improvement phase 355 ns tΔBit(Bus) Transmitted bit width variation RL = 60Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF Bus recessive bit length variation relative to TXD bit length, see Figure 6-6 tΔBit(Bus) = tBit(Bus) - tBit(TxD) , tBit(TxD) ≥ 125ns –10 10 ns tΔBit(RxD) Received bit width variation RL = 60Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF RXD recessive bit length variation relative to TXD bit length, see Figure 6-6 tΔBit(RxD) = tBit(RxD) - tBit(TxD) , tBit(TxD) ≥ 125ns –30 20 ns tΔREC Receiver timing symmetry RL = 60Ω, CL1 = open, CL2 = 100pF, CL(RXD) = 15pF RXD recessive bit length variation relative to bus bit length, see Figure 6-6 tΔREC = tBit(RxD) - tBit(Bus) , tBit(TxD) ≥ 125ns –20 15 ns TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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5.11 Typical Characteristics

J u n c t i o n T e m p e r a t u r e (  C ) VOD(D)(V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 5 1 . 5 2 . 5 3 . 5 V C C = 4 . 5 V V C C = 5 V V C C = 5 . 5 V RL = 60Ω CL = Open RCM = Open VIO = 3.3V Figure 5-1. VOD(DOM) vs Temperature and VCC J u n c t i o n T e m p e r a t u r e (  C ) ICC Recessive (mA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 . 2 5 1 . 5 1 . 7 5 2 . 2 5 2 . 5 RL = 60Ω CL = Open RCM = Open VCC = 5V VIO = 3.3V Figure 5-2. ICC Recessive vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) ISUP_SLEEP(A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 1 5 2 0 2 5 3 0 3 5 V S U P = 4 . 5 V V S U P = 7 V V S U P = 1 2 V V S U P = 1 8 V V S U P = 2 8 V V S U P = 4 0 V RL = 60Ω CL = Open RCM = Open VCC = 5V VIO = 3.3V Figure 5-3. ISUP in Sleep Mode vs VSUP and Temperature J u n c t i o n T e m p e r a t u r e (  C ) Total Loop Delay, tPROP(LOOP1)(ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 9 0 9 5 1 0 0 1 0 5 1 1 0 1 1 5 1 2 0 1 2 5 1 3 0 1 3 5 1 4 0 1 4 5 1 5 0 V I O = 1 . 7 V V I O = 3 . 3 V V I O = 5 . 5 V RL = 60Ω CL = 100pF CL(RXD) = 15pF VCC = 5V VSUP = 12V Figure 5-4. Loop Propagation Delay vs VIO and Temperature www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCAN1473A-Q1

6 Parameter Measurement Information

2.5 V GND CANL CANH RXD Figure 6-1. Common-Mode Bias Unit and Receiver RL/2 CANH CANL TXD CL2 RXD nSTB RL/2CL1 CL(RXD) Figure 6-2. Test Circuit RL CANH CANL TXD CL Figure 6-3. Supply Test Circuit TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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0.9V 0.5V VOD VIH tTXDDTO VOD(D) Figure 6-7. TXD Dominant Time Out Test Circuit and Measurement CANH CANL TXD VBUS VBUS IOS VCANH, VCANL VBUS or 200 s IOS VCANH, VCANL Figure 6-8. Driver Short-Circuit Current Test and Measurement t > tWK_FILTER(MAX) t > tWK_FILTER(MAX) t > tWK_FILTER(MAX) VDIFF 2.0 V 1.15 V 0.4 V tBIAS VSYM 0.1 Figure 6-9. Bias Reaction Time Measurement TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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t > tINH_MASK VIH

0.7 VIO

INH_MASK 0 V Device in Silent Mode tINH_SLP_STB 1. nFAULT clears upon exiting silent mode Figure 6-10. INH Disable Timing Diagram t > tINH_MASK VIH

0.3 VIO

INH_MASK 0 V INH Disabled INH Enabled nFAULT1 INH tINH_SLP_STB Device in Silent Mode 1. nFAULT clears upon exiting silent mode Figure 6-11. INH Enable Timing Diagram www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCAN1473A-Q1

INH = H VSUP VSUP -1V tPWRUP UVSUP(R) TCAN1473 INH Figure 6-12. Power-Up Timing TXD RDIFF_ACT_REC(MAX) RSE_SIC_CANH/L(MAX) RDIFF_ACT_REC(MIN) RSE_SIC_CANH/L(MIN) 50% RSE-CANH/L (MIN) RDIFF_PAS_ REC (MIN) RSE_SIC_C ANH/L RDIFF_ACT _REC RDIFF_PAS_REC(MIN) RSE_CANH/L(MIN) tREC_START (MAX) tSIC_START (MAX) tSIC_END (MIN) R t Figure 6-13. SIC Timing and Impedance During the Active and Passive Recessive Phase TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The TCAN1473A-Q1 devices meet or exceed the specifications of the Signal Improvement Capability (SIC) specification of the ISO 11898-2:2024 Controller Area Network physical layer standard. The TCAN1473A-Q1 is data rate agnostic making the device backward compatible for supporting classic CAN applications while also supporting CAN FD networks up to 8 megabits per second (Mbps). The transceiver has three separate supply inputs, V SUP, VCC, and V IO. By using V IO, the TCAN1473A-Q1 can interface directly to a 1.8V, 2.5V, 3.3V, or 5V controller without the need for a level shifter. The TCAN1473A-Q1 allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present in the system via the INH output pin. This enables a low-current sleep state in which power is gated to all system components except for the TCAN1473A-Q1, which remains in a low-power state while monitoring the CAN bus. When a wake-up pattern is detected on the bus or when a local wake up is requested via the WAKE input, the device initiates node start-up by driving INH high. The INH pin behavior is adjusted using the INH_MASK feature. The TCAN1473A-Q1 includes many protection and diagnostic features including undervoltage detection, CAN bus fault detection, SWE timer, battery connection detection, thermal shutdown (TSD), driver dominant timeout (TXD DTO), and bus fault protection up to ±58V.

7.1.1 Signal Improvement

The TCAN1473A-Q1 includes the Signal Improvement Capability (SIC) that enhances the maximum data rate achievable in complex star topologies by minimizing signal ringing. Signal ringing is the result of reflections caused by impedance mismatch at various points in a complex CAN network. An example of a star network is shown Figure 7-1. ECU 5 ECU 6 ECU 3 ECU 1 (terminated) ECU 2 ECU 4 ECU 7ECU 8 (terminated) Figure 7-1. CAN Network: Star Topology Recessive-to-dominant signal edge is typically clean when driven by the transmitter. Transmitter output impedance of CAN transceiver is R ID(dom) and matches to the network characteristic impedance. For a regular CAN FD transceiver, dominant-to-recessive edge is when the driver output impedance goes to approximately 60kΩ and signal reflected back experiences impedance mismatch which causes ringing. The TCAN1473A-Q1 resolves this issue by TX-based Signal improvement capability (SIC). The TCAN1473A-Q1 continues to drive the bus recessive strongly for at least until t SIC_END to minimize the reflections and the recessive bit is clean at the sampling point. In the active recessive phase, transmitter output impedance is low (R DIFF_ACT_REC). After this phase, the device enters into a passive recessive phase where the driver goes into high impedance state. This www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCAN1473A-Q1

phenomenon is explained using Figure 7-2. For further information, please refer to the white paper on how SIC unlocks the real potential of CAN-FD transceivers. TXD RDIFF_ACT_REC(MAX) RSE_SIC_CANH/L(MAX) RDIFF_ACT_REC(MIN) RSE_SIC_CANH/L(MIN) 50% RSE-CANH/L (MIN) RDIFF_PAS_ REC (MIN) RSE_SIC_C ANH/L RDIFF_ACT _REC RDIFF_PAS_REC(MIN) RSE_CANH/L(MIN) tREC_START (MAX) tSIC_START (MAX) tSIC_END (MIN) R t Figure 7-2. TX-based Signal Improvement Capability

7.2 Functional Block Diagram

INH_MASK 1. A pull-down resistor of 4MΩ (typical) is activated on INH pin when the device is in Sleep mode. Figure 7-3. TCAN1473A-Q1 Functional Block Diagram TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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7.3 Feature Description

7.3.1 Supply Pins

The TCAN1473A-Q1 implements three independent supply inputs for regulating different portions of the device.

7.3.1.1 VSUP Pin

This pin is connected to the battery supply. Providing the supply to the internal regulators that support the digital core and the low power CAN receiver.

7.3.1.2 VCC Pin

This pin provides the 5V supply voltage for the CAN transceiver.

7.3.1.3 VIO Pin

This pin provides the digital I/O voltage to match the CAN FD controller I/O voltage. Supporting I/O voltages from 1.7V to 5.5V providing a wide range of controller support.

7.3.2 Digital Inputs and Outputs

7.3.2.1 TXD Pin

TXD is a logic-level input signal, referenced to V IO, from a CAN FD controller to the TCAN1473A-Q1. TXD is biased to the VIO level to force a recessive input in case the pin floats.

7.3.2.2 RXD Pin

RXD is a logic-level signal output, referenced to V IO, from the TCAN1473A-Q1 to a CAN FD controller. The RXD pin is driven to the VIO level as logic-high outputs once a valid VIO is present. When a power-on or wake-up event takes place, the RXD pin is pulled low. 7.3.2.3 nFAULT Pin nFAULT is a logic-level output signal, referenced to V IO, from the TCAN1473A-Q1 to a CAN FD controller. The nFAULT output is driven to the VIO level as logic-high output. The nFAULT output is used to transmit the TCAN1473A-Q1 status indicator flags to the CAN FD controller. Please see Table 7-1 for the specific fault scenarios that are indicated externally via the nFAULT pin. The TCAN1473A-Q1 puts the nFAULT pin in the high-impedance state in the Sleep mode to conserve power because there are no fault scenarios that are indicated externally in the Sleep mode.

7.3.2.4 EN Pin

EN is a logic-level input signal, referenced to V IO, from a CAN FD controller to the TCAN1473A-Q1. The EN input pin is for mode selection in conjunction with the nSTB pin. EN is internally pulled low to prevent excessive system power and false wake-up events. 7.3.2.5 nSTB Pin nSTB is a logic-level input signal, referenced to VIO, from a CAN FD controller to the TCAN1473A-Q1. The nSTB input pin is for mode selection in conjunction with the EN pin. nSTB is internally pulled low to prevent excessive system power and false wake-up events.

7.3.2.6 INH_MASK Pin

INH_MASK is a logic-level input signal, referenced to V IO, from a CAN FD controller to the TCAN1473A-Q1. The INH_MASK input pin can be used to disable and enable the INH function when in Silent mode. This feature can be used to control the power supply to any power-intensive system blocks to avoid powering up the system blocks from low-power mode due to spurious wake-up events. INH_MASK function must not be used if the INH is used to control the power supply to the transceiver or the controller behind the transceiver - using INH_MASK in such a scenario prevents the device from entering silent mode and enabling the INH function. See Figure 8-2 for an example application schematic for using INH_MASK function. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCAN1473A-Q1

INH_MASK has a pull-down resistor that forces the INH feature to the enable state upon a cold start. To activate INH_MASK, the transceiver must be in silent mode. Once in silent mode, the INH_MASK pin must be pulled high for t > t INH_MASK, disabling INH. The TCAN1473A-Q1 latches this value and retains the value through V CC and VIO power cycles and state transitions. The latched value is lost if the TCAN1473A-Q1 enters an undervoltage fault on V SUP. To enable INH function again, the transceiver must be in Silent mode, and the INH_MASK pin must be pulled low for t > t INH_MASK. See Figure 6-10 and Figure 6-11 for the procedure to use the INH_MASK feature. The TCAN1473A-Q1 reports a change in state of INH_MASK to the system controller by the driving nFAULT low while in silent mode. To use nFAULT = low as an acknowledgment for the change in state of INH_MASK, nFAULT must be high (that is, no pre-existing faults) before initiating the change in state of INH_MASK. A mode transition into normal, standby, go-to-sleep, or sleep mode clears the nFAULT pin.

7.3.3 GND

GND is the ground pin of the transceiver. GND must be connected to the PCB ground.

7.3.4 INH Pin

The INH pin is a high-voltage output used to control external regulators. These regulators are typically used to support the microprocessor and V IO pin. The INH function is on in all modes except for sleep mode. In sleep mode, the INH pin is turned off, going into a high-impedance state. This allows the node to be placed into the lowest power state while in sleep mode. A 100k Ω load can be added to the INH output for a fast transition time from the driven high state to the low state and to force the pin low when left floating. This terminal must be considered a high-voltage logic terminal, not a power output. The INH pin must be used to drive the EN terminal of the system’s power management device and must not be used as a switch for the power management supply. This terminal is not reverse-battery protected and thus must not be connected outside the system module. The INH function can be disabled/enabled using the INH_MASK pin in Silent mode. Refer to INH_MASK Pin for details.

7.3.5 WAKE Pin

The WAKE pin is a high-voltage reverse-blocked input used for the local wake-up (LWU) function. The WAKE pin is bi-directional edge-triggered and recognizes a local wake-up (LWU) on either a rising or falling edge of WAKE pin transition. The LWU function is explained further in the Local Wake-Up (LWU) via WAKE Input Terminal section.

7.3.6 CAN Bus Pins

These are the CAN high and CAN low, CANH and CANL, differential bus pins. These pins are internally connected to the CAN transceiver and the low-voltage wake receiver.

7.3.7 Faults

7.3.7.1 Internal and External Fault Indicators

The following device status indicator flags are implemented to allow for the MCU to determine the status of the device and the system. In addition to faults, the nFAULT terminal also signals wake-up requests and a “cold” power-up sequence on the VSUP battery terminal so the system can do any diagnostics or cold booting sequence necessary. The RXD terminal indicates wake-up request and the faults are multiplexed (ORed) to the nFAULT output. TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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Table 7-1. TCAN1473A-Q1 Transceiver Status Indicator EVENT FLAG NAME CAUSE INDICATORS(1) FLAG IS CLEARED COMMENT Power-up PWRON Power up on VSUP and any return of VSUP after it has been below UVSUP nFAULT = low upon entering silent mode from standby or sleep mode After a transition to normal mode A cold start condition generates a local wake-up WAKERQ, WAKESR and a PWRON flag. Wake-up Request WAKERQ (2) Wake-up event on CAN bus, state transition on WAKE pin, or initial power up nFAULT = RXD = low after wake-up upon entering standby mode After a transition to normal mode or VCC < UVCC(F) or VIO < UVIO(F) for t ≥ tUV Wake-up request can only be set from standby, go-to-sleep, or sleep mode. Resets timers for UVVCC or UVVIO. Wake-up Source Recognition(3) WAKESR Available upon entering normal mode(4) nFAULT = low indicates a local wake-up event from the WAKE pin nFAULT = high indicates a remote wake-up event from the CAN bus After four recessive-to- dominant edges on TXD in normal mode, leaving normal mode, or VCC < UVCC(F) or VIO < UVIO(F) for t ≥ tUV A cold start condition generates a local wake-up WAKERQ, WAKESR and a PWRON flag. INH_MASK Change INHMASK INH_MASK value changed nFAULT = low after entering silent mode A mode transition into normal, standby, go-to-sleep, or sleep modes To use nFAULT as the flag indicator, nFAULT must be high before initiating change in state of INH_MASK (meaning there must be no pre-existing faults) Undervoltage UVCC VCC < UVCC(F) Not externally indicated VCC > UVCC(R), or a wake-up request occurs UVIO VIO < UVIO(F) Not externally indicated VIO > UVIO(R), or a wake-up request occurs UVSUP VSUP < UVSUP(F) Not externally indicated VSUP > UVSUP(R) A VSUP undervoltage event generates a cold start condition once VSUP > UVSUP(R) CAN Bus Fault CBF See CAN Bus Fault nFAULT = low in normal mode only(5) Upon leaving normal mode, or if no CAN bus fault is detected for four consecutive dominant-to- recessive transitions of the TXD pin while in normal mode CAN bus fault must persist for four consecutive dominant- to-recessive transitions Local Faults TXDCLP TXD low when CAN active mode is entered nFAULT = low upon entering silent mode from normal mode RXD = low & TXD = high, TXD = high & a mode transition into normal, standby, go-to-sleep, or sleep modes CAN driver remains disabled until the TXDCLP is cleared. CAN receiver remains active during the TXDCLP fault TXDDTO TXD dominant time out, dominant (low) signal for t ≥ tTXDDTO CAN driver remains disabled until the TXDDTO is cleared. CAN receiver remains active during the TXDDTO fault TXDRXD TXD and RXD pins are shorted together for t ≥ tTXDDTO CAN driver remains disabled until the TXDRXD is cleared. CAN receiver remains active during the TXDRXD fault CANDOM CAN bus dominant fault, when dominant bus signal received for t ≥ tBUSDOM RXD = high, or a transition into normal, standby, go-to-sleep, or sleep modes CAN driver remains enabled during CANDOM fault TSD Thermal shutdown, TJ ≥ TSDR TJ < TSDF and RXD = low & TXD = high, or transition into normal, standby, go-to-sleep, or sleep modes CAN driver remains disabled until the TSD event is cleared (1) VIO and VSUP are present (2) Transitions to go-to-sleep mode is blocked until WAKERQ flag is cleared (3) Wake-up source recognition reflects the first wake up source. If additional wake-up events occur the source still indicates the original wake-up source (4) Indicator is only available in normal mode until the flag is cleared (5) CAN Bus failure flag is indicated after four dominant-to-recessive edges on TXD

7.3.7.1.1 Power-Up (PWRON Flag)

This is an internal and external flag that can be used to control the power-up sequence of the system. When a new battery connection to the transceiver is made the PWRON flag is set signifying a cold start condition. The TCAN1473A-Q1 treats any undervoltage conditions on the V SUP, VSUP < UV SUP(F), as a cold start. Therefore, when the V SUP > UV SUP(R) condition is met the TCAN1473A-Q1 sets the PWRON flag which can be used by the system to enter a routine that is only called upon in cold start situations. The PWRON flag is indicated by nFAULT driven low after entering silent mode from either standby mode or sleep mode. This flag is cleared after a transition to normal mode. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCAN1473A-Q1

Standby mode:1 INH = high in STB mode Silent mode2 nSTB = high EN = low Read nFAULT low = cold start high = wake-up request System preconditioning routine Yes No nFAULT = low? Go to normal mode: nSTB = high EN = high Read nFAULT 3 WAKESR flag low = local wake-up high = remote wake-up Normal mode Go to normal mode: nSTB = high EN = high

1 On entering Standby mode from power-up or Sleep mode

2 VCC and VIO are present

3 Optional

Figure 7-4. Distinguishing between PWRON and Wake Request by Entering Silent Mode

7.3.7.1.2 Wake-Up Request (WAKERQ Flag)

This is an internal and external flag that can be set in standby, go-to-sleep, or sleep mode. This flag is set when either a valid local wake-up (LWU) request occurs, or a valid remote wake request occurs, or on power up on VSUP. The setting of this flag clears the t UV timer for the UV CC or UVIO fault detection. This flag is cleared upon entering normal mode or during an undervoltage event on VCC or VIO.

7.3.7.1.3 Undervoltage Faults

The TCAN1473A-Q1 device implements undervoltage detection circuits on all supply terminals: V SUP, VCC, and VIO. The undervoltage flags are internal indicator flags and are not indicated on the nFAULT output pin. UVSUP is set when the voltage on V SUP drops below the undervoltage detection voltage threshold, UV SUP. The PWRON and WAKERQ flags are set once VSUP > UVSUP(R). UVCC is set when the voltage on VCC drops below the undervoltage detection voltage threshold, UVCC, for longer than the tUV undervoltage filter time. UVIO is set when the voltage on V IO drops below the undervoltage detection voltage threshold, UV IO, for longer than the tUV undervoltage filter time.

7.3.7.1.4 CAN Bus Fault (CBF Flag)

The TCAN1473A-Q1 device can detect the following six fault conditions and set the nFAULT pin low as an interrupt so that the controller can be notified and act if a CAN bus fault exists. These failures are detected while transmitting a dominant signal on the CAN bus. If one of these fault conditions persists for four consecutive dominant-to-recessive bit transitions, the nFAULT indicates a CAN bus failure flag in Normal mode by driving the nFAULT pin low. The CAN bus driver remains active. Table 7-2 shows what fault conditions can be detected by the TCAN1473A-Q1. Table 7-2. Bus Fault Pin State and Detection Table FAULT Condition

1 CANH Shorted to VBAT

2 CANH Shorted to VCC

3 CANH Shorted to GND

4 CANL Shorted to VBAT

5 CANL Shorted to VCC

6 CANL Shorted to GND

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Bus fault detection is a system level situation. If the fault is occurring at the ECU the general communication of the bus can be compromised. Until a diagnostic determination can be made the transceiver remains in CAN active mode during a CAN bus fault enabling the ECU to transmit data to the CAN bus and receive data from the CAN bus. For complete coverage of a node, a system level diagnostic step must be performed for each node and the information must be communicated back to a central point. While in normal mode, if no CAN bus fault is detected for four consecutive dominant-to-recessive transitions on the TXD pin then the CBF flag is cleared and nFAULT is driven high. The bus fault failure circuitry is able to detect bus faults for a range of differential resistance loads (RCBF) and for any time greater than tCBF.

7.3.7.1.5 TXD Clamped Low (TXDCLP Flag)

TXDCLP is an external flag that is set if the transceiver detects that the TXD is clamped low before entering CAN active mode. If a TXDCLP condition exists the nFAULT pin is driven low upon entering silent mode from normal mode and the CAN bus driver is disabled until the fault is cleared. The TXDCLP flag is cleared at power-up, when entering CAN active mode with TXD recessive, or when TXD is recessive while RXD is dominant, if no other local failures exist.

7.3.7.1.6 TXD Dominant State Timeout (TXDDTO Flag)

TXDDTO is an external flag that is set if the TXD pin is held dominant for t > t TXDDTO. If a TXD DTO condition exists, the nFAULT pin is driven low upon entering silent mode from normal mode. The TXDDTO flag is cleared on the next dominant-to-recessive transition on TXD or upon a transition into normal, standby, go-to-sleep, or sleep modes.

7.3.7.1.7 TXD Shorted to RXD Fault (TXDRXD Flag)

TXDRXD is an external flag that is set if the transceiver detects that the TXD and RXD lines have been shorted together for t ≥ tTXDDTO. If a TXDRXD condition exists the nFAULT pin is driven low upon entering silent mode from normal mode and the CAN bus driver is disabled until the TXDRXD fault is cleared. The TXDRXD flag is cleared on the next dominant-to-recessive transition with TXD high and RXD low or upon a transition into normal, standby, go-to-sleep, or sleep modes.

7.3.7.1.8 CAN Bus Dominant Fault (CANDOM Flag)

CANDOM is an external flag that is set if the CAN bus is stuck dominant state for t > t BUSDOM. If a CANDOM condition exists the nFAULT pin is driven low upon entering silent mode from normal mode. The CANDOM flag is cleared on the next dominant-to-recessive transition on RXD or upon a transition into normal, standby, go-to-sleep, or sleep modes.

7.3.8 Local Faults

Local faults are detected in both normal mode and silent mode, but are only indicated via the nFAULT pin when the TCAN1473A-Q1 transitions from normal mode to silent mode. All other mode transitions clear the local fault flag indicators.

7.3.8.1 TXD Clamped Low (TXDCLP)

If the TXD pin is clamped low prior to entering CAN active mode the CAN driver is disabled releasing the bus line to the recessive level. The CAN driver is activated again when entering normal mode with TXD recessive, when TXD is recessive while RXD is dominant, if no other local failures exist, or on power-up. During a TXDCLP fault the high-speed receiver remains active and the RXD output pin mirrors the CAN bus.

7.3.8.2 TXD Dominant Timeout (TXD DTO)

While the CAN driver is in active mode a TXD dominant state timeout circuit prevents the local node from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the timeout period, t > t TXDDTO. The TXD dominant state timeout circuit is triggered by a falling edge on the TXD pin. If no rising edge is seen before on TXD before t > tTXDDTO than the CAN driver is disabled releasing the bus lines to the recessive level. This keeps the bus free for communication between other nodes on the network. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCAN1473A-Q1

The CAN driver is activated again on the next dominant-to-recessive transition on the TXD pin. During a TXDDTO fault the high-speed receiver remains active and the RXD output pin mirrors the CAN bus. Normal CAN communication CAN Bus Signal TXD fault stuck dominant: example PCB failure or bad software Fault is repaired & transmission capability restored TXD (driver) %XVZRXOGEH³VWXFNGRPLQDQW´EORFNLQJFRPPXQLFDWLRQIRUWKHZKROHQHWZRUNEXW7;''72 prevents this and frees the bus for communication after the time tTXDDTO. tTXDDTO Communication from local node Communication from repaired node RXD (receiver) Communication from other bus node(s) Communication from repaired local node Communication from other bus node(s) tTXDDTO Driver disabled freeing bus for other nodes Figure 7-5. Timing Diagram for TXD DTO The minimum dominant TXD time allowed by the dominant state timeout circuit limits the minimum possible transmitted data rate of the transceiver. The CAN protocol allows a maximum of eleven successive dominant bits to be transmitted in the worst case, where five successive dominant bits are followed immediately by an error frame. The minimum transmitted data rate can be calculated using the minimum tTXDDTO time in Equation 1. Minimum Data Rate = 11 bits / tTXDDTO = 11 bits / 1.2ms = 9.2kbps (1)

7.3.8.3 Thermal Shutdown (TSD)

If the junction temperature of the TCAN1473A-Q1 exceeds the thermal shutdown threshold the device turns off the CAN driver circuits thus blocking the TXD to bus transmission path. The CAN bus terminals are biased to recessive level during a TSD fault and the receiver to RXD path remains operational. The TSD fault condition is cleared when the junction temperature, TJ, of the device drops below the thermal shutdown release temperature, TSDF, of the device. If the fault condition that caused the TSD fault is still present, the temperature can rise again and the device enters thermal shutdown again. Prolonged operation with TSD fault conditions can affect device reliability. The TSD circuit includes hysteresis to avoid any oscillation of the driver output. During the fault the TSD fault condition is indicated to the CAN FD controller using the nFAULT terminal.

7.3.8.4 Undervoltage Lockout (UVLO)

The supply terminals, V SUP, V IO and V CC, are monitored for undervoltage events. If an undervoltage event occurs, the TCAN1473A-Q1 enters a protected state where the bus pins present no load to the CAN bus. This protects the CAN bus and system from unwanted glitches and excessive current draw that can impact communication between other CAN nodes on the CAN bus. If an undervoltage event occurs on V SUP in any mode, the TCAN1473A-Q1 CAN transceiver enters the CAN off state. If an undervoltage event occurs on V CC,, the TCAN1473A-Q1 remains in normal or silent mode but the CAN transceiver changes to the CAN autonomous active state. During a UV CC event, RXD remains high as long as VIO is present and the wake-up circuitry is inactive. See Figure 7-12. If the undervoltage event persists longer than tUV, the TCAN1473A-Q1 transitions to sleep mode. TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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If an undervoltage event occurs on the VIO, the TCAN1473A-Q1 transitions to standby mode. If the undervoltage event persists longer than tUV, the TCAN1473A-Q1 transitions to sleep mode. Once an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically needs 200µs to transition to normal operation.

7.3.8.5 Unpowered Devices

The device is designed to be a passive or no load to the CAN bus if the device is unpowered. The CANH and CANL pins have low leakage currents when the device is unpowered, thus, presenting no load to the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in operation. The logic terminals also have low leakage currents when the device is unpowered, so the terminals do not load down other circuits which may remain powered.

7.3.8.6 Floating Terminals

The TCAN1473A-Q1 has internal pull-ups and pull-downs on critical pins to make sure a known operating behavior if the pins are left floating. See Table 7-3 for the pin fail-safe biasing protection description. Table 7-3. Pin Fail-safe Biasing PIN FAIL-SAFE PROTECTION VALUE COMMENT TXD Recessive level 60kΩ Weak pull-up to VIO EN Low-power mode Weak pull-down to GND nSTB Low-power mode INH_MASK INH enabled Weak pull-down to GND This internal bias must not be relied upon by design but rather a fail-safe option. Special care needs to be taken when the transceiver is used with a CAN FD controller that has open-drain outputs. The TCAN1473A-Q1 implements a weak internal pullup resistor on the TXD pin. The bit timing requirements for CAN FD data rates require special consideration and the pull-up strength must be considered carefully when using open-drain outputs. An adequate external pullup resistor must be used to make sure the TXD output of the CAN FD controller maintains proper bit timing input to the CAN device.

7.3.8.7 CAN Bus Short-Circuit Current Limiting

The TCAN1473A-Q1 has several protection features that limit the short-circuit current when a CAN bus line is shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state timeout which prevents permanently having the higher short-circuit current of a dominant state in case of a system fault. During CAN communication the bus switches between the dominant and recessive states, thus the short-circuit current can be viewed either as the current during each bus state or as an average current. The average short- circuit current must be used when considering system power for the termination resistors and common-mode choke. The percentage of time that the driver can be dominant is limited by the TXD dominant state timeout and the CAN protocol which has forced state changes and recessive bits such as bit stuffing, control fields, and interframe spacing. These makes sure there is a minimum recessive time on the bus even if the data field contains a high percentage of dominant bits. The short-circuit current of the bus depends on the ratio of recessive to dominant bits and the respective short-circuit currents. The average short-circuit current can be calculated using Equation 2. IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC] (2) Where:

• IOS(AVG) is the average short-circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCAN1473A-Q1

• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short-circuit current
• IOS(SS)_DOM is the dominant steady state short-circuit current The short-circuit current and possible fault cases of the network must be taken into consideration when sizing the power ratings of the termination resistance and other network components.

7.4 Device Functional Modes

The TCAN1473A-Q1 has six operating modes: normal, standby, silent, go-to-sleep, sleep, and off mode. Operating mode selection is controlled using the nSTB pin and EN pin in conjunction with supply conditions, temperature conditions, and wake events. EN = high and nSTB = high and VIO > UVIO Standby Mode CAN: Bus bias autonomous WAKE sources: WUP & LWU INH: VSUP level SWE timer active3 INH_MASK Input: Ignored (EN = low or WAKERQ set) and nSTB = low EN = low and nSTB = high and VIO > UVIO EN = low and nSTB = high EN = high and nSTB = low and WAKERQ Cleared Wake-Up Event: WUP or LWU EN = high and t > tGOTOSLEEP (EN = low and t < tGOTOSLEEP) or WUP or LWU Normal Mode CAN: Bus bias active INH: VSUP level SWE timer inactive3 INH_MASK Input: Ignored Silent Mode CAN: Bus bias active INH: VSUP level SWE timer inactive/active3 INH_MASK Input: Disable/Enables INH6 EN = high and nSTB = high EN = high and nSTB = low EN = high and nSTB = high EN = low and nSTB = high EN = high and nSTB = low and WAKERQ Cleared VSUP < UVVSUP(F) Power On Start Up Power Off CAN: High impedance INH: High impedance RXD: High impedance Go-To-Sleep Mode CAN: Bus bias autonomous WAKE sources: WUP & LWU INH: VSUP level SWE timer inactive INH_MASK Input: Ignored From any other mode VCC falls below UVCC or Vio falls below UVIO for t > tUV 2,4 SWE timer expires: t > tINACTIVE Sleep Mode CAN: Bus bias autonomous EN: x1 WAKE sources: WUP & LWU INH: High impedance nFAULT: High impedance SWE timer inactive INH_MASK Input: Ignored 4 or 5 4 or 5 (EN = low and nSTB = low) or VIO < UVIO 3,5 Figure 7-6. TCAN1473A-Q1 State Machine TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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1. The enable pin can be in a logical high or low state while in sleep mode but since the pin has an internal pull-down, the lowest possible power consumption occurs when the pin is left either floating or pulled low externally. 2. At power-up, the undervoltage timers for VCC and VIO are disabled, allowing for longer period for VCC and VIO supplies to power up (up to tINACTIVE). VCC or VIO need to be above UVCC(R) and UVIO(R) respectively to enable the respective tUV timers. The VCC undervoltage timer starts when VCC falls below UVCC(F), while VIO undervoltage timer starts when VIO falls below UVIO(F). When either of these timers exceed tUV, the device enters sleep mode. 3. The Sleep Wake Error (SWE) timer starts as soon as the device enters Standby mode. The timer halts and resets as soon as the device enters Normal mode. If the device enters Silent mode from Standby mode, the SWE timer does not halt and the device needs to be transitioned to Normal mode before the SWE timer expires. If the device enters Silent mode from Normal mode, the SWE timer is not active in Silent mode. 4. When the Sleep mode is entered from Go-To-Sleep Mode or from a UVCC or UVIO event, a low-to-high transition on nSTB is required to move the device into Normal or Silent mode. If EN is high during the rising edge on nSTB, the device moves to Normal mode. If EN is low during the rising edge on nSTB, the device moves to Silent mode. VIO must be above UVIO(R) to leave Sleep mode using the EN and nSTB signals. 5. When Sleep mode is entered due to an SWE timer timeout (>tINACTIVE), there is an extra requirement to exit Sleep mode and transition into Normal or Silent mode directly using the EN and nSTB signals. To move to Normal mode, the nSTB pin must be high and a low-to-high transition must occur on EN. To move to Silent mode, the nSTB pin must be high and a high-to-low transition must occur on EN. If the device entered Sleep mode while the nSTB is already high, there must be a transition on the EN pin while nSTB is low prior to the sequence described above. See Figure 7-7 for more information. VIO must be above UVIO(R) to leave Sleep mode by using the EN and nSTB signals. nSTB EN NormalSleep nSTB EN SilentSleep Sleep to Normal Sleep to Silent >tMODE1(max)1 >tMODE1(max)1 1. nSTB must remain low for a minimum of tMODE1 after the edge on EN. Once this tMODE1 has elapsed, nSTB can be driven high. The following edge on EN causes the device to exit Sleep mode. The final edge on EN does not have any minimum delay from the rising edge of nSTB. The enable pin can be in a logical high or low state while in sleep mode, but since the pin has an internal pull-down, the lowest possible power consumption occurs when the pin is left either floating or pulled low externally. Figure 7-7. TCAN1473A-Q1 Transitioning from Sleep Mode to Normal or Silent Mode if Sleep Mode is Entered Due to SWE Timer Timeout Table 7-4. TCAN1473A-Q1 Mode Overview MODE VCC and VIO VSUP EN nSTB WAKERQ FLAG DRIVER RECEIVER RXD INH Normal > UVCC and > UVIO > UVSUP High High X Enabled Enabled Mirrors bus state On Silent > UVCC and > UVIO > UVSUP Low High X Disabled Enabled Mirrors bus state On Standby > UVCC and > UVIO > UVSUP High Low Set Disabled Low power bus monitor enabled Low signals wake-up On > UVCC and > UVIO > UVSUP Low Low X Disabled Low power bus monitor enabled Low signals wake-up On > UVCC and < UVIO > UVSUP Low Low X Disabled Low power bus monitor enabled High impedance On Go-to-sleep(1) > UVCC and > UVIO > UVSUP High Low Cleared Disabled Low power bus monitor enabled High or high impedance (no VIO) On(2) www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCAN1473A-Q1

Table 7-4. TCAN1473A-Q1 Mode Overview (continued) MODE VCC and VIO VSUP EN nSTB WAKERQ FLAG DRIVER RECEIVER RXD INH Sleep(3) > UVCC and > UVIO > UVSUP High Low Cleared Disabled Low power bus monitor enabled High or high impedance (no VIO) High Impedance < UVCC or <UVIO > UVSUP X X X Disabled Low power bus monitor enabled High or high impedance (no VIO) High impedance Protected X < UVSUP X X X Disabled Disabled High impedance High impedance (1) Go-to-sleep: Transitional mode for EN = H, nSTB = L until tGOTOSLEEP timer has expired. (2) The INH pin transitions to high impedance after the tGOTOSLEEP timer has expired. (3) Mode change from go-to-sleep mode to sleep mode once tGOTOSLEEP timer has expired.

7.4.1 Operating Mode Description

7.4.1.1 Normal Mode

This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD. Entering normal mode clears both the WAKERQ and the PWRON flags. The SWE timer halts and resets upon entering normal mode.

7.4.1.2 Silent Mode

Silent mode is commonly referred to as listen only and receive only mode. In this mode, the CAN driver is disabled but the receiver is fully operational and CAN communication is unidirectional into the device. The receiver is translating the differential signal from CANH and CANL to a digital output on the RXD terminal. In silent mode, PWRON and Local Failure flags are indicated on the nFAULT pin. If the device enters silent mode from standby mode, the SWE timer does not halt and the device needs to be transitioned to normal mode before the SWE timer expires. If the SWE timer expires in silent mode, the device is transitioned to sleep mode.

7.4.1.3 Standby Mode

Standby mode is a low-power mode where the driver and receiver are disabled, reducing current consumption. However, this is not the lowest power mode of the device since the INH terminal is on, allowing the rest of the system to resume normal operation. During standby mode, a wake-up request ( WAKERQ) is indicated by the RXD terminal being low. The wake-up source is identified via the nFAULT pin after the device is returned to normal mode. In standby mode, a fail-safe timer called Sleep Wake Error (SWE) timer is enabled. The timer adds an additional layer of protection by requiring the system controller to configure the transceiver to normal mode before expiring. This feature forces the TCAN1473A-Q1 to transition to the lowest power mode, sleep mode, after t INACTIVE if the processor does not come up properly and fails to transition the device to Normal mode.

7.4.1.4 Go-To-Sleep Mode

Go-to-sleep mode is the transitional mode of the device from any state to sleep. In this state, the driver and receiver are disabled, reducing the current consumption. The INH pin is active to supply an enable to the V IO controller which allows the rest of the system to operate normally. If the device is held in this state for t ≥ tGOTOSLEEP, the device transitions to sleep mode and the INH turns off transitioning to the high impedance state. If any wake-up events persist, the TCAN1473A-Q1 remains in standby mode until the device is switched into normal mode to clear the pending wake-up events.

7.4.1.5 Sleep Mode

Sleep mode is the lowest power mode of the TCAN1473A-Q1. In sleep mode, the CAN transmitter and the main receiver are switched off and the transceiver cannot send or receive data. The low power receiver is able to monitor the bus for any activity that validates the wake-up pattern (WUP) requirements, and the WAKE TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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monitoring circuit monitors for state changes on the WAKE terminal for a local wake-up (LWU) event. I SUP current is reduced to its minimum level when the CAN transceiver is in CAN autonomous inactive state. The INH pin is switched off in sleep mode causing any system power supplies controlled by INH to be switched off thus reducing system power consumption. Sleep mode is exited:

• If a valid wake-up pattern (WUP) is received via the CAN bus pins
• On a local WAKE (LWU) event
• On a low-to-high transition of the nSTB pin When the Sleep mode is entered due to an SWE timer timeout (>t INACTIVE), there is an extra requirement to enter Normal or Silent mode directly (without entering Standby mode via LWU or WUP) using the EN and nSTB signals. To move to the Normal mode, the nSTB pin must be high and a low-to-high transition must occur on EN. To move to the Silent mode, the nSTB pin must be high and a high-to-low transition must occur on EN. If the device entered the Sleep mode while the nSTB was already high, there must be a transition on the EN pin while nSTB is low prior to the sequence described above. See Figure 7-7 for more information. V IO must be above UVIO(R) to leave the Sleep mode using the EN and nSTB signals.

7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)

The TCAN1473A-Q1 family implements a low-power wake receiver in the standby and sleep mode that uses the multiple filtered dominant wake-up pattern (WUP) defined in the ISO11898-2:2024 standard. The WUP is based upon ISO 11898-2, consisting of three parts: a filtered dominant bus, then a filtered recessive bus, followed by a second filtered dominant bus. The first filtered dominant initiates the WUP and the bus monitor is now waiting on a filtered recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received, the bus monitor is now waiting on a filtered dominant, and other bus traffic does not reset the bus monitor. Immediately upon receiving of the second filtered dominant, the bus monitor recognizes the WUP. Once the bus monitor recognizes the WUP, the device drives the RXD terminal low. If a valid V IO is present, the controller is signaled for a wake-up request. If a valid V IO is not present when the wake-up pattern is received, the transceiver drives the RXD output pin low once VIO > UVIOR. For a dominant or recessive to be considered filtered, the bus must be in that state for more than t WK(FILTER) time. Due to variability in the t WK(FILTER), the following scenarios are applicable. Bus state times less than the tWK(FILTER) minimum are never detected as part of a WUP, and no wake request is generated. Bus state times between tWK(FILTER) minimum and t WK(FILTER) maximum can be detected as part of a WUP and a wake request can be generated. Bus state times more than t WK(FILTER) maximum is always detected as part of a WUP, and a wake request is always generated. See Wake-Up Pattern (WUP) for TCAN1473AC-Q1 for the timing diagram of the WUP. The pattern and t WK(FILTER) time used for the WUP and wake request prevents noise and bus stuck dominant faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request. The ISO 11898-2:2024 standard has defined wakeup filter time to enable 1Mbps arbitration. For an additional layer of robustness and to prevent false wake-ups, the transceiver implements the t WK(TIMEOUT) timer. For a remote wake-up event to successfully occur, the entire wake-up pattern must be received within the timeout value. If the full wake-up pattern is not received before the t WK(TIMEOUT) expires then the internal logic is reset and the transceiver remains in the current mode without waking up. The full pattern must then be transmitted again within the tWK(TIMEOUT) window. See Wake-Up Pattern (WUP) for TCAN1473AC-Q1 . A recessive bus of at least t WK(FILTER) must separate the next WUP pattern if the CAN bus is dominant when the tWK(TIMEOUT) expires. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCAN1473A-Q1

•WWK_FILTER •WWK_FILTER •WWK_FILTER Bus Filtered Dominant Filtered Dominant Filtered Recessive Wake-Up Pattern (WUP) received in t < tWK_TIMEOUT Wake Request Waiting for Filtered Recessive Waiting for Filtered Dominant Mode Sleep Mode Standby Mode WUP Detect * tINH_SLP_STB *The RXD pin is only driven once VIO is present. Figure 7-8. Wake-Up Pattern (WUP) for TCAN1473AC-Q1

7.4.1.5.2 Local Wake-Up (LWU) Using WAKE Input Terminal

The WAKE terminal is a bi-directional high-voltage reverse-battery protected input which can be used for local wake-up (LWU) requests using a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low transition since the terminal has bi-directional input thresholds. The WAKE pin can be used with a switch to V SUP or to ground. Unused terminals must be pulled to V SUP or ground to avoid unwanted parasitic wake-up events. Figure 7-9. WAKE Circuit Example Figure 7-9 shows two possible configurations for the WAKE pin, a low-side and high-side switch configuration. The objective of the series resistor, R SERIES, is to protect the WAKE input of the device from over current conditions that can occur in the event of a ground shift or ground loss. The minimum value of R SERIES can be calculated using the maximum supply voltage, V SUPMAX, and the maximum allowable current of the WAKE pin, IIO(WAKE). RSERIES is calculated using: RSERIES = VSUPMAX / IIO(WAKE) (3) TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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With absolute maximum voltage, V SUPMAX, of 45V and maximum allowable I IO(WAKE) of 3mA, the minimum required RSERIES value is 15kΩ. The RBIAS resistor is used to set the static voltage level of the WAKE input when the switch is released. When the switch is in use in a high-side switch configuration, the RBIAS resistor in combination with the RSERIES resistor sets the WAKE pin voltage above the V IH threshold. The maximum value of R BIAS can be calculated using the maximum supply voltage, V SUPMAX, the maximum WAKE threshold voltage V IH, the maximum WAKE input current IIH and the series resistor value RSERIES. RBIAS is calculated using: RBIAS < ((VSUPMAX - VIH) / IIH) - RSERIES (4) With V SUPMAX of 45V, V IH of 44V at I IH of 3µA, the R BIAS resistor value must be less than 330k Ω. The recommendation is to use R Series less than 50k Ω to provide better margin for the WAKE pin voltage to rise above VIH when the switch is released. The LWU circuitry is active in sleep mode. The WAKE circuitry is switched off in normal mode. INH t tWAKE_HT no wake-up Wake WAKE threshold not crossed Mode Sleep Mode Standby Mode LWU Request RXD t > tWAKE_HT wake-up * RXD is driven with valid VIO tINH_SLP_STB Figure 7-10. LWU Request Rising Edge www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCAN1473A-Q1

Mode Sleep Mode Standby Mode LWU Request RXD t tWAKE_HT no wake-up WAKE threshold not crossed t > tWAKE_HT wake-up * RXD is driven with valid VIO tINH_SLP_STB Figure 7-11. LWU Request Falling Edge

7.4.2 CAN Transceiver

7.4.2.1 CAN Transceiver Operation

The TCAN1473A-Q1 supports the ISO 11898-2:2016 CAN physical layer standard autonomous bus biasing scheme. Autonomous bus biasing enables the transceiver to switch between CAN active, CAN autonomous active, and CAN autonomous inactive which helps to reduce RF emissions.

7.4.2.1.1 CAN Transceiver Modes

The TCAN1473A-Q1 CAN transceiver has four modes of operation; CAN off, CAN autonomous active, CAN autonomous inactive and CAN active. TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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CAN Transmitter: off CAN Receiver: off RXD: High impedance CANH and CANL: High impedance CAN wake-up or ((normal or silent) and (VCC < UVCC or VIO < UVIO)) t > tSILENCE and (standby or go-to-sleep or sleep) CAN Autonomous: Inactive CAN Transmitter: off CAN Receiver: off RXD: wake-up/high CANH and CANL: bias to GND CAN Autonomous: Active CAN Transmitter: off CAN Receiver: off RXD: low signals wake-up1 CANH and CANL: bias to 2.5 V from VSUP VSUP > UVSUP(R) t > t SILENCE and (standby or sleep or go-to- sleep) (normal or silent) and V CC > UV CC and V IO > UV IO (t < t SILENCE and (standby or go-to-sleep or sleep)) or V CC UV CC or V IO < UV IO CAN Active CAN Transmitter: on2 CAN Receiver: on RXD: Mirrors CAN bus CANH & CANL: VCC/2 (~2.5 V) (normal or silent) and V CC > UV CC and V IO > UV IO From any mode VSUP < UVSUP(F) 1. Wake-up is inactive in normal or silent mode. 2. CAN transmitter is off in silent mode. Figure 7-12. TCAN1473A-Q1 CAN Transceiver State Machine In CAN off mode, the CAN transceiver is switched off and the CAN bus lines are truly floating. In this mode, the device presents no load to the CAN bus while preventing reverse currents from flowing into the device if the battery or ground connection is lost. The CAN off state is entered if:

• VSUP < UVSUPF The CAN transceiver switches between the CAN off state and CAN autonomous inactive mode if:
• VSUP > UVSUPR When the CAN transceiver is in standby, go-to-sleep or sleep mode, the bias circuit can be in either the CAN autonomous inactive or CAN autonomous active state. In the autonomous inactive state, the CAN pins are biased to GND. When a remote wake-up (WUP) event occurs, the CAN bus is biased to 2.5V and the CAN transceiver enters the CAN autonomous active state. If the controller does not transition the transceiver into normal mode before the tSILENCE timer expires, the CAN transceiver enters the CAN autonomous inactive state. The CAN transceiver switches to the CAN autonomous mode if any of the following conditions are met:
• The operating mode changes from CAN off mode to CAN autonomous inactive
• The operating mode changes from normal or silent mode to standby, go-to-sleep, or sleep mode: – If the bus is inactive for t < tSILENCE before the mode change, the transceiver enters autonomous active state – If the bus is inactive for t > tSILENCE before the mode change, the transceiver enters autonomous inactive state
• VCC < UVCC(F)
• VIO < UVIO(F) The CAN transceiver switches from the CAN autonomous inactive mode to the CAN autonomous active mode if:
• A remote wake-up event occurs
• The transceiver transitions to normal or silent mode and VCC < UVCC(F) or VIO < UVIO(F) www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TCAN1473A-Q1

The CAN transceiver switches from the CAN autonomous active mode to the CAN autonomous inactive mode if:

• The transceiver is in standby, go-to-sleep, or sleep mode and t > tSILENCE When the transceiver is in normal or silent mode, the CAN transceiver is in active mode. In normal mode, the CAN driver and receiver are fully operational and CAN communication is bi-directional. In silent mode, the CAN driver is off but the CAN receiver is fully operational. The CAN bias voltage in CAN active mode is derived from VCC and is held at VCC/2 The CAN transceiver switches from the CAN autonomous inactive or CAN autonomous active modes to the CAN active mode if:
• The transceiver transitions to normal mode and VCC > UVCC(R), VIO > UVIO(R) The CAN transceiver blocks the transmitter after entering CAN active mode if the TXD pin is asserted low before leaving standby mode. This prevents disruptions to CAN bus in the event that the TXD pin is stuck low (TXDCLP). The CAN transceiver switches from the CAN active mode to the CAN autonomous inactive mode if:
• The transceiver switches to standby, go-to-sleep, or sleep modes and t > tSILENCE The CAN transceiver switches from the CAN active mode to the CAN autonomous active mode if:
• The transceiver switches to standby, go-to-sleep, or sleep modes and t < tSILENCE
• VCC < UVCC(F)
• VIO < UVIO(F)

7.4.2.1.2 Driver and Receiver Function Tables

Table 7-5. Driver Function Table DEVICE MODE TXD INPUTS(1) BUS OUTPUTS DRIVEN BUS STATE(2) CANH CANL Normal Low High Low Dominant High or Open High impedance High impedance VCC/2 Silent x High impedance High impedance VCC/2 Standby x High impedance High impedance Autonomous biasing Sleep x High impedance High impedance Autonomous biasing (1) x = irrelevant (2) For bus states and typical bus voltages see Bus States. Table 7-6. Receiver Function Table DEVICE MODE CAN DIFFERENTIAL INPUTS VID = VCANH – VCANL BUS STATE RXD TERMINAL Normal / Silent VID ≥ 0.9V Dominant Low 0.5V < VID < 0.9V Indeterminate Indeterminate VID ≤ 0.5V Recessive High Open (VID ≈ 0V) Open High Standby VID ≥ 1.15V Dominant High Low if wake-up event persists 0.4V < VID < 1.15V Indeterminate VID ≤ 0.4 Recessive Open (VID ≈ 0V) Open TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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Table 7-6. Receiver Function Table (continued) DEVICE MODE CAN DIFFERENTIAL INPUTS VID = VCANH – VCANL BUS STATE RXD TERMINAL Sleep / Go-to- sleep(1) VID ≥ 1.15V Dominant High Tri-state if VIO or VSUP are not present 0.4V < VID < 1.15V Indeterminate VID ≤ 0.4V Recessive Open (VID ≈ 0V) Open (1) Low power wake-up receiver is active

7.4.2.1.3 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-13. A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to one half of the CAN transceiver supply voltage via the high resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins. A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes can be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the CAN bus is greater than the differential voltage of a single CAN driver. The TCAN1473A-Q1 CAN transceiver implements low-power standby and sleep modes which enable a third bus state where, if the CAN bus is inactive for t > tSILENCE, the bus pins are biased to ground using the high-resistance internal resistors of the receiver. Recessive Dominant Recessive Time, t Typical Bus Voltage Normal or Silent or all other Modes with t < tSILENCE CANL CANH VDIFF VDIFF Standby, Go-to-sleep or Sleep Mode t > tSILENCE Figure 7-13. Bus States www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TCAN1473A-Q1

8 Application Information Disclaimer

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TCAN1473A-Q1 transceiver is typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. These types of applications typically also include power management technology that allows for power to be gated to the application using an enable (EN) or inhibit (INH) pin. A single 5V regulator can be used to drive both V CC and VIO, or independent 5V and 3.3V regulators can be used to drive VCC and VIO separately as shown in Figure 8-1. The bus termination is shown for illustrative purposes. The TCAN1473A-Q1 features an INH_MASK feature. The INH_MASK input pin can be used to disable and enable the INH function as long as the INH is not controlling the power supply to the transceiver or the controller behind the transceiver. This feature can be used to control the power supply to any power-intensive system blocks to avoid powering up the system blocks from low-power mode due to spurious wake-up events which saves power. See Figure 8-2 for an example application schematic.

8.1.1 Typical Application

Optional: Terminating Node Optional: Filtering, Transient and ESD VIN VIO VBAT 3 k EN CANH TXD RXD VIO WAKEVSUP CANL EN nSTB 100 nF VCC 100 nF CAN FD Controller 7 9 10 INH_MASK (leave floating or connect to GND) VREG Figure 8-1. Typical Application (Not Using INH_MASK feature) TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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Optional: Terminating Node Optional: Filtering, Transient and ESD VIN VIO VBAT 3 k EN CANH TXD RXD VIO WAKEVSUP CANL EN nSTB 100 nF VCC 100 nF CAN FD Controller 910

5 V VOUT

INH_MASK 11 VIN VOUT EN VIN VDD VREG VREG Power-intensive system block Figure 8-2. Typical Application (Using INH_MASK feature)

8.1.2 Design Requirements

8.1.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application can have a maximum bus length of 40 meters and maximum stub length of 0.3m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1473A-Q1. Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO11898-2:2016 standard. The organizations made system level trade off decisions for data rate, cable length, and parasitic loading of the bus. Examples of these CAN systems level specifications are ARINC825, CANopen, DeviceNet, SAEJ2284, SAEJ1939, and NMEA200. A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the differential output driver is specified with a bus load that can range from 50 Ω to 65Ω where the differential output must be greater than 1.5V. The TCAN1473A-Q1 is specified to meet the 1.5V requirement down to 50 Ω and is specified to meet 1.4V differential output at 45 Ω bus load. The differential input resistance, R ID, of the TCAN1473A-Q1 is a minimum of 50k Ω. If 100 TCAN1473A-Q1 transceivers are in parallel on a bus, this is equivalent to a 500 Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TCAN1473A-Q1

54Ω. Therefore, the TCAN1473A-Q1 theoretically supports over 100 transceivers on a single bus segment. However, for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is often lower. Bus length can also be extended beyond 40 meters by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate. This flexibility in CAN network design is one of the key strengths allowing for these system level network extensions and additional standards to build on the original ISO11898-2 CAN standard. However, when using this flexibility, the CAN network system designer must take the responsibility of good network design for a robust network operation.

8.1.3 Detailed Design Procedure

8.1.3.1 CAN Termination

Termination can be a single 120 Ω resistor at each end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common-mode voltage of the bus is desired then split termination can be used, see Figure 8-3 . Split termination improves the electromagnetic emissions behavior of the network by filtering higher-frequency common-mode noise that can be present on the differential signal lines. Standard Termination Split Termination CSPLIT TCAN Transceiver CANL CANH TCAN Transceiver CANL CANH RTERM/2 RTERM RTERM/2 Figure 8-3. CAN Bus Termination Concepts

8.1.4 Application Curves

V C C ( V ) ICCDominant (mA) 1 0 2 0 3 0 4 0 5 0 RL = 60Ω CL = Open Temperature = 25°C VIO = 3.3V VSUP = 12V Figure 8-4. Current Consumption (ICC(D)) in Dominant Mode vs VCC Supply TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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8.2 Power Supply Recommendations

The TCAN1473A-Q1 is designed to operate off of three supply rails; V SUP, VCC, and VIO. VSUP is a high-voltage supply pin designed to connect to the V BAT rail, VCC is a low-voltage supply pin with an input voltage range from 4.5V to 5.5V that supports the CAN transceiver and V IO is a low-voltage supply pin with an input voltage range from 1.7V to 5.5V that provides the I/O voltage to match the system controller. For a reliable operation, a 100nF decoupling capacitor must be placed as close to the supply pins as possible. This helps to reduce supply voltage ripple present on the output of switched-mode power supplies, and also helps to compensate for the resistance and inductance of the PCB power planes.

8.3 Layout

Robust and reliable CAN node design can require special layout techniques depending on the application and automotive design requirements. Since transient disturbances have high frequency content and a wide bandwidth, high-frequency layout techniques must be applied during PCB design.

8.3.1 Layout Guidelines

The layout example provides information on components around the device. Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise from propagating onto the board. Transient voltage suppression (TVS) device can be added for extra protection, shown as D1. The production solution can be either a bi-directional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C6 and C7. A series common-mode choke (CMC) is placed on the CANH and CANL lines between the device and connector J1. Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device. Use supply and ground planes to provide low inductance. Note that high-frequency currents follow the path of least impedance and not the path of least resistance. Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.

• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver, examples are C1 on VCC, C2 on VIO , and C3 and C4 on the VSUP supply.
• VIO pin of the transceiver is connected to the microcontroller IO supply voltage 'µC V'.
• Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R3 and R4, with the center or split tap of the termination connected to ground via capacitor C5. Split termination provides common-mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, additional care must be taken to make sure the terminating node is not removed from the bus thus also removing the termination.
• INH, pin 7, can have a 100kΩ resistor (R1) to ground.
• WAKE, pin 9, can recognize either a rising or a falling edge of a wake signal and is usually connected to an external switch. It should be configured as shown with C8 which is a 22nF capacitor to GND where R5 is 33kΩ and R6 is 3kΩ. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TCAN1473A-Q1

8.3.2 Layout Example

µC V EN EN GND VSUP CANH CANL C3 C4 nSTB GND Choke VSUP nSTB WAKE INH_MASK nFAULT GND GND Figure 8-5. Example Layout TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 www.ti.com

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9 Device and Documentation Support

9.1 Documentation Support

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (July 2024) to Revision A (October 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TCAN1473A-Q1 SLLSFV7A – JULY 2024 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TCAN1473A-Q1

www.ti.com 30-Dec-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTCAN1473ADMTRQ1 Active Preproduction VSON (DMT) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 PTCAN1473ADMTRQ1.A Active Preproduction VSON (DMT) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 PTCAN1473ADRQ1 Active Preproduction SOIC (D) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 PTCAN1473ADRQ1.A Active Preproduction SOIC (D) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 PTCAN1473ADYYRQ1 Active Preproduction SOT-23-THIN (DYY) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 PTCAN1473ADYYRQ1.A Active Preproduction SOT-23-THIN (DYY) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 150 TCAN1473ACDYYRQ1 Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 150 TCAN1473AC (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 30-Dec-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TCAN1473ACDYYRQ1 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCAN1473ACDYYRQ1 SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 Pack Materials-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

0.1 C A B

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 0.9 mm max heightDMT 14 PLASTIC SMALL OUTLINE - NO LEAD3 x 4.5, 0.65 mm pitch 4225088/A

www.ti.com PACKAGE OUTLINE C 14X 0.35 0.25 4.2 0.1 14X 0.45 0.35 3.9 1.6 0.1 12X 0.65 1.0 0.80.05 0.00 B 3.1 2.9 A 4.6 4.4 (0.2) TYP

0.1 MIN

(0.13) (0.19) TYP VSON - 1 mm max heightDMT0014B PLASTIC SMALL OUTLINE - NO LEAD 4225087/B 01/2021 PIN 1 INDEX AREA SEATING PLANE 0.08 C 7 8 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM15 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.200 SCALE 30.000 SECTION A-A SECTION A-A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP 14X (0.3) (4.2) (2.8) 12X (0.65) (1.6) ( 0.2) VIA TYP 14X (0.6) (0.69) TYP (0.55) TYP (1.85) VSON - 1 mm max heightDMT0014B PLASTIC SMALL OUTLINE - NO LEAD 4225087/B 01/2021 SYMM 7 8 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.3) 14X (0.6) (1.47) (1.18) (2.8) (R0.05) TYP 12X (0.65) (1.38) VSON - 1 mm max heightDMT0014B PLASTIC SMALL OUTLINE - NO LEAD 4225087/B 01/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 15 77.4% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 7 8 SYMM TYP METAL

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