Logic IC

PTCAN1472DRQ1

Texas Instruments

TCAN1472-Q1 Automotive Fault-Protected CAN FD Transceiver with Signal Improvement Capability (SIC) and Standby Mode JUNE 2024

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TCAN1472-Q1 Automotive Fault-Protected CAN FD Transceiver with Signal Improvement Capability (SIC) and Standby Mode

1 Features

AEC Q100: Qualified for automotive applications
Functional Safety-Capable
Meets the requirements of ISO 11898-2:2024 standard including CAN SIC specifications of Annex A
Classical CAN and CAN FD up to 8Mbps – Actively improves the bus signal by reducing ringing effects in complex topologies – Backward compatible for use in classic CAN networks
VIO level shifting supports: 1.7V to 5.5V
Operating Modes – Normal mode – Low-power standby mode supporting remote wake-up request
Passive behavior when unpowered – Bus and logic terminals are high impedance (no load to operating bus or application) – Hot plug capable: power up or down glitch free operation on bus and RXD output – Defined device behavior with floating logic pins and in undervoltage supply conditions
Protection features – IEC ESD protection on bus pins – ±58V CAN bus fault tolerant – Undervoltage protection on VCC and VIO (V variants only) supply terminals – TXD dominant state timeout (TXD DTO) – Thermal shutdown protection (TSD)
Available in SOIC (8), small footprint SOT-23 (8) and leadless, VSON (8) package with wettable flanks for improved automated optical inspection (AOI) capability

2 Applications

Automotive gateway
Advanced driver assistance system (ADAS)
Body electronics and lighting
Hybrid, electric & powertrain systems
Automotive infotainment & cluster

3 Description

The TCAN1472-Q1 and TCAN1472V-Q1 are high speed Controller Area Network (CAN) SIC transceivers that meet the physical layer requirements of the ISO 11898-2:2024 Annex A Signal Improvement Capability (SIC) specifications. The devices reduce signal ringing at dominant-to- recessive edge and enable higher throughput in complex network topologies. Signal improvement capability allows the applications to extract real benefit of CAN FD (flexible data rate) by operating at 2Mbps, or operating at 5Mbps or higher in large networks with multiple unterminated stubs. The devices meet the timing specifications mandated by Annex A SIC part of ISO11898-2:2024; thus, have much tighter bit timing symmetry compared to a regular CAN FD transceivers. Providing larger timing window to sample the correct bit, and enabling error- free communication in large complex star networks where ringing and bit distortion are inherent. These devices are pin-compatible to 8-pin CAN FD transceivers, such as TCAN1044A-Q1 or TCAN1042- Q1. The TCAN1472-Q1 devices with suffix 'V' include internal logic level translation via the V IO logic supply terminal to allow for interfacing directly to 1.8V, 2.5V, or 3.3V controllers. The transceivers support low power standby mode which allows remote wake- up via CAN bus compliant with ISO 11898-2:2024 defined wake-up pattern (WUP). The device family also includes many protection features such as undervoltage detection, thermal shutdown (TSD), driver dominant timeout (TXD DTO), and ±58V bus fault protection.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TCAN1472-Q1 SOT-23 (DDF) 2.9mm x 1.6mm VSON (DRB) 3mm x 3mm SOIC (D) 4.9mm x 3.91mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. ADVANCE INFORMATION TCAN1472-Q1 SLLSFW8 – JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

Device Number Bus Fault Protection Low voltage I/O Logic Support on Pin 5 Pin 8 Mode Selection TCAN1472-Q1 ± 58V No Low Power Standby Mode with Remote WakeTCAN1472V-Q1 ± 58V Yes TCAN1472-Q1 STB RXD TXD CANH CANL VCC Port x RXD TXD 5V Voltage Regulator VIN VOUT GND Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD CAN FD Controller 1.8V / 2.5V / 3.3V Regulator VBAT VIN VIO VOUT Simplified Block Diagram TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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11 Mechanical, Packaging, and Orderable

4 Pin Configurations and Functions

4RXD 5 NC, VIO Not to scale Figure 4-1. SOIC (D) and SOT-23 (DDF) Package, 8 Pin (Top View) 1TXD 8 STB 2GND 7 CANH 3VCC 6 CANL 4RXD 5 NC,VIO Not to scale Thermal Pad Figure 4-2. VSON (DRB) Package, 8 Pin (Top View) Table 4-1. Pin Functions PINS TYPE DESCRIPTION NAME NO. TXD 1 Digital Input CAN transmit data input, integrated pull-up GND 2 GND Ground connection VCC 3 Supply 5V supply voltage RXD 4 Digital Output CAN receive data output, tristate when powered off VIO Supply Logic supply voltage NC -- No Connect (not internally connected); Devices without VIO CANL 6 Bus IO Low-level CAN bus input/output line CANH 7 Bus IO High-level CAN bus input/output line STB 8 Digital Input Standby mode control input, integrated pull-up Thermal Pad (VSON only) — Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB) ground plane for thermal relief TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

(1) (2) MIN MAX UNIT VCC Supply voltage –0.3 6 V VIO Supply voltage I/O level shifter (Devices with the "V" suffix) –0.3 6 V VBUS CAN bus I/O voltage range on CANH and CANL –58 58 V VDIFF Max differential voltage between CANH and CANL VDIFF = (CANH - CANL) –45 45 V VLogic_Input Logic pin input voltage (TXD, STB) –0.3 6 V VRXD Logic output voltage range (RXD) –0.3 6 V IO(RXD) RXD output current –8 8 mA TJ Junction temperature –40 165 °C TSTG Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

5.2 ESD Ratings

VESD Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM classification level 3A for all pins ±4000 V HBM classification level 3B for global pins CANH and CANL with respect to GND ±10000 V Charged-device model (CDM), per AEC Q100-011 CDM classification level C5 for all pins ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 ESD Ratings, IEC Transients

VESD System level electrostatic discharge CAN bus terminals (CANH, CANL) to GND SAE J2962-2 per ISO 10605 Powered contact discharge ±8000 V SAE J2962-2 per ISO 10605 Powered air discharge ±15000 V IEC 62228-3 per ISO 10605 ±8000 V VTran ISO 7637-2 Transient immunity(1) Pulse 1 –100 V Pulse 2a 75 V Pulse 3a –150 V Pulse 3b 100 V Direct capacitor coupling, SAE J2962-2 per ISO 7637-3(2) DCC slow transient pulse ±30 V (1) Tested according to IEC 62228-3:2019 CAN Transceivers, Section 6.3; standard pulses parameters defined in ISO 7637-2 (2011) (2) Tested according to SAE J2962-2 www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

5.4 Recommended Operating Conditions

VCC Supply voltage 4.5 5 5.5 V VIO Supply voltage for I/O level shifter (Devices with VIO ) 1.7 5.5 V IOH(RXD) RXD terminal high-level output current –1.5 mA IOL(RXD) RXD terminal low-level output current 1.5 mA TJ Junction temperature –40 150 °C

5.5 Thermal Characteristics

THERMAL METRIC(1) TCAN1472(V)-Q1 UNIT D (SOIC) DDF (SOT) DRB (VSON) RΘJA Junction-to-ambient thermal resistance 113.6 129.2 52.3 ℃/W RΘJC(top) Junction-to-case (top) thermal resistance 52.5 55.0 58.4 ℃/W RΘJB Junction-to-board thermal resistance 61.1 48.1 24.7 ℃/W ΨJT Junction-to-top characterization parameter 7.4 1.7 1.7 ℃/W ΨJB Junction-to-board characterization parameter 60.2 47.9 24.6 ℃/W RΘJC(bot) Junction-to-case (bottom) thermal resistance - – 8.9 ℃/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.6 Supply Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V (for devices with VIO), Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Supply current normal mode Dominant TXD = 0 V, STB = 0 V RL = 60 Ω, CL = open See Figure 6-1 45 70 mA Dominant TXD = 0 V, STB = 0 V RL = 50 Ω, CL = open See Figure 6-1 49 80 mA Recessive TXD = VIO, STB = 0 V RL = 50 Ω, CL = open See Figure 6-1 4.5 11 mA Dominant with bus fault TXD = 0 V, STB = 0 V CANH = CANL = ±25 V RL = open, CL = open See Figure 6-1 130 mA Supply current standby mode (devices with VIO ) TXD = STB = VIO , RL = 50 Ω, CL = open, Tj <= 85 °C, See Figure 6-1 1 µATXD = STB = VIO , RL = 50 Ω, CL = open, Tj <= 125 °C, See Figure 6-1 0.2 2 TXD = STB = VIO , RL = 50 Ω, CL = open, Tj <= 150 °C, See Figure 6-1 5 Supply current standby mode (devices without VIO ) TXD = STB = VCC , RL = 50 Ω, CL = open, Tj <= 85 °C, See Figure 6-1 15 TXD = STB = VCC , RL = 50 Ω, CL = open, Tj <= 125 °C, See Figure 6-1 16 µA TXD = STB = VCC , RL = 50 Ω, CL = open, Tj <= 150 °C, See Figure 6-1 21 TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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5.6 Supply Characteristics (continued)

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V (for devices with VIO), Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIO Devices with VIO I/O supply current normal mode Dominant TXD = 0 V, STB = 0 V RL = 60 Ω, CL = open RXD floating 125 300 µA Recessive TXD = VIO, STB = 0 V RL = 60 Ω, CL = open RXD floating 25 48 µA I/O supply current standby mode TXD = VIO, STB = VIO RL = 60 Ω, CL = open RXD floating, Tj <= 85 °C 13.5 µA TXD = VIO, STB = VIO RL = 60 Ω, CL = open RXD floating, Tj <= 125 °C 8.5 15 TXD = VIO, STB = VIO RL = 60 Ω, CL = open RXD floating, Tj <= 150 °C UVCC(R) Undervoltage detection VCC rising Ramp up 4.2 4.4 V UVCC(F) Undervoltage detection on VCC falling Ramp down 3.5 4 V UVIO(R) Undervoltage detection VIO rising (Devices with VIO) Ramp up 1.6 1.65 V UVIO(F) Undervoltage detection on VIO falling (Devices with VIO) Ramp down 1.4 1.5 V

5.7 Dissipation Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Average power dissipation Normal mode VCC = 5 V, VIO = 3.3 V, TJ = 27°C, RL = 60Ω, CL_RXD = 15 pF TXD input = 250 kHz 50% duty cycle square wave 60 mW VCC = 5.5 V, VIO = 5.5 V, TJ = 150°C, RL = 50Ω, CL_RXD = 15 pF TXD input = 2.5 MHz 50% duty cycle square wave 120 mW TTSD Thermal shutdown temperature 192 TTSD_HYS Thermal shutdown hysteresis 10

5.8 Electrical Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver Electrical Characteristics VCANH(D) Dominant output voltage normal mode CANH VCC = 4.5 V to 5.5 V, TXD = 0 V, STB = 0 V 50 Ω ≤ RL ≤ 65 Ω, CL = open, See Figure 6-2 and Figure 7-5 2.75 3.5 4.5 V VCANL(D) CANL 0.5 1.5 2.25 V VCANH(D) Dominant output voltage normal mode CANH VCC = 4.75 V to 5.25 V, TXD = 0 V, STB = 0 V 45 Ω ≤ RL ≤ 65 Ω, CL = open, See Figure 6-2 and Figure 7-5 3 3.5 4.26 V VCANL(D) CANL 0.75 1.5 2.01 V VCANH(R), VCANL(R) Recessive output voltage normal mode CANH and CANL VCC = 4.5 V to 5.5 V, TXD = VIO, STB = 0 V RL = open (no load), CL = open, See Figure 6-2 and Figure 7-5 2 2.5 3 V VCANH(R), VCANL(R) Recessive output voltage normal mode CANH and CANL VCC = 4.75 V to 5.25 V, TXD = VIO, STB = 0 V 45 Ω ≤ RL ≤ 65 Ω , CL = 4.7 nF See Figure 6-2 and Figure 7-5 2.256 2.756 V www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

5.8 Electrical Characteristics (continued)

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSYM Driver symmetry (VO(CANH) + VO(CANL))/(VCANH(R) + VCANL(R)) TXD = 250 kHz, 1 MHz, 2.5 MHz, STB = 0 V 45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open, See Figure 6-2 and Figure 7-5 0.95 1.05 V/V VDIFF(D) Differential output voltage normal mode Dominant CANH - CANL TXD = 0 V, STB = 0 V 45 Ω ≤ RL ≤ 65 Ω, CL = open, See Figure 6-2 and Figure 7-5 1.5 3 V TXD = 0 V, STB = 0 V 45 Ω ≤ RL ≤ 70 Ω, CL = open, See Figure 6-2 and Figure 7-5 1.5 3.3 V TXD = 0 V, STB = 0 V RL = 2240 Ω, CL = open, See Figure 6-2 and Figure 7-5 1.5 5 V VDIFF(R) Differential output voltage normal mode Recessive CANH - CANL TXD = VIO, STB = 0 V 45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open, See Figure 6-2 and Figure 7-5 –50 50 mV TXD = VIO, STB = 0 V RL = open, CL = open, See Figure 6-2 and Figure 7-5 –50 50 mV VCANH(INACT) Bus output voltage standby mode CANH TXD = STB = VIO RL = open , CL = open, See Figure 6-2 and Figure 7-5 -0.1 0.1 V VCANL(INACT) CANL -0.1 0.1 V VDIFF(INACT) CANH - CANL -0.2 0.2 V RDIFF(DOM) Differential input resistance in dominant phase TXD= 0 V, STB = 0 V, See Figure 7-2 40 Ω RSE_SIC_ACT_ REC Single ended resistance CANH/CANL in active recessive phase 2 V ≤ VCANH/L ≤ VCC - 2 V 37.5 50 66.5 Ω RDIFF_SIC_AC T_REC Differential input resistance in active recessive drive phase 2 V ≤ VCANH/L ≤ VCC - 2 V 75 100 133 Ω ICANH(OS) Short-circuit bus output current, TXD is dominant or recessive or toggling, normal mode V(CANH) = -15 V to 40 V, CANL = open, TXD = 0 V or VIO or 250 kHz, 2.5 MHz square wave, See Figure 6-7 and Figure 7-5 –115 115 mA ICANL(OS) V(CAN_L) = -15 V to 40 V, CANH = open, TXD = 0 V or VIO or 250 kHz, 2.5 MHz square wave, See Figure 6-7 and Figure 7-5 –115 115 mA Receiver Electrical Characteristics VIT Input threshold voltage normal mode -12 V ≤ VCM ≤ 12 V, STB= 0 V, See Figure 6-3 and Figure 7-6 500 900 mV VIT(STB) Input threshold standby mode -12 V ≤ VCM ≤ 12 V, STB= VIO , See Figure 6-3 and Figure 7-6 400 1150 mV VDIFF_RX(D) Normal mode dominant state differential input voltage range -12 V ≤ VCM ≤ 12 V, STB= 0 V, See Figure 6-3 and Figure 7-6 0.9 9 V VDIFF_RX(R) Normal mode recessive state differential input voltage range -12 V ≤ VCM ≤ 12 V , STB= 0 V, See Figure 6-3 and Figure 7-6 -4 0.5 V VDIFF_RX(D_IN ACT) Standby mode dominant state differential input voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V, See Figure 6-3 and Figure 7-6 1.15 9 V VDIFF_RX(R_IN ACT) Standby mode recessive state differential input voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V, See Figure 6-3 and Figure 7-6 -4 0.4 V VHYS Hysteresis voltage for input threshold normal mode -12 V ≤ VCM ≤ 12 V, STB= 0 V, See Figure 6-3 and Figure 7-6 100 mV VCM Common mode range normal and standby modes See Figure 6-3 and Figure 7-6 –12 12 V ILKG(OFF) Unpowered bus input leakage current CANH = CANL = 5 V, VCC = VIO = GND 5 µA CI Input capacitance to ground (CANH or CANL) TXD = VIO 30 pF CID Differential input capacitance across bus terminals 15 pF TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RDIFF_PAS_RE C Differential input resistance in passive recessive phase TXD = VIO, STB = 0 V -12 V ≤ VCM ≤ 12 V, Delta V/Delta I 40 90 kΩ RSE_PAS_REC Single ended input resistance in passive recessive phase (CANH or CANL) 20 45 kΩ mR Input resistance matching [1 – (RIN(CANH) / RIN(CANL))] × 100 % V(CAN_H) = V(CAN_L) = 5 V –1 1 % TXD Terminal (CAN Transmit Data Input) VIH High-level input voltage Devices without VIO 0.7 VCC V VIH High-level input voltage Devices with VIO 0.7 VIO V VIL Low-level input voltage Devices without VIO 0.3 VCC V VIL Low-level input voltage Devices with VIO 0.3 VIO V IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µA IIL Low-level input leakage current TXD = 0 V, VCC = VIO = 5.5 V –200 -100 –20 µA ILKG_TXD(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 0 1 µA CI_TXD Input capacitance VIN = 0.4×sin(2×π×2×106×t)+2.5 V 6 pF RXD Terminal (CAN Receive Data Output) VOH High-level output voltage Devices without VIO IO = –1.5 mA, See Figure 6-3

0.8 VCC V

VOH High-level output voltage IO = –1.5 mA, Devices with VIO See Figure 6-3 0.8 VIO V VOL Low-level output voltage Devices without VIO IO = 1.5 mA, See Figure 6-3

0.2 VCC V

VOL Low-level output voltage Devices with VIO IO = 1.5 mA, Devices with VIO See Figure 6-3

0.2 VIO V

ILKG_RXD(OFF) Unpowered leakage current RXD = 5.5 V, VCC = VIO = 0 V –1 0 1 µA STB Terminal (Standby Mode Input) VIH High-level input voltage Devices without VIO 0.7 VCC V VIH High-level input voltage Devices with VIO 0.7 VIO V VIL Low-level input voltage Devices without VIO 0.3 VCC V VIL Low-level input voltage Devices with VIO 0.3 VIO V IIH High-level input leakage current VCC = VIO = STB = 5.5 V –2 2 µA IIL Low-level input leakage current VCC = VIO = 5.5 V, STB = 0 V –20 –2 µA ILKG_STB(OFF) Unpowered leakage current STB = 5.5V, VCC= VIO = 0 V –1 0 1 µA

5.9 Switching Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Device Switching Characteristics www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

5.9 Switching Characteristics (continued)

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) 95 145 ns See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF 100 155 ns See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 105 170 ns See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 120 190 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) 110 150 ns See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF 115 160 ns See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 120 175 ns See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 135 190 ns tMODE Mode change time, from normal to standby or from standby to normal See Figure 6-5 30 µs tWK_FILTER Filter time for a valid wake-up pattern See Figure 7-7 0.5 0.95 µs tWK_TIMEOUT Bus wake-up timeout value See Figure 7-7 0.8 6 ms Tstartup Time duration after VCC or VIO hass cleared rising undervoltage threshold, and device can resume normal operation 1.5 ms Tfilter(STB) Filter on STB pin to filter out any glitches 0.5 1 2 µs Driver Switching Characteristics tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to driver recessive (dominant to recessive) See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ to 5.5 V 50 70 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V 50 70 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ to 2.75 V 55 75 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ to 1.89 V 55 80 ns tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to driver dominant (recessive to dominant) See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ to 5.5 V 45 75 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V 50 75 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ to 2.75 V 50 80 ns See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ to 1.89 V 55 80 ns tsk(p) Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), See Figure 6-2 3.5 10 ns TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tBUS_R Differential output signal rise time See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) 20 30 ns tBUS_F Differential output signal fall time See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) 30 40 ns tTXD_DTO Dominant timeout See Figure 6-6 , 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), STB = 0 V 1.2 4.0 ms Receiver Switching Characteristics tprop(busrec-RXD) Propagation delay time, bus recessive input to RXD high output (dominant to recessive) See Figure 6-3 , STB = 0 V, CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V 60 85 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V 65 95 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 70 105 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 80 110 ns tprop(busdom-RXD) Propagation delay time, bus dominant input to RXD low output (recessive to dominant) See Figure 6-3 , STB = 0 V, CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V 50 75 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V 50 80 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 55 90 ns See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 65 110 ns tRXD_R RXD output signal rise time See Figure 6-3, STB = 0 V, CL(RXD) = 15 pF(≤ ±1%) 8 20 ns tRXD_F RXD output signal fall time 7 25 ns Signal Improvement Timing Characteristics tPAS_REC_START Start time of passive recessive phase Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase 530 ns tACT_REC_START Start time of active signal improvement phase Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase 120 ns tACT_REC_END End time of active signal improvement phase 355 ns tΔ Bit(Bus) Transmitted bit width variation TXD <= 5Mbps square wave, tΔ Bit(Bus) = tBit(Bus) - tBit(TxD) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4 –10 10 ns tΔ BIT(RxD) Received bit width variation TXD <= 5Mbps square wave, tΔ BIT(RxD) = tBit(RxD) - tBit(TxD) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), CL(RXD) = 15 pF, See Figure 6-4 –30 20 ns tΔ REC Receiver timing symmetry TXD <= 5Mbps square wave, tΔ REC = tBit(RxD) - tBit(Bus) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4 –20 15 ns www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

6 Parameter Measurement Information

Figure 6-1. ICC Test Circuit VODRL CANH CANL TXD CL TXD 0.9V 0.5 V VOD tprop(TXD-busdom) 50% 50% VO(CANH) VO(CANL) tR tF 0 V VCC tprop(TXD-busrec) 90% 10% + + ± ± Figure 6-2. Driver Test Circuit and Measurement VO CL_RXD CANH RXD CANL VID VID 0.5 V 0.9 V 1.5 V 0 V VO(RXD) VOH VOL tprop(busrec-RXD) tR tF IO tprop(busdom-RXD) 90% 50% 10% Figure 6-3. Receiver Test Circuit and Measurement TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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70% 70% 30% 30% 30% VI 0 V 500 mV 900 mV VDIFF RL CANH CANL TXD CL VO CL_RXD RXD VI

0 V STB

tBIT(RXD) tPROP(LOOP2) tBIT(BUS) tBIT(TXD)n x tBIT(TXD) 30% 900 mV tprop(TXD-busdom) tprop(busdom-RXD) tprop(TXD-busrec) tprop(busrec-RXD) tPROP(LOOP1) n = 1 to 5; TXD rise/fall time < 10 ns Figure 6-4. Transmitter and Receiver Timing Behavior Test Circuit and Measurement www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

VO CL_RXD RXD STBVI 0 V tMODE STB RXD VOH VOL VIH 0 V 50% 50% Figure 6-5. tMODE Test Circuit and Measurement VODRL CANH CANL TXD CL TXD 0.9V 0.5V VOD VIH tTXD_DTO VOD(D) Figure 6-6. TXD Dominant Timeout Test Circuit and Measurement CANH CANL TXD = H or L or toggling VBUS IOS IOS Figure 6-7. Driver Short-Circuit Current Test and Measurement TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TCAN1472V(D)-Q1 devices meet or exceed the specifications of the Annex A Signal Improvement capability (SIC) specification of ISO 11898-2:2023 Controller Area Network physical layer standard. The devices are data rate agnostic making them backward compatible for supporting classical CAN applications while also supporting CAN FD networks up to 8Mbps. These devices have standby mode support which puts the transceiver in ultra-low current consumption mode. Upon receiving a valid wake-up pattern (WUP) on the CAN bus, the device signals to the microcontroller through the RXD pin. The MCU can then put the device into normal mode using the STB pin. The TCAN1472V-Q1 has two separate supply rails, V CC bus-side supply and V IO logic supply for logic-level translation for interfacing directly to 1.8V, 2.5V, 3.3V, or 5V controllers.

7.1.1 Signal Improvement

Signal improvement is an additional capability added to CAN FD transceiver that enhances the maximum data rate achievable in complex star topologies by minimizing signal ringing. Signal ringing is the result of reflections caused by impedance mismatch at various points in a CAN network due to the nodes that act as stubs. An example of a complex network is shown in Figure 7-1. ECU 5 ECU 6 ECU 3 ECU 1 (terminated) ECU 2 ECU 4 ECU 7ECU 8 (terminated) Figure 7-1. CAN Network: Star topology Recessive-to-dominant signal edge is usually clean and driven by the transmitter. Transmitter output impedance of CAN transceiver is approximately 50 Ω and matches to the network characteristic impedance. For a regular CAN FD transceiver, dominant-to-recessive edge is when the driver output impedance goes to approximately 60kΩ and signal reflected back experiences impedance mismatch which causes ringing. TCAN1472-Q1 resolves this issue by TX-based Signal improvement capability (SIC). The device continues to drive the bus recessive until tSIC_TX_base so that reflections die down and recessive bit is clean at sampling point. In the active recessive phase, transmitter output impedance is low (approximately 100 Ω). After this phase is over and device goes to passive recessive phase, driver output impedance goes to high-Z. This phenomenon is explained with Figure 7-2. For more information on the TI signal improvement technology, and how it compares with similar devices in market, please refer to the white paper How Signal Improvement Capability Unlocks the Real Potential of CAN-FD Transceivers. www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

RDIFF_ACT_REC(MAX) RSE_SIC_CANH/L(MAX) RDIFF_ACT_REC(MIN) RSE_SIC_CANH/L(MIN) 50% RSE-CANH/L (MIN) RDIFF_PAS_ REC (MIN) RSE_SIC_C ANH/L RDIFF_ACT _REC RDIFF_PAS_REC(MIN) RSE_CANH/L(MIN) tREC_START (MAX) tSIC_START (MAX) tSIC_END (MIN) R t Figure 7-2. TX based SIC

7.2 Functional Block Diagram

Figure 7-3. Block Diagram TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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7.3 Feature Description

7.3.1 Pin Description

7.3.1.1 TXD

The TXD input is a logic-level signal from a CAN controller to the transceiver. The input is referenced to V CC for TCAN1472-Q1, or to VIO for TCAN1472V-Q1.

7.3.1.2 GND

GND is the ground pin of the transceiver. The pin must be connected to the PCB ground.

7.3.1.3 VCC

VCC provides the 5V power supply to the CAN transceiver.

7.3.1.4 RXD

The RXD output is a logic-level signal from the CAN transceiver to the CAN controller. The output is referenced to V CC for TCAN1472-Q1 and V IO for TCAN1472V-Q1. For TCAN1472V-Q1, RXD is only driven once V IO is present. When a wake event takes place, RXD is driven low.

7.3.1.5 VIO (TCAN1472V-Q1 only)

The VIO pin provides the digital I/O voltage to match the CAN controller voltage; thus, avoiding the requirement for a level shifter. The pin supports a wide range of controller interface voltage levels from 1.7V to 5.5V.

7.3.1.6 CANH and CANL

These are the CAN high and CAN low differential bus pins. The pins are connected to the CAN transceiver and the low-voltage WUP CAN receiver.

7.3.1.7 STB (Standby)

The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either the system processor or from a static system voltage source. If normal mode is the only intended mode of operation, then the STB pin can be tied directly to GND.

7.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-4 and Figure 7-5. A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to V CC/2 via the high-resistance internal input resistors RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins. A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver. The TCAN1472-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 7-4 and Figure 7-5. www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

Recessive Dominant Recessive Time, t Typical Bus Voltage Normal Mode Standby Mode CANL CANH VDIFF VDIFF Figure 7-4. Bus States Bias Unit 2.5V A B GND CANL CANH RXD A. Normal Mode B. Standby Mode Figure 7-5. Simplified Recessive Common Mode Bias Unit and Receiver

7.3.3 TXD Dominant Timeout (DTO)

During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the timeout period t TXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the timeout period of the circuit, t TXD_DTO, the CAN driver is disabled. Freeing the bus for communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is seen on the TXD pin; thus, clearing the dominant time out. The receiver remains active and biased to V CC/2 and the RXD output reflects the activity on the CAN bus during the TXD DTO fault. The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. The minimum transmitted data rate may be calculated using Equation 1. Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2ms = 9.2kbps (1) TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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TXD fault stuck dominant: example PCB failure or bad software Fault is repaired & transmission capability restored TXD (driver) %XVZRXOGEH³VWXFNGRPLQDQW´EORFNLQJFRPPXQLFDWLRQIRUWKHZKROHQHWZRUNEXW7;''72 prevents this and frees the bus for communication after the time tTXD_DTO. tTXD_DTO Communication from local node Communication from repaired node RXD (receiver) Communication from other bus node(s) Communication from repaired local node Communication from other bus node(s) tTXD_DTO Driver disabled freeing bus for other nodes Figure 7-6. Example Timing Diagram for TXD Dominant Timeout

7.3.4 CAN Bus Short-circuit Current Limiting

The TCAN1472-Q1 has several protection features that limit the short-circuit current when a CAN bus line is shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state timeout which prevents permanently having the higher short-circuit current of a dominant state in case of a system fault. During CAN communication the bus switches between the dominant and recessive states; thus, the short-circuit current may be viewed as either the current during each bus state or as a DC average current. When selecting termination resistors or a common mode choke for the CAN design the average power rating, IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has forced state changes and recessive bits due to bit stuffing, control fields, and inter frame space. These make sure there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of dominant bits. The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short-circuit currents. The average short-circuit current may be calculated using Equation 2. IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC] (2) Where:

IOS(AVG) is the average short-circuit current
% Transmit is the percentage the node is transmitting CAN messages
% Receive is the percentage the node is receiving CAN messages
% REC_Bits is the percentage of recessive bits in the transmitted CAN messages
% DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short-circuit current
IOS(SS)_DOM is the dominant steady state short-circuit current This short-circuit current and the possible fault cases of the network are taken into consideration when sizing the power supply used to generate the transceivers VCC supply. www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

7.3.5 Thermal Shutdown (TSD)

If the junction temperature of the TCAN1472-Q1 exceeds the thermal shutdown threshold, TTSD, the device turns off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared when the junction temperature of the device drops below T TSD. The CAN bus pins are biased to V CC/2 during a TSD fault and the receiver to RXD path remains operational. The TCAN1472-Q1 TSD circuit includes hysteresis which prevents the CAN driver output from oscillating during a TSD fault.

7.3.6 Undervoltage Lockout

The supply pins, V CC and V IO, have undervoltage detection that places the device into a protected state. This protects the bus during an undervoltage event on either supply pin. Table 7-1. Undervoltage Lockout - TCAN1472-Q1 VCC DEVICE STATE BUS RXD PIN > UVVCC Normal Per TXD Mirrors bus < UVVCC Protected High impedance High impedance Table 7-2. Undervoltage Lockout - TCAN1472V-Q1 VCC VIO DEVICE STATE BUS RXD PIN > UVVCC > UVVIO Normal Per TXD Mirrors bus < UVVCC > UVVIO STB = VIO: standby mode High impedance VIO: Remote wake request(1) STB = GND: Protected Recessive > UVVCC < UVVIO Protected High impedance < UVVCC < UVVIO Protected High impedance (1) See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode Once the undervoltage condition is cleared and t MODE has expired, the TCAN1472-Q1 transitions to normal mode and the host controller can send and receive CAN traffic again.

7.3.7 Unpowered Device

The TCAN1472-Q1 is designed to be a passive or no load to the CAN bus if the device is unpowered. The bus pins were designed to have low leakage currents when the device is unpowered to not load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains operational. The logic pins also have low leakage currents when the device is unpowered to not load other circuits which may remain powered.

7.3.8 Floating pins

The TCAN1472-Q1 has internal pull-ups on critical pins which place the device into known states if the pin floats. This internal bias should not be relied upon by design though, especially in noisy environments, but instead should be considered a failsafe protection feature. When a CAN controller supporting open-drain outputs is used, an adequate external pull-up resistor must be chosen. Making sures the TXD output of the CAN controller maintains acceptable bit time to the input of the CAN transceiver. See Table 7-3 for details on pin bias conditions. Table 7-3. Pin Bias Pin Pull-up or Pull-down Comment TXD Pull-up Weakly biases TXD towards recessive to prevent bus blockage or TXD DTO triggering STB Pull-up Weakly biases STB towards low-power standby mode to prevent excessive system power TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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7.4 Device Functional Modes

7.4.1 Operating Modes

The TCAN1472-Q1 has two main operating modes; normal mode and standby mode. Operating mode selection is made by applying a high or low level to the STB pin on the TCAN1472-Q1. Table 7-4. Operating Modes STB Device Mode Driver Receiver RXD Pin High Low current standby mode with bus wake-up Disabled Low-power receiver and bus monitor enable High (recessive) until valid WUP is received. See (1) Low Normal Mode Enabled Enabled Mirrors bus state (1) See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

7.4.2 Normal Mode

This is the normal operating mode of the TCAN1472-Q1. The CAN driver and receiver are fully operational and CAN communication is bi-directional. The driver is translating a digital input on the TXD input to a differential output on the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL to a digital output on the RXD output.

7.4.3 Standby Mode

This is the low-power mode of the TCAN1472-Q1. The CAN driver and main receiver are switched off and bi-directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure 7-7. The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device to normal mode by pulling the STB pin low. The CAN bus pins are weakly pulled to GND in this mode (see Figure 7-4 and Figure 7-5). In standby mode, only the V IO supply is required therefore the V CC may be switched off for additional system level current savings.

7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

The TCAN1472-Q1 supports a remote wake-up request that is used to indicate to the host controller that the bus is active and the node should return to normal operation. The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2024 standard to qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1472-Q1. The Wake-Up Pattern (WUP) comprises four pulses: a filtered dominant, followed by a filtered recessive, then another filtered dominant, and finally another filtered recessive. After the first filtered dominant pulse, the bus monitor waits for a filtered recessive without being reset by other bus traffic and does the same until second filtered recessive pulse. Upon receiving the second filtered recessive pulse, WUP is recognized. RXD is set permanently low upon subsequent dominant pulses. For a dominant or recessive to be considered filtered, the bus must be in that state for more than the tWK_FILTER time. Due to variability in t WK_FILTER the following scenarios are applicable. Bus state times less than tWK_FILTER(MIN) are never detected as part of a WUP, and therefore, no wake request is generated. Bus state times between t WK_FILTER(MIN) and t WK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be generated. Bus state times greater than t WK_FILTER(MAX) are always detected as part of a WUP, and thus a wake request is always generated. See Figure 7-7 for the timing diagram of the wake-up pattern. The pattern and t WK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing false wake-up requests while allowing any valid message to initiate a wake-up request. The ISO 11898-2:2024 standard has defined wakeup filter time to enable 1Mbps arbitration. www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this section. See Figure 7-7 for the timing diagram of the wake-up pattern with wake timeout feature. Bus VDiff tWK_FILTER tWK_FILTER tWK_FILTER Bus Filtered Dominant Filtered Dominant Filtered Recessive Wake Up Pattern (WUP) where t tWK_TIMEOUT RXD tWK_FILTER Bus Wake Via RXD Requests Bus Wake via RXD Request Waiting for Filtered Recessive Waiting for Filtered Dominant VIO > UVIO tWK_FILTER Filtered Recessive Waiting for Filtered Recessive Figure 7-7. Wake-Up Pattern (WUP) with tWK_TIMEOUT

7.4.4 Driver and Receiver Function

The digital logic input and output levels for the TCAN1472-Q1 are CMOS levels with respect to V CC. For TCAN1472V-Q1, these are referred to VIO for compatibility with MCUs having 1.8V, 2.5V, 3.3V, or 5V supply. Table 7-5. Driver Function Table Device Mode TXD Input(1) Bus Outputs Driven Bus State(2) CANH CANL Normal Low High Low Dominant High or open High impedance High impedance Biased recessive Standby X High impedance High impedance Biased to ground (1) X = irrelevant (2) For bus state and bias see Figure 7-4 and Figure 7-5. Table 7-6. Receiver Function Table Normal and Standby Mode Device Mode CAN Differential Inputs VID = VCANH – VCANL Bus State RXD Pin Normal VID ≥ 0.9V Dominant Low 0.5V < VID < 0.9V Undefined Undefined VID ≤ 0.5V Recessive High Standby VID ≥ 1.15V Dominant High Low if a remote wake event occurred. See Figure 7-7 0.4V < VID < 1.15V Undefined VID ≤ 0.4V Recessive Any Open (VID ≈ 0V) Open High TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Application

The TCAN1472-Q1 transceiver can be used in applications with a host controller or FPGA that includes the link layer portion of the CAN protocol. Figure 8-1 shows a typical configuration for 5V controller applications. The bus termination is shown for illustrative purposes. TCAN1472-Q1 STB RXD TXD CANH CANL VCC Port x RXD TXD 5V Voltage Regulator VIN VOUT GND Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD CAN FD Controller VBAT NC Figure 8-1. Transceiver Application Using 5V I/O Connections www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

8.2.1 Design Requirements

8.2.1.1 CAN Termination

Termination may be a single 120 Ω resistor at each end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used, see Figure 8-2 . Split termination improves the electromagnetic emissions behavior of the network by filtering higher-frequency common-mode noise that may be present on the differential signal lines. Standard Termination Split Termination CSPLIT TCAN Transceiver CANL CANH TCAN Transceiver CANL CANH RTERM/2 RTERM RTERM/2 Figure 8-2. CAN Bus Termination Concepts

8.2.2 Detailed Design Procedures

8.2.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1472-Q1. Additionally, since TCAN1472V(D)-Q1 has SIC, in a given network size, higher data rate can be achieved because signal ringing is attenuated. Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO 11898-2 standard. There are system level trade off decisions for data rate, cable length, and parasitic loading of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE J2284, SAE J1939, and NMEA 2000. A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2024 specification, the driver differential output is specified with a bus load that can range from 45 Ω to 65Ω where the differential output must be greater than 1.5V. The TCAN1472-Q1 family is specified to meet the 1.5V requirement down to 45Ω bus load. The differential input resistance of the TCAN1472-Q1 is a minimum of 40k Ω. If 100 TCAN1472-Q1 transceivers are in parallel on a bus, this is equivalent to a 400 Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately 52 Ω. Therefore, the TCAN1472-Q1 family theoretically supports over 100 transceivers on a single bus segment. However, for a CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate. This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility the CAN network system, the designer must take the responsibility of good network design for a robust network operation. TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

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(with termination) RTERM RTERM System Controller CAN FD Controller TCAN1043-Q1 Node 2 System Controller CAN FD Controller TCAN1472-Q1 Node 3 System Controller CAN FD Controller TCAN1044A-Q1 Figure 8-3. Typical CAN Bus www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

8.3 System Examples

The TCAN1472V(D)-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that bus termination is shown for illustrative purposes. TCAN1472-Q1 STB RXD TXD CANH CANL VCC Port x RXD TXD 5V Voltage Regulator VIN VOUT GND Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD CAN FD Controller 1.8V / 2.5V / 3.3V Regulator VBAT VIN VIO VOUT Figure 8-4. Typical Transceiver Application Using 1.8V, 2.5V, 3.3V IO Connections

8.4 Power Supply Recommendations

The TCAN1472-Q1 transceiver is designed to operate with a main VCC input voltage supply range between 4.5V and 5.5V. The TCAN1472V-Q1 implements an I/O level shifting supply input, V IO, designed for a range between 1.8V and 5.5V. Both supply inputs must be well regulated. A decoupling capacitance, typically 100nF, should be placed near the CAN transceiver main V CC supply pin in addition to bypass capacitors. A decoupling capacitor, typically 100nF, should be placed near the CAN transceiver VIO supply pin in addition to bypass capacitors. TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

8.5 Layout

8.5.1 Layout Guidelines

Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and noise from propagating onto the board. This layout example shows an optional transient voltage suppression (TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize trace and via inductance. Note High frequency current follows the path of least impedance and not the path of least resistance.
This layout example shows how split termination could be implemented on the CAN node. The termination is split into two resistors, R4 and R5, with the center or split tap of the termination connected to ground via capacitor C3. Split termination provides common mode filtering for the bus. See CAN Termination, and CAN Bus Short Circuit Current Limiting for information on termination concepts and power ratings needed for the termination resistor(s).

8.5.2 Layout Example

µC V L1(optional) Figure 8-5. Layout Example www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES June 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCAN1472DRQ1 SOIC D 8 2500 340.5 336.1 25.0 TCAN1472VDRQ1 SOIC D 8 2500 340.5 336.1 25.0 TCAN1472DDFRQ1 SOT-23 DDF 8 3000 210.0 185.0 210.0 TCAN1472VDDFRQ1 SOT-23 DDF 8 3000 210.0 185.0 210.0 TCAN1472DRBRQ1 SON DRB 8 3000 346.0 346.0 35.0 TCAN1472VDRBRQ1 SON DRB 8 3000 346.0 346.0 35.0 TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] .041 [1.04] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead ﬂash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] (.217) [5.5] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSDE METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:6X SYMM 4 5 SEE DETAILS IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE SYMM 4 5 SEE DETAILS SYMM TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (.217) [5.5] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have diﬀerent recommendations for stencil design. HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE BASED ON .005 INCH [0.127 MM] THICK STENCIL SOLDER PASTE EXAMPLE SCALE:6X SYMM SYMM 4 5 IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM SYMM 4 5 www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE C 8X 0.35 0.25 2.4 0.05 1.95 1.6 0.05 6X 0.65

1 MAX

8X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP

0.1 MIN

(0.05) VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 SCALE 30.000 SECTION A-A SECTION A-A TYPICAL TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.3) (2.4) (2.8) 6X (0.65) (1.6) ( 0.2) VIA TYP (0.55) (0.95) 8X (0.6) (R0.05) TYP VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 SYMM SCALE:20X LAND PATTERN EXAMPLE NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.3) 8X (0.6) (1.47) (1.07) (2.8) (0.635) 6X (0.65) VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 82% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

C TYP2.95 2.65

1.1 MAX

6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000 www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

(2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED TCAN1472-Q1 SLLSFW8 – JUNE 2024 www.ti.com

Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

(2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have diﬀerent recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X www.ti.com TCAN1472-Q1 SLLSFW8 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TCAN1472-Q1 ADVANCE INFORMATION

www.ti.com 13-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTCAN1472DDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 150 Samples PTCAN1472DRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 Samples PTCAN1472DRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 150 Samples PTCAN1472VDDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 150 Samples PTCAN1472VDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 Samples PTCAN1472VDRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 13-Jul-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated

Product Information

PTCAN1472DRQ1 specifications and overview.

Summary

TCAN1472-Q1 Automotive Fault-Protected CAN FD Transceiver with Signal Improvement Capability (SIC) and Standby Mode JUNE 2024

Description

TCAN1472-Q1 Automotive Fault-Protected CAN FD Transceiver with Signal Improvement Capability (SIC) and Standby Mode JUNE 2024

Source title PTCAN1472DRQ1 Datasheet(PDF) - Texas Instruments

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TCAN1472-Q1 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

Package Information

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

11 Mechanical, Packaging, and Orderable

4 Pin Configurations and Functions

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5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 ESD Ratings, IEC Transients

5.4 Recommended Operating Conditions

5.5 Thermal Characteristics

5.6 Supply Characteristics

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5.6 Supply Characteristics (continued)

5.7 Dissipation Ratings

5.8 Electrical Characteristics

5.8 Electrical Characteristics (continued)

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0.8 VCC V

0.2 VCC V

0.2 VIO V

5.9 Switching Characteristics

5.9 Switching Characteristics (continued)

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6 Parameter Measurement Information

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0 V STB

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7 Detailed Description

7.1 Overview

7.1.1 Signal Improvement

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Pin Description

7.3.1.1 TXD

7.3.1.2 GND

7.3.1.3 VCC

7.3.1.4 RXD

7.3.1.5 VIO (TCAN1472V-Q1 only)

7.3.1.6 CANH and CANL

7.3.1.7 STB (Standby)

7.3.2 CAN Bus States

7.3.3 TXD Dominant Timeout (DTO)

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7.3.4 CAN Bus Short-circuit Current Limiting

7.3.5 Thermal Shutdown (TSD)

7.3.6 Undervoltage Lockout

7.3.7 Unpowered Device

7.3.8 Floating pins

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7.4 Device Functional Modes

7.4.1 Operating Modes

7.4.2 Normal Mode

7.4.3 Standby Mode

7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

7.4.4 Driver and Receiver Function

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8 Application and Implementation

8.1 Application Information

8.2 Typical Application

8.2.1 Design Requirements

8.2.1.1 CAN Termination

8.2.2 Detailed Design Procedures

8.2.2.1 Bus Loading, Length and Number of Nodes

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8.3 System Examples

8.4 Power Supply Recommendations

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8.5 Layout

8.5.1 Layout Guidelines

8.5.2 Layout Example