Logic IC

PTCAN1044ADDFRQ1

Texas Instruments

TCAN1044A-Q1 and TCAN1044AV-Q1 Automotive Fault-Protected CAN FD Transceiver with Standby mode REVISED OCTOBER 2021

Manufacturer: Texas Instruments

Document: 41 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse P parts

Online Datasheet

Read PTCAN1044ADDFRQ1 online.

TCAN1044A-Q1_V01 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 41

Technical content

TCAN1044A-Q1 and TCAN1044AV-Q1 Automotive Fault-Protected CAN FD Transceiver with Standby mode

1 Features

AEC-Q100 (Grade 1) Qualified for automotive

applications

Meets the requirements of ISO 11898-2:2016 physical layer standard
Functional Safety-Capable – Documentation available to aid in functional safety system design
Support of classical CAN and optimized CAN FD performance at 2, 5, and 8 Mbps – Short and symmetrical propagation delays for enhanced timing margin
TCAN1044AV I/O voltage range supports 1.7 V to 5.5 V
Support for 12-V and 24-V battery applications
Receiver common mode input voltage: ±12 V
Protection features: – Bus fault protection: ±58 V – Undervoltage protection – TXD-dominant time-out (DTO)
Data rates down to 9.2 kbps – Thermal-shutdown protection (TSD)
Operating modes: – Normal mode – Low power standby mode supporting remote wake-up request
Optimized behavior when unpowered – Bus and logic pins are high impedance (no load to operating bus or application) – Hot-plug capable: power up/down glitch-free operation on bus and RXD output
8-Pin SOIC, small footprint SOT-23 and leadless VSON-8 package with improved automated optical inspection (AOI) capability

2 Applications

Automotive and transportation – Body control modules – Automotive gateway – Advanced driver assistance system (ADAS) – Infotainment

3 Description

The TCAN1044A-Q1 and TCAN1044AV-Q1 are high speed controller area network (CAN) transceivers that meets the physical layer requirements of the ISO 11898-2:2016 high-speed CAN specification. The transceivers have certified electromagnetic compatibility (EMC) operation making it an ideal choice for classical CAN and CAN FD networks up to 5 megabits per second (Mbps). Up to 8 Mbps operation in simpler networks is possible with these devices. The TCAN1044AV-Q1 includes internal logic level translation via the V IO pin to allow for interfacing the transceiver I/O's directly to 1.8-V, 2.5-V, 3.3-V, or 5-V logic levels. The transceiver supports a low-power standby mode and wake over CAN which is compliant to the ISO 11898-2:2016 defined wake-up pattern (WUP). The transceivers also include thermal-shutdown (TSD), TXD-dominant time-out (DTO), supply undervoltage detection, and ±58-V bus fault protection. The devices have defined fail-safe behavior in supply undervoltage or floating pin scenarios. These transceivers are not only available in industry-standard SOIC-8 and VSON-8 packages, but also have a space-saving small footprint SOT-23 package option. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCAN1044A-Q1 TCAN1044AV-Q1 SOIC (D) 4.90 mm x 3.91 mm VSON (DRB) 3.00 mm x 3.00 mm SOT-23 (DDF) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TCAN1044AV STB RXD TXD CANH CANL VCC Port x RXD TXD 5-V Voltage Regulator VIN VOUT GND Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD CAN FD Controller 1.8 V / 2.5 V / 3.3 V Regulator VBAT VIN VIO VOUT Simplified Schematic TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

13.1 Receiving Notification of Documentation Updates..26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2021) to Revision B (October 2021) Page Changes from Revision * (February 2021) to Revision A (July 2021) Page TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

5 Device Comparison

Table 5-1. Device Comparison Table Part Number Low Voltage I/O Logic Support on Pin 5 Pin 8 Mode Selection TCAN1044A-Q1 No Low Power Standby Mode with Remote WakeTCAN1044AV-Q1 Yes

6 Pin Configuration and Functions

4RXD 5 NC, VIO Not to scale Figure 6-1. DDF Package, 8-Pin SOT, Top View 1TXD 8 STB 2GND 7 CANH 3VCC 6 CANL 4RXD 5 NC, VIO Not to scale Figure 6-2. D Package, 8-Pin SOIC, Top VIew 1TXD 8 STB 2GND 7 CANH 3VCC 6 CANL 4RXD 5 NC,VIO Not to scale Thermal Pad Figure 6-3. DRB Package, 8-Pin VSON, Top View Table 6-1. Pin Functions Pins Type Description Name No. TXD 1 Digital Input CAN transmit data input; integrated pull-up GND 2 GND Ground connection VCC 3 Supply 5-V supply voltage RXD 4 Digital Output CAN receive data output, tri-stated when device powered off NC — Not internally connected; Devices without VIO VIO Supply I/O supply voltage for devices with suffix 'V' CANL 6 Bus IO Low-level CAN bus input/output line CANH 7 Bus IO High-level CAN bus input/output line STB 8 Digital Input Standby input for mode control; integrated pull-up Thermal Pad (VSON only) — Connect the thermal pad to any internal PCB ground plane using multiple vias for optimal thermal performance. www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7 Specifications

7.1 Absolute Maximum Ratings

(1) (2) MIN MAX UNIT VCC Supply voltage –0.3 6 V VIO Supply voltage I/O level shifter –0.3 6 V VBUS CAN Bus I/O voltage –58 58 V VDIFF Max differential voltage between CANH and CANL –45 45 V VLogic_Input Logic input terminal voltage –0.3 6 V VRXD RXD output terminal voltage range –0.3 6 V IO(RXD) RXD output current –8 8 mA TJ Junction temperature –40 165 °C TSTG Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

7.2 ESD Ratings

VESD Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM classification level 3A for all pins ±4000 V HBM classification level 3B for global pins CANH and CANL with respect to GND ±10000 V Charged-device model (CDM), per AEC Q100-011 CDM classification level C5 for all pins ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings - IEC Specifications

VESD System level Electrostatic discharge CAN bus terminals to GND Unpowered contact discharge per ISO 10605 (1) ±8000 V SAE J2962-2 per ISO 10605 Powered Contact Discharge (2) ±8000 V SAE J2962-2 per ISO 10605 Powered Air Discharge (2) ±15000 V VTran Transient voltage per ISO 7637-2(3) Pulse 1 –100 V Pulse 2a 75 V Pulse 3a –150 V Pulse 3b 100 V Transient voltage per ISO 7637-3(4) DCC slow transient pulse ±30 V (1) Tested according to IEC 62228-3:2019 CAN Transceivers. (2) Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed by OEM approved independent third party, EMC report available upon request. (3) Tested according to IEC 62228-3:2019 CAN Transceivers. (4) Tested according to SAE J2962-2.

7.4 Recommended Operating Conditions

VCC Supply voltage 4.5 5 5.5 V TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7.4 Recommended Operating Conditions (continued)

VIO Supply voltage for I/O level shifter 1.7 5.5 V IOH(RXD) RXD terminal high-level output current, Devices with VIO –1.5 mA IOL(RXD) RXD terminal low-level output current, Devices with VIO 1.5 mA IOH(RXD) RXD terminal high-level output current, Devices without VIO –2 mA IOL(RXD) RXD terminal low-level output current, Devices without VIO 2 mA TJ Operating junction temperature -40 150 ℃

7.5 Thermal Characteristics

THERMAL METRIC(1) TCAN1044Ax-Q1 UNIT D (SOIC) DDF (SOT) DRB (VSON) RθJA Junction-to-ambient thermal resistance 127.5 122 55.2 ℃/W RθJC(top) Junction-to-case (top) thermal resistance 67.6 63 62.4 ℃/W RθJB Junction-to-board thermal resistance 70.9 42.4 27.5 ℃/W ΨJT Junction-to-top characterization parameter 19.3 2.4 2.3 ℃/W ΨJB Junction-to-board characterization parameter 70.2 42.2 27.4 ℃/W RθJC(bot) Junction-to-case (bottom) thermal resistance -- -- 11.5 ℃/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Supply Characteristics

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Supply current Normal mode Dominant STB = 0 V, TXD = 0 V RL = 60 Ω, CL = open See Figure 8-1 45 70 mA STB = 0 V, TXD = 0 V RL = 50 Ω, CL = open See Figure 8-1 49 80 mA Recessive STB = 0 V, TXD = VCC or VIO RL = 50 Ω, CL = open See Figure 8-1 4.5 7.5 mA Dominant with bus fault STB = 0 V, TXD = 0 V CANH = CANL = ±25 V RL = open, CL = open See Figure 8-1 130 mA Supply current Standby mode Devices with VIO STB = TXD = VIO RL = 50 Ω, CL = open See Figure 8-1 1.5 µA Supply current Standby mode Devices without VIO STB = TXD = VCC RL = 50 Ω, CL = open See Figure 8-1 15 µA IIO I/O supply current Normal mode Dominant STB = 0 V, TXD = 0 V RXD floating 125 300 µA I/O supply current Normal mode Recessive STB = 0 V, TXD = 0 V RXD floating 25 48 µA I/O supply current Standby mode STB = VIO, TXD = 0 V RXD floating 8.5 14 µA UVCC Rising undervoltage detection on VCC for protected mode 4.2 4.4 V Falling undervoltage detection on VCC for protected mode 3.5 4 4.25 V VHYS(UVCC) Hysteresis voltage on UVCC 200 mV UVVIO Rising undervoltage detection on VIO (Devices with VIO) 1.56 1.65 V Falling undervoltage detection on VIO (Devices with VIO) 1.4 1.51 1.59 V VHYS(UVIO) Hysteresis voltage on UVIO 40 mV www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7.7 Dissipation Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Average power dissipation Normal mode VCC = 5 V, VIO = 1.8 V, TJ = 27°C, RL = 60 Ω, CL_RXD = 15 pF TXD input = 250 kHz 50% duty cycle square wave 95 mW VCC = 5 V, VIO = 3.3 V, TJ = 27°C, RL = 60 Ω, CL_RXD = 15 pF TXD input = 250 kHz 50% duty cycle square wave 95 mW VCC = 5 V, VIO = 5 V, TJ = 27°C, RL = 60 Ω, CL_RXD = 15 pF TXD input = 250 kHz 50% duty cycle square wave 95 mW VCC = 5.5 V, VIO = 1.8 V, TJ = 150°C, RL = 60Ω, CL_RXD = 15 pF TXD input = 2.5 MHz 50% duty cycle square wave 120 mW VCC = 5.5 V, VIO = 3.3 V, TJ = 150°C, RL = 60 Ω, CL_RXD = 15 pF TXD input = 2.5 MHz 50% duty cycle square wave 120 mW VCC = 5.5 V, VIO = 5 V, TJ = 150°C, RL = 60 Ω, CL_RXD = 15 pF TXD input = 2.5 MHz 50% duty cycle square wave 120 mW TTSD Thermal shutdown temperature 175 195 210 TTSD(HYS) Thermal shutdown hysteresis 12

7.8 Electrical Characteristics

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver Electrical Characteristics VO(DOM) Dominant output voltage Normal mode CANH STB = 0 V, TXD = 0 V 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open See Figure 8-2 and Figure 9-3 2.75 4.5 V CANL 0.5 2.25 V VO(REC) Recessive output voltage Normal mode CANH and CANL STB = 0 V, TXD = VIO RL = open (no load), RCM = open See Figure 8-2 and Figure 9-3 2 0.5 VCC 3 V VSYM Driver symmetry (VO(CANH) + VO(CANL))/VCC STB = 0 V, TXD = 250 kHz, 1 MHz, 2.5 MHz RL = 60 Ω, CSPLIT = 4.7 nF, CL = open, RCM = open See Figure 8-2 and Figure 10-2 0.9 1.1 V/V VSYM_DC DC output symmetry (VCC - VO(CANH) - VO(CANL)) STB = 0 V RL = 60 Ω, CL = open See Figure 8-2 and Figure 9-3 –400 400 mV VOD(DOM) Differential output voltage Normal mode Dominant CANH - CANL STB = 0 V, TXD = 0 V 50 Ω ≤ RL ≤ 65 Ω, CL = open See Figure 8-2 and Figure 9-3 1.5 3 V STB = 0 V, TXD = 0 V 45 Ω ≤ RL ≤ 70 Ω, CL = open See Figure 8-2 and Figure 9-3 1.4 3.3 V STB = 0 V, TXD = 0 V RL = 2240 Ω, CL = open See Figure 8-2 and Figure 9-3 1.5 5 V VOD(REC) Differential output voltage Normal mode Recessive CANH - CANL STB = 0 V, TXD = VIO RL = 60 Ω, CL = open See Figure 8-2 and Figure 9-3 –120 12 mV STB = 0 V, TXD = VIO RL = open, CL = open See Figure 8-2 and Figure 9-3 –50 50 mV TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7.8 Electrical Characteristics (continued)

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO(STB) Bus output voltage Standby mode CANH STB = VIO RL = open See Figure 8-2 and Figure 9-3 -0.1 0.1 V CANL -0.1 0.1 V CANH - CANL -0.2 0.2 V IOS(SS_DOM) Short-circuit steady-state output current, dominant Normal mode STB = 0 V, TXD = 0 V V(CANH) = -15 V to 40 V, CANL = open See Figure 8-7 and Figure 9-3 –115 mA STB = 0 V, TXD = 0 V V(CAN_L) = -15 V to 40 V, CANH = open See Figure 8-7 and Figure 9-3 115 mA IOS(SS_REC) Short-circuit steady-state output current, recessive Normal mode STB = 0 V, TXD = VIO –27 V ≤ VBUS ≤ 32 V, where VBUS = CANH = CANL See Figure 8-7 and Figure 9-3 –5 5 mA Receiver Electrical Characteristics VIT Input threshold voltage Normal mode STB = 0 V -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 500 900 mV VIT(STB) Input threshold Standby mode STB = VIO -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 400 1150 mV VDOM Dominant state differential input voltage range Normal mode STB = 0 V -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 0.9 9 V VREC Recessive state differential input voltage range Normal mode STB = 0 V -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 -4 0.5 V VDOM(STB) Dominant state differential input voltage range Standby mode STB = VIO -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 1.15 9 V VREC(STB) Recessive state differential input voltage range Standby mode STB = VIO -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 -4 0.4 V VHYS Hysteresis voltage for input threshold Normal mode STB = 0 V -12 V ≤ VCM ≤ 12 V See Figure 8-3 and Table 9-6 115 mV VCM Common-mode range Normal and standby modes See Figure 8-3 and Table 9-6 –12 12 V ILKG(IOFF) Unpowered bus input leakage current CANH = CANL = 5 V, VCC = VIO = GND 5 µA CI Input capacitance to ground (CANH or CANL) TXD = VIO (1) 20 pF CID Differential input capacitance 10 pF RID Differential input resistance STB = 0 V, TXD = VIO (1) -12 V ≤ VCM ≤ 12 V 40 90 kΩ RIN Single-ended input resistance (CANH or CANL) 20 45 kΩ RIN(M) Input resistance matching [1 – (RIN(CANH) / RIN(CANL))] × 100 % V(CAN_H) = V(CAN_L) = 5 V –1 1 % TXD Terminal (CAN Transmit Data Input) VIH High-level input voltage Devices without VIO 0.7 VCC V VIH High-level input voltage Devices with VIO 0.7 VIO V VIL Low-level input voltage Devices without VIO 0.3 VCC V VIL Low-level input voltage Devices with VIO 0.3 VIO V IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µA IIL Low-level input leakage current TXD = 0 V VCC= VIO = 5.5 V –200 -100 –20 µA ILKG(OFF) Unpowered leakage current TXD = 5.5 V VCC= VIO = 0 V –1 0 1 µA CI Input capacitance VIN = 0.4×sin(2×π×2×106×t)+2.5 V 5 pF RXD Terminal (CAN Receive Data Output) www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IO = –2 mA Devices without VIO See Figure 8-3

0.8 VCC V

VOH High-level output voltage IO = –1.5 mA Devices with VIO See Figure 8-3

0.8 VIO V

VOL Low-level output voltage IO = 2 mA Devices without VIO See Figure 8-3

0.2 VCC V

VOL Low-level output voltage IO = 1.5mA Devices with VIO See Figure 8-3

0.2 VIO V

ILKG(OFF) Unpowered leakage current RXD = 5.5 V VCC = VIO = 0 V –1 0 1 µA STB Terminal (Standby Mode Input) VIH High-level input voltage Devices without VIO 0.7 VCC V VIH High-level input voltage Devices with VIO 0.7 VIO V VIL Low-level input voltage Devices without VIO 0.3 VCC V VIL Low-level input voltage Devices with VIO 0.3 VIO V IIH High-level input leakage current VCC = VIO = STB = 5.5 V –2 2 µA IIL Low-level input leakage current STB = 0 V VCC = VIO = 5.5 V, –20 –2 µA ILKG(OFF) Unpowered leakage current STB = 5.5V VCC = VIO = 0 V –1 0 1 µA (1) VIO = VCC in non-V variants of device

7.9 Switching Characteristics

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Device Switching Characteristics tPROP(LOOP1) Total loop delay Driver input (TXD) to receiver output (RXD), recessive to dominant STB = 0 V, VIO = 2.8 V to 5.5 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-4 125 210 ns tPROP(LOOP1) Total loop delay Driver input (TXD) to receiver output (RXD), recessive to dominant STB = 0 V, VIO = 1.7 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-4 165 255 ns tPROP(LOOP2) Total loop delay Driver input (TXD) to receiver output (RXD), dominant to recessive STB = 0 V, VIO = 2.8 V to 5.5 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-4 150 210 ns tPROP(LOOP2) Total loop delay Driver input (TXD) to receiver output (RXD), dominant to recessive STB = 0 V, VIO = 1.7 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-4 180 255 ns tMODE Mode change time, from normal to standby or from standby to normal See Figure 8-5 20 µs tWK_FILTER Filter time for a valid wake-up pattern See Figure 9-5 0.5 1.8 µs tWK_TIMEOUT Bus wake-up timeout 0.8 6 ms Driver Switching Characteristics tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) STB = 0 V RL = 60 Ω, CL = 100 pF See Figure 8-2 80 ns tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 70 ns tsk(p) Pulse skew (|tpHR - tpLD|) 14 ns tR Differential output signal rise time 28 ns tF Differential output signal fall time 50 ns tTXD_DTO Dominant timeout See Figure 8-6 1.2 4.0 ms TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7.9 Switching Characteristics (continued)

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver Switching Characteristics tpRH Propagation delay time, bus recessive input to high output (dominant to recessive) STB = 0 V CL(RXD) = 15 pF See Figure 8-3 81 ns tpDL Propagation delay time, bus dominant input to low output (recessive to dominant) 66 ns tR RXD output signal rise time 10 ns tF RXD output signal fall time 10 ns FD Timing Characteristics tBIT(BUS) Bit time on CAN bus output pins tBIT(TXD) = 500 ns STB = 0 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 8-4 450 525 ns Bit time on CAN bus output pins tBIT(TXD) = 200 ns 160 205 ns Bit time on CAN bus output pins tBIT(TXD) = 125 ns(1) 85 130 ns tBIT(RXD) Bit time on RXD output pins tBIT(TXD) = 500 ns 410 540 ns Bit time on RXD output pins tBIT(TXD) = 200 ns 130 210 ns Bit time on RXD output pins tBIT(TXD) = 125 ns(1) 75 135 ns ΔtREC Receiver timing symmetry tBIT(TXD) = 500 ns -50 20 ns Receiver timing symmetry tBIT(TXD) = 200 ns -40 10 ns Receiver timing symmetry tBIT(TXD) = 125 ns(1) -40 10 ns (1) Measured during characterization and not an ISO 11898-2:2016 parameter. www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

7.10 Typical Characteristics

Temperature ( °C) V OD(DOM) (V) -40 -20 0 20 40 60 80 100 120 140 160 1.5 1.7 1.9 2.1 2.3 2.5 VCC = 5 V VIO = 3.3 V RL = 60 Ω Figure 7-1. VOD(DOM) vs Temperature VCC (V) V OD(DOM) (V) 1.5 2.5 Temp = 25°C RL = 60 Ω Figure 7-2. VOD(DOM) vs VCC Temperature ( °C) ICC (mA) -40 -20 0 20 40 60 80 100 120 140 160 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25 VCC = 5 V VIO = 3.3 V RL = 60 Ω Figure 7-3. ICC Standby vs Temperature Temperature ( °C) IIO (mA) -40 -20 0 20 40 60 80 100 120 140 160 VCC = 5 V VIO = 3.3 V RL = 60 Ω Figure 7-4. IIO Standby vs Temperature TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

8 Parameter Measurement Information

Figure 8-1. ICC Test Circuit VODRL CANH CANL TXD RCM RCM VCMCL TXD 0.9V 0.5V VOD tpLD tpHR 50% 50% VO(CANH) VO(CANL) 10% tR tF 90% 0V VCC Figure 8-2. Driver Test Circuit and Measurement VO CL_ RXD CANH RXD CANL VID VID 0.5V 0.9V 1.5V VO(RXD ) 50% VOH VOL tpD L tpR H 90% 10% tR tF IO Figure 8-3. Receiver Test Circuit and Measurement www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

70% 70% 30% 30% 30% VI 0 V 500 mV 900 mV VDIFF RL CANH CANL TXD CL VO CL_RXD RXD VI

0 V STB

tBIT(RXD) tLOOP2 tBIT(BUS) tBIT(TXD)5 x tBIT(TXD) tLOOP1 Figure 8-4. Transmitter and Receiver Timing Test Circuit and Measurement RL CANH CANL TXD CL VO CL_RXD RXD STBVI tMODE STB RXD VOH VOL VIH 50% 50% Figure 8-5. tMODE Test Circuit and Measurement TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9 Detailed Description

9.1 Overview

The TCAN1044A(V)-Q1 devices meet or exceed the specifications of the ISO 11898-2:2016 high speed CAN (Controller Area Network) physical layer standard. The devices have been certified to the requirements of ISO 11898-2:2016 physical layer requirements according to the GIFT/ICT high speed CAN test specification. The transceivers provide a number of different protection features making them ideal for the stringent automotive system requirements while also supporting CAN FD data rates up to 8 Mbps. The TCAN1044A(V)-Q1 support the following CAN and CAN FD standards:

Physical layer: – ISO 11898-2:2016 High speed medium access unit – ISO 11898-5:2007 High speed medium access unit with low-power mode – SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps – SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps – SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps – SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps – SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps
EMC Requirements – IEC 62228-3 EMC evaluation of transceivers - CAN transceivers – VeLIO (Vehicle LAN Interoperability and Optimization) CAN and CAN-FD Transceiver Requirements – SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
Conformance test requirements: – ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed medium access unit conformance test plan TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9.2 Functional Block Diagram

Figure 9-1. Block Diagram

9.3 Feature Description

9.3.1 Pin Description

9.3.1.1 TXD

The TXD input is a logic-level signal, referenced to either VCC or VIO from a CAN controller to the transceiver.

9.3.1.2 GND

GND is the ground pin of the transceiver. The pin must be connected to the PCB ground.

9.3.1.3 VCC

VCC provides the 5-V power supply to the CAN transceiver. www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9.3.1.4 RXD

RXD is the logic-level signal, referenced to either V CC or VIO, from the TCAN1044A-Q1 to a CAN controller. This pin is only driven once VIO is present.

9.3.1.5 VIO

The VIO pin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement for a level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.

9.3.1.6 CANH and CANL

The CANH and CANL pins are the CAN high and CAN low differential bus pins. These pins are internally connected to the CAN transmitter, receiver and the low-power wake-up receiver.

9.3.1.7 STB (Standby)

The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either the system processor or from a static system voltage source. If normal mode is the only intended mode of operation, the STB pin can be tied directly to GND.

9.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 9-2 and Figure 9-3. A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to V CC/2 via the high-resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins. A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver. The TCAN1044A(V)-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 9-2 and Figure 9-3. Recessive Dominant Recessive Time, t Typical Bus Voltage Normal Mode Standby Mode CANL CANH VDIFF VDIFF Figure 9-2. Bus States TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

2.5V A B GND CANL CANH RXD A. A - Normal Mode B - Standby Mode Figure 9-3. Simplified Recessive Common Mode Bias Unit and Receiver

9.3.3 TXD Dominant Timeout (DTO)

During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the timeout period t TXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the timeout period of the circuit, t TXD_DTO, the CAN driver is disabled. This frees the bus for communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to V CC/2 and the RXD output reflects the activity on the CAN bus during the TXD DTO fault. The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. The minimum transmitted data rate may be calculated using Equation 1. Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps (1) Normal CAN communication CAN Bus Signal TXD fault stuck dominant: example PCB failure or bad software Fault is repaired & transmission capability restored TXD (driver) %XVZRXOGEH³VWXFNGRPLQDQW´EORFNLQJFRPPXQLFDWLRQIRUWKHZKROHQHWZRUNEXW7;''72 prevents this and frees the bus for communication after the time tTXD_DTO. tTXD_DTO Communication from local node Communication from repaired node RXD (receiver) Communication from other bus node(s) Communication from repaired local node Communication from other bus node(s) tTXD_DTO Driver disabled freeing bus for other nodes Figure 9-4. Example Timing Diagram for TXD Dominant Timeout

9.3.4 CAN Bus short-circuit current limiting

The TCAN1044A(V)-Q1 has several protection features that limit the short-circuit current when a CAN bus line is shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state timeout which prevents permanently having the higher short-circuit current of a dominant state in case of www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

a system fault. During CAN communication the bus switches between the dominant and recessive states, thus the short-circuit current may be viewed as either the current during each bus state or as a DC average current. When selecting termination resistors or a common-mode choke for the CAN design the average power rating, IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of dominant bits. The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short-circuit currents. The average short-circuit current may be calculated using Equation 2. IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC] (2) Where:

IOS(AVG) is the average short-circuit current
% Transmit is the percentage the node is transmitting CAN messages
% Receive is the percentage the node is receiving CAN messages
% REC_Bits is the percentage of recessive bits in the transmitted CAN messages
% DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short-circuit current
IOS(SS)_DOM is the dominant steady state short-circuit current This short circuit current and the possible fault cases of the network should be taken into consideration when sizing the power supply used to generate the transceivers VCC supply.

9.3.5 Thermal Shutdown (TSD)

If the junction temperature of the TCAN1044A(V)-Q1 exceeds the thermal shutdown threshold, T TSD, the device turns off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared when the junction temperature of the device drops below T TSD. The CAN bus pins are biased to V CC/2 during a TSD fault and the receiver to RXD path remains operational. The TCAN1044A(V)-Q1 TSD circuit includes hysteresis which prevents the CAN driver output from oscillating during a TSD fault.

9.3.6 Undervoltage Lockout

The supply pins, V CC and V IO, have undervoltage detection that places the device into a protected state. This protects the bus during an undervoltage event on either supply pin. Table 9-1. Undervoltage Lockout - TCAN1044A-Q1 VCC DEVICE STATE BUS RXD PIN > UVVCC Normal Per TXD Mirrors bus < UVVCC Protected High impedance High impedance Table 9-2. Undervoltage Lockout - TCAN1044AV-Q1 VCC VIO DEVICE STATE BUS RXD PIN > UVVCC > UVVIO Normal Per TXD Mirrors bus < UVVCC > UVVIO STB = High: Standby Mode Weak biased to GND VIO: Remote wake request See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode STB =Low: Protected Mode High impedance Recessive > UVVCC < UVVIO Protected High impedance High impedance < UVVCC < UVVIO Protected High impedance High impedance Once the undervoltage condition is cleared and t MODE has expired the TCAN1044A-Q1 will transition to normal mode and the host controller can send and receive CAN traffic again TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9.3.7 Unpowered Device

The TCAN1044A(V)-Q1 is designed to be an ideal passive or no load to the CAN bus if the device is unpowered. The bus pins were designed to have low leakage currents when the device is unpowered, so they do not load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains operational. The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits which may remain powered.

9.3.8 Floating pins

The TCAN1044A(V)-Q1 has internal pull-ups on critical pins which place the device into known states if the pin floats. This internal bias should not be relied upon by design though, especially in noisy environments, but instead should be considered a failsafe protection feature. When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be chosen. This ensures that the TXD output of the CAN controller maintains acceptable bit time to the input of the CAN transceiver. See Table 9-3 for details on pin bias conditions. Table 9-3. Pin Bias Pin Pull-up or Pull-down Comment TXD Pull-up Weakly biases TXD towards recessive to prevent bus blockage or TXD DTO triggering STB Pull-up Weakly biases STB towards low-power standby mode to prevent excessive system power

9.4 Device Functional Modes

9.4.1 Operating Modes

The TCAN1044A(V)-Q1 has two main operating modes; normal mode and standby mode. Operating mode selection is made by applying a high or low level to the STB pin. Table 9-4. Operating Modes STB Device Mode Driver Receiver RXD Pin High Low current standby mode with bus wake-up Disabled Low-power receiver and bus monitor enable High (recessive) until valid WUP is received See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode Low Normal Mode Enabled Enabled Mirrors bus state

9.4.2 Normal Mode

This is the normal operating mode of the TCAN1044A(V)-Q1. The CAN driver and receiver are fully operational and CAN communication is bi-directional. The driver is translating a digital input on the TXD input to a differential output on the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL to a digital output on the RXD output.

9.4.3 Standby Mode

This is the low-power mode of the TCAN1044A(V)-Q1. The CAN driver and main receiver are switched off and bi-directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure 9-5. The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device to normal mode by pulling the STB pin low. The CAN bus pins are weakly pulled to GND in this mode; see Figure 9-2 and Figure 9-3. In standby mode, only the V IO supply is required therefore the V CC may be switched off for additional system level current savings. www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

The TCAN1044A(V)-Q1 supports a remote wake-up request that is used to indicate to the host controller that the bus is active and the node should return to normal operation. The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1044A(V)-Q1. The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low every time an additional filtered dominant signal is received from the bus. For a dominant or recessive to be considered filtered, the bus must be in that state for more than the tWK_FILTER time. Due to variability in t WK_FILTER the following scenarios are applicable. Bus state times less than tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be generated. Bus state times greater than t WK_FILTER(MAX) are always detected as part of a WUP, and thus a wake request is always generated. See Figure 9-5 for the timing diagram of the wake-up pattern. The pattern and t WK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing false wake-up requests while allowing any valid message to initiate a wake-up request. The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The t WK_FILTER timing for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP. For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this section. See Figure 9-5 for the timing diagram of the wake-up pattern with wake timeout feature. Bus VDiff tWK_FILTER tWK_FILTER tWK_FILTER Bus Filtered Dominant Filtered Dominant Filtered Recessive Wake Up Pattern (WUP) received in t < tWK_Timeout RXD tWK_FILTER Filtered Dominant RXD Output Bus Wake Via RXD Requests Bus Wake via RXD Request Waiting for Filtered Recessive Waiting for Filtered Dominant Figure 9-5. Wake-Up Pattern (WUP) with tWK_TIMEOUT TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

9.4.4 Driver and Receiver Function

The TCAN1044A-Q1 logic I/Os support CMOS levels with respect to either V CC for 5-V systems (TCAN1044A- Q1) or VIO for compatibility with MCUs that support 1.8-V, 2.5-V, 3.3-V, or 5-V systems (TCAN1044AV-Q1). Table 9-5. Driver Function Table Device Mode TXD Input(1) Bus Outputs Driven Bus State(2) CANH CANL Normal Low High Low Dominant High or open High impedance High impedance Biased recessive Standby X High impedance High impedance Biased to ground (1) X = irrelevant (2) For bus state and bias see Figure 9-2 and Figure 9-3 Table 9-6. Receiver Function Table Normal and Standby Mode Device Mode CAN Differential Inputs VID = VCANH – VCANL Bus State RXD Pin Normal VID ≥ 0.9 V Dominant Low 0.5 V < VID < 0.9 V Undefined Undefined VID ≤ 0.5 V Recessive High Standby VID ≥ 1.15 V Dominant High Low if a remote wake event occurred See Figure 9-5 0.4 V < VID < 1.15 V Undefined VID ≤ 0.4 V Recessive Any Open (VID ≈ 0 V) Open High www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

10.2 Typical Application

The TCAN1044A(V)-Q1 transceiver can be used in applications with a host controller or FPGA that includes the link layer portion of the CAN protocol. Figure 10-1 shows a typical configuration for 5-V controller applications. The bus termination is shown for illustrative purposes. TCAN1044A STB RXD TXD CANH CANL VCC Port x RXD TXD 5-V Voltage Regulator VIN VOUT GND VIN Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD NC CAN FD Controller 3 5 Figure 10-1. Transceiver Application Using 5-V IO Connections

10.2.1 Design Requirements

10.2.1.1 CAN Termination

Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used, see Figure 10-2. Split termination improves the electromagnetic emissions behavior of the network by filtering higher-frequency common-mode noise that may be present on the differential signal lines. TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

Standard Termination Split Termination CSPLIT TCAN Transceiver CANL CANH TCAN Transceiver CANL CANH RTERM/2 RTERM RTERM/2 Figure 10-2. CAN Bus Termination Concepts

10.2.2 Detailed Design Procedures

10.2.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1044A(V)-Q1 Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO 11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE J2284, SAE J1939, and NMEA 2000. A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output must be greater than 1.5 V. The TCAN1044A(V)-Q1 family is specified to meet the 1.5-V requirement down to 50 Ω and is specified to meet 1.4-V differential output at 45- Ω bus load. The differential input resistance of the TCAN1044A(V)-Q1 is a minimum of 40 k Ω. If 100 TCAN1044A(V)-Q1 transceivers are in parallel on a bus, this is equivalent to a 400- Ω differential load in parallel with the nominal 60- Ω bus termination which gives a total bus load of approximately 52 Ω. Therefore, the TCAN1044A(V)-Q1 family theoretically supports over 100 transceivers on a single bus segment. However, for a CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets, and signal integrity thus a practical maximum number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate. This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility the CAN network system designer must take the responsibility of good network design to ensure robust network operation. Please refer to the application report SLLA270: Controller Area Network Physical layer requirements . This document discusses in detail all system design physical layer parameters. www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

(with termination) RTERM RTERM System Controller CAN FD Controller TCAN1043-Q1 Node 2 System Controller CAN FD Controller TCAN1044AV-Q1 Node 3 System Controller CAN FD Controller TCAN1044A-Q1 Figure 10-3. Typical CAN Bus

10.3 System Examples

The TCAN1044AV-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that The bus termination is shown for illustrative purposes. TCAN1044AV STB RXD TXD CANH CANL VCC Port x RXD TXD 5-V Voltage Regulator VIN VOUT GND Optional: Terminating Node Optional: Filtering, Transient and ESD MCU VDD CAN FD Controller 1.8 V / 2.5 V / 3.3 V Regulator VBAT VIN VIO VOUT Figure 10-4. Typical Transceiver Application Using 1.8-V, 2.5-V, 3.3-V IO Connections

11 Power Supply Recommendations

The TCAN1044A-Q1 transceiver is designed to operate with a main V CC input voltage supply range between 4.5 V and 5.5 V. The TCAN1044AV-Q1 implements an IO level shifting supply input, VIO, designed for a range between 1.8 V and 5.5 V. Both the V CC and V IO inputs must be well regulated. In addition to the power supply filtering a decoupling capacitance, typically 100 nF, should be placed near the CAN transceiver's main VCC and VIO supply pins. TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

12 Layout

Robust and reliable CAN node design may require special layout techniques depending on the application and design requirements. Since transient disturbances have high frequency content and a wide bandwidth, high-frequency layout techniques should be applied during PCB design.

12.1 Layout Guidelines

Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and noise from propagating onto the board. This layout example shows a optional transient voltage suppression (TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize trace and via inductance. Note High-frequency current follows the path of least impedance and not the path of least resistance.
This layout example shows how split termination could be implemented on the CAN node. The termination is split into two resistors, R2 and R3, with the center or split tap of the termination connected to ground via 9.3.4, and Equation 2 for information on termination concepts and power ratings needed for the termination resistor(s).

12.2 Layout Example

µC V Choke STB VIO µC V Figure 12-1. Layout Example www.ti.com TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCAN1044A-Q1, TCAN1044AV-Q1 SLLSFJ3B – FEBRUARY 2021 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1044A-Q1 TCAN1044AV-Q1

www.ti.com 16-Nov-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTCAN1044ADDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 150 PTCAN1044ADRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 PTCAN1044AVDDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 150 PTCAN1044AVDRQ1 ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 150 TCAN1044AVDDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 2HHF TCAN1044AVDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 1044AV TCAN1044AVDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 1044AV (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 16-Nov-2021 Addendum-Page 2 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TCAN1044AVDDFRQ1 SOT- 23-THIN PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2021 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCAN1044AVDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TCAN1044AVDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0 TCAN1044AVDRQ1 SOIC D 8 2500 853.0 449.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2021 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP2.95 2.65

1.1 MAX

6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225036/A 06/2019 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRB0008J A 0.08 C 0.05 C B SYMM SYMM PIN 1 INDEX AREA 3.1 2.9 3.1 2.9

1 MAX

0.05 0.00 SEATING PLANE C SECTION A-A TYPICAL (0.13)

0.1 MIN

1.75 1.55 (0.2) TYP (0.19) 8X 0.36 0.26 2.5 2.3 6X 0.65 1.95 8X 0.5 0.3 PIN 1 ID (OPTIONAL)

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

0.07 MAX

0.07 MIN

(1.65) (2.4) (2.8) (0.95) (0.575) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP (Ø 0.2) VIA TYP

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (1.51) (1.06) (2.8) (0.63) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP METAL TYP

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICA TION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety , security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for , and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021, Texas Instruments Incorporated

Product Information