PTCA9847RGER

TCA9847_V01 TI2 | Alldatasheet

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Technical content

TCA9847 Ultra Low-Voltage 8-Channel 1MHz Capable I2C Multiplexer

1 Features

• 1-to-8 bidirectional translating multiplexer with ultra low voltage translation down to 0.65V
• I2C Bus and SMBus compatible
• Active-low reset input
• Two address pins, allowing up to 16 devices on the I2C bus
• Channel selection through an I2C Bus, in any combination
• Power up with all switch channels deselected
• Low RON switches
• Allows voltage-level translation between 0.65V,
• No glitch on power up
• Supports hot insertion
• Low standby current
• Operating power-supply voltage range of 1.65V to 3.6V
• 3.6V tolerant inputs
• 0 to 1MHz clock frequency
• Latch-up performance exceeds 100mA per JESD 78, class II
• ESD protection exceeds JESD 22 – ±2000V human-body model (A114-A) – ±500V charged-device model (C101)

2 Applications

• Servers
• Routers (telecom switching equipment)
• Factory automation
• Products with I2C target address conflicts (such as multiple, identical temperature sensors)

3 Description

The TCA9847 device is an 8-channel, bidirectional translating multiplexer that can be controlled through the I2C bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. These downstream channels can be used to resolve I 2C target address conflicts. For example, if eight identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0-7. The system controller can reset the TCA9847 in the event of a time-out, or other improper operation by asserting a low in the RESET input. Similarly, the power-on reset deselects all channels and initializes the I 2C/SMBus state machine. Asserting RESET causes the same reset and initialization to occur without powering down the part. This allows recovery if one of the downstream I 2C buses get stuck in a low state. The pass gates of the switches are constructed so that VDD1/VDD2 pins can be used to limit the maximum high voltage, which is passed by the TCA9847. Limiting the maximum high voltage allows the use of different bus voltages on each pair, so that 0.65V, 0.8V, 1.2V, or 1.8V parts can communicate with 3.3V parts, without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 3.6V tolerant.

Package Information

PART NUMBER PACKAGE (1) PACKAGE SIZE(2) TCA9847 PW (TSSOP, 24) 7.8mm × 6.4mm RGE (VQFN, 24) 4mm × 4mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. VDD1 TCA984x SDA SCL SD0 SC0 SD7 SC7 GND I2C Controller Targets A1 , A2 …….. AN Targets H1 , H2 …….. HN Note: Pull up resistors omitted for simplicity VDD2 #RESET Simplified Application Diagram ADVANCE INFORMATION TCA9847 SLVSLJ4 – APRIL 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. PW Package, 24-Pin TSSOP (Top View) SD0 1 Not to Scale SC0 SD1 SC1 SD2 SC2 SD3 SC3 GND SD4 SC4 SD5 SC513 SD614 SC615

16 SD7

17 SC7

Figure 4-2. RGE Package, 24-Pin VQFN (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME TSSOP,(PW) VQFN (RGE) A0 2 23 I Address input 0. Connect directly to VDD2 or ground. A1 21 18 I Address input 1. Connect directly to VDD2 or ground. VDD1 1 22 Power Logic level power supply VDD2 24 21 Power Core logic power supply RESET 3 24 I Active-low reset input. Connect to VDD2 or VDPUM (2) through a pullup resistor, if not used. SD0 4 1 I/O Serial data 0. Connect to VDPU0 (2) through a pullup resistor. SC0 5 2 I/O Serial clock 0. Connect to VDPU0 (2) through a pullup resistor. SD1 6 3 I/O Serial data 1. Connect to VDPU1 (2) through a pullup resistor. SC1 7 4 I/O Serial clock 1. Connect to VDPU1 (2) through a pullup resistor. SD2 8 5 I/O Serial data 2. Connect to VDPU2 (2) through a pullup resistor. SC2 9 6 I/O Serial clock 2. Connect to VDPU2 (2) through a pullup resistor. SD3 10 7 I/O Serial data 3. Connect to VDPU3 (2) through a pullup resistor. SC3 11 8 I/O Serial clock 3. Connect to VDPU3 (2) through a pullup resistor. SD4 13 10 I/O Serial data 4. Connect to VDPU4 (2) through a pullup resistor. SC4 14 11 I/O Serial clock 4. Connect to VDPU4 (2) through a pullup resistor. SD5 15 12 I/O Serial data 5. Connect to VDPU5 (2) through a pullup resistor. SC5 16 13 I/O Serial clock 5. Connect to VDPU5 (2) through a pullup resistor. SD6 17 14 I/O Serial data 6. Connect to VDPU6 (2) through a pullup resistor. SC6 18 15 I/O Serial clock 6. Connect to VDPU6 (2) through a pullup resistor. SD7 19 16 I/O Serial data 7. Connect to VDPU7 (2) through a pullup resistor. SC7 20 17 I/O Serial clock 7. Connect to VDPU7 (2) through a pullup resistor. SCL 22 19 I/O Serial clock bus. Connect to VDPUM (2) through a pullup resistor. SDA 23 20 I/O Serial data bus. Connect to VDPUM (2) through a pullup resistor. www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA9847 ADVANCE INFORMATION

Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME TSSOP,(PW) VQFN (RGE) GND 12 9 — Supply ground (1) I = input, O = output (2) VDPUX is the pullup reference voltage for the associated data line. VDPUM is the controller I2C reference voltage and VDPU0-VDPU7 are the target channel reference voltages. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage –0.5 4 V VI Input voltage(2) –0.5 4 V II Input current –20 20 mA IO Output current –25 25 mA ICC Supply current –100 100 mA Tamb Ambient Temperature Ambient Temperature -40 125 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input negative-voltage and output voltage ratings can be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

Tamb = –40°C to 125°C; unless otherwise specified MIN TYP MAX UNIT VDD1 Supply voltage 1 0.65 3.6 V VDD2 Supply voltage 2 1.65 3.6 V IDD (VDD2) Supply Current on VDD2 VDD1 = 3.6; VDD2 = 3.6; SC0-7 and SD0-7 is not connected; RESET = VDD1; A0=A1=SCL; continuous register read/write IDD (VDD2) Supply Current on VDD2 SCL = 0 kHz 5 12 μA IDD (VDD2) Supply Current on VDD2 SCL = 100 kHz 8 20 μA IDD (VDD2) Supply Current on VDD2 SCL = 1000 kHz 65 150 μA IDD (VDD1) Supply Current on VDD1 VDD1 = 3.6; VDD2 = 3.6; SC0-7 and SD0-7 is not connected; RESET = VDD1; A0=A1=SCL; continuous register read/write SCL = 0kHz –5 –2 +2 μA SCL = 100kHz 5 15 μA SCL = 1000kHz 45 100 μA VPOR Power-On Reset Voltage 1.2 1.5 V TA Operating free-air temperature –40 125 °C www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA9847 ADVANCE INFORMATION

5.4 Thermal Information

THERMAL METRIC(1) TCA984x UNITPW(TSSOP) RGE(VQFN)

24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance TBD TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance TBD TBD °C/W RθJB Junction-to-board thermal resistance TBD TBD °C/W ΨJT Junction-to-top characterization parameter TBD TBD °C/W ΨJB Junction-to-board characterization parameter TBD TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance TBD TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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5.5 Electrical Characteristics (Global)

TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Recommended Supply Sequencing and Ramp Rates (dV/dt)f fall rate of change of voltage –40°C to +125°C 0.1 2000 ms (dV/dt)r rise rate of change of voltage –40°C to +125°C 0.1 2000 ms td(rst) reset delay time –40°C to +125°C 10 us ΔVDD(gl) glitch supply voltage difference –40°C to +125°C 1 V tw(gl)VDD supply voltage glitch pulse width –40°C to +125°C 10 us VPOR(trip) power-on reset trip voltage Falling VDD2 –40°C to +125°C 0.7 V Rising VDD2 –40°C to +125°C 1.5 V SCL/SDA VIH Logic voltage high –40°C to +125°C 0.7VDD1 3.6 V VIL Logic voltage low –40°C to +125°C –0.5 +0.3VD V IOL LOW-level output current VOL = 0.4V –40°C to +125°C 20 mA IIL Input leakage current VI = VDD or 0 –40°C to +125°C –1 1 uA CIN Logic input capacitance VI = VSS; all channels disabled –40°C to +125°C 10 12 pF SEL Inputs: A0-A1, RESET VIH Logic voltage high –40°C to +125°C 0.7VDD1 3.6 V VIL Logic voltage low –40°C to +125°C –0.5 +0.3VD V IIL Input leakage current VI = VDD or 0 –40°C to +125°C –1 1 μA CIN Logic input capacitance VI = VSS; all channels disabled –40°C to +125°C 2 4 pF Pass Gate RON ON-state resistance VDD1 = 0.8V; VDD2 ≥ 1.65V; Vi(sw) = 0.16V; IO = 3mA –40°C to +125°C 10 24 Ω VDD1 = 0.65V; VDD2 ≥ 1.65V; Vi(sw) = 0.16V; IO = 3mA –40°C to +125°C 10 24 Ω VDD1 = 1.2V; VDD2 ≥ 1.8V; Vi(sw) = 0.24V; IO = 6mA –40°C to +125°C 7 18 Ω VDD1 > 2V; VDD2 ≥ 2.5V; Vi(sw) = 0.4V; IO = 20mA –40°C to +125°C 5 12 Ω Io(sw) Switch Output Current VDD2 = 1.65V to 3.6V; Vi(sw) = VDD1 to 3.6V; Vo(sw) = VDD1 to 3.6V –40°C to +125°C 0 100 μA IL Leakage current VI = VDD or GND –40°C to +125°C –1 +1.5 μA COFF Input/Ouput Capacitance VI = GND; all switches disables –40°C to +125°C 3 5 pF

5.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1) MIN MAX UNIT STANDARD MODE fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 μs tscl I2C clock low time 4.7 μs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0(1) μs ticr I2C input rise time 1000 ns www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA9847 ADVANCE INFORMATION

5.6 I2C Interface Timing Requirements (continued)

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1) MIN MAX UNIT ticf I2C input fall time 300 ns tocf I2C output (SDn) fall time (10pF to 400pF bus) 300 ns tbuf I2C bus free time between stop and start 4.7 μs tsts I2C start or repeated start condition setup 4.7 μs tsth I2C start or repeated start condition hold 4 μs tsps I2C stop condition setup 4 μs tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low 1 μs Cb I2C bus capacitive load 400 pF FAST MODE fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 μs tscl I2C clock low time 1.3 μs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0(1) μs ticr I2C input rise time 20 + 0.1Cb (3) 300 ns ticf I2C input fall time 20 + 0.1Cb (3) 300 ns tocf I2C output (SDn) fall time (10pF to 400pF bus) 20 + 0.1Cb (3) 300 ns tbuf I2C bus free time between stop and start 1.3 μs tsts I2C start or repeated start condition setup 0.6 μs tsth I2C start or repeated start condition hold 0.6 μs tsps I2C stop condition setup 0.6 μs tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low 1 μs Cb I2C bus capacitive load 400 pF FAST MODE PLUS fscl I2C clock frequency I2C clock frequency 0 1000 kHz tsch I2C clock high time I2C clock high time 0.26 μs tscl I2C clock low time I2C clock low time 0.5 μs tsp I2C spike time I2C spike time 50 ns tsds I2C serial-data setup time I2C serial-data setup time 100 ns tsdh I2C serial-data hold time I2C serial-data hold time 0(1) μs ticr I2C input rise time I2C input rise time 120 ns ticf I2C input fall time I2C input fall time 20 x (VDD / 5.5V) (3) 120 ns tbuf I2C bus free time between stop and start I2C bus free time between stop and start 0.5 μs tsts I2C start or repeated start condition setup I2C start or repeated start condition setup 0.26 μs tsth I2C start or repeated start condition hold I2C start or repeated start condition hold 0.26 μs tsps I2C stop condition setup I2C stop condition setup 0.6 μs tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 0.45 μs tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.45 μs tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low 0.45 μs TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1) MIN MAX UNIT Cb I2C bus capacitive load I2C bus capacitive load 550 pF (1) A device internally must provide a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL. (2) Data taken using a 1kΩ pullup resistor and 50pF load (3) Cb = total bus capacitance of one bus line in pF

5.7 Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT twrs(L) Low-level reset time 100 ns tREC(STA) Recovery time from RESET to start 0 ns

5.8 Switching Characteristics

over recommended operating free-air temperature range, CL ≤100pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tpd (1) Propagation delay time RON = 20 Ω, CL = 50pF SDA or SCL SDn or SCn 1 ns trst (2) RESET time (SDA clear) RESET SDA 500 ns (1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by anideal voltage source (zero output impedance). (2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. trst must be a minimum of tWL. www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA9847 ADVANCE INFORMATION

6 Parameter Measurement Information

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. Not all parameters and waveforms are applicable to all devices. Figure 6-1. I2C Load Circuit and Voltage Waveforms TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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0.3 V CC

SDn, SCn RL = 1 k/c87 VCC CL = 50 pF (see Note A) SDA LOAD CONFIGURATION DUT SDA VCC/2 tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. I/Os are configured as inputs. D. Not all parameters and waveforms are applicable to all devices. Figure 6-2. Reset Load Circuit and Voltage Waveforms www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA9847 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The TCA9847 is an 8-channel, bidirectional translating I 2C multiplexer. The controller SCL/SDA signal pair is directed to eight channels of target devices, SC0/SD0-SC7/SD7. Any individual downstream channel can be selected as well as any combination of the eight channels. The device offers an active-low RESET input which resets the state machine and allows the TCA9847 to recover if one of the downstream I 2C buses get stuck in a low state. The state machine of the device can also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a POR cause all channels to be deselected. The connections of the I 2C data path are controlled by the same I 2C controller device that is switched to communicate with multiple I 2C targets. After the successful acknowledgment of the target address (hardware selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected channels. The TCA9847 can also be used for voltage translation, allowing the use of different bus voltages on each achieved by using external pullup resistors to pull the bus up to the desired voltage for the controller and each target channel. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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7.2 Functional Block Diagram

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7.3 Feature Description

The TCA9847 is an 8-channel, bidirectional translating multiplexer for I 2C buses that supports standard-mode (100kHz), fast-mode (400kHz), and fast-mode-plus (1MHz) operation. The TCA9847 features I 2C control using a single 8-bit control register in which each bit controls the enabling and disabling of one of the corresponding 8 multiplexer channels for I 2C data flow. Depending on the application, voltage translation of the I 2C bus can Additionally, in the event that communication on the I 2C bus enters a fault state, the TCA9847 can be reset to resume normal operation using the RESET pin feature or by a power-on reset which results from cycling power to the device.

7.4 Device Functional Modes

7.4.1 RESET Input

The RESET input is an active-low signal that can be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of t WL, the TCA9847 resets the registers and I 2C state machine and deselects all channels. The RESET input must be connected to VCC through a pullup resistor.

7.4.2 Power-On Reset

When power is applied to the VCC pin, an internal power-on reset holds the TCA9847 in a reset condition until VCC has reached V PORR. At this point, the reset condition is released, and the TCA9847 registers and I 2C state machine are initialized to the default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below VPORF to reset the device.

7.5 Programming

7.5.1 I2C Interface

The TCA9847 has a standard bidirectional I 2C interface that is controlled by a controller device to be configured or read the status of this device. Each target on the I 2C bus has a specific device address to differentiate between other target devices that are on the same I 2C bus. Many target devices require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V CC through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I 2C lines. (See also I2C Bus Pullup Resistor Calculation application note . Data transfer can be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition (See Figure 7-1 and Figure 7-2). The following is the general procedure for a controller to access a target device: 1. If a controller wants to send data to a target:

• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition. 2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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7.5.2 Device Address

The last bit of the target address defines the operation (read or write) to be performed. When high (1), a read is selected, while a low (0) selects a write operation. Table 7-1 shows the TCA9847 address reference. Table 7-1. Address Reference INPUTS I2C BUS TARGETADDRESS A1 A0 L SCL 0xE0h (hexadecimal) L L 0xE2h (hexadecimal) L SDA 0xE4h (hexadecimal) L: H 0xE6h (hexadecimal) H SCL 0xE8h (hexadecimal) H L 0xEAh (hexadecimal) H SDA 0xECh (hexadecimal) H H 0xEEh (hexadecimal) SCL SCL 0xB0h (hexadecimal) SCL L 0xB2h (hexadecimal) SCL SDA 0xB4h (hexadecimal) SCL H 0xB6h (hexadecimal) SDA SCL 0xB8h (hexadecimal) SDA L 0xBAh (hexadecimal) SDA SDA 0xBCh (hexadecimal) SDA 1 0xBEh (hexadecimal)

7.5.3 Bus Transactions

Data must be sent to and received from the target devices, and this is accomplished by reading from or writing to registers in the target device. Registers are locations in the memory of the target which contain information, whether configuration information or some sampled data to send back to the controller. The controller must write information to these registers to instruct the target device to perform a task. While having registers in I 2C targets is common, note that not all target devices have registers. Some devices are simple and contain only 1 register, which can be written to directly by sending the register data immediately after the target address, instead of addressing a register. The TCA9847 is an example of a single-register device, which is controlled through I2C commands. Because the device has 1 bit to enable or disable a channel, there is only 1 register needed, and the controller merely writes the register data after the target address, skipping the register number.

7.5.3.1 Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. The target acknowledges, letting the controller know the target is ready. After this action, the controller starts sending the control register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates the transmission with a STOP condition. There is no limit to the number of bytes sent, but the last byte sent is what is in the register. Figure 7-3 shows an example of writing a single byte to a target register. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 A Control Register (8 bits) A P START R/W=0 ACK ACK STOP Write to one register in a device Controller controls SDA line Target controls SDA line Figure 7-3. Write to Register

7.5.3.2 Reads

Reading from a target is very similar to writing, but the controller sends a START condition, followed by the target address with the R/ W bit set to 1 (signifying a read). The target acknowledges the read request, and the controller releases the SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller becomes the controller-receiver, and the target becomes the target-transmitter. The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that the controller is ready for more data. After the controller has received the number of bytes the controller is expecting, the controller sends a NACK, signaling to the target to halt communications and release the bus. The controller follows this action up with a STOP condition. Figure 7-4 shows an example of reading a single byte from a target register. S 1 1 1 0 A2 A1 A0 1 Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 NA Control Register (8 bits) A P START R/W=1 ACK NACK STOP Controller controls SDA line Target controls SDA line Figure 7-4. Read from Control Register

7.5.4 Control Register

Following the successful acknowledgment of the address byte, the bus controller sends a command byte that is stored in the control register in the TCA9847 (see Figure 7-5). This register can be written and read through the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple SCn/SDn channels can be selected at the same time. When a channel is selected, the channel becomes active after a stop condition has been placed on the I 2C bus. This action makes sure that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA9847 ADVANCE INFORMATION

of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the TCA9847, the TCA9847 saves the last byte received. Channel□Selection□Bits□(Read/Write) Channel□1 Channel□0 Channel□2 Channel□3 Channel□4 Channel□5 Channel□6 Channel□7 B7 B6 B5 B4 B3 B2 B1 B0 Figure 7-5. Control Register Table 7-2 shows the TCA9847 Command Byte Definition. Table 7-2. Command Byte Definition CONTROL REGISTER BITS COMMAND B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X

0 Channel 0 disabled

1 Channel 0 enabled

X Channel 1 disabled

1 Channel 1 enabled

1 Channel 2 enabled

1 Channel 3 enabled

1 Channel 4 enabled

1 Channel 5 enabled

X X X X X X X Channel 6 disabled

1 Channel 6 enabled

1 Channel 7 enabled

0 0 0 0 0 0 0 0 No channel selected, power-up/reset default state

7.5.5 RESET Input

The RESET input is an active-low signal that can be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of t WL, the TCA9847 resets the registers and I 2C state machine and deselects all channels. The RESET input must be connected to VCC through a pullup resistor. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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7.5.6 Power-On Reset

When power (from 0V) is applied to VDD, an internal power-on reset holds the TCA9847 in a reset condition until VDD has reached V POR. At that point, the reset condition is released and the TCA9847 registers and I 2C state machine initialize to the default states. After that, V CC must be lowered to below V POR and then back up to the operating voltage for a power-reset cycle.

7.5.7 Software Reset

The software reset call provides a mechanism to return all devices on the I²C bus to the power-up default state by issuing a specifically formatted I²C command. This operation assumes that the I²C bus is operating correctly and that no device is holding the bus in a latched or “hung” condition. The software reset sequence is defined as the following: 1. The I²C controller issues a START condition. 2. The controller transmits the reserved General Call address '0000 000' with the R/W bit set to 0 (write). 3. A device acknowledges only when the device detects the full General Call address 0000 0000 (00h). If the R/W bit is set to 1 (read), no acknowledge is generated. 4. After the General Call address is acknowledged, the controller transmits a single data byte with the value 06h. a. The device acknowledges only when this data byte is equal to 06h. b. If the data byte is not 06h, or if more than one data byte is transmitted, the device does not acknowledge further. c. When the correct byte has been received and acknowledged, the controller must issue a STOP condition to complete the software reset sequence. At this point, the device resets the registers to the power-up default values and becomes ready for subsequent bus transactions after the required bus-free time. d. If a Repeated START condition is issued instead of a STOP, the reset is not performed. e. Any missing acknowledge from the device at any point in this sequence shall be treated by the controller as a Software Reset Abort. In such a case, the device does not initiate any register reset.

7.5.8 Device ID

The Device ID is a 24-bit (3-byte) read-only value containing the following fields:

• 12 bits: Manufacturer identifier (unique per manufacturer, for example, TI)
• 9 bits: Part number (assigned by the manufacturer)
• 3 bits: Die revision (assigned by the manufacturer) The Device ID is hardwired and accessible using the following procedure: 1. Send a START command. 2. The controller transmits the Reserved Device ID I²C address (1111 1000) with R/W = 0 (write). 3. The controller sends the target device address, with the LSB as “don’t care.” Only the matching device acknowledges. 4. Issue a Repeated START condition. a. A STOP command followed by a START command resets the target state machine and the Device ID read cannot be performed. Also, a STOP command or a Re-START command followed by an access to another target device resets the target state machine and the Device ID Read cannot be performed. 5. The controller sends the Reserved Device ID I²C address (1111 1001) with R/W = 1 (read). 6. The device transmits the Device ID in the following order: • a. First byte + 4 MSBs of second byte: Manufacturer ID (12 bits) b. 4 LSBs of second byte + 5 MSBs of third byte: Part Identification (9 bits) c. 3 LSBs of third byte: Die Revision (3 bits) 7. The controller completes the read by sending a NACK after the last byte, resetting the device’s internal state machine and then issuing a STOP command. www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA9847 ADVANCE INFORMATION

If the controller sends additional acknowledgments after the third byte, the device restarts the data sequence from the first byte. manufacturer id 1 1 1 1 1 1 1 1 1 1 1 1 Part identification 1 0 0 0 0 1 0 0 0 revision 0 0 0 Figure 7-6. Device ID S 1 1 1 1 1 0 0 0 A A7 A6 A5 A4 A3 A2 A1 0 A Sr 1 1 1 START condition R / W Don’t care Acknowledgement from one of the targets Acknowledgement from target to be identified Re Start 1 1 0 0 1 A R / W Acknowledgement from target to be identified M11 M10 M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 Acknowledgement from one of the targets Acknowledgement from target to be identified R2 R1 R0 A P Acknowledgement from target to be identified NO Acknowledgement from target to be identified Stop If more than 3 bytes are read, the target device loops back to the rst byte (manufacturer byte) and keeps sending data un l the controller generates a ‘no acknowledge’. Device ID address I2C bus target address of the device to be identified Device ID address Part identificationManufacturer name = 111111111111 Revision id Figure 7-7. Device ID Sequence TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The downstream channels are used to resolve I 2C target address conflicts. For example, if eight identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0-7. When the temperature at a specific location is read, the appropriate channel can be enabled and all other channels switched off, the data can be retrieved, and the I2C controller can move on and read the next channel. In an application where the I 2C bus contains many additional target devices that do not result in I 2C target address conflicts, these target devices can be connected to any desired channel to distribute the total bus capacitance across multiple channels. If multiple switches are enabled simultaneously, additional design requirements must be considered (see the Design Requirements section and Detailed Design Procedure section).

8.2 Typical Application

Figure 8-1 shows an application in which the TCA9847 can be used. VDD1 VDD2 VDD SDA SCL I2C/ SMBUS Controller SDA SCL SD0 SC0 SD1 SC1 SD2 SC2 SD7 SC7 RESET TCA9847 VDPU1 = 1.65V to 3.6V VDPU0 = 1.65V to 3.6V VDPU2 = 1.65V to 3.6V VDPU7 = 1.65V to 3.6V Target 0 Target 1 Target 2 Target 7 GND GND VDPUC = 0.65V to 3.6V 0.65V 1.8V Pin numbers shown are for the PW package. Figure 8-1. Typical Application Schematic www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCA9847 ADVANCE INFORMATION

8.2.1 Design Requirements

A typical application of the TCA9847 contains one or more data pullup voltages, V DPUX, one for the controller device (V DPUM) and one for each of the selectable target channels (V DPU0 – V DPU7). In the event where the controller device and all target devices operate at the same voltage, then V DPUM = V DPUX = VCC. In an application where voltage translation is necessary, additional design requirements must be considered to determine an appropriate VCC voltage. The A0, A1 pins are hardware selectable to control the target address of the TCA9847. These pins can be tied directly to GND or VCC in the application. If multiple target channels are activated simultaneously in the application, then the total I OL from SCL/SDA to GND on the controller side is the sum of the currents through all pullup resistors, Rp. The pass-gate transistors of the TCA9847 are constructed such that the V CC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. For the TCA9847 to act as a voltage translator, the V pass voltage must be equal to or lower than the lowest bus voltage.

8.2.1.1 Voltage Translation Requirements

There is no buffering capability between the upstream and the downstream buses. This is simply a pass transistor, which acts like a multiplexer and a series resistor, between these bus segment

8.2.2 Detailed Design Procedure

After all the targets are assigned to the appropriate target channels and bus voltages are identified, the pullup resistors, R p, for each of the buses need to be selected appropriately. The minimum pullup resistance is a function of VDPUX, VOL,(max), and IOL as shown in Equation 1: DPUX OL(max) p(min) OL V V R I (1) The maximum pullup resistance is a function of the maximum rise time, t r (300ns for fast-mode operation, fSCL = 400kHz) and bus capacitance, Cb as shown in Equation 2: TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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r p(max) b tR 0.8473 C u (2) The maximum bus capacitance for an I 2C bus must not exceed 400pF for fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9847, C io(OFF), the capacitance of wires, connections and traces, and the capacitance of each individual target on a given channel. If multiple channels are activated simultaneously, each of the targets on all channels contribute to total bus capacitance.

8.3 Power Supply Recommendations

Whenever the TCA9847 is powered on. the device executes a power-on reset. Make sure the power supply sequencing follows the power-on reset requirements given below. The power-on reset requirements must be followed to make sure the I2C bus logic is initialized properly.

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9847 can be reset to the default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. A power-on reset is shown in Figure 8-2. VCC Ramp-Up Time to Re-RampTimeRamp-DownVdrops below V– 50 mVCC PORF VCC_RTVCC_FT VCC_TRR VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Figure 8-2. Power-On Reset Waveform Table 8-1 specifies the performance of the power-on reset feature for TCA9847 for both types of power-on reset. Table 8-1. Recommended Supply Sequencing and Ramp Rates (1) PARAMETER MIN MAX UNIT VCC_FT Fall time See Figure 8-2 0.1 2000 ms VCC_RT Rise time See Figure 8-2 0.1 2000 ms VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50mV or when VCC drops to GND) See Figure 8-2 10 μs VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1μs See Figure 8-3 1 V VCC_GW Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC See Figure 8-3 10 μs (1) All supply sequencing and ramp rate values are measured at TA = 25°C Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (V CC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 8-3 and Table 8-1 provide more information on how to measure these specifications. www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCA9847 ADVANCE INFORMATION

TimeVCC_GH VCC_GW Figure 8-3. Glitch Width and Glitch Height VPOR is critical to the power-on reset. V POR is the voltage level at which the reset condition is released and all the registers and the I 2C/SMBus state machine are initialized to the default states. The value of V POR differs based on the VCC being lowered to or from 0. Figure 8-4 and Table 8-1 provide more details on this specification. VCCVPORRVPORF Time POR Time Figure 8-4. VPOR TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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8.4 Layout

8.4.1 Layout Guidelines

For PCB layout of the TCA9847, common PCB layout practices must be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I 2C signal speeds. Having a dedicated ground plane on an inner layer of the board is common, and pins that are connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias. By-pass and decoupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. In an application where voltage translation is not required, all V DPUX voltages and V CC can be at the same potential and a single copper plane can connect all of pullup resistors to the appropriate reference voltage. In an application where voltage translation is required, V DPUM and VDPU0 – VDPU7, can all be on the same layer of the board with split planes to isolate different voltage potentials. To reduce the total I 2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as possible and the widths of the traces must also be minimized (for example, 5-10 mils depending on copper weight).

8.4.2 Layout Example

1W min. W Figure 8-5. Layout Schematic www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCA9847 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, I2C Bus Pullup Resistor Calculation application note
• Texas Instruments, Maximum Clock Frequency of I2C Bus Using Repeaters application note
• Texas Instruments, Understanding the I2C Bus application note
• Texas Instruments, Choosing the Correct I2C Device for New Designs application note
• Texas Instruments, TCA9548AEVM EVM user's guide

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES April 2026 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TCA9847RGER VQFN RGE 24 3000 330 12.4 4.25 4.25 1.15 8 12 Q2 TCA9847PWR TSSOP PW 24 3000 330 16.4 6.95 8.30 1.60 8 16 Q1 www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCA9847 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9847RGER VQFN RGE 24 3000 346 346 33 TCA9847PWR TSSOP PW 24 3000 353 353 32 TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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11.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C22X 0.65 2X7.15 24X 0.300.19 TYP6.66.2

1.2 MAX

0.150.050.25GAGE PLANE-80 B NOTE 44.54.3 A NOTE 37.97.7 0.750.50(0.15) TYP TSSOP - 1.2 mm max heightPW0024ASMALL OUTLINE PACKAGE 4220208/A 02/2017 12 13 0.1CAB PIN 1 INDEX AREA SEE DETAIL A 0.1C SEATINGPLANE TYPICAL A 20 SCALE 2.000 DETAIL A www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCA9847 ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT 0.05 MAXALL AROUND0.05 MINALL AROUND 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024ASMALL OUTLINE PACKAGE 4220208/A 02/2017NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 10X SYMM SYMM1 12 13 15.000 METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSED METALEXPOSED METALNON-SOLDER MASKSOLDER MASK DETAILSDEFINED(PREFERRED)SOLDER MASKDEFINED TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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www.ti.com EXAMPLE STENCIL DESIGN 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024ASMALL OUTLINE PACKAGE SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE: 10X SYMM SYMM 12 13 www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCA9847 ADVANCE INFORMATION

www.ti.com 4224376 / C 07/2021 VQFN - 1 mm max heightPLASTIC QUAD FLATPACK- NO LEADRGE0024CA 0.08C 0.1CAB0.05C B SYMM SYMM 4.13.9 4.13.9PIN 1 INDEX AREA 2X2.5 20X 0.5 67 1213 181924 24X 0.300.1824X 0.500.30 (0.2) TYP PIN 1 ID(OPTIONAL) TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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www.ti.com VQFN - 1 mm max heightRGE0024CPLASTIC QUAD FLATPACK- NO LEAD SYMM SYMMLAND PATTERN EXAMPLESCALE: 20X 2X(0.8) 2X(0.8) (3.8) ( 2.1)1 6 7 1213 181924 (R0.05) SOLDER MASK DETAILSNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINED 0.07 MAXALL AROUND0.07 MINALL AROUNDMETALSOLDER MASKOPENINGSOLDER MASKOPENINGMETAL UNDERSOLDER MASK (Ø0.2) VIATYP (3.8) www.ti.com TCA9847 SLVSLJ4 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCA9847 ADVANCE INFORMATION

NOTES: (continued)6.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.. EXAMPLE STENCIL DESIGN 4224376 / C 06/2021 www.ti.com VQFN - 1 mm max heightRGE0024CPLASTIC QUAD FLATPACK- NO LEAD SYMM SYMMSOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILEXPOSED PAD80% PRINTED COVERAGE BY AREASCALE: 20X (3.8) (0.57)TYP (0.57)TYP 4X ( 0.94)1 6 7 1213 (R0.05) TYPMETALTYP 25 (3.8) TCA9847 SLVSLJ4 – APRIL 2026 www.ti.com

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www.ti.com 6-May-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTCA9847PWR Active Preproduction TSSOP (PW) | 24 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTCA9847RGER Active Preproduction VQFN (RGE) | 24 3000 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2 0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

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