PTCA39306DCUR

TCA39306 TI | Alldatasheet

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TCA39306 Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator

1 Features

• 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C applications
• Standard-mode, fast-mode, and fast-mode plus I2C and SMBus compatible
• I3C compatible (12.5 MHz supported)
• Allows voltage-level translation between – 0.9-V VREF1 and 1.8-V, 2.5-V, 3.3-V, or 5-V VREF2 – 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V, or 5-V VREF2 – 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2 – 2.5-V VREF1 and 3.3-V or 5-V VREF2 – 3.3-V VREF1 and 5-V VREF2
• Provides bidirectional voltage translation with no direction Pin
• Low ON-state resistance between input and output ports provides less signal distortion
• Open-drain I2C I/O ports (SCL1, SDA1, SCL2, and SDA2)
• 5-V Tolerant I2C I/O ports to support mixed-mode signal operation
• High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = Low
• Lockup-free operation for isolation when EN = Low
• Flow-through pinout for ease of printed-circuit- board trace routing
• ESD lrotection Exceeds JESD 22 – 2000-V human-body model (A114-A) – 1000-V charged-device model (C101)

2 Applications

• I2C, SMBus, PMBus, MDIO, UART, low-speed SDIO, GPIO, and other two-signal interfaces
• Servers
• Routers (telecom switching equipment)
• Personal computers
• Industrial automation

3 Description

The TCA39306 is a dual bidirectional voltage-level translator compatible with I 2C, SMBus, and I 3C with an enable (EN) input, and is operational from 0.9-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2. The device allows bidirectional voltage translations between 0.85 V and 5 V, without the use of a direction pin. The low ON-state resistance (R ON) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports. In addition to voltage translation, the TCA39306 can be used to isolate a higher speed bus from a lower speed bus by controlling the EN pin to disconnect the slower bus during fast-mode communication. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCA39306 VSSOP (8) 2.30 mm x 2.00 mm SOT-23 (8) 2.90 mm x 1.60 mm X2SON (8)(2) 1.35 mm x 0.80 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. (2) Product Preview TCA39306I2C, SMBus, or I3C Controller Responder devicesSCL1 SDA1 SCL1 SDA1 VREF2VREF1 EN 200kΩ Simplified Application Diagram ADVANCE INFORMATION TCA39306 SCPS274 – JUNE 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

12.1 Receiving Notification of Documentation Updates..25

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2021 * Initial Release TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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5 Pin Configuration and Functions

Figure 5-1. DDF Package, 8-Pin SOT, Top View 1GND 8 EN 2VREF1 7 V REF2 3SCL1 6 SCL2 4SDA1 5 SDA2 Figure 5-2. DCU Package, 8-Pin VSSOP, Top View 1GND 2VREF1 3SCL1 EN SDA1

5 SDA2

6 SCL2

7 VREF2

Figure 5-3. DTM Package, 8-Pin X2SON, Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. DCU, DDF DTM EN 8 8 I Switch enable input GND 1 1 — Ground, 0 V SCL1 3 3 I/O Serial clock, low-voltage side SCL2 6 6 I/O Serial clock, high-voltage side SDA1 4 4 I/O Serial data, low-voltage side SDA2 5 5 I/O Serial data, high-voltage side VREF1 2 2 I Low-voltage-side reference supply voltage for SCL1 and SDA1 VREF2 7 7 I High-voltage-side reference supply voltage for SCL2 and SDA2 www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA39306

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VREF1 DC reference voltage range –0.5 7 V VREF2 DC reference bias voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VI/O Input-output voltage range (2) –0.5 7 V Continuous channel current 128 mA IIK Input Clamp Current (VI < 0 ) –50 mA TJ(Max) Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input-output negative voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JS-002, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input-output voltage SCL1, SDA1, SCL2, SDA2 0 5.5 V VREF1 (1) Reference Voltage 0 5.5 V VREF2 (1) Reference Voltage 0 5.5 V EN- Switch(2) Switch mode enable voltage (Switch mode enable voltage) 1.5 5.5 V EN Enable input voltage 0 5.5 V IPASS Pass switch current 64 mA TA Ambient temperature –40 125 °C Application for more information. (2) To support switching, VREF1 and VREF2 Do not need to be connected. EN pin should use a voltage not less than 1.5V when the switch mode is to be enabled. Enabled voltage on this pin should be equal to 1.5V or I/O supply voltage, whichever is higher. TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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6.4 Thermal Information

THERMAL METRIC(1) TCA39306 UNITDCU DTM

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 275.5 289.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 127.1 185.5 °C/W RθJB Junction-to-board thermal resistance 186.9 193.8 °C/W ΨJT Junction-to-top characterization parameter 65.7 27.4 °C/W ΨJB Junction-to-board characterization parameter 185.9 193.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VIK Input clamp voltage II = -18 mA EN = 0 V -1.2 0 V IIH Input leakage current VI = 5 V, VO = 0V EN = 0 V 5 µA VT Threshold voltage IO = 500 µA VI = 0.1 V, VO = 0 V, Find VEN where IO = 500 µA 0.7 1.0 V CI(EN) Input capacitance VI = 3 V or 0 V 11 pF CIO(off) Off capacitance SCLn, SDAn VO = 3 V or 0 V EN = 0 V 4 6 pF CIO(on) On capacitance SCLn, SDAn VO = 3 V or 0 V EN = 3 V 10.5 12.5 pF RON (2) On-state resistance SCLn, SDAn (-40 to 85C) VI = 0 V(3) IO = 64 mA EN = 4.5 V 3.5 5.5 Ω VI = 0 V(3) IO = 64 mA EN = 3 V 4.7 7 Ω VI = 0 V(3) IO = 64 mA EN = 2.3 V 6.3 9.5 Ω VI = 0 V(3) IO = 15 mA EN = 1.5 V 25.5 32 Ω VI = 2.4 V(4) IO = 15 mA EN = 4.5 V 1 6 15 Ω VI = 1.7 V(4) IO = 15 mA EN = 2.3 V 20 60 140 Ω VI = 2.4 V(4) IO = 15 mA EN = 3 V 20 60 140 Ω RON (2) On-state resistance SCLn, SDAn (-40 to 125C) VI = 0 V(3) IO = 64 mA EN = 4.5 V 3.5 5.5 Ω VI = 0 V(3) IO = 64 mA EN = 3 V 4.7 7 Ω VI = 0 V(3) IO = 64 mA EN = 2.3 V 6.3 9.5 Ω VI = 0 V(3) IO = 15 mA EN = 1.5 V 25.5 32 Ω VI = 2.4 V(4) IO = 15 mA EN = 4.5 V 1 6 15 Ω VI = 2.4 V(4) IO = 15 mA EN = 3 V 20 60 140 Ω VI = 1.7 V(4) IO = 15 mA EN = 2.3 V 20 60 140 Ω www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA39306

6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT RON On-state resistance SCLn, SDAn VI = 0 V, VCC2 = 5 V(5) IO = 64 mA VCC1 = 1 V 5 25 Ω VCC1 = 1.8 V 4 10 VCC1 = 2.5 V 3 8 VCC1 = 3.3 V 3 7 IO = 32 mA VCC1 = 1 V 5 10 Ω VCC1 = 1.8 V 4 9 VCC1 = 2.5 V 3 8 VCC1 = 3.3 V 3 7 VI = 1.8 V, VCC2 = 5 V(5) IO = 15 mA VCC1 = 3.3 V 4 13 Ω VI = 1 V, VCC2 = 3.3 V(5) IO = 10 mA VCC1 = 1.8 V 7 24 Ω VI = 0 V, VCC2 = 3.3 V(5) IO = 10 mA VCC1 = 1 V 5 18 Ω VI = 0 V, VCC2 = 1.8 V(5) IO = 10 mA VCC1 = 1 V 6 19 Ω (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals, at the indicated current through the switch. Minimum ON-state resistance is determined by the lowest voltage of the two terminals. (3) Measured in current source configuration only. See Figure 7-1 (4) Measured in current sink configuration only. See Figure 7-1 (5) Measured in application connected current source configuration only. See Figure 7-3

6.6 Switching Characteristics (Translating Down)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPLH Low-to-high propagation delay EN = 3.3 V, VIH = 3.3 V, VIL = 0, VM = 1.15 V(1) CL = 15 pF 0 0.3 nsCL = 30 pF 0 0.6 CL = 50 pF 0 0.8 TPHL High to low propagation delay CL = 15 pF 0 0.5 nsCL = 30 pF 0 1 CL = 50 pF 0 1.2 TPLH Low-to-high propagation delay EN = 2.5 V, VIH = 3.3 V, VIL = 0, VM = 0.75 V(1) CL = 15 pF 0 0.4 nsCL = 30 pF 0 0.6 CL = 50 pF 0 1 TPHL High to low propagation delay CL = 15 pF 0 0.8 nsCL = 30 pF 0 1.3 CL = 50 pF 0 1.3 TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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6.6 Switching Characteristics (Translating Down) (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPLH Low-to-high propagation delay EN = 2.5 V, VIH = 2.5 V, VIL = 0, VM = 0.75 V(1) CL = 15 pF 0 0.4 nsCL = 30 pF 0 0.7 CL = 50 pF 0 1 TPHL High to low propagation delay CL = 15 pF 0 0.6 nsCL = 30 pF 0 1 CL = 50 pF 0 1.3 (1) Translating Down: the high-voltage side driving toward the low-voltage side. See Figure 7-2

6.7 Switching Characteristics (Translating Up)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPLH Low-to-high propagation delay EN = 3.3 V, VIH = 2.3 V, VT = 3.3 V, VM = 1.15 V(1) CL = 15 pF 0 0.4 nsCL = 30 pF 0 0.6 CL = 50 pF 0 0.9 TPHL High to low propagation delay CL = 15 pF 0 0.7 nsCL = 30 pF 0 1.1 CL = 50 pF 0 1.4 TPLH Low-to-high propagation delay EN = 2.5 V, VIH = 2.3 V, VT = 3.3 V, VM = 0.75 V(1) CL = 15 pF 0 0.4 nsCL = 30 pF 0 0.6 CL = 50 pF 0 1 TPHL High to low propagation delay CL = 15 pF 0 0.8 nsCL = 30 pF 0 1.3 CL = 50 pF 0 1.3 TPLH Low-to-high propagation delay EN = 2.5 V, VIH = 1.5 V, VT = 2.5 V, VM = 0.75 V(1) CL = 15 pF 0 0.4 nsCL = 30 pF 0 0.6 CL = 50 pF 0 1 TPHL High to low propagation delay CL = 15 pF 0 0.8 nsCL = 30 pF 0 1.3 CL = 50 pF 0 1.3 (1) Translating up: the low-voltage side driving toward the high-voltage side. See Figure 7-2 www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA39306

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPLH Low-to-high propagation delay(1) VCC1 = 0.85 V, VCC2 = 1.98 V, RL_Input = 1.35 kΩ CL = 15 pF 13 ns CL = 50 pF 32 VCC1 = 0.85 V, VCC2 = 3.6 V, RL_Input = 1.35 kΩ CL = 15 pF 15 ns CL = 50 pF 45 VCC1 = 0.85 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 20 ns CL = 50 pF 46 VCC1 = 1.65 V, VCC2 = 3.6 V, RL_Input = 1.35 kΩ CL = 15 pF 8 ns CL = 50 pF 20 VCC1 = 1.65 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 15 ns CL = 50 pF 35 VCC1 = 3 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 2 ns CL = 50 pF 5 TPHL High-to-low propagation delay(1) VCC1 = 0.85 V, VCC2 = 1.98 V, RL_Input = 1.35 kΩ CL = 15 pF 3 ns CL = 50 pF 4 VCC1 = 0.85 V, VCC2 = 3.6 V, RL_Input = 1.35 kΩ CL = 15 pF 3 ns CL = 50 pF 5 VCC1 = 0.85 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 3 ns CL = 50 pF 5 VCC1 = 1.65 V, VCC2 = 3.6 V, RL_Input = 1.35 kΩ CL = 15 pF 2 ns CL = 50 pF 3 VCC1 = 1.65 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 3 ns CL = 50 pF 3 VCC1 = 3 V, VCC2 = 5.5 V, RL_Input = 1.35 kΩ CL = 15 pF 1.5 ns CL = 50 pF 2 (1) Measured with an application propagation delay setup. See Figure 7-4 TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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7 Parameter Measurement Information

–VEN IO VI Source Current VI + RON*IO –VEN – IOVI Sink Current VI - RON*IO A) Current Source Configuration B) Current Sink Configuration Figure 7-1. Current Source and Current Sink Configurations for Direct RON Measurements VREF1 VREF2 EN SCL1/SDA1 SCL2/SDA2 –VI RL VCC2 –VEN VO Figure 7-2. Direct Propagation Measurement www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA39306

–VI IO VI + RON*IO Figure 7-3. Application Setup for RON Delay 200 k VCC2VCC1 VREF1 VREF2 EN SCL1/SDA1 SCL2/SDA2 –VI RL VCC2 VO Figure 7-4. Application Setup for Propagation Delays Delay TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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(see Note A) Load Circuit NOTES: A. CL includes probe and jig capacitance B. All input pulses are supplied by generators having the following characteristics: WZZG10 MHz, ZO = 50 Q, tr G2 ns, tf G2 ns. C. The outputs are measured one at a time, with one transition per measurement. USAGE SWITCH Translating up S1 Translating down S2 RL Open Figure 7-5. Load Circuit for Outputs www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA39306

8 Detailed Description

8.1 Overview

The TCA39306 is a dual bidirectional voltage-level translator compatible with I 2C, SMBus, and I 3C with an The device allows bidirectional voltage translations between 0.85 V and 5 V, without the use of a direction pin. The low ON-state resistance (RON) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports. In addition to voltage translation, the TCA39306 can be used to isolate a higher speed bus from a lower speed bus by controlling the EN pin to disconnect the slower bus during fast-mode communication. In I2C applications, the bus capacitance limit of 400 pF for Standard and Fast Modes, 550 pF for Fast Mode Plus restricts the number of devices and bus length. The capacitive load on both sides of the device must be taken into account when approximating the total load of the system, ensuring the sum of both sides is under 400/550 pF. Both the SDA and SCL channels of the device have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete-transistor voltage-translation solutions, because the fabrication of the switch is symmetrical.

8.1.1 Definition of threshold voltage

This document references a threshold voltage denoted as V th, which appears multiple times throughout this document when discussing the NFET between VREF1 and VREF2. The value of Vth is approximately 0.6 V at room temperature.

8.1.2 Correct Device Set Up

In a normal set up shown in Figure 8-1, the enable pin and V REF2 are shorted together and tied to a 200-k Ω resistor, and a reference voltage equal to V REF1 plus the FET threshold voltage is established. This reference voltage is used to help pass lows from one side to another more effectively while still separating the different pull up voltages on both sides. 200 kŸ RPU RPU RPURPU VREF2VREF1 VCC1 = +1.8 V Vgs VCC2 = +3.3 V SDA2 SCL1 SDA1 SCL2 VCC1 < VCC2 Normal Setup +1.8 V + VTH IREF2 = 4 µA EN Figure 8-1. Normal Setup Care should be taken to ensure V REF2 has an external resistor tied between it and V CC2. If V REF2 is tied directly to the V CC2 rail without a resistor, then there is no external resistance from the V CC2 to V CC1 to limit the current such as in Figure 8-2. This effectively looks like a low impedance path for current to travel through TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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and potentially break the pass FET if the current flowing through the pass FET is larger than the absolute maximum continuous channel current specified in section 6.1. The continuous channel current is larger with a higher voltage difference between VCC1 and VCC2. Figure 8-2 shows an improper set up. If VCC2 is larger than VCC1 but less than Vth, the impedance between VCC1 and VCC2 is high resulting in a low drain to source current, which does not cause damage to the device. Concern arises when VCC2 becomes larger than V CC1 by Vth. During this event, the NFET turns on and begin to conduct current. This current is dependent on the gate to source voltage and drain to source voltage. 200k Ÿ RPU RPU RPURPU VREF2VREF1 VCC1 = +1.8 V Vgs VCC2 = +3.3 V SDA2 SCL1 SDA1 SCL2 VCC1 < VCC2 Abnormal Setup EN Figure 8-2. Abnormal Setup

8.1.3 Disconnecting a Responder from the Main Bus Using the EN Pin

TCA39306 can be used as a switch to disconnect one side of the device from the main bus, whether isolating I3C and I2C devices or different speed groups. This can be advantageous in multiple situations. One instance of this situation is if there are devices on the I2C bus which only supports fast mode (400 kHz) while other devices on the bus support fast mode plus (1 MHz). An example of this is displayed in Figure 8-3.

3.3 V I2C bus

(1 MHz) TCA39306 3.3 V I2C bus (400 kHz) EN GPIO Note: GPIO logic high must not exceed 3.3 V +Vth in this example Figure 8-3. Example of an I2C bus with multiple supported frequencies In this situation, if the controller is on the 1 MHz side then communicating at 1 MHz should not be attempted if TCA39306 were enabled. It needs to be disabled for the device to avoid possibly glitching state machines in devices which were designed to operate correctly at 400 kHz or slower. When the device is disabled, the controller can communicate with the 1 MHz devices without disturbing the 400 kHz bus. When the device is enabled, communication across both sides at 400 kHz is acceptable.

8.1.4 Supporting Remote Board Insertion to Backplane with TCA39306

Another situation where TCA39306 is advantageous when using its enable feature is when a remote board with I2C lines needs to be attached to a main board (backplane) with an I 2C bus such as in Figure 8-4. If connecting a remote board to a backplane is not done properly, the connection could result in data corruption during a transaction or the insertion could generate an unintended pulse on the SCL line. Which could glitch an I 2C device state machine causing the I2C bus to get stuck. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCA39306

3.3 V I2C bus TCA39306 3.3 V I2C bus EN GPIO Note: GPIO logic high must not exceed 3.3 V +Vth in this example Remote Board Figure 8-4. An example of connecting a remote board to a main board (backplane) TCA39306 can be used to support this application because it can be disabled while making the connection. Then it is enabled once the remote board is powered on and the buses on both sides are IDLE.

8.1.5 Switch Configuration

TCA39306 has the capability of being used with its V REF1 voltage equal to V REF2. This essentially turns the device from a translator to a device which can be used as a switch, and in some situations this can be useful. The switch configuration is shown in Figure 8-5 and translation mode is shown in Figure 8-6. TCA39306 Vref2 Switch Configuration: Vref1=Vref2 and Enable is controlled by a GPIO 200 k VCC1 EN GPIO: high logic does not exceed Vref2 + Vth SCL1 R VCC2 SDA1 R VCC2 SCL2 SDA2 Vref1 VCC2 RR Where Vcc2 = Vcc1 VCC1 VCC1 Figure 8-5. Switch Configuration TCA39306 Vref2 Translation Configuration where Vcc2 >= Vref1 + 0.7 V 200 k VCC1 EN SCL1 R VCC2 SDA1 R VCC2 SCL2 SDA2 Vref1 VCC2 RR VCC1 VCC1 Figure 8-6. Translation Configuration When TCA39306 is in the switch configuration (V REF1 = V REF2), the propagation delays are different compared to the translator configuration. Taking a look at the propagation delays, if the pull up resistance and capacitance on both sides of the bus are equal, then in switch mode the device has the same propagation delay from side one to two and side two to one. The propagation delays become lower when V CC1/VCC2 is larger. For example, the propagation delay at 1.8 V is longer than at 5 V in the switching configuration. When the device is in TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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translation mode, side one propagate lows to side two faster than side two can propagate lows to side 1. This time difference becomes larger the larger the difference between VCC2 and VCC1 becomes.

8.1.6 Controller on Side 1 or Side 2 of Device

I2C and SMBus are bidirectional protocol meaning devices on the bus can both transmit and receive data. TCA39306 was designed to allow for signals to be able to be transmitted from either side, thus allowing for the controller to be able to placed on either side of the device. Figure 8-7 shows the controller on side two as opposed to the diagram on page 1 of this data sheet. TCA39306 Vref2 200 k VCC1 EN SCL1 SDA1 SCL2 SDA2 Vref1 VCC2 I2C responder devices I2C or SMBus Controller (processor) Figure 8-7. Controller on side 2

8.1.7 LDO and TCA39306 Concerns

The V REF1 pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO may lose its regulation because of the bias current from V REF2 to V REF1. If the LDO cannot sink the bias current, then the current has no other paths to ground and instead charges up the capacitance on the V REF1 node (both external and parasitic). This results in an increase in voltage on the V REF1 node. If no other paths for current to flow are established (such as back biasing of body diodes or clamping diodes through other devices on the V REF1 node), then the V REF1 voltage ends up stabilizing when V gs of the pass FET is equal to V th. This means V REF1 node voltage is VCC2 - Vth. Note that any secondary/primaries running off of the LDO now see the V CC2 - Vth voltage which may cause damage to those secondary/primaries if they are not rated to handle the increased voltage. Vgs VREF1 pin VREF2 pin VCC1 < VCC2 EN 200 k VCC2 = +3.3 V Ven = Vref1 + VTH VREF1 = Vcc2 - Vth -LDO Vout CREF1 Ibias = (Vcc2 – Ven) / 200 k Translator Setup with Vref1 provided by LDO and no path for bias current Figure 8-8. Example of no leakage current path when using LDO To ensure LDO does not lose regulation due to the bias current of TCA39306, a weak pull down resistor can be placed on VREF1 to ground to provide a path for the bias current to travel. The recommended pull down resistor is calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current increases during operation. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCA39306

VCC1 < VCC2 EN 200 k VCC2 = +3.3 V Ven = Vref1 + VTH LDO Vout = +1.8 V CREF1 Ibias = (Vcc2 – Ven) / 200 k Rpulldown Translator Setup Figure 8-9. Example with Leakage current path when using an LDO Ven = VREF1 + Vth (1) where

• Vth is approximately 0.6 V Ibias = (VCC2 - Ven)/200k (2) Rpulldown = VOUT/Ibias (3) Recommended Rpulldown = Rpulldown x 0.75 (4)

8.1.8 Current Limiting Resistance on VREF2

The resistor is used to limit the current between V REF2 and V REF1 (denoted as R CC) and helps to establish the reference voltage on the enable pin. The 200k resistor can be changed to a lower value; however, the bias current proportionally increases as the resistor decreases. Ibias = (VCC2 - Ven)/RCC : Ven = VREF1 + Vth (5) where

• Vth is approximately 0.6 V Keep in mind R CC should not be sized low enough that I CC exceeds the absolute maximum continuous channel current specified in section 6.1 which is described in Equation 6. RCC(min) ≥ (VCC2 - Ven)/0.128 : Ven = VREF1 + Vth (6) where
• Vth is approximately 0.6V TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Enable (EN) Pin

The device is a double-pole, single-throw switch in which the gate of the transistors is controlled by the voltage on the EN pin. In Figure 9-1, the device is always enabled when power is applied to V REF2. In Figure 9-2, the device is enabled when a control signal from a processor is in a logic-high state.

8.3.2 Voltage Translation

The primary feature of the device is translating voltage from an I 2C bus referenced to V REF1 up to an I 2C bus referenced to V DPU, to which V REF2 is connected through a 200-k Ω pullup resistor. Translation on a standard, open-drain I 2C bus is achieved by simply connecting pullup resistors from SCL1 and SDA1 to V REF1 and connecting pullup resistors from SCL2 and SDA2 to V DPU. Information on sizing the pullup resistors can be found in the Sizing Pullup Resistors section.

8.4 Device Functional Modes

EN(1) TRANSLATOR FUNCTION H Logic Lows are propagated from one side to the other, Logic Highs blocked (independent pull up resistors passively drive the line high) L Disconnect (1) The SCL switch conducts if EN is ≥ 0.6 V higher than SCL1 or SCL2. The same is true of SDA. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA39306

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 General Applications of I2C

As with the standard I 2C system, pullup resistors are required to provide the logic-high levels on the translator bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with standard-mode and fast-mode I 2C devices in addition to SMBus devices. Standard-mode I 2C devices only specify 3 mA in a generic I 2C system where standard-mode devices and multiple controllers are possible. Under certain conditions, high termination currents can be used. When the SDA1 or SDA2 port is low, the clamp is in the ON state, and a low-resistance connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port when the SDA2 port is high, the voltage on the SDA1 port is limited to the voltage set by V REF1. When the SDA1 port is high, the SDA2 port is pulled to the pullup supply voltage of the drain (V DPU) by the pullup resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. The SCL1-SCL2 channel also functions in the same way as the SDA1-SDA2 channel.

9.2 Typical Application

Figure 9-1 and Figure 9-2 show how these pullup resistors are connected in a typical application, as well as two options for connecting the EN pin. TCA39306 SW SW RPURPU VREF1 VREF2 EN SCL2 SDA2SDA1 SCL1 GND SCL SDA GND I2C Controller VCC VPU_1 = 1.8 V SCL SDA GND I2C Responder VCC RPURPU VPU_2 = 3.3 V 200 kΩ Figure 9-1. Typical Application Circuit (Switch Always Enabled) TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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VPU_1 = 1.8 V SCL SDA GND I2C Responder VCC RPURPU VPU_2 = 3.3 V 200 k

3.3 V EN Signal

Figure 9-2. Typical Application Circuit (Switch Enable Control)

9.2.1 Design Requirements

MIN TYP(1) MAX UNIT VREF2 Reference voltage VREF1 + 0.6 2.1 5 V EN Enable input voltage VREF1 + 0.6 2.1 5 V VREF1 Reference voltage 0.9 1.5 4.4 V IPASS Pass switch current 6 mA IREF Reference-transistor current 5 μA (1) All typical values are at TA = 25°C.

9.2.2 Detailed Design Procedure

9.2.2.1 Bidirectional Voltage Translation

For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to V REF2 and both pins pulled to high-side V DPU through a pullup resistor (typically 200 k Ω). This allows V REF2 to regulate the EN input. A 100-pF filter capacitor connected to V REF2 is recommended. The I 2C bus controller output can be push-pull or open-drain (pullup resistors may be required) and the I 2C bus device output can be open-drain (pullup resistors are required to pull the SCL2 and SDA2 outputs to V DPU). However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state capable and be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. If both outputs are open-drain, no direction control is needed.

9.2.2.2 Sizing Pullup Resistors

To get an estimate for the range of values that can be used for the pullup resistor, please refer to the application note SLVA689. Maximum Pullup Resistance (R p(max)) vs Bus Capacitance (C b) and Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (V DPUX) respectively show the maximum and minimum pullup resistance allowable by the I2C specification for standard-mode (100 kHz) and fast-mode (400 kHz) operation.

9.2.2.3 Bandwidth

The maximum frequency of the device depends on the application. The device can operate at speeds of > 100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA39306

However, this is an analog type of measurement. For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important in determining the overall shape of the digital signal. In the case of the device, digital clock frequency of >100 MHz can be achieved. The device does not provide any drive capability like the TCA9517 or other buffered translators. Therefore, higher-frequency applications require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the device is being driven by standard CMOS push-pull output driver. Ideally, it is best to minimize the trace length from device on the sink side (1.8 V) to minimize signal degradation. You can then use a simple formula to compute the maximum practical frequency component or the knee frequency (f knee). All fast edges have an infinite spectrum of frequency components. However, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than f knee are insignificant in determining the shape of the signal. To calculate fknee: For signals with rise-time characteristics based on 10- to 90-percent thresholds, f knee is equal to 0.5 divided by the rise time of the signal. For signals with rise-time characteristics based on 20- to 80-percent thresholds, which is very common in many current device specifications, fknee is equal to 0.4 divided by the rise time of the signal. Some guidelines to follow that help maximize the performance of the device:

• Keep trace length to a minimum by placing the device close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
• To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.

9.2.3 Application Curve

Cb (pF) Rp(max) (kOhm) 0 50 100 150 200 250 300 350 400 450 D008 Standard-mode Fast-mode Standard mode Fast mode (fSCL = 100 kHz, tr = 1 μs) (fSCL = 400 kHz, tr = 300 ns) Figure 9-3. Maximum Pullup Resistance (Rp(max)) vs Bus Capacitance (Cb) VDPUX < 2 V VDPUX > 2 V VOL = 0.2 x VDPUX , IOL = 2 mA when VDPUX ≤ 2 V VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V Figure 9-4. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX)

9.3 Systems Examples: I3C Usage Considerations

The TCA39306 has bandwidth to support the high speeds needed for I3C, but there are special considerations which are required. Since I3C uses both push-pull and open-drain, it may not be possible to support all I3C applications with a FET-based translator. TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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9.3.1 I3C Bus Switching

Bus switching is when the bus path is enabled or disabled, but does not translate the bus voltage. External pull-up resistors are not needed for I3C, because the controller enables or disables the pull-up resistor on the SDA line. This presents a unique challenge for FET-based translators, like the TCA39306, because they rely on a pull-up resistor to pull the output side of the switch all the way to supply. For the switching use case, there is no translation, but the enable voltage must be high enough to ensure the switch stays on for the entire voltage range of the bus (0 V to bus voltage). To ensure low enough R ON for the full push-pull voltage range, the EN voltage must be at least 1 V t (~0.6V) above the maximum desired pass-voltage. This comes out to V EN ≥ V BUS + 0.6 V. Since the switch enable voltage is being directly controlled, the V REF1 and V REF2 pins are not needed, and can be shorted to ground to improve power consumption. It is possible to control the EN pin with a voltage equal to V BUS, but external pull-up resistors on the downstream side are a requirement to ensure the bus is pulled entirely to VBUS. TCA39306 SW SW VREF1 VREF2 EN SCL2 SDA2SDA1 SCL1 GND SCL SDA GND I3C Controller VCC SCL SDA GND I3C Responder VCC VEN VBUS + 0.6 V Off On Figure 9-5. I3C Bus Switching Application (Without Pull-up Resistors) www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCA39306

VEN = VBUSOff On RPURPU VBUS = 3.3 V RPU RPU Figure 9-6. I3C Bus Switching Application (With Pull-up Resistors)

9.3.2 I3C Bus Voltage Translation

Bus voltage translation is when the bus voltage is translated up or down. This presents a unique challenge with I3C for FET-based translators, like the TCA39306, because they rely on a pull-up resistor to translate the voltage up from the low-voltage side. The pull-up resistor selected must be strong enough to meet the timing requirements (based on bus capacitance and translation voltages), but not so strong to violate the V IL requirements of the I3C devices. The pull-up resistors are needed on both sides. The reason for this is that with the normal translation setup, the switch is "on" when either side's bus voltage drops to roughly V PU_1. This means that the pull-up resistors are required to pull the bus voltage on the high-voltage side from V PU_1 to V PU_2. When the device on the high-voltage side is controlling the bus, the switch will turn off at V PU_1. The pull-up resistors on the low-voltage side are used to bleed off any additional current that might "leak" through the switch. TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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VPU_1 = 1.8 V SCL SDA GND I3C Responder VCC RPURPU VPU_2 = 3.3 V 200 kΩ RPURPU Figure 9-7. I3C Bus Translation

10 Power Supply Recommendations

For supplying power to the device, the V REF1 pin can be connected directly to a power supply. The V REF2 pin must be connected to the V DPU power supply through a 200-k Ω resistor. Failure to have a high-impedance resistor between V REF2 and V DPU results in excessive current draw and unreliable device operation. It is also worth noting, that in order to support voltage translation, the device must have the EN and VREF2 pins shorted and then pulled up to VDPU through a high-impedance resistor. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCA39306

11 Layout

11.1 Layout Guidelines

For printed-circuit board (PCB) layout of the device, common PCB layout practices should be followed, but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other on leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. The 100-pF filter capacitor should be placed as close to VREF2 as possible. A larger decoupling capacitor can also be used, but a longer time constant of two capacitors and the 200-k Ω resistor results in longer turnon and turnoff times for the TCA39306 device. These best practices are shown in Figure 11-1. For the layout example provided in Figure 11-1, it would be possible to fabricate a PCB with only two layers by using the top layer for signal routing and the bottom layer as a split plane for power (V CC) and ground (GND). However, a four-layer board is preferable for boards with higher-density signal routing. On a four-layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface-mount component pad, which must attach to V CC or GND, and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace must be routed to the opposite side of the board, but this technique is not demonstrated in Figure 11-1.

11.2 Layout Example

Figure 11-1. Layout Example TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated device. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCA39306

13.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PTCA39306DDFR SOT-23- TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTCA39306DDFR SOT-23-THN DDF 8 3000 180.0 1.80.0 18.0 PTCA39306DCUR VSSOP DCU 8 3000 223.0 270.0 35.0 PTCA39306DTMR X2SON DTM 8 5000 205.0 200.0 33.0 www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCA39306

13.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C TYP2.95 2.65

1.1 MAX

6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 4.000 TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SYMM SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCA39306

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com PACKAGE OUTLINE C 6X 0.5 1.5 8X 0.25 0.17 3.2

3.0 TYP

0.1 0.0 0.12 GAGE PLANE 0 -6 0.9 0.6 B 2.4 2.2 NOTE 3 A 2.1 1.9 NOTE 3 0.35 0.20 (0.13) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 4 5

0.08 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-187 variation CA. A 30 SCALE 6.000 DETAIL A TYPICAL www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCA39306

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SYMM SYMM 4 5 SEE SOLDER MASK DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL NON-SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) SOLDER MASK DEFINED TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE STENCIL DESIGN 8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 25X SYMM SYMM 4 5 www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCA39306

www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5

0.4 MAX

0.04 0.00 6X 0.27 0.17 0.54 2X 0.27 0.17 B 0.85 0.75 A 1.4 1.3 (0.102) TYP 4224755/A 01/2019 X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.05 C

0.1 C B A

0.05 C SYMM SYMM PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 12.000 TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT ( 0.22)

0.0325 MIN

0.0325 MAX

6X (0.2) (0.5) (0.78) (R0.05) TYP 6X (0.42) (0.27) X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/A 01/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). NON SOLDER MASK DEFINED EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:40X SYMM SYMM (45 X 0.1) (45 X 0.75) SEE SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK OPENING METAL EDGE EXPOSED METAL www.ti.com TCA39306 SCPS274 – JUNE 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TCA39306

www.ti.com EXAMPLE STENCIL DESIGN (0.411) 4X (0.42) 6X (0.2) (0.5) (0.78) PINS: 1,3,5,7 (0.27) (R0.05) TYP ( 0.22) (0.2) TYP X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/A 01/2019 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM BASED ON 0.075 mm THICK STENCIL SOLDER PASTE EXAMPLE SCALE: 40X EXPOSED METAL TCA39306 SCPS274 – JUNE 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com 16-Jun-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTCA39306DCUR ACTIVE VSSOP DCU 8 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTCA39306DTMR ACTIVE X2SON DTM 8 5000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 16-Jun-2021 Addendum-Page 2

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