Microcontroller

PTBG0064LA-A

Renesas Technology Corp

RENESAS MCU Rev. 1.11 Mar 22, 2024

Manufacturer: Renesas Technology Corp

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RL78-H1D RENESAS | Alldatasheet

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R01DS0318EJ0111 Rev. 1.11 Page 1 of 143 Mar 22, 2024 RL78/H1D RENESAS MCU Analog front-end (24-bit ΔΣA/D converter with programmable gain instrumentation amplifier, Amplifier unit and 12-bit D/A converter), External signal sa mpler/Sampling output timer detector and Integrated LCD controller/driver. True Low Power Platform (as low as 70.8 μA/MHz, and 0.68 μA in Halt mode( RTC2 + LVD)), 1.8 V to 5.5V operation, 64 to 128 Kbyte Flash, 33 DMIPS at 24 MHz, for Healthcare and Flow meter applications. Datasheet 1. OUTLINE

1.1 Features

Ultra-low power consumption technology

VDD = 2.4 to 5.5 V (10-bit SAR A/D converter: 2.4 to 5.5 V, operating voltage of the analog front-end (AFE): 2.7 to 5.5 V) Note 1, VDD = 1.8 to 5.5 VNote 2
HALT mode
S T O P m o d e
SNOOZE mode RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed from high speed (0.04167 µs: @ 24 MHz operation with high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs: @ 32.768 kHz operation with subsystem clock)
Multiply/divide and multiply/accumulate instructions are supported.
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4 banks
On-chip RAM: 5.5 KB Note 1, 8 KBNote 2 Code flash memory
Code flash memory: 64 to 128 KB
Block size: 1 KB
Prohibition of block erase and rewriting (security function)
On-chip debug function
Self-programming (with boot swap function/flash shield window function) Data flash memory
Data flash memory: 4 KB
Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
Number of rewrites: 1,000,000 times (TYP .)
Voltage of rewrites: V DD = 2.4 to 5.5 VNote 1, 1.8 to 5.5 VNote 2 High-speed on-chip oscillator
Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
High accuracy: ±1.0% (VDD = 2.4 to 5.5 V, TA = -20 to +85°CNote 1, VDD = 1.8 to 5.5 V, TA = -20 to +85°CNote 2) Operating ambient temperature
TA = -40 to +85°C (A: Consumer applicationsNote 1, D: Industrial applicationsNote 2) Power management and reset function
On-chip power-on-reset (POR) circuit
On-chip voltage detector (LVD) (Select interrupt and reset from 9Note 1 or 12Note 2 levels) Data transfer controller (DTC)
Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
Activation sources: Activated by interrupt sources (35 sources).
Chain transfer function Event link controller (ELC)
Event signals of 18 to 26 types can be linked to the specified peripheral function. R01DS0318EJ0111 Rev. 1.11 Mar 22, 2024

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 2 of 143 Mar 22, 2024 Serial interfaces

Simplified SPI(CSI Note 3)/Simplified SPI(CSI)(SPI supported): 3 channels
UART/UART (LIN-bus supported):3 channels
I2C/simplified I2C: 4 channels
Serial interface UARTMG (9600 bps @ 38.4 kHz): 1 channel (R5F11R only) Timers
16-bit timer: Timer array unit (TAU): 8 channels, Timer RJ: 2 channels (R5F11R only)
8-bit timer:2 channelsNote 1, 6 channelsNote 2
12-bit interval timer: 1 channel
Real-time clock 2: 1 channel (calendar for 99 years, alarm function, and clock correction function)
Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)
External signal sampler: 1 channel (R5F11R only)
Sampling output timer detector (SMOTD): 6 channels for input, 3 channels for output (R5F11R only) LCD controller/driver
Internal voltage boosting method, capacitor split method, and external resistance division method are switchable.
Segment signal output: 27 (23) to 36 (32) Note 4
Common signal output: 4 (8) Note 4 Analog front-end power supply circuit (R5F11N and R5F11P only)
AFE reference power supply (ABGR)
LDO for supplying power to internal circuits (REGA)
LDO for supplying power to a sensor (SBIAS): 0.5 to 2.2 V 24-bit ΔΣ A/D converter with programmable gain instrumentation amplifier (R5F11N and R5F11P only)
24-bit second-order ΔΣ A/D converter (AV DD = 2.7 to 5.5 V) - SNDR: 85 dB (TYP.) - Output data rate: 488 sps to 15.625 ksps in normal mode 61 sps to 1.953 ksps in low power mode
Programmable gain instrumentation amplifier (PGA0) - Analog input: 1 to 5 channels (differential input mode or single-ended input mode) - D/A converter for offset adjustment - Variable gain: x1 to x64 Amplifier unit (R5F11N and R5F11P only)
Programmable gain instrumentation amplifier (PGA1): 1 channel (R5F11NL, R5F11PL, and R5F11NG only) - Analog input: 1 or 2 channels - Variable gain: x12, x16, x20, x24
Rail-to-rail operational amplifier (AMP0): 1 channel
General-purpose operational amplifier (AMP1, AMP2): 2 channels (R5F11NL, R5F11PL, and R5F11NG only) D/A converter (R5F11N and R5F11P only)
8-bit resolution R-2R resistor ladder D/A converter (DAC0) (AV DD = 2.7 to 5.5 V): 1 channel
12-bit resolution R-2R resistor ladder D/A converter (DAC1) (AVDD = 2.7 to 5.5 V): 1 channel (R5F11NL, R5F11PL, and R5F11NG only) 10-bit SAR A/D converter
10-bit resolution A/D converter (VDD = 2.4 to 5.5 VNote 1, VDD = 1.8 to 5.5 VNote 2)
Analog input: 3 channels
Internal reference voltage (TYP. 1.45 V) Note 5 and temperature sensor Note 5 I/O ports
I/O ports: 29 to 63 (N-ch open drain I/O [withstand voltage of 6 V]: 2)
Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor
On-chip clock output/buzzer output controller Others
On-chip BCD (binary-coded decimal) correction circuit Note 1. In case of R5F11N and R5F11P . Note 2. In case of R5F11R. Note 3. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Note 4. The number in parentheses indicates the number of signal outputs when 8 coms are used.

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 3 of 143 Mar 22, 2024 Note 5. Selectable only in HS (high-speed main) mode. Remark The functions mounted depend on the product. See 1.6 Outline of Functions. ROM, RAM capacities Flash ROM Data Flash RAM RL78/H1D 80-pin LFQFP 64-pin LFQFP 64-pin TFBGA 48-pin LFQFP 128 KB 4 KB 5.5 KB R5F11NMG R5F11NLG R5F11PLG R5F11NGG 96 KB 4 KB 5.5 KB R5F11NMF R5F11NLF R5F11PLF R5F11NGF 64 KB 4 KB 5.5 KB R5F11NME — — —

128 KB 4 KB 8 KB R5F11RMG — — —

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 4 of 143 Mar 22, 2024

1.2 Ordering Information

Remark 1. Products (R5F11PL) in 64-pin TFBGA have the same functi onality as those (R5F11NG) in 48-pin LFQFP. The only difference is the package. Remark 2. For the fields of application, refer to Part Number, Memory Size, and Package. Pin Count Package Fields of Application Orderable Part Number RENESAS Code Product Name Packaging Specifications 80 pins 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) AR 5 F 1 1 N M G A F B , R5F11NMFAFB, R5F11NMEAFB 64 pins 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch) A R5F11NLGAFB, R5F11NLFAFB 64 pins 64-pin plastic TFBGA (4 × 4 mm, 0.4 mm pitch) A R5F11PLGABG, R5F11PLFABG #U0, #W0 PTBG0064LA-A 48 pins 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch) A R5F11NGGAFB, R5F11NGFAFB 80 pins 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) D R5F11RMGDFB #10, #30, #50, #70 PLQP0080KB- B <R>

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 5 of 143 Mar 22, 2024 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/H1D Caution Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product page on the Renesas website for the latest part numbers. <R> Packaging specification: #10, #30, #70: Tray (LFQFP) #50: Embossed Tape (LFQFP) # U 0 : T r a y ( T F B G A ) #W0: Embossed Tape (TFBGA) R 5 F 1 1 N M G A x x x F B # 3 0Part No. Package type: FB: LFQFP, 0.50 mm pitch BG: TFBGA, 0.40 mm pitch Fields of application: A: Consumer applications, TA = -40 to +85°C D: Industrial applications, TA = -40 to +85°C ROM capacity: E: 64 KB F: 96 KB G: 128 KB Pin count: G: 48-pin L: 64-pin M: 80-pin RL78/H1D group 11N: AFE incorporated, LFQFP package 11P: AFE incorporated, TFBGA package 11R: External signal sampler and SMOTD incorporated Memory type: F: Flash memory Renesas MCU Renesas semiconductor product ROM number (Omitted with blank products)

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 6 of 143 Mar 22, 2024

1.3 Pin Configuration (Top View)

1.3.1 80-pin products (R5F11NM)

80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 µF). Caution 2. Connect the REGA pin to AVSS pin via a capacitor (0.22 μF). Caution 3. Make the AVSS pin the same potential as the VSS pin. Caution 4. Make the AVDD pin the same potential as the VDD pin. Caution 5. Connect the SBIAS pin to AVSS pin via a capacitor (0.22 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). Remark 3. Set the AMP0P and AMP0N functions in the above figure by the amplifier unit 1 input select register (AMP0S). P11/SEG30 P12/SEG31 P13/SEG32 P14/SEG33 P15/SEG34 P16/SEG35 P17/(TI07/TO07) P84/(TI05/TO05) P85/INTP7 P86/(INTP6) ANI12 ANI13 ANI14 AV SS AMP0O AMP0N/AMP0P AMP0P PGA00P PGA00N SBIAS P70/SEG8 P71/SEG9 P72/SEG10 P73/SEG11 P74/SEG12 P75/SEG13 P76/SEG14 P77/TI07/TO07/SEG15 P30/INTP3/RTC1HZ/SEG16 P31/TI01/TO01/SEG17 P35/SCK00/SCL00/SEG19 P36/SI00/RxD0/TOOLRxD/SDA00/PCLBUZ1/SEG20 P37/SO00/TxD0/TOOLTxD/SEG21 P125/(TI06/TO06)/V VL4 VL2 VL1 P126/(TI05/TO05)/CAPL P127/(TI04/TO04)/CAPH 1 2 3 4 5 6 7 8 9 1 01 11 21 31 4 1 51 61 71 81 92 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 REGA AVDD P80/(SO20/TxD2)/(TI02/TO02) P81/(SI20/RxD2/SDA20)/(TI00)/(TO00) P82/(INTP2)/(SCK20/SCL20)/(TI07/TO07) P83/(TI03/TO03)/(PCLBUZ1) P44/(SO00/TxD0) P43/(SI00/RxD0/SDA00)/(TI00)/(TO00) P40/TOOL0/(INTP1)/(SCK00/SCL00)/(TI01/TO01) P124/XT2/EXCLKS P123/XT1 P137/INTP0/(SSI00) P122/X2/EXCLK/INTP5 P121/X1/INTP1 REGC VSS VDD P60/(INTP3)/SCLA0 P61/(INTP4)/SDAA0 P10/INTP2/SCK20/SCL20/SEG29 P07/SI20/RxD2/SDA20/TI05/TO05/SEG28 P06/SO20/TxD2/TI00/SEG27 P05/TI06/TO06/SEG26 P04/INTP6/(SCK10/SCL10)/SEG25 P03/(SI10/RxD1/SDA10)/TO00/SEG24 P02/(SO10/TxD1)/PCLBUZ0/SEG23 P01/(INTP5)/SEG22 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P53/(INTP0)/SEG4 P52/SCK10/SCL10/TI02/TO02/SEG5 P51/SI10/RxD1/SDA10/TI04/TO04/SEG6 P50/SO10/TxD1/TI03/TO03/SEG7 RL78/H1D (Top View) P32/INTP4/SSI00/SEG18 RESET

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 7 of 143 Mar 22, 2024 1.3.2 64-pin products (R5F11NL)

64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 µF). Caution 2. Connect the REGA pin to AVSS pin via a capacitor (0.22 μF). Caution 3. Make the AVSS pin the same potential as the VSS pin. Caution 4. Make the AVDD pin the same potential as the VDD pin. Caution 5. Connect the SBIAS pin to AVSS pin via a capacitor (0.22 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). Remark 3. Set the AMP0P and AMP0N functions in the above figure by the amplifier unit 1 input select register (AMP0S). Set the AMP1P and AMP1N functions in the above figure by the amplifier unit 2 input select register (AMP1S). Set the AMP2P and AMP2N functions in the above figure by the amplifier unit 3 input select register (AMP2S). P11/ANI11/SEG30 P12/SEG31 P13/SEG32 P14/SEG33 AMP2N/AMP2P/AMP1P AMP1O AMP1N/AMP1P/AMP0P PGA1O AV SS AMP0O AMP0N/AMP0P PGA10P/PGA00P/AMP1P PGA10N/PGA00N/AMP2P SBIAS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P07/SI20/RxD2/SDA20/TI05/TO05/SEG28 P06/SO20/TxD2/TI00/SEG27 COM1 COM2 COM5/SEG1 COM6/SEG2 COM7/SEG3 P52/SCK10/SCL10/TI02/TO02/SEG5 P51/SI10/RxD1/SDA10/TI04/TO04/SEG6 P50/SO10/TxD1/TI03/TO03/SEG7 P70/SEG8 P71/SEG9 P76/SEG14 P77/TI07/TO07/SEG15 P30/INTP3/RTC1H Z/SEG16 P31/TI01/TO01/SEG17 P35/SCK00/SCL00/SEG19 P36/SI00/RxD0/TOOLRxD/SDA00/PCLBUZ1/SEG20 P37/SO00/TxD0/TOOLTxD/SEG21 P125/(TI06/TO06)/V P126/(TI05/TO05)/CAPL P127/(TI04/TO04)/CAPH 1 2 3 4 5 6 7 8 91 01 11 21 31 41 51 6 AVDD P82/(TI07/TO07) P83/(TI03/TO03)/(PCLBUZ1) P40/TOOL0/(INTP1)/(TI01/TO01) P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK/INTP5 P121/X1/INTP1 REGC VSS P60/(INTP3)/SCLA0 VDD P61/(INTP4)/SDAA0 P15/SEG34 AMP2O P10/INTP2/SCK20/SCL20/SEG29 P05/ANI10/TI06/TO06/SEG26 P03/ANI8/TO00/SEG24 COM0 COM3 COM4/SEG0 RL78/H1D (Top View) REGA VL4 VL2 VL1 P32/INTP4/SSI00/SEG18 RESET

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 8 of 143 Mar 22, 2024 1.3.3 64-pin products (R5F11PL)

64-pin plastic TFBGA (4 × 4 mm, 0.4 mm pitch) HGFEDCBA A B CDE F GH Top View Bottom View INDEX MARK

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 9 of 143 Mar 22, 2024 Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 µF). Caution 2. Connect the REGA pin to AVSS pin via a capacitor (0.22 µF). Caution 3. Make the AVSS pin the same potential as the VSS pin. Caution 4. Make the AVDD pin the same potential as the VDD pin. Caution 5. Connect an SBIAS pin (either of two) to the AV SS pin via a capacitor (0.22 μF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection registers 0, 1, and 3 (PIOR0, PIOR1, and PIOR3). Remark 3. Set the AMP0P and AMP0N functions in the above figure by the amplifier unit 1 input select register (AMP0S). Set the AMP1P and AMP1N functions in the above figure by the amplifier unit 2 input select register (AMP1S). Set the AMP2P and AMP2N functions in the above figure by the amplifier unit 3 input select register (AMP2S). ABCDEFGH VSS P71/(TI05/ TO05) P77/TI07/ TO07 P35/SCK00/ SCL00 P36/SI00/ RxD0/ TOOLRxD/ SDA00/ PCLBUZ1 P61/(INTP4)/ SDAA0 V DD VSS P50/SO10/ TxD1/TI03/ TO03 P51/SI10/Rx D1/SDA10/ TI04/TO04 P76/(TI06/ TO06) P32/INTP4/ SSI00 P37/SO00/ TxD0/ TOOLTxD P60/(INTP3)/ SCLA0 V SS P121/X1/ INTP1 7 P53/(INTP0) P52/SCK10/ SCL10/TI02/ TO02 P70 P30/INTP3/ RTC1HZ V SS RESET REGC P122/X2/ EXCLK/ INTP5 P02/(SO10/ TxD1)/ PCLBUZ0 P03/ANI8/ (SI10/RxD1/ SDA10)/ TO00 P04/ANI9/IN TP6/(SCK10/ SCL10) P01/(INTP5) V SS P40/TOOL0/ (INTP1)/TI01 /TO01 P137/INTP0 P123/XT1 P05/ANI10/ TI06/TO06 P07/SI20/ RxD2/ SDA20/ TI05/TO05 P06/SO20/ TxD2/TI00 P10/INTP2/ SCK20/ SCL20 V SS VSS VSS P124/XT2/ EXCLKS 4 AMP1O AV SS AVSS AVSS AVSS AVSS REGA AV DD AMP2O AMP1N/ AMP1P/ AMP0P PGA11P/ PGA01P PGA11N/ PGA01N AMP0N/ AMP0P AV SS AVSS SBIAS AVSS AMP2N/ AMP2P/ AMP1P PGA1O AV SS AMP0O PGA10P/ PGA00P/ AMP1P PGA10N/ PGA00N/ AMP2P SBIAS ABCDEFGH

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 10 of 143 Mar 22, 2024 1.3.4 48-pin products (R5F11NG)

48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 µF). Caution 2. Connect the REGA pin to AVSS pin via a capacitor (0.22 µF). Caution 3. Make the AVSS pin the same potential as the VSS pin. Caution 4. Make the AVDD pin the same potential as the VDD pin. Caution 5. Connect the SBIAS pin to AVSS pin via a capacitor (0.22 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection registers 0, 1, and 3 (PIOR0, PIOR1, and PIOR3). Remark 3. Set the AMP0P and AMP0N functions in the above figure by the amplifier unit 1 input select register (AMP0S). Set the AMP1P and AMP1N functions in the above figure by the amplifier unit 2 input select register (AMP1S). Set the AMP2P and AMP2N functions in the above figure by the amplifier unit 3 input select register (AMP2S). P71/(TI05/TO05) P76/(TI06/TO06) P35/SCK00/SCL00 P36/SI00/RxD0/TOOLRxD/SDA00/PCLBUZ1 P60/(INTP3)/SCLA0 VDD AMP2N/AMP2P/AMP1P AMP1O PGA1O AVSS PGA11P/PGA01P PGA11N/PGA01N AMP0O AMP0N/AMP0P PGA10P/PGA00P/AMP1P PGA10N/PGA00N/AMP2P 123456789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 VSS REGC P121/X1/INTP1 P122/X2/EXCLK/INTP5 P137/INTP0 P123/XT1 P124/XT2/EXCLKS P40/TOOL0/(INTP1)/TI01/TO01 AVDD REGA SBIAS P10/INTP2/SCK20/SCL20 P07/SI20/RxD2/SDA20/TI05/TO05 P06/SO20/TxD2/TI00 P05/ANI10/TI06/TO06 P04/ANI9/INTP6/(SCK10/SCL10) P03/ANI8/(SI10/RxD1/SDA10)/TO00 P53/(INTP0) P52/SCK10/SCL10/TI02/TO02 P51/SI10/RxD1/SDA10/TI04/TO04 P50/SO10/TxD1/TI03/TO03 P77/TI07/TO07 P30/INTP3/RTC1HZ P37/SO00/TxD0/TOOLTxD P61/(INTP4)/SDAA0 P01/(INTP5) P02/(SO10/TxD1)/PCLBUZ0 AMP2O RL78/H1D (Top View) P70 AMP1N/AMP1P/AMP0P P32/INTP4/ SSI00 RESET

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 11 of 143 Mar 22, 2024 1.3.5 80-pin products (R5F11RM)

80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 µF). Caution 2. Make the AVSS pin the same potential as the VSS pin. Caution 3. Make the AVDD pin the same potential as the VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). P11/SEG30 P12/TxDMG0/SEG31 P13/RxDMG0/SEG32 P14/TRJIO1/SEG33 P15/TRJIO0/SEG34 P16/SMO0/SEG35 P17/SMO1 P84/SMO2 P85/SMP0/EXSDI0 P86/SMP1/EXSDI1 P150/SMP2 P151/SMP3 P20/SMP4 AV SS P21/SMP5 P22/INTP7 P23/INTP6 P24/(INTP5) P25/INTP4 P26/INTP3 P70/SEG8 P71/SEG9 P72/SEG10 P73/SEG11 P74/SEG12 P75/SEG13 P76/SEG14 P77/TI07/TO07/SEG15 P30/RTC1HZ/SEG16 P31/TI01/TO01/SEG17 P35/SCK00/SCL00/SEG19 P36/SI00/RxD0/TOOLRxD/SDA00/PCLBUZ1/SEG20 P37/SO00/TxD0/TOOLTxD/SEG21 P125/(TI06/TO06)/V VL4 VL2 VL1 P126/(TI05/TO05)/CAPL P127/(TI04/TO04)/CAPH 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P27/INTP2 AVDD P80/(SO20/TxD2)/(TI02/TO02)/TRJO0 P81/(SI20/RxD2/SDA20)/(TI00)/(TO00)/TRJO1 P82/(SCK20/SCL20)/(TI07/TO07)/EXSDO0 P83/(TI03/TO03)/EXSDO1/(PCLBUZ1) P44/(SO00/TxD0)/(SMP1) P43/(SI00/RxD0/SDA00)/(SMP0) P40/TOOL0/(SCK00/SCL00)/(TI01/TO01) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/(SSI00) P122/X2/EXCLK/INTP5 P121/X1/INTP1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P10/SCK20/SCL20/SEG29 P07/SI20/RxD2/SDA20/TI05/TO05/SEG28 P06/SO20/TxD2/TI00/SEG27 P05/ANI10/TI06/TO06/SEG26 P04/ANI9/(SCK10/SCL10)/SEG25 P03/ANI8/(SI10/RxD1/SDA10)/TO00/SEG24 P02/(SO10/TxD1)/PCLBUZ0/SEG23 P01/SEG22 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P53/SEG4 P52/SCK10/SCL10/TI02/TO02/SEG5 P51/SI10/RxD1/SDA10/TI04/TO04/SEG6 P50/SO10/TxD1/TI03/TO03/SEG7 RL78/H1D (Top View) P32/SSI00/SEG18

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 12 of 143 Mar 22, 2024

1.4 Pin Identification

AMP0N to AMP2N :OP AMP Negative Input REGA :Regulator Capacitance for AMP0P to AMP2P :OP AMP Positive Input Analog AMP0O to AMP2O :OP AMP Output REGC :Regulator Capacitance ANI8 to ANI14 :Analog Input SBIAS :Reference Voltage Output AVDD :Analog Power Supply RESET :Reset AVSS :Analog Ground RTC1HZ :Real-time Clock Correction CAPH, CAPL :Capacitor for LCD RxD0 to RxD2, RxDMG0 :Receive Data COM0 to COM7 :LCD Common Output SCK00, SCK10, SCK20, :Serial Clock Input/Output EXCLK :External Clock Input SCLA0 :Serial Clock Input/Output (Main System Clock) SCL00, SCL10, SCL20 :Serial Clock Output EXCLKS :External Clock Input SDAA0, SDA00, SDA10, :Serial Data Input/Output (Sub System Clock) SDA20 EXSDI0, EXSDI1 :External Sampling Input SEG0 to SEG35 :LCD Segment Output EXSDO0, EXSDO1 :External Sampling Clock SI00, SI10, SI20 :Serial Data Input Output SO00, SO10, SO20 :Serial Data Output INTP0 to INTP7 :External Interrupt Input SSI00 :Slave Select Input P01 to P07 :Port 0 SMP0 to SMP5 :Sampling Input P10 to P17 :Port 1 SMO0 to SMO2 :Sampling Clock Output P20 to P27 :Port 2 TI00 to TI07 :Timer Input P30 to P32, :Port 3 TO00 to TO07,TRJO0, TRJO1 :Timer Output P35 to P37 TOOL0 :Data Input/Output for Tool P40, P43, P44 :Port 4 TOOLRxD, TOOLTxD :Data Input/Output for P50 to P53 :Port 5 External Device P60 to P61 :Port 6 TRJIO0, TRJIO1 :Timer Input/Output P70 to P77 :Port 7 TxD0 to TxD2, TxDMG0 :Transmit Data P80 to P86 :Port 8 VDD :Power Supply P121 to P127 :Port 12 VL1 to VL4 :LCD Power Supply P137 :Port 13 VSS :Ground P150, P151 :Port 15 X1, X2 :Crystal Oscillator PCLBUZ0, PCLBUZ1 :Programmable Cl ock Output/ (Main System Clock) Buzzer Output XT1, XT2 :Crystal Oscillator PGA00N, PGA01N :PGA Negative Input (Subsystem Clock) PGA10N, PGA11N PGA00P, PGA01P :PGA Positive Input PGA10P, PGA11P PGA1O :PGA Output

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 13 of 143 Mar 22, 2024

1.5 Block Diagram

1.5.1 80-pin products (R5F11NM) RTC1HZ WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12 - BIT INTERVAL TIMER REAL -TIME CLOCK2 BUZZER OUTPUT PCLBUZ0, PCLBUZ1CLOCK OUTPUT CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT CRC SDAA0 SCLA0 SERIAL INTERFACE IICA0 RAM MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH ME MORY DATA FLASH MEMORY SERIAL ARRAY UNIT1 (2 ch) RxD2 TxD2 UART2 SCK 20 SO20 SI20 CSI 20 SCL20 SDA20 IIC20

3 ANI12 to ANI14

PORT 6 P60, P612 PORT 7 P70 to P778 SERIAL ARRAY UNIT0 (4 ch) UART1 CSI00 (SPI) CSI 10 IIC00 IIC 10 RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK 10 SI10 SO10 SCL00 SDA00 SCL10 SDA10 PORT 0 P01 to P077 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA SEG 0 to SEG35 36 8COM0 to COM7 VL1 to VL4 CAPH CAPL TOOLRxD, TOOLTxD PORT 1 P 10 to P17 PORT 3 P30 to P32, P35 to P37 PORT 4 P40, P43, P443 PORT 5 P50 to P534 PORT 12 P121 to P1244 P125 to P1273 P137PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0ON -CHIP DEBUG VOLTAGE REGULATOR REGC INTERRUPT CONTROL INTP0 to INTP78 SYSTEM CONTROL HIGH- SPEED ON-CHIP OSCILLATOR RESET X2/EXCLK XT1 XT2/EXCLKS PORT 8 P80 to P867 TIMER ARRAY UNIT0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 TI01/TO01 TI02/TO02 TI03/TO03 TI04/TO04 TI05/TO05 TI06/TO06 TI07/TO07 UART0 SSI00 8-BIT INTERVAL TIMER UNIT0(2ch) ch 00 ch 01 DATA TRANSFER CONTROL INT 10bit A/D CONVERTER TI00 TO00 AFE Volta ge Regulator REGA Sensor Bias SBIAS AMP0N/AMP0P AMP0O OPAMP (1ch) PGA00P PGA00N D/A converte r (1ch) AVDD AVSS Input Mux AMP0 DAC 0 Delta-Sigma A/D converter (24bit) PGA0 Input Mux ( 8bit R-2R ) (PG A0) (A M P ) AMP0P VSSVDD

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 14 of 143 Mar 22, 2024 1.5.2 64-pin products (R5F11NL) RTC1HZ WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER REAL -TIME CLOCK2 BUZZER OUTPUT PCLBUZ1 CLOCK OUTPUT CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT CRC SDAA0 SCLA0 SERIAL INTERFACE IICA0 RAM MULTIPLIER & DIVIDER, MULITIPLY - ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY SERIAL ARRAY UNIT1 (2 ch) RxD2 TxD2 UART2 SCK2 0 SO20 SI20 CSI20 SCL20 SDA20 IIC20 10bit A/D CONVERTER

3 ANI8,ANI10,ANI11

PORT 6 P60, P612 PORT 7 P70,P71,P76, P774 SERIAL ARRAY UNIT0 (4 ch) UART1 CSI00 (SPI) CSI10 IIC00 IIC10 RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK1 0 SI10 SO10 SCL00 SDA00 SCL10 SDA10 PORT 0 P03,P05 ,P06 ,P074 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA SEG0 to SEG3, SEG5to SEG9, SEG14to SEG21, SEG24, SEG26to SEG34 8COM0 to COM7 VL1 to VL4 CAPH CAPL TOOLRxD, TOOLTxD PORT 1 P10 to P15 PORT 3 P30 to P32, P35 to P376 PORT 4 P401 PORT 5 P50 to P523 PORT 12 P121 to P1244 P125 to P1273 P137PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0ON-CHIP DEBUG VOLTAGE REGULATOR REGC INTERRUPT CONTROL INTP0 to INTP56 SYSTEM CONTROL HIGH-SPEED ON -CHIP OSCILLATOR RESET X2/EXCLK XT1 XT2/EXCLKS PORT 8 P82, P832 TIMER ARRAY UNIT0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 TI01/TO01 TI02/TO02 TI03/TO03 TI04/TO04 TI05/TO05 TI06/TO06 TI07/TO07 UART0 8-BIT INTERVAL TIMER UNIT0(2ch) ch 00 ch 01 DATA TRANSFER CONTROL INT TI00 TO00 SSI00 AFE Voltage Regulator RE GA Sensor Bias SBI AS AM P0 N / AMP 0P AM P2 O AM P1 O AM P1 N / AMP 1P / AMP0 P AM P0 O AM P2 N / AMP 2P / AMP1 P PGA 1O OPAMP (3ch) P GA10P / PGA00P / AMP1P PGA 10N / P GA0 0N / AM P2P D/A converter (2c h) AVDD AVSS Input Mux AM P0 AM P1 AM P2 DAC 0 Delta-Sigma A/D converter (24bi t) PGA0 Input Mux DAC 1 (8 bi t R -2R ) (1 2b it R -2R ) Input MuxPGA1 (PGA0) (PGA 1) (AMP) VSSVDD

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 15 of 143 Mar 22, 2024 1.5.3 64-pin products (R5F11PL), 48-pin products (R5F11NG) Remark 64-pin products (R5F11PL) have the same functionality as 48-pin products (R5F11NG). The only difference is the package. RTC1HZ WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER REAL-TIME CLOCK2 BUZZER OUTPUT PCLBUZ0, PCLBUZ1CLOCK OUTPUT CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT CRC SDAA0 SCLA0 SERIAL INTERFACE IICA0 RAM MULTIPLIER & DIVIDER, MULITIPLY - ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY SERIAL ARRAY UNIT1 (2 ch) RxD2 TxD2 UART2 SCK20 SO20 SI20 CSI 20 SCL20 SDA20 IIC20 10bit A/D CONVERTER

3 ANI8 to ANI10

PORT 6 P60, P612 PORT 7 P70,P71,P76,P774 SERIAL ARRAY UNIT0 (4 ch) UART1 CSI00 (SPI) CSI 10 IIC00 IIC10 RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK10 SI10 SO10 SCL00 SDA00 SCL10 SDA10 PORT 0 P01 to P077 TOOLRxD, TOOLTxD PORT 1 P10 PORT 3 P30,P32, P35 to P37 PORT 4 P40 PORT 5 P50 to P534 PORT 12 P121 to P1244 P137PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0ON- CHIP DEBUG VOLTAGE REGULATOR REGC INTERRUPT CONTROL INTP0 to INTP67 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X2/EXCLK XT1 XT2/EXCLKS TIMER ARRAY UNIT0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 TI01/TO01 TI02/TO02 TI03/TO03 TI04/TO04 TI05/TO05 TI06/TO06 TI07/TO07 UART0 8-BIT INTERVAL TIMER UNIT 0( 2ch) ch 00 ch 01 DATA TRANSFER CONTROL INT PGA 1 1P/P GA0 1P PGA 1 1N/PGA0 1N AFE Vo ltage Re gulat or REGA Se nsor B ias SB IAS A MP0N / AMP0P AM P2O AM P1O A MP1N / AMP1P / AMP0P AM P0O A MP2N / AMP2P / AMP1P PGA 1 O OPAMP (3ch) P GA10P / P GA00P / AMP1P PGA 1 0N / PGA00N / AM P2 P D/ A c onve rt er (2 ch) AVDD AVSS Input Mux AMP0 AMP1 AMP2 DAC 0 De lt a -S ig ma A/D convert er (24bit) PGA 0 Input Mux DAC 1 (8 bit R-2R) (1 2b it R-2R) Input MuxPGA 1 (PGA0 ) (PGA1) (AMP) TI00 TO00 SSI00 VSSVDD

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 16 of 143 Mar 22, 2024 1.5.4 80-pin products (R5F11RM) WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER BUZZER OUTPUT PCLBUZ0, PCLBUZ1CLOCK OUTPUT CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT CRC SDAA0 SCLA0 SERIAL INTERFACE IICA0 RAM MULTIPLIER & DIVIDER, MULITIPLY - ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY PORT 2 P20 to P278 PORT 6 P60, P612 PORT 7 P70 to P778 SERIAL ARRAY UNIT0 (4 ch) UART1 CSI00 (SPI) CSI10 IIC00 IIC10 RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK10 SI10 SO10 SCL00 SDA00 SCL10 SDA10 PORT 0 P01 to P077 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA SEG0 to SEG35 36 8COM0 to COM7 VL1 to VL4 CAPH CAPL TOOLRxD, TOOLTxD AVSS, VSS AVDD, VDD PORT 1 PORT 3 P30 to P32, P35 to P37 PORT 4 P40, P43, P443 PORT 5 P50 to P534 PORT 12 P121 to P1244 P125 to P1273 P137PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0ON-CHIP DEBUG VOLTAGE REGULATOR REGC INTERRUPT CONTROL INTP0 to INTP78 PORT 15 P150,P1512 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK XT1 XT2/EXCLKS PORT 8 P80 to P867 TIMER ARRAY UNIT0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 UART0 8-BIT INTERVAL TIMER UNIT0(2ch) ch 00 ch 01 DATA TRANSFER CONTROL INT 8-BIT INTERVAL TIMER UNIT1(2ch) ch 10 ch 11 8-BIT INTERVAL TIMER UNIT2(2ch) ch 20 ch 21 TIMER RJ UNIT0 TRJIO0 TRJO0 TIMER RJ UNIT1 TRJIO1 TRJO1 EXTERNAL SIGNAL SAMPLER EXSDI0 EXSDI1 EXSDO0 EXSDO1 SMOTD(6ch) SMP0 SMP1 SMP2 SMP3 SMP4 SMP5 SMO0 SMO1 SMO2 UARTMG RxDMG0 TxDMG0 TI01/TO01 TI02/TO02 TI03/TO03 TI04/TO04 TI05/TO05 TI06/TO06 TI07/TO07 10bit A/D CONVERTER UNIT1 (2 ch) RxD2 TxD2 UART2 SCK20 SO20 SI20 CSI20 SCL20 SDA20 IIC20 SSI00 RESET P10 to P178 REAL-TIME CLOCK2RTC1HZ

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 17 of 143 Mar 22, 2024

1.6 Outline of Functions

(1/3) Item 80-pin LFQFP 64-pin LFQFP 64-pin TFBGA 48-pin LFQFP 80-pin LFQFP R5F11NMx (x = E to G) R5F11NLx (x = F, G) R5F11PLx, R5F11NGx (x = F, G) R5F11RMG Code flash memory (KB) 64 to 128 96 to 128 96 to 128 128 Data flash memory (KB) 4 4 4 4 RAM (KB) 5.5 5.5 5.5 8 Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: V DD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 2.4 to 2.7 V 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V High-speed on-chip oscillator clock HS (high-speed main) operation mode: 1 to 24 MHz DD = 2.7 to 5.5 V), HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V) HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 38.4 kHz (TYP.): VDD = 1.8 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.04167 µs (High-speed on-chip oscillator clock: f IH = 24 MHz operation) 0.05 µs (High-speed system clock: fMX = 20 MHz operation) 30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 53 36 29 63 CMOS I/O 46 29 22 56 CMOS input 555 5 CMOS output ——— — N-ch open-drain I/O (6 V tolerance) 222 2

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 18 of 143 Mar 22, 2024 (2/3) Item 80-pin LFQFP 64-pin LFQFP 64-pin TFBGA 48-pin LFQFP 80-pin LFQFP R5F11NMx (x = E to G) R5F11NLx (x = F, G) R5F11PLx, R5F11NGx (x = F, G) R5F11RMG Timer 16-bit timer TAU 8 channels (Timer outputs: 8, PWM outputs: 7 Note 1) 8-bit or 16-bit interval timer 2 channels (8 bits)/1 channel (16 bits) 6 channels (8 bits)/3 channels (16 bits) Watchdog timer 1 channel 12-bit interval timer 1 channel Real-time clock 2 1 channel RTC output 1

1 Hz (subsystem clock: f

SUB = 32.768 kHz) 16-bit timer RJ — 2 channels, timer outputs: 2 External signal sampler — 1 channel Sampling output timer detector (SMOTD) — Input: 6 channels Output: 3 channels Clock output/buzzer output 2 1 2 2 (Main system clock: f MAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter Internal 3 channels External 2 channels: Internal reference voltage (1.45 V), temperature sensor output voltage (only selectable in HS (high-speed main) mode) 24-bit ΔΣ A/D converter with programmable gain instrumentation amplifier 0 (PGA0) Analog input: 1 channel (differential or single-ended) Analog input: 1 channel (differential or single-ended), 3 channels (single-ended) Analog input: 2 channels (differential or single-ended), 3 channels (single-ended) D/A converter 12-bit 1 channel (with an output amplifier but no external output pin) 1 channel (with an output amplifier but no external output pin) 8-bit 1 channel (without an output amplifier and no external output pin) 1 channel (without an output amplifier and no external output pin) 1 channel (without an output amplifier and no external output pin) Programmable gain instrumentation amplifier 1 (PGA1) — 1 channel 1 channel — Rail-to-rail operational amplifier 1 channel 1 channel 1 channel — General-purpose operational amplifier — 2 channels 2 channels — Serial interface • Simplified SPI(CSI)(SPI supported): 1 channel/UART (LIN-bus supported): 1 channel/simplified I 2C: 1 channel

Simplified SPI(CSI): 1 channel/UART: 1 channel/simplified I2C: 1 channel
Simplified SPI(CSI): 1 channel/UART: 1 channel/simplified I2C: 1 channel I2C bus 1 channel 1 channel Serial interface UARTMG — 1 channel

RL78/H1D 1. OUTLINE R01DS0318EJ0111 Rev. 1.11 Page 19 of 143 Mar 22, 2024 Note 1. The number of outputs depends on the setting of channels in use and the number of the master. Note 2. The number in parentheses indicates the number of signal outputs when 8 coms are used. Note 3. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. (3/3) Item 80-pin LFQFP 64-pin LFQFP 64-pin TFBGA 48-pin LFQFP 80-pin LFQFP R5F11NMx (x = E to G) R5F11NLx (x = F, G) R5F11PLx, R5F11NGx (x = F, G) R5F11RMG LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 36 (32) Note 2 27 (23) Note 2 — 36 (32) Note 2 Common signal output 4 (8) Note 2 4 (8) Note 2 — 4 (8) Note 2 Data transfer controller (DTC) 26 sources 24 sources 25 sources 35 sources Event link controller (ELC) Event input: 20, Event trigger output: 7 Event input: 18, Event trigger output: 10 Event input: 19, Event trigger output: 10 Event input: 26, Event trigger output: 5 Vectored interrupt sources Internal 29 29 29 43 External 867 8 Reset • Reset by RESET pin

Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note 3
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.04 V
Power-down-reset: 1.50 ±0.04 V Voltage detector • Rising edge: 2.50 V to 4.06 V (9 stages)
Falling edge: 2.45 V to 3.98 V (9 stages)
Rising edge: 1.88 V to 4.06 V (12 stages)
Falling edge: 1.84 V to 3.98 V (12 stages) On-chip debug function Provided Power supply voltage V DD = 2.4 to 5.5 V (10-bit SAR A/D converter: 2.4 to 5.5 V, operating voltage of the analog front-end (AFE): 2.7 to 5.5 V) VDD = 1.8 to 5.5 V Operating ambient temperature T A = -40 to +85°C (A: Consumer applications) T A = -40 to +85°C (D: Industrial applications)

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 20 of 143 Mar 22, 2024 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) This chapter describes the electrical specifications for the products A: Consumer applications (TA = -40 to +85°C). Caution 1. The RL78 microcontroller has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2 Functions other than port pins in the User’s Manual: Hardware.

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 21 of 143 Mar 22, 2024

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). This val ue regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Connect the REGA pin to AVSS via a capacitor (0.22 μF). This value regulates the absolute maximum rating of the REGA pin. Do not use this pin with voltage applied to it. Note 3. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. The reference voltage is V SS (for the VDD systems) = AVSS (for the AVDD systems) Absolute Maximum Ratings (1/3) Parameter Symbols Conditions Ratings Unit Supply voltage VDD -0.5 to +6.5 V AVDD AVDD = VDD -0.5 to +6.5 V AVSS AVSS = VSS -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD + 0.3 Note 1 V REGA pin input voltage V IREGA REGA -0.3 to +2.8 and -0.3 to AVDD + 0.3 Note 2 V Input voltage V I1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P121 to P124, P125 to P127, P137, EXCLK, EXCLKS, RESET -0.3 to VDD + 0.3 Note 3 V VI2 P60, P61 (N-ch open-drain) -0.3 to +6.5 V Output voltage VO1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127 -0.3 to V DD + 0.3 Note 3 V Analog input voltage V AI1 ANI8 to ANI11 -0.3 to VDD + 0.3 Note 3 V VAI2 ANI12 to ANI14 PGA00P, PGA01P , PGA10P, PGA11P , PGA00N, PGA01N, PGA10N, PGA11N, AMP0P to AMP2P , AMP0N to AMP2N -0.3 to AV DD + 0.3 Note 3 V Analog output voltage V OA SBIAS, PGA1O, AMP0O to AMP2O -0.3 to AVDD + 0.3 Note 3 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 22 of 143 Mar 22, 2024 Note 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recomm ended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 μF ± 30%) and connect a capacitor (0.47 μF ± 30%) between the CAPL and CAPH pins. Note 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Absolute Maximum Ratings (2/3) Parameter Symbols Conditions Ratings Unit LCD voltage V LI1 VL1 input voltage Note 1 -0.3 to +2.8 V VLI2 VL2 input voltage Note 1 -0.3 to +6.5 V VLI3 VL3 input voltage Note 1 -0.3 to +6.5 V VLI4 VL4 input voltage Note 1 -0.3 to +6.5 V VLI5 CAPL, CAPH input voltage Note 1 -0.3 to +6.5 V VLO1 VL1 output voltage -0.3 to +2.8 V VLO2 VL2 output voltage -0.3 to +6.5 V VLO3 VL3 output voltage -0.3 to +6.5 V VLO4 VL4 output voltage -0.3 to +6.5 V VLO5 CAPL, CAPH output voltage -0.3 to +6.5 V VLO6 COM0 to COM7 SEG0 to SEG35 output voltage External resistance division method -0.3 to V DD + 0.3 Note 2 V Capacitor split method -0.3 to V DD + 0.3 Note 2 V Internal voltage boosting method -0.3 to V LI4 + 0.3 Note 2 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 23 of 143 Mar 22, 2024 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Absolute Maximum Ratings (3/3) Parameter Symbols Conditions Ratings Unit Output current, high I OH1 Per pin -40 mA Total of all pins -170 mA P40, P43, P44, P80 to P83 -70 mA P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P70 to P77, P84 to P86, P125 to P127 -100 mA Output current, low I OL1 Per pin 40 mA Total of all pins 170 mA P40, P43, P44, P80 to P83 70 mA P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P60, P61, P70 to P77, P84 to P86, P125 to P127 100 mA Operating ambient temperature T A In normal operation mode -40 to +85 °C In flash memory programming mode Storage temperature T stg -65 to +150 °C

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 24 of 143 Mar 22, 2024

2.2 Oscillator Characteristics

2.2.1 X1 and XT1 oscill ator characteristics

Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 and XT1 oscillator, refer to 5.4 System Clock Oscillator in the User’s Manual: Hardware. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Resonator Conditions MIN. TYP . MAX. Unit X1 clock oscillation frequency (fX) Note Ceramic resonator/crystal resonator 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 XT1 clock oscillation frequency (fXT) Note Crystal resonator 32 32.768 35 kHz

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 25 of 143 Mar 22, 2024

2.2.2 On-chip oscillator characteristics

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 26 of 143 Mar 22, 2024

2.3 DC Characteristics

2.3.1 Pin characteristics

Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin (IOH1) to an output pin. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P02 to P04, P06, P07, P10, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP . MAX. Unit Output current, high Note 1 IOH1 Per pin for P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 -10.0 Note 2 mA Total of P40, P43, P44, P80 to P83 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -55 mA 2.7 V ≤ VDD < 4.0 V -10 mA 2.4 V ≤ VDD < 2.7 V -5 mA Total of P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P70 to P77, P84 to P86, P125 to P127 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -69 mA 2.7 V ≤ VDD < 4.0 V -23 mA 2.4 V ≤ VDD < 2.7 V -12 mA Total of all pins (When duty ≤ 70% Note 3) 2.4 V ≤ VDD ≤ 5.5 V -124 mA

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 27 of 143 Mar 22, 2024 Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin (IOL1). Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 IOL1 Per pin for P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 20.0 Note 2 mA Per pin for P60 and P61 15.0 Note 2 mA Total of P40, P43, P44, P80 to P83 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 70 mA 2.7 V ≤ VDD < 4.0 V 15 mA 2.4 V ≤ VDD < 2.7 V 9 mA P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P60, P61, P70 to P77, P84 to P86, P125 to P127 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 90 mA 2.7 V ≤ VDD < 4.0 V 35 mA 2.4 V ≤ VDD < 2.7 V 20 mA Total of all pins (When duty ≤ 70% Note 3) 160 mA

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 28 of 143 Mar 22, 2024 Caution The maximum value of V IH of pins P02 to P04, P06, P07, P10, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 Normal input buffer 0.8 V DD VDD V VIH2 For TTL mode supported ports TTL input buffer 4.0 V ≤ VDD ≤ 5.5 V

2.2 VDD V

3.3 V ≤ V

DD < 4.0 V

2.0 V DD V

2.4 V ≤ VDD < 3.3 V

1.50 VDD V

VIH4 P60, P61 0.7 VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127 Normal input buffer 0 0.2 V DD V VIL2 For TTL mode supported ports TTL input buffer 4.0 V ≤ VDD ≤ 5.5 V 00 . 8 V TTL input buffer DD < 4.0 V 00 . 5 V TTL input buffer

2.4 V ≤ V

DD < 3.3 V 00 . 3 2 V VIL4 P60, P61 0 0.3 VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 29 of 143 Mar 22, 2024 Caution P02 to P04, P06, P07, P10, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127

4.0 V ≤ V

DD ≤ 5.5 V, IOH = -10.0 mA VDD - 1.5 V 4.0 V ≤ VDD ≤ 5.5 V, IOH = -3.0 mA VDD - 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH = -2.0 mA VDD - 0.6 V 2.4 V ≤ VDD ≤ 5.5 V, IOH = -1.5 mA VDD - 0.5 V Output voltage, low V OL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 DD ≤ 5.5 V, IOL = 20.0 mA 1.3 V 4.0 V ≤ VDD ≤ 5.5 V, IOL = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 3.0 mA 0.6 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 1.5 mA 0.4 V 2.4 V ≤ VDD ≤ 5.5 V, IOL = 0.6 mA 0.4 V VOL3 P60, P61 4.0 V ≤ VDD ≤ 5.5 V, IOL = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 3.0 mA 0.4 V 2.4 V ≤ VDD ≤ 5.5 V, IOL = 2.0 mA 0.4 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 30 of 143 Mar 22, 2024 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127, P137, RESET VI = VDD 1µ A ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VDD In input port or external clock input 1µ A In resonator connection 10 µA Input leakage current, low I LIL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127, P137, RESET VI = VSS -1 µA ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VSS In input port or external clock input -1 µA In resonator connection -10 µA On-chip pull-up resistance R U1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 V I = VSS or In input port 10 20 100 k Ω

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 31 of 143 Mar 22, 2024

2.3.2 Supply current characteristics

Note 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The following points apply in the HS (high-speed main) mode.

The currents in the “TYP .” column do not include the operating currents of the peripheral modules.
The currents in the “MAX.” column include the operating currents of the peripheral modules, except for those flowing into the LCD controller/driver, A/D converter, LVD, I/O port, and on-chip pull-up/pull-down resistors, and those flowing while the data flash memory is being rewritten. In the subsystem cloc k operation, the currents in both the “TYP.” and “MAX.” columns do not include the operating currents of the peripheral modules. However, in HALT mode, including the current flowing into the real-time clock 2. The current flowing into AFE is not included. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ V DD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Note 6. IDD1 do not include the current flowing to the AFE. The current value of the RL78 microcontrollers is the sum of I DD1, IDD2, or IDD3 and AFE current (AVDD systems) when the AFE operates in the operating mode, HALT mode, or STOP mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C. (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, Note 6 IDD1 Operating mode HS (high-speed main) mode Note 5 fIH = 24 MHz Note 3 Basic operation VDD = 5.0 V 1.7 mA VDD = 3.0 V 1.7 Normal operation V DD = 5.0 V 3.7 6.2 VDD = 3.0 V 3.7 6.2 fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 2.8 4.8 VDD = 3.0 V 2.8 4.8 HS (high-speed main) mode Note 5 fMX = 20 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 3.1 5.2 mA Resonator connection 3.3 5.3 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.0 5.2 Resonator connection 3.3 5.3 f MX = 16 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.6 4.5 Resonator connection 2.8 4.6 fMX = 16 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 2.6 4.5 Resonator connection 2.8 4.6 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 1.9 3.0 Resonator connection 1.9 3.0 f MX = 10 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.9 3.0 Resonator connection 1.9 3.0 Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = -40°C Normal operation Square wave input 4.3 5.8 µA Resonator connection 4.6 5.8 f SUB = 32.768 kHzNote 4 TA = +25°C Normal operation Square wave input 4.3 5.8 Resonator connection 4.6 5.8 fSUB = 32.768 kHzNote 4 TA = +50°C Normal operation Square wave input 4.5 7.6 Resonator connection 4.5 7.6 fSUB = 32.768 kHzNote 4 TA = +70°C Normal operation Square wave input 4.7 9.2 Resonator connection 5.1 9.2 fSUB = 32.768 kHzNote 4 TA = +85°C Normal operation Square wave input 5.2 12.6 Resonator connection 5.7 12.6

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 32 of 143 Mar 22, 2024 (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, Note 8 IDD2 Note 2 HALT mode HS (high-speed main) mode Note 6 fIH = 24 MHz Note 4 VDD = 5.0 V 0.42 1.83 mA VDD = 3.0 V 0.42 1.83 fIH = 16 MHz Note 4 VDD = 5.0 V 0.39 1.38 VDD = 3.0 V 0.39 1.38 HS (high-speed main) mode Note 6 fMX = 20 MHz Note 3, VDD = 5.0 V Square wave input 0.26 1.55 mA Resonator connection 0.40 1.68 fMX = 20 MHz Note 3, VDD = 3.0 V Square wave input 0.25 1.55 Resonator connection 0.40 1.68 fMX = 16 MHz Note 3, VDD = 5.0 V Square wave input 0.23 1.22 Resonator connection 0.36 1.39 fMX = 16 MHz Note 3, VDD = 3.0 V Square wave input 0.22 1.22 Resonator connection 0.35 1.39 fMX = 10 MHz Note 3, VDD = 5.0 V Square wave input 0.19 0.82 Resonator connection 0.29 0.90 fMX = 10 MHz Note 3, VDD = 3.0 V Square wave input 0.18 0.82 Resonator connection 0.28 0.90 Subsystem clock operation fSUB = 32.768 kHz Note 5 TA = -40°C Square wave input 0.32 0.69 µA Resonator connection 0.51 0.89 fSUB = 32.768 kHz Note 5 TA = +25°C Square wave input 0.41 0.82 Resonator connection 0.62 1.00 fSUB = 32.768 kHz Note 5 TA = +50°C Square wave input 0.52 1.40 Resonator connection 0.75 1.60 fSUB = 32.768 kHz Note 5 TA = +70°C Square wave input 0.82 2.70 Resonator connection 1.08 2.90 fSUB = 32.768 kHz Note 5 TA = +85°C Square wave input 1.38 4.95 Resonator connection 1.62 5.15 IDD3 STOP mode Note 7 TA = -40°C 0.20 0.59 µA TA = +25°C 0.26 0.72 TA = +50°C 0.33 1.30 TA = +70°C 0.53 2.60 TA = +85°C 0.93 4.85

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 33 of 143 Mar 22, 2024 Note 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The following points apply in the HS (high-speed main) mode.

The currents in the “TYP .” column do not include the operating currents of the peripheral modules.
The currents in the “MAX.” column include the operating currents of the peripheral modules, except for those flowing into the LCD controller/driver, A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors, and those flowing while the data flash memory is being rewritten. In the subsystem cloc k operation, the currents in both the “TYP.” and “MAX.” columns do not include the operating currents of the peripheral modules. However, in HALT mode, including the current flowing into the real-time clock 2. In the STOP mode, the currents in both the “TYP.” and “MAX.” columns do not include the operating currents of the peripheral modules. The current flowing into AFE is not included. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When high-speed on-chip oscillator and high-speed system cl ock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). Note 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ V DD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Note 7. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Note 8. IDD2 and IDD3 do not include the current flowing to the AFE. The current value of the RL78 microcontrollers is the sum of I DD1, IDD2, or IDD3 and AFE current (AVDD systems) when the AFE operates in the operating mode, HALT mode, or STOP mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 34 of 143 Mar 22, 2024

Peripheral functions (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current I FIL Note 1 0.20 µA RTC2 operating current I RTC Notes 1, 3 fSUB = 32.768 kHz 0.02 µA 12-bit interval timer operating current I TMKA Notes 1, 2, 4 fSUB = 32.768 kHz, fMAIN stopped 0.02 µA 8-bit interval timer operating current ITMRT Notes 1, 14 fSUB = 32.768 kHz, fMAIN stopped, per unit 8-bit counter mode × 2-channel operation 0.12 µA 16-bit counter mode operation 0.10 µA Watchdog timer operating current I WDT Notes 1, 5 fIL = 15 kHz 0.22 µA A/D converter operating current IADC Notes 1, 6 When conversion at maximum speed Normal mode, V DD = 5.0 V 1.3 1.7 mA Low-voltage mode, VDD = 3.0 V 0.5 0.7 mA Internal reference voltage (1.45 V) current IADREF Notes 1, 7 85 µA Temperature sensor operating current ITMPS Note 1 85 µA LVD operating current ILVI Notes 1, 8 0.06 µA Self-programming operating current IFSP Notes 1, 9 2.0 12.2 mA BGO operating current IBGO Notes 1, 10 2.0 12.2 mA SNOOZE operating current I SNOZ Notes 1, 11 A/D converter operation The mode is performed 0.50 0.60 mA During A/D conversion, low-voltage mode, VDD = 3.0 V 1.20 1.44 Simplified SPI(CSI)/UART operation 0.70 0.84 mA DTC operation 3.1 mA LCD operating current ILCD1 Notes 12, 13 External resistance division method f LCD = fSUB LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 5.0 V, VL4 = 5.0 V 0.04 0.20 µA ILCD2 Note 12 Internal voltage boosting method f LCD = fSUB LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 3.0 V, VL4 = 3.0 V (VLCD = 04H) 0.85 2.20 µA VDD = 5.0 V, VL4 = 5.1 V (VLCD = 04H) 1.55 3.70 µA ILCD3 Note 12 Capacitor split method f LCD = fSUB LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 3.0 V, VL4 = 3.0 V 0.20 0.50 µA

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 35 of 143 Mar 22, 2024 Note 1. Current flowing to VDD. Note 2. When high speed on-chip oscillator and high-speed system clock are stopped. Note 3. Current flowing only to the real-time cl ock 2 (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 micr ocontrollers is the sum of the values of either I DD1 or IDD2, and IRTC, when the real-time clock 2 operates in the operating mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2. Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is th e sum of the values of either I DD1 or IDD2, and ITMKA , when the 12-bit interval timer operates in the operating mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the 12-bit interval timer. Note 5. Current flowing only to the watchdog time r (including the operating current of th e low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of I DD1 or IDD2 and IADC, IADREF when the A/D converter operates in the operating mode or the HALT mode. Note 7. Operation current flowing to the internal reference voltage. Note 8. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of I DD1, IDD2, or IDD3 and ILVI when the LVD circuit operates in the operating mode, HALT mode, or STOP mode. Note 9. Current flowing only during self-programming. Note 10. Current flowing only during data flash rewrite. Note 11. For shift time to the SNOOZE mode, see 27.3.3 SNOOZE mode in the User’s Manual: Hardware. Note 12. Current flowing only to the LCD controller/driver (V DD pin). The current value of the RL78 microcontrollers is the sum of the LCD operating current (I LCD1, ILCD2, or ILCD3) and the supply current (I DD1 or IDD2) when the LCD controller/driver operates in the operating mode or HALT mode. Not including the current that flows through the LCD panel. Note 13. Not including the current that flows through the external divider resistor. Note 14. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either I DD1 or IDD2, and IIT, when the 8-bit interval time r operates in the operating mode or HALT mode. When the low-spee d on-chip oscillator is selected, IFIL should be added. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25°C

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 36 of 143 Mar 22, 2024

AFE functions Note 1. Current flowing to AVDD. The typical conditions are the conditions when TA = 25°C and AVDD = 3.3 V. Note 2. Current flowing only into the operating circuit indicated in the column for conditions. Note 3. Including the static current of VREFAMP, PGA0, and 24-bit ΔΣ A/D converter. Remark Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 24-bit  A/D converter operating current I DSAD Normal mode Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, VREFAMP, PGA0, 24-bit  A/D converter, and digital filter Differential input mode, OSR = 256, SBIAS I OUT = 0 mA 0.94 1.46 mA Low power mode Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, VREFAMP, PGA0, 24-bit  A/D converter, and digital filter Differential input mode, OSR = 256, SBIAS I OUT = 0 mA 0.60 0.91 mA Amplifier operating current I PGA1 Low power mode Notes 1, 2 Circuits that operate: ABGR, PGA1, and DAC1 I L = 0 mA 0.60 1.10 mA High-speed mode Notes 1, 2 Circuits that operate: ABGR, PGA1, and DAC1 I L = 0 mA 1.10 1.80 mA IAMP0 Low power mode Notes 1, 2 Circuits that operate: ABGR and AMP0 I L = 0 mA 0.10 0.15 mA High-speed mode Notes 1, 2 Circuits that operate: ABGR and AMP0 I L = 0 mA 0.30 0.48 mA IAMP1, IAMP2 Low power mode Notes 1, 2 Circuits that operate: ABGR and AMP1 or AMP2 I L = 0 mA 0.10 0.14 mA High-speed mode Notes 1, 2 Circuits that operate: ABGR and AMP1 or AMP2 I L = 0 mA 0.23 0.35 mA 8-bit D/A converter operating current I DAC0 SBIAS normal mode Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, and DAC0 Note 3 IL = 0 mA, SBIAS IOUT = 0 mA 1.00 1.50 mA SBIAS low-power mode Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, and DAC0 Note 3 IL = 0 mA, SBIAS IOUT = 0 mA 0.85 1.30 mA 12-bit D/A converter operating current I DAC1 When AVDD is selected as the reference voltage Notes 1, 2 Circuits that operate: ABGR and DAC1 I L = 0 mA 0.61 0.97 mA When SBIAS (normal mode) is selected as the reference voltage Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, and DAC1 Note 3 IL = 0 mA, SBIAS IOUT = 0 mA 1.06 1.62 mA When SBIAS (low-power mode) is selected as the reference voltage Notes 1, 2 Circuits that operate: ABGR, REGA, SBIAS, and DAC1 Note 3 IL = 0 mA, SBIAS IOUT = 0 mA 0.91 1.42 mA

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 37 of 143 Mar 22, 2024

2.4 AC Characteristics

2.4.1 Basic operation

Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 7)) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock (f MAIN) operation HS (high-speed main) mode

2.7 V ≤ V

DD ≤ 5.5 V 0.0417 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs Subsystem clock (fSUB) operation In the self- programming mode HS (high-speed main) mode DD ≤ 5.5 V 0.0417 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs External main system clock frequency f EX EXCLK 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz fEXT EXCLKS 32 35 kHz External main system clock input high-level width, low-level width t EXH, tEXL EXCLK 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns tEXHS, tEXLS EXCLKS 13.7 µs Timer input high-level width, low-level width t TIH, tTIL TI00 to TI07 1/fMCK + ns Timer output frequency f TO TO00 to TO07 HS (high-speed main) mode DD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz Buzzer output frequency f PCL PCLBUZ0, PCLBUZ1 HS (high-speed main) mode DD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz Interrupt input high- level width, low-level width t INTH, tINTL INTP0 to INTP7 2.4 V ≤ VDD ≤ 5.5 V 1 µs RESET low-level width tRSL 10 µs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 38 of 143 Mar 22, 2024 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 1.0 0.1 2.7 0.01 2.4 0.0417 0.0625 0.05 During self programming When high-speed system clock is selected When the high-speed on-chip oscillator clock is selected Cycle time TCY [µs] Supply voltage V DD [V]

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 39 of 143 Mar 22, 2024 AC Timing Test Points External System Clock Timing TI/TO Timing Interrupt Request Input Timing RESET Input Timing VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07 INTP0 to INTP7 tINTL tINTH tRSL RESET

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 40 of 143 Mar 22, 2024

2.5 Peripheral Functions Characteristics

2.5.1 Serial array unit

Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. The following conditions are required for low voltage interface. 2.4 V ≤ VDD < 2.7 V: MAX. 2.6 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Remark 1. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) (1) During communication at same potential (UART mode) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 1 2.4 V ≤ VDD ≤ 5.5 V fMCK/6 Note 2 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3

4.0 Mbps

User’s device Rx Tx Baud rate error tolerance TxDq RxDq High-/Low-bit width 1/Transfer rate

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 41 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) (2) During communication at same potential (Simplified SPI(CSI) mode) (master mode, SCKp... internal clock output) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ fCLK/4 2.7 V ≤ VDD ≤ 5.5 V 167 ns 2.4 V ≤ VDD ≤ 5.5 V 250 ns SCKp high-/low-level width t KH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 - 12 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 - 18 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 - 38 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 ns 2.7 V ≤ VDD ≤ 5.5 V 44 ns 2.4 V ≤ VDD ≤ 5.5 V 75 ns SIp hold time (from SCKp↑) Note 2 tKSI1 2.4 V ≤ VDD ≤ 5.5 V 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 20 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 25 ns 2.4 V ≤ VDD ≤ 5.5 V 25 ns

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 42 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) (3) During communication at same potential (Simplified SPI(CSI) mode) (slave mode, SCKp... external clock output) (1/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns fMCK ≤ 20 MHz 8/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V f MCK > 16 MHz 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/f MCK and 500 ns SCKp high-/low-level width t KH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V tKCY2/2 - 7 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 - 8 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY2/2 - 18 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 20 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 30 ns SIp hold time (from SCKp↑) Note 2 tKSI2 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK + 44 ns 2.4 V ≤ VDD ≤ 5.5 V 2/fMCK + 75 ns

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 43 of 143 Mar 22, 2024 Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 4) Simplified SPI(CSI) mode connection diagram (during communication at same potential) Simplified SPI(CSI) mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) (3) During communication at same potential (Simplified SPI(CSI) mode) (slave mode, SCKp... external clock output) (2/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SSI00 setup time tSSIK DAPmn = 0 2.7 V ≤ VDD ≤ 5.5 V 120 ns 2.4 V ≤ VDD ≤ 5.5 V 200 ns DAPmn = 1 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 120 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 200 ns SSI00 hold time tKSSI DAPmn = 0 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 120 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 200 ns DAPmn = 1 2.7 V ≤ VDD ≤ 5.5 V 120 ns 2.4 V ≤ VDD ≤ 5.5 V 200 ns RL78 microcontroller SCKp SOp User's device SCK SI SIp SO SCK00 SO00 User's device SCK SI SI00 SO SSI00 SSO RL78 microcontroller

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 44 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) SIp SOp tKCY1, 2 Input data Output data SCKp tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Input data Output data tKCY1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SIp SOp SCKp tKL1, 2

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 45 of 143 Mar 22, 2024 Note 1. The value must be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (4) During communication at sa me potential (simplified I2C mode) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ

1000 Note 1 kHz

2.4 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ

400 Note 1 kHz

2.4 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ

300 Note 1 kHz

when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 2.4 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns 2.4 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 2.4 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns 2.4 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 ns Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 85 Note 2 ns 2.4 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note 2 ns 2.4 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230 Note 2 ns Data hold time (transmission) t HD: DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 03 0 5 n s 2.4 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 03 55 n s 2.4 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 04 0 5 n s

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 46 of 143 Mar 22, 2024 Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SCLr, SDAr) load capacitance Remark 2. r: IIC number (r = 00, 10, 20), g: PIM number (g = 0, 1, 3, 4, 5, 8), Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10) RL78 microcontroller SDAr SCLr User’s device SDA SCL VDD Rb SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 47 of 143 Mar 22, 2024 Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only. Note 2. Use it with VDD ≥ Vb. Note 3. The following conditions are required for low voltage interface. 2.4 V ≤ VDD < 2.7 V: MAX. 2.6 Mbps Note 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 4 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1, 2, 3 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 4

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 48 of 143 Mar 22, 2024 Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD ≤ 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use it with VDD ≥ Vb. (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V

2.8 Note 2 Mbps

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V

1.2 Note 4 Mbps

2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V

0.43 Note 7 Mbps

Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2.2 Vb 2.2 Vb Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2.0 Vb 2.0 Vb

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 49 of 143 Mar 22, 2024 Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 1.5 Vb 1.5 Vb

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 50 of 143 Mar 22, 2024 UART mode connection diagram (during communication at different potential) UART mode bit width (during communication at different potential) (reference) Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) RL78 microcontroller TxDq RxDq User’s device Rx Tx Vb Rb Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 51 of 143 Mar 22, 2024 Note Use it with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) internal clock output) (1/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 300 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ

500 Note ns

2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ

1150 Note ns

tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 170 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 458 ns SCKp low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 12 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 18 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 50 ns

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 52 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. Use it with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) internal clock output) (2/2) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↑) Note 1 SIp hold time (from SCKp↑) Note 1 Delay time from SCKp↓ to SOp output Note 1 SIp setup time (to SCKp↓) Note 2 SIp hold time (from SCKp↓) Note 2 Delay time from SCKp↑ to SOp output Note 2

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 53 of 143 Mar 22, 2024 Simplified SPI(CSI) mode connection diagram (during communication at different potential) Remark 1. Rb[Ω]: Communication line (SCKp, SO p) pull-up resistance, C b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) RL78 microcontroller SCKp SOp User’s device SCK SI SIp SO <Master> Vb Rb Vb Rb

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 54 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 55 of 143 Mar 22, 2024 Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with VDD ≥ Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) external clock input) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

20 MHz < fMCK 12/fMCK ns

8 MHz < fMCK ≤ 20 MHz 10/f MCK ns

4 MHz < fMCK ≤ 8 MHz 8/f MCK ns

fMCK ≤ 4 MHz 6/f MCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

20 MHz < fMCK 16/fMCK ns

16 MHz < fMCK ≤ 20 MHz 14/f MCK ns

8 MHz < fMCK ≤ 16 MHz 12/f MCK ns

fMCK ≤ 4 MHz 6/f MCK ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

20 MHz < fMCK 36/fMCK ns

16 MHz < fMCK ≤ 20 MHz 32/f MCK ns

8 MHz < fMCK ≤ 16 MHz 26/f MCK ns

4 MHz < fMCK ≤ 8 MHz 16/f MCK ns

fMCK ≤ 4 MHz 10/f MCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V t KCY2/2 - 12 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 - 18 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 - 50 ns SIp setup time (to SCKp↑) Note 3 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/f MCK + 20 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 30 ns SIp hold time (from SCKp↑) Note 4 tKSI2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/f MCK + 31 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 31 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 31 ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 ns

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 56 of 143 Mar 22, 2024 Simplified SPI(CSI) mode connection diagram (during communication at different potential) Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) RL78 microcontroller SCKp SOp User’s device SCK SI SIp SO Vb Rb <Slave>

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 57 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 5, 8) SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2 Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 58 of 143 Mar 22, 2024 Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with VDD ≥ Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by usi ng port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (8) Communication at different potentia l (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency Hold time when SCLr = “L” t Hold time when SCLr = “H” t Data setup time (reception) t Data hold time (transmission)

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 59 of 143 Mar 22, 2024 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, C b[F]: Communication line (SDA r, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 10, 20), g: PIM, POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10) RL78 microcontroller SDAr SCLr User’s device SDA SCL Vb Rb Vb Rb SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 60 of 143 Mar 22, 2024

2.5.2 Serial interface IICA

Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ (1) I 2C standard mode (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Standard mode: fCLK ≥ 1 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 100 kHz 2.4 V ≤ VDD ≤ 5.5 V 0 100 kHz Setup time of restart condition t SU: STA 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs 2.4 V ≤ VDD ≤ 5.5 V 4.7 µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs 2.4 V ≤ VDD ≤ 5.5 V 4.0 µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs 2.4 V ≤ VDD ≤ 5.5 V 4.7 µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs 2.4 V ≤ VDD ≤ 5.5 V 4.0 µs Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V 250 ns 2.4 V ≤ VDD ≤ 5.5 V 250 ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 3.45 µs 2.4 V ≤ VDD ≤ 5.5 V 0 µs Setup time of stop condition t SU: STO 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs 2.4 V ≤ VDD ≤ 5.5 V 4.0 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs 2.4 V ≤ VDD ≤ 5.5 V 4.7 µs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 61 of 143 Mar 22, 2024 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD: DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ (2) I 2C fast mode (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 400 kHz 2.4 V ≤ VDD ≤ 5.5 V 0 400 kHz Setup time of restart condition t SU: STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs 2.4 V ≤ VDD ≤ 5.5 V 0.6 µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs 2.4 V ≤ VDD ≤ 5.5 V 0.6 µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 1.3 µs 2.4 V ≤ VDD ≤ 5.5 V 1.3 µs Hold time when SCLA0 = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs 2.4 V ≤ VDD ≤ 5.5 V 0.6 µs Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V 100 ns 2.4 V ≤ VDD ≤ 5.5 V 100 ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.9 µs 2.4 V ≤ VDD ≤ 5.5 V 0 µs Setup time of stop condition t SU: STO 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs 2.4 V ≤ VDD ≤ 5.5 V 0.6 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 1.3 µs 2.4 V ≤ VDD ≤ 5.5 V 1.3 µs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 62 of 143 Mar 22, 2024 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD: DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing (3) I 2C fast mode plus (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 1000 kHz Setup time of restart condition t SU: STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs Hold time when SCLA0 = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V 50 ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 µs Setup time of stop condition t SU: STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs tSU: DATtHD: STA Restart condition SCLn SDAn tLOW tHIGH tR tF tSU: STA tHD: STA tSU: STO Stop condition Stop condition Start condition tHD: DAT tBUF

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 63 of 143 Mar 22, 2024

2.6 Analog Characteristics

2.6.1 A/D converte r characteristics

(1) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI8 to ANI14, internal reference voltage, and temperature sensor output voltage Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. Refer to 2.6.2 Temperature sensor/internal reference voltage output characteristics. (TA = –40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = VDD, reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 81 0 bit Overall error Note 1 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution Target pin: ANI8 to ANI14 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs 10-bit resolution Target pin: internal reference voltage and temperature sensor output voltage (HS (high-speed main) mode)

3.6 V ≤ V

DD ≤ 5.5 V 2.375 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.5626 39 μs 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale error Notes 1, 2 EZS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Full-scale error Notes 1, 2 EFS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity error Note 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB Differential linearity error Note 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI8 to ANI11 0 VDD V ANI12 to ANI14 0 AV DD V Internal reference voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 64 of 143 Mar 22, 2024 (2) When reference voltage (+) = Inte rnal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI8 to ANI11, ANI12 to ANI14 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. Refer to 2.6.2 Temperature sensor/internal reference voltage output characteristics.

2.6.2 Temperature sensor/internal refe rence voltage output characteristics

(TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = VBGR Note 3, reference voltage (–) = VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 8b it Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale error Notes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(0.60 + 0.35) %FSR Integral linearity error Note 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(2.0 + 0.5) LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(1.0 + 0.2) LSB Analog input voltage V AIN 0 VBGR Note 3 V (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP . MAX. Unit Temperature sensor output voltage V TMPS25 TA = +25°C 1.05 V Internal reference voltage V BGR 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor output voltage that depends on the temperature -3.6 mV/°C Operation stabilization wait time t AMP 2.4 V ≤ VDD ≤ 5.5 V 5 µs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 65 of 143 Mar 22, 2024

2.6.3 POR circui t characteristics

Note 1. If the power supply voltage falls while the voltage detector is of f, be sure to either shift to STOP mode or execute a reset by using the voltage detector or external reset pin before the power supply voltage falls below the minimum operating voltage specified in 2.4 AC Characteristics. Note 2. Minimum time required for a POR reset when V DD falls below V PDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). (TA = -40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall timeNote 1 1.46 1.50 1.54 V Minimum pulse width Note 2 TPW1 Other than STOP/SUB HALT/SUB RUN 300 µs TPW2 STOP/SUB HALT/SUB RUN 300 µs VDD VPDR 0.7 V VPOR TPW2 TPW1

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 66 of 143 Mar 22, 2024

2.6.4 LVD circuit characteristics

Caution Set the detection voltage (V LVD) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: V DD = 2.7 to 5.5 V @ 1 MHz to 24 MHz VDD = 2.4 to 5.5 V @ 1 MHz to 16 MHz (1) LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V VLVD1 Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V VLVD2 Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V VLVD3 Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V VLVD4 Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V VLVD5 Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V VLVD6 Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V VLVD7 Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V VLVD8 Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Minimum pulse width tLW 300 µs Detection delay time 300 µs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 67 of 143 Mar 22, 2024 (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 68 of 143 Mar 22, 2024

2.6.5 Programmable gain instru mentation amplifier and 24-bit ΔΣ A/D converter

(1) Analog input in di fferential input mode (2) Analog input in single-ended input mode (3) Programmable gain instrumentation amplifier and 24-bit ΔΣ A/D converter (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, normal mode: fs1 = 1 MHz, FDATA1 = 3.90625 ksps, low-power mode: fs2 = 0.125 MHz, FDATA2 = 488.28125 sps, SBIAS = 2.1 V, d OFR = 0 mV, VCOM = 1.0 V, external clock input used) Parameter Symbol Conditions MIN. TYP. MAX. Unit Full-scale differential input voltage range VID VID = (PGA0xP - PGA0xN) (x = 0, 1) ― ±800 /GTOTAL0 ― mV Input voltage range V I 0.2 ― 1.8 V Common mode input voltage range V COM dOFR = 0 mV 0.2+(|VID|x GSET01)/2 ― 1.8-(|VID|x GSET01)/2 V Input bias current I IN VI = 1.0 V ±50 nA Input offset current I INO VI = 1.0 V ±20 nA (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, normal mode: fs1 = 1 MHz, FDATA1 = 3.90625 ksps, low-power mode: fs2 = 0.125 MHz, FDATA2 = 488.28125 sps, SBIAS = 2.1 V, d OFR = 0 mV, VCOM = 1.0 V, external clock input used) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage range V I 0.2 ― 1.8 V Input bias current I IN VI = 1.0 V ±50 nA (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, normal mode: fs1 = 1 MHz, FDATA1 = 3.90625 ksps, low-power mode: fs2 = 0.125 MHz, FDATA2 = 488.28125 sps, SBIAS = 2.1 V, d OFR = 0 mV, VCOM = 1.0 V, external clock input used, in differential input mode) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 24 bit Sampling frequency fs1 Normal mode 1 MHz fs2 Low-power mode 0.125 MHz Output data rate f DATA1 Normal mode 0.488 15.625 ksps fDATA2 Low-power mode 61.035 1953.125 sps Gain setting range G TOTAL0 GTOTAL0 = GSET01 x GSET02 16 4 V/V 1st gain setting range G SET01 1, 2, 3, 4, 8 V/V 2nd gain setting range G SET02 1, 2, 4, 8 V/V Offset adjustment bit range dOFFB 5b it Offset adjustment range d OFR Referred to input - 164/GSET01 + 164/GSET01 mV Offset adjustment steps d OFS Referred to input 11/GSET01 mV

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 69 of 143 Mar 22, 2024 Note Calculate the gain drift and offset drift by using the following expression (for 85°C products): For gain drift: (MAX(EG(T(-40) to T(85))) - MIN(EG(T(-40) to T(85)))) / (85°C -(-40°C)) For offset drift: (MAX(EOS(T(-40) to T(85))) - MIN(EOS(T(-40) to T(85)))) / (85°C -(-40°C)) MAX(EG(T(-40) to T(85))): The maximum value of gain error when the temperature range is -40°C to 85°C MIN(EG(T(-40) to T(85))): The minimum value of gain error when the temperature range is -40°C to 85°C MAX(EOS(T(-40) to T(85))): The maximum value of offset error when the temperature range is -40°C to 85°C MIN(EOS(T(-40) to T(85))):The minimum value of offset error when the temperature range is -40°C to 85°C Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The typical conditions are the conditions when T A = 25°C and AVDD = 3.3 V. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, normal mode: fs1 = 1 MHz, FDATA1 = 3.90625 ksps, low-power mode: fs2 = 0.125 MHz, FDATA2 = 488.28125 sps, SBIAS = 2.1 V, d OFR = 0 mV, VCOM = 1.0 V, external clock input used, in differential input mode) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Gain error EG0 TA = 25°C GSET01 = 1, GSET02 = 1 Excluding SBIAS error ±0.2 ±2.7 % TA = 25°C GSET01 = 8, GSET02 = 4 Excluding SBIAS error ±0.1 % Gain drift Note dEG0 GSET01 = 1, GSET02 = 1 Excluding SBIAS drift GSET01 = 8, GSET02 = 4 Excluding SBIAS drift (9.1) ppm/°C Offset error E OS0 TA = 25°C GSET01 = 1, GSET02 = 1 Referred to input ±0.32 ±2.90 mV TA = 25°C GSET01 = 8, GSET02 = 4 Referred to input ±0.03 mV Offset drift Note dEOS GSET01 = 1, GSET02 = 1 Referred to input GSET01 = 8, GSET02 = 4 Referred to input (±0.02) μV/°C SND ratio SNDR G SET01 = 1, GSET02 = 1, fin = 50 Hz Normal mode, Pin = -1 dBFS (82) (85) dB GSET01 = 8, GSET02 = 4, fin = 50 Hz Normal mode, Pin = -1 dBFS (73) (80) dB Noise Vn G SET01 = 1, GSET02 = 1, OSR = 2048 (13) μVRms GSET01 = 8, GSET02 = 4, OSR = 2048 (0.6) μVRms Integral non-linearity error INL G SET01 = 1, GSET02 = 1, OSR = 2048 (±10) ppmFS Common mode rejection ratio CMRR0 V COM = 1.0±0.8 V, fin = 50 Hz GSET01 = 1, GSET02 = 1 (72) (90) dB Power supply rejection ratio PSRR0 AV DD = 2.7 to 5.5 V, GSET01 = 1, GSET02 = 1 (60) (85) dB ΔΣ A/D converter input clock frequency fADC 3.8 4.0 4.2 MHz

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 70 of 143 Mar 22, 2024

2.6.6 Sensor power supply (SBIAS)

2.6.7 Internal BI AS power supply

Remark The typical conditions are the conditions when TA = 25°C and AVDD = 3.3 V. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, COUT = 0.22 μF, VOUT = 1.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage range V OUT 0.5 2.2 V Output voltage adjustment steps VSTEP 0.1 V Output voltage precision V A IOUT = 1 mA (- 3) (+ 3) % Maximum output current I OUT 5m A Short circuit current I SHORT VOUT = 0 V 40 65 mA Load regulation L R 1 mA ≤ IOUT ≤ 5 mA (15) mV Power supply rejection ratio PSRR AV DD = 5.0 V + 0.1 Vpp ripple f = 100 Hz, IOUT = 2.5 mA, VOUT = 2.1 V (45) (70) dB (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage V BIAS 0.95 1.00 1.05 V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 71 of 143 Mar 22, 2024

2.6.8 Programmable gain inst rumentation amplifier (PGA1)

Note See the setting of PGA1GC3 to PGA1GC0. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Differential input voltage range VID VID = (PGA1xP - PGA1xN) (x = 0, 1) ±800 /GTOTAL1 mV Input voltage range V IN 0.3 AVDD - 0.6 V Common mode input voltage range V COM 0.3+ ((|VID|+|EOS|) ×GSET11)/2 AVDD-0.6+ ((|VID|+|EOS|) ×GSET11)/2 V Output voltage range V OUT 0.1 AVDD - 0.1 V Maximum output current I OUT -0.1 +0.1 mA Input bias current I IN ±50 nA Input bias offset current I OS ±20 nA Gain setting range G TOTAL1 GSET11 × GSET12 V/V 1st gain setting range G SET11 12, 16, 20, 24 V/V 2nd gain setting range G SET12 Note V/V Gain error EG1 TA = 25°C GSET11 = 24, GSET12 = 1 ±2.7 % Gain drift dE G1 GSET11 = 24, GSET12 = 1 (5.6) (22.0) ppm/°C Offset error EOS1 TA = 25°C GSET11 = 24, GSET12 = 1 Referred to input -10 +10 mV Bandwidth BW11 Low-power mode GSET11 = 24, GSET12 = 1 (1.5) kHz BW12 High-speed mode GSET11 = 24, GSET12 = 1 (67) kHz Slew rate SR11 Low-power mode (6) mV/ μs SR12 High-speed mode (220) mV/ μs Peak-to-peak voltage noise Enb11 0.1 Hz to 10 Hz Low-power mode (3.0) μVrms Enb12 0.1 Hz to 10 Hz High-speed mode (2.6) μVrms

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 72 of 143 Mar 22, 2024 Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The typical conditions are the conditions when TA = 25°C and AVDD = 3.3 V. Remark 3. Unless otherwise specified, values are for operation in high-speed mode. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP . MAX. Unit Input-referred noise En11 f = 1 kHz Low-power mode (210) nV/ √Hz En12 f = 1 kHz High-speed mode (110) nV/ √Hz En13 f = 10 Hz Low-power mode (460) nV/ √Hz En14 f = 10 Hz High-speed mode (410) nV/ √Hz Common mode rejection ratio CMRR1 G SET11 = 24, GSET12 = 1 f = 50 Hz (100) dB Power supply rejection ratio PSRR1 2.7 V ≤ AV DD ≤ 5.5 V f = 50 Hz When SBIAS is selected as the reference voltage of the 12-bit D/A converter. (80) dB

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 73 of 143 Mar 22, 2024

2.6.9 Operational am plifier 0 (AMP0)

Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The typical conditions are the conditions when TA = 25°C and AVDD = 3.3 V. Remark 3. Unless otherwise specified, values are for operation in high-speed mode. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Common mode input voltage range V CM 0.1 AVDD - 0.1 V Output voltage range VOUT IOUT= ±1 mA 0.07 AVDD - 0.15 V Maximum output current IOUT (-2) (+2) mA Input bias current IIN ±50 nA Input offset voltage VOS1 Low-power mode -10 +10 mV VOS2 High-speed mode -7 +7 mV Slew rate SR1 Low-power mode (0.04) V/μs SR2 High-speed mode (0.7) V/μs Gain bandwidth GBW1 Low-power mode (0.06) MHz GBW2 High-speed mode (1) MHz Phase margin PM1 Low-power mode (70) deg PM2 High-speed mode (60) deg Settling time Tset1 Low-power mode CL = 50 pF, RL = 10 kΩ (300) μs Tset2 High-speed mode CL = 50 pF, RL = 10 kΩ (14) μs Stabilization wait time Tstaw1 AMPEn = 0 → 1, Low-power mode CL = 50 pF, RL = 10 kΩ (300) μs Tstaw2 AMPEn = 0 → 1, High-speed mode CL = 50 pF, RL = 10 kΩ (14) μs Input-referred noise En1 f = 1 kHz Low-power mode (200) nV/ √Hz En2 f = 1 kHz High-speed mode (80) nV/ √Hz Common mode rejection ratio CMRR DC (70) dB Power supply rejection ratio PSRR DC (90) dB

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 74 of 143 Mar 22, 2024

2.6.10 Operational amplifie rs 1 and 2 (AMP1, AMP2)

Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The typical conditions are the conditions when TA = 25°C and AVDD = 3.3 V. Remark 3. Unless otherwise specified, values are for operation in high-speed mode. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Common mode input voltage range V CM1 Low-power mode 0.2 AVDD - 0.5 V VCM2 High-speed mode 0.3 AVDD - 0.6 V Output voltage range VOUT 0.1 AVDD - 0.1 V Maximum output current IOUT 2.7 V ≤ AVDD ≤ 5.5 V -100 +100 μA Input bias current IIN ±50 nA Input offset voltage VOS1 Low-power mode -10 +10 mV VOS2 High-speed mode -10 +10 mV Slew rate SR1 Low-power mode (0.02) V/μs SR2 High-speed mode (1.1) V/μs Gain bandwidth GBW1 Low-power mode (0.04) MHz GBW2 High-speed mode (1.7) MHz Phase margin PM1 Low-power mode (70) deg PM2 High-speed mode (60) deg Settling time Tset1 Low-power mode CL = 50 pF, RL = 10 kΩ (750) μs Tset2 High-speed mode CL = 50 pF, RL = 10 kΩ (13) μs Stabilization wait time Tstaw1 AMPEn = 0 → 1, Low-power mode CL = 50 pF, RL = 10 kΩ (800) μs Tstaw2 AMPEn = 0 → 1, High-speed mode CL = 50 pF, RL = 10 kΩ (13) μs Input-referred noise En1 f = 1 kHz Low-power mode (230) nV/ √Hz En2 f = 1 kHz High-speed mode (90) nV/ √Hz Common mode rejection ratio CMRR DC (90) dB Power supply rejection ratio PSRR DC (90) dB

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 75 of 143 Mar 22, 2024 2.6.11 8-bit D/A converter (DAC0) Note Errors of the SBIAS output voltage are not included. Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The 8-bit D/A converter characteristics are the values obtained with the amplifier unit connected. 2.6.12 12-bit D/A converter (DAC1) (1) When reference voltage (+) = 2.1 V (SBIAS) Note Errors of the SBIAS output voltage are not included. Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The 12-bit D/A converter characteristics are the values obtained with the amplifier unit connected. (2) When reference voltage (+) = AV DD Remark 1. Values in parentheses are target design values (i.e. not guaranteed) and therefore are not tested for shipment. Remark 2. The 12-bit D/A converter characteristics are the values obtained with the amplifier unit connected. (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = 2.1 V (SBIAS)) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution DARES0 8 bit Absolute accuracy LE Note ±2.5 LSB Differential non-linearity error DADLE0 ±2.0 LSB Settling time DAtset0 CL = 50 pF, RL = 10 k Ω (6) μs (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = 2.1 V (SBIAS)) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution DARES1 (12) bit Output voltage range DAOUT 12-bit resolution 0.35 SBIAS V Integral non-linearity error DAILE 12-bit resolution ±4.0 LSB Differential non-linearity error DADLE1 12-bit resolution ±1.0 LSB Offset error DAErr 12-bit resolution ±30 mV Gain error DAEG 12-bit resolution Note ±20 mV Settling time DAtset1 12-bit resolution CL = 50 pF, RL = 10 kΩ (60) μs (TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = AVDD) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution DARES1 (12) bit Output voltage range DAOUT 12-bit resolution 0.35 AVDD - 0.47 V Integral non-linearity error DAILE 12-bit resolution ±4.0 LSB Differential non-linearity error DADLE1 12-bit resolution ±1.0 LSB Offset error DAErr 12-bit resolution ±30 mV Gain error DAEG 12-bit resolution ±20 mV Settling time DAtset1 12-bit resolution CL = 50 pF, RL = 10 kΩ (60) μs

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 76 of 143 Mar 22, 2024

2.7 Power supply voltage ri sing slope characteristics

Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 2.4 AC Characteristics.

2.8 LCD Characteristics

2.8.1 Resistance division method

(TA = -40 to +85°C, VSS = 0 V) Parameter Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SV DD 54 V/ms (1) Static display mode (TA = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.0 VDD V (2) 1/2 bias method, 1/4 bias method A = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.7 VDD V (3) 1/3 bias method (TA = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.5 VDD V

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 77 of 143 Mar 22, 2024

2.8.2 Internal voltage boosting method

Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% Note 2. This is the time required to wait from when the reference vo ltage is specified by using t he VLCD register (or when the internal voltage boosting method is selected (by setting t he MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (1) 1/3 bias method (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range V L1 C1 to C4 Note 1 = 0.47 µF Note 2 VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage V L2 C1 to C4 Note 1 = 0.47 µF 2 VL1 - 0.1 2 V L1 2 VL1 V Tripler output voltage V L4 C1 to C4 Note 1 = 0.47 µF 3 VL1- 0.15 3 V L1 3 VL1 V Reference voltage setup time Note 2 tVWAIT1 5m s Voltage boost wait time Note 3 tVWAIT2 C1 to C4 Note 1 = 0.47 µF 500 ms

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 78 of 143 Mar 22, 2024 Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 µF±30% Note 2. This is the time required to wait from when the reference vo ltage is specified by using t he VLCD register (or when the internal voltage boosting method is selected (by setting t he MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (2) 1/4 bias method (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range V L1 C1 to C5 Note 1 = 0.47 µF Note 2 VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V Doubler output voltage V L2 C1 to C5 Note 1 = 0.47 µF 2 VL1 - 0.08 2 V L1 2 VL1 V Tripler output voltage VL3 C1 to C5 Note 1 = 0.47 µF 3 VL1 - 0.12 3 V L1 3 VL1 V Quadruply output voltage V L4 C1 to C5 Note 1 = 0.47 µF 4 VL1 - 0.16 4 V L1 4 VL1 V Reference voltage setup time Note 2 tVWAIT1 5m s Voltage boost wait time Note 3 tVWAIT2 C1 to C5 Note 1 = 0.47µF 500 ms

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 79 of 143 Mar 22, 2024

2.8.3 Capacitor split method

Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). Note 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% (1) 1/3 bias method (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 voltage VL4 C1 to C4 = 0.47 µF Note 2 VDD V VL2 voltage VL2 C1 to C4 = 0.47 µF Note 2 2/3 VL4 - 0.1 2/3 V L4 2/3 VL4 + 0.1 V VL1 voltage VL1 C1 to C4 = 0.47 µF Note 2 1/3 VL4 - 0.1 1/3 V L4 1/3 VL4 + 0.1 V Capacitor split wait time Note 1 tVWAIT 100 ms

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 80 of 143 Mar 22, 2024

2.9 RAM data retention characteristics

Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset is effected, but RAM data is not retained when a POR reset is effected.

2.10 Flash Memory Programming Characteristics

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.

2.11 Dedicated Flash Memory Programmer Communication (UART)

(TA = -40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.46 Note 5.5 V (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit System clock frequency f CLK 2.4 V ≤ VDD ≤ 5.5 V 1 24 MHz Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years T A = 85°C 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 year T A = 25°C 1,000,000 Retained for 5 years T A = 85°C 100,000 Retained for 20 years T A = 85°C 10,000 (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM Data retention mode Operation mode VDDDR

RL78/H1D 2. ELECTRICAL SPECIFICATIONS (R5F11N, R5F11P) (A: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 81 of 143 Mar 22, 2024

2.12 Timing of Entry to Flash Memory Programming Modes

<1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: The segment shows that it is necessary to finish spec ifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends tHD: Time to hold the TOOL0 pin at the low level after an external reset is released (excluding the processing time of the firmware to control the flash memory) (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external reset ends until the initial communication settings are specified t SUINIT POR and LVD reset must end before the external reset ends. 100 ms How long from when the TOOL0 pin is placed at the low level until an external reset ends t SU POR and LVD reset must end before the external reset ends. 10 µs Time to hold the TOOL0 pin at the low level after an external reset is released (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must end before the external reset ends. 1m s RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 82 of 143 Mar 22, 2024 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) This chapter describes the electrical specifications for the products “D: Industrial applications (TA = -40 to +85°C)”. Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2 Functions other than port pins in the User’s Manual: Hardware.

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3.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). This val ue regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. The reference voltage is V SS (for the VDD systems) = AVSS (for the AVDD systems). Absolute Maximum Ratings (1/3) Parameter Symbol Conditions Ratings Unit Supply voltage VDD -0.5 to +6.5 V AVDD AVDD = VDD -0.5 to +6.5 V AVSS AVSS = VSS -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD + 0.3 Note 1 V Input voltage V I1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P121 to P124, P125 to P127, P137, EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 Note 2 V VI2 P60, P61 (N-ch open-drain) -0.3 to +6.5 V VI3 P20 to P27, P150, P151 -0.3 to AVDD + 0.3 Note 2 V Output voltage V O1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127 -0.3 to V DD + 0.3 Note 2 V VO2 P20 to P27, P150, P151 -0.3 to AVDD + 0.3 Note 2 V Analog input voltage V AI1 ANI8 to ANI10 -0.3 to VDD + 0.3 Note 2 V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 84 of 143 Mar 22, 2024 Note 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recomm ended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 μF ± 30%) and connect a capacitor (0.47 μF ± 30%) between the CAPL and CAPH pins. Note 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Absolute Maximum Ratings (2/3) Parameter Symbol Conditions Ratings Unit LCD voltage VLI1 VL1 input voltage Note 1 -0.3 to +2.8 V VLI2 VL2 input voltage Note 1 -0.3 to +6.5 V VLI3 VL3 input voltage Note 1 -0.3 to +6.5 V VLI4 VL4 input voltage Note 1 -0.3 to +6.5 V VLI5 CAPL, CAPH input voltage Note 1 -0.3 to +6.5 V VLO1 VL1 output voltage -0.3 to +2.8 V VLO2 VL2 output voltage -0.3 to +6.5 V VLO3 VL3 output voltage -0.3 to +6.5 V VLO4 VL4 output voltage -0.3 to +6.5 V VLO5 CAPL, CAPH output voltage -0.3 to +6.5 V VLO6 COM0 to COM7 SEG0 to SEG35 output voltage External resistance division method -0.3 to V DD + 0.3 Note 2 V Capacitor split method -0.3 to VDD + 0.3 Note 2 V Internal voltage boosting method -0.3 to V LI4 + 0.3 Note 2 V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 85 of 143 Mar 22, 2024 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Absolute Maximum Ratings (3/3) Parameter Symbol Conditions Ratings Unit Output current, high I OH1 Per pin -40 mA Total of all pins -170 mA P40, P43, P44, P80 to P83 -70 mA P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P70 to P77, P84 to P86, P125 to P127 -100 mA I OH2 Per pin -40 mA Total of all pins -140 mA P21 to P27 -70 mA P20, P150, P151 -70 mA Output current, low I OL1 Per pin 40 mA Total of all pins 170 mA P40, P43, P44, P80 to P83 70 mA P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P60, P61, P70 to P77, P84 to P86, P125 to P127 100 mA I OL2 Per pin 40 mA Total of all pins 140 mA P21 to P27 70 mA P20, P150, P151 70 mA Operating ambient temperature T A In normal operation mode -40 to +85 °C In flash memory programming mode Storage temperature T stg -65 to +150 °C

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3.2 Oscillator Characteristics

3.2.1 X1 and XT1 characteristics

3.2.2 On-chip oscillator characteristics

Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Resonator Conditions MIN. TYP . MAX. Unit X1 clock oscillation frequency (fX) Note Ceramic resonator/ crystal resonator DD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 1.8 V ≤ VDD < 2.4 V 1.0 8.0 X1 clock oscillation frequency (fXT) Note Crystal resonator 32 32.768 35 kHz 31 38.4 39 (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 2.7 V ≤ VDD ≤ 5.5 V 1 24 MHz 2.4 V ≤ VDD < 2.7 V 1 16 MHz 1.8 V ≤ VDD < 2.4 V 1 8 MHz High-speed on-chip oscillator clock frequency accuracy -20 to +85°C 1.8 V ≤ V Low-speed on-chip oscillator clock frequency f IL 15 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 %

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3.3 DC Characteristics

3.3.1 Pin characteristics

Note 1. Value of current at which the device operation is guaranteed even if the current flows from the V DD pin (IOH1) and AVDD pin (IOH2) to an output pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P02 to P04, P06, P07, P10, P12, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Item Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 IOH1 Per pin for P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 -10.0 Note 2 mA Total of P40, P43, P44, P80 to P83 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -55 mA 2.7 V ≤ VDD < 4.0 V -10 mA 1.8 V ≤ VDD < 2.7 V -5 mA Total of P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P70 to P77, P84 to P86, P125 to P127 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -69 mA 2.7 V ≤ VDD < 4.0 V -23 mA 1.8 V ≤ VDD < 2.7 V -12 mA Total of all pins (When duty ≤ 70% Note 3) 1.8 V ≤ VDD ≤ 5.5 V -124 mA IOH2 Per pin for P20 to P27, P150, P151 1.8 V ≤ AVDD ≤ 5.5 V -10.0 Note 2 mA Total of P21 to P27 (When duty ≤ 70% Note 3) 4.0 V ≤ AVDD ≤ 5.5 V -50 mA 2.7 V ≤ AVDD < 4.0 V -10 mA 1.8 V ≤ AVDD < 2.7 V -5 mA Total of P20, P150, P151 (When duty ≤ 70% Note 3) 4.0 V ≤ AVDD ≤ 5.5 V -21 mA 2.7 V ≤ AVDD < 4.0 V -5 mA 1.8 V ≤ AVDD < 2.7 V -3 mA Total of all pins (When duty ≤ 70% Note 3) 1.8 V ≤ AVDD ≤ 5.5 V -71 mA (1/5)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 88 of 143 Mar 22, 2024 Note 1. Value of current at which the device operation is guaranteed even if the current flows from the V SS pin (IOL1) and AVSS pin (IOL2) to an output pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Item Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 IOL1 Per pin for P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P121 to P127 20.0 Note 2 mA Per pin for P60, P61 15.0 Note 2 mA Total of P40, P43, P44, P80 to P83 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 70 mA 2.7 V ≤ VDD < 4.0 V 15 mA 1.8 V ≤ VDD < 2.7 V 9 mA Total of P01 to P07, P10 to P17, P30 to P32, P35 to P37, P50 to P53, P60, P61, P70 to P77, P84 to P86, P125 to P127 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 90 mA 2.7 V ≤ VDD < 4.0 V 35 mA 1.8 V ≤ VDD < 2.7 V 20 mA Total of all pins (When duty ≤ 70% Note 3) 1.8 V ≤ VDD ≤ 5.5 V 160 mA IOL2 Per pin for P20 to P27, P150, P151 1.8 V ≤ AVDD ≤ 5.5 V 20 mA Total of P21 to P27 (When duty ≤ 70% Note 3) 4.0 V ≤ AVDD ≤ 5.5 V 60 mA 2.7 V ≤ AVDD < 4.0 V 10 mA 1.8 V ≤ AVDD < 2.7 V 5 mA Total of P20, P150, P151 (When duty ≤ 70% Note 3) 4.0 V ≤ AVDD ≤ 5.5 V 25 mA 2.7 V ≤ AVDD < 4.0 V 8 mA 1.8 V ≤ AVDD < 2.7 V 5 mA Total of all pins (When duty ≤ 70% Note 3) 1.8 V ≤ AVDD ≤ 5.5 V 85 mA (2/5)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 89 of 143 Mar 22, 2024 Caution The maximum V IH value on P02 to P04, P06, P07, P10, P12, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (3/5) Item Symbol Conditions MIN. TYP . MAX. Unit Input voltage, high V IH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 Normal input buffer 0.8 V DD VDD V VIH2 For TTL mode supported ports TTL input buffer, 4.0 V ≤ VDD ≤ 5.5 V

2.2 V DD V

TTL input buffer, DD < 4.0 V TTL input buffer,

1.8 V ≤ V

DD < 3.3 V

1.5 V DD V

VIH3 P20 to P27, P150, P151 0.8 AVDD AVDD V VIH4 P60, P61 0.7 VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 Normal input buffer 0 0.2 V DD V VIL2 For TTL mode supported ports TTL input buffer, 4.0 V ≤ VDD ≤ 5.5 V 00 .8 V TTL input buffer, DD < 4.0 V 00 . 5 V TTL input buffer, DD < 3.3 V 00 . 3 2 V VIL3 P20 to P27, P150, P151 0 0.2 AVDD V VIL4 P60, P61 0 0.3 VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 90 of 143 Mar 22, 2024 Caution The maximum V IH value on P02 to P04, P06, P07, P10, P12, P35 to P37, P40, P43, P44, P50 to P52, and P80 to P82 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (4/5) Item Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 DD ≤ 5.5 V, IOH = -10.0 mA V DD - 1.5 V 4.0 V ≤ VDD ≤ 5.5 V, IOH = -3.0 mA V DD - 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH = -2.0 mA V DD - 0.6 V 1.8 V ≤ VDD ≤ 5.5 V, IOH = -1.5 mA V DD - 0.5 V VOH2 P20 to P27, P150, P151

4.0 V ≤ AV

DD ≤ 5.5 V, IOH = -10.0 mA AV DD - 1.5 V 4.0 V ≤ AVDD ≤ 5.5 V, IOH = -3.0 mA AV DD - 0.7 V 2.7 V ≤ AVDD ≤ 5.5 V, IOH = -2.0 mA AV DD - 0.6 V 1.8 V ≤ AVDD ≤ 5.5 V, IOH = -1.5 mA AV DD - 0.5 V Output voltage, low V OL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P70 to P77, P80 to P86, P125 to P127 DD ≤ 5.5 V, IOL = 20.0 mA 1.3 V 4.0 V ≤ VDD ≤ 5.5 V, IOL = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 3.0 mA 0.6 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 1.5 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL = 0.6 mA 0.4 V VOL2 P20 to P27, P150, P151 DD ≤ 5.5 V, IOL = 20.0 mA 1.3 V 4.0 V ≤ AVDD ≤ 5.5 V, IOL = 8.5 mA 0.7 V 2.7 V ≤ AVDD ≤ 5.5 V, IOL = 3.0 mA 0.6 V 2.7 V ≤ AVDD ≤ 5.5 V, IOL = 1.5 mA 0.4 V 1.8 V ≤ AVDD ≤ 5.5 V, IOL = 0.6 mA 0.4 V VOL3 P60, P61 4.0 V ≤ V DD ≤ 5.5 V, IOL = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL = 3.0 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL = 2.0 mA 0.4 V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 91 of 143 Mar 22, 2024 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (5/5) Item Symbol Conditions MIN. TYP . MAX. Unit Input leakage current, high ILIH1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127, P137, RESET VI = VDD 1µ A ILIH2 P20 to P27, P150, P151 VI = AVDD 1µ A ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VDD In input port mode or when using external clock input 1µ A When a resonator is connected 10 µA Input leakage current, low I LIL1 P01 to P07, P10 to P17, P30 to P32, P35 to P37, P40, P43, P44, P50 to P53, P60, P61, P70 to P77, P80 to P86, P125 to P127, P137, RESET VI = VSS -1 µA ILIL2 P20 to P27, P150, P151 VI = AVSS -1 µA ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VSS In input port mode or when using external clock input -1 µA When a resonator is connected -10 µA On-chip pull-up resistance R U1 P01 to P07, P10 to P16, P30 to P32, P35 to P37, P50 to P53, P70 to P77, P125 to P127 V I = VSS, in input port mode DD ≤ 5.5 V 10 20 100 k Ω 1.8 V ≤ VDD < 2.4 V 10 30 100 k Ω RU2 P17, P40, P43, P44, P80 to P86, V I = VSS, in input port mode 10 20 100 k Ω RU3 P20 to P27, P150 and P151 V I = AVSS, in input port mode 10 20 100 k Ω

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3.3.2 Supply current characteristics

(Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) Mode Note 5 fIH = 24 MHz Note 3 Basic operation VDD = 5.0 V 1.7 mA VDD = 3.0 V 1.7 Normal operation VDD = 5.0 V 3.7 6.4 VDD = 3.0 V 3.7 6.4 fIH = 16 MHz Note 3 Normal operation V DD = 5.0 V 2.8 5.0 VDD = 3.0 V 2.8 5.0 LS (low-speed main) Mode Note 5 fIH = 8 MHz Note 3 Normal operation VDD = 3.0 V 1.2 2.1 mA VDD = 2.0 V 1.2 2.1 HS (high-speed main) Mode Note 5 fMX = 20 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 3.1 5.4 mA Resonator connection 3.3 5.5 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.0 5.4 Resonator connection 3.3 5.5 fMX = 16 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.6 4.7 Resonator connection 2.8 4.8 fMX = 16 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 2.6 4.7 Resonator connection 2.8 4.8 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 1.9 3.1 Resonator connection 1.9 3.1 fMX = 10 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.9 3.1 Resonator connection 1.9 3.1 LS (low-speed main) Mode Note 5 fMX = 8 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.1 2.1 mA Resonator connection 1.1 2.1 fMX = 8 MH Note 2, VDD = 2.0 V Normal operation Square wave input 1.1 2.1 Resonator connection 1.1 2.1 Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = -40°C Normal operation Square wave input 4.3 5.8 μA Resonator connection 4.6 5.8 f SUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 4.3 5.8 Resonator connection 4.6 5.8 fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 4.5 7.6 Resonator connection 4.5 7.6 fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 4.7 9.2 Resonator connection 5.1 9.2 fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 5.2 12.6 Resonator connection 5.7 12.6 fSUB = 38.4 kHz Note 4 TA = -40°C Normal operation Square wave input 5.0 6.8 μA Resonator connection 5.4 6.8 fSUB = 38.4 kHz Note 4 TA = +25°C Normal operation Square wave input 5.0 6.8 Resonator connection 5.4 6.8 f SUB = 38.4 kHz Note 4 TA = +50°C Normal operation Square wave input 5.3 8.9 Resonator connection 5.3 8.9 fSUB = 38.4 kHz Note 4 TA = +70°C Normal operation Square wave input 5.5 10.8 Resonator connection 6.0 10.8 fSUB = 38.4 kHz Note 4 TA = +85°C Normal operation Square wave input 6.1 14.8 Resonator connection 6.7 14.8 (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 93 of 143 Mar 22, 2024 Note 1. Total current flowing into VDD and AVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD, I/O ports, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. The current flowing into AFE is not included. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Note 5. Relationship between operation voltage width, operation frequency of CPU, and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V @ 1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V @ 1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V @ 1 MHz to 8 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition for the TYP . value is TA = 25°C.

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 94 of 143 Mar 22, 2024 (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high-speed main) Mode Note 6 fIH = 24 MHz Note 4 VDD = 5.0 V 0.42 2.03 mA VDD = 3.0 V 0.42 2.03 fIH = 16 MHz Note 4 VDD = 5.0 V 0.39 1.58 VDD = 3.0 V 0.39 1.58 LS (low-speed main) Mode Note 6 fIH = 8 MHz Note 4 VDD = 3.0 V 0.25 0.81 mA VDD = 2.0 V 0.25 0.81 HS (high-speed main) Mode Note 6 fMX = 20 MHz Note 3 VDD = 5.0 V Square wave input 0.26 1.75 mA Resonator connection 0.40 1.88 fMX = 20 MHz Note 3 VDD = 3.0 V Square wave input 0.25 1.75 Resonator connection 0.40 1.88 fMX = 16 MHz Note 3 VDD = 5.0 V Square wave input 0.23 1.42 Resonator connection 0.36 1.59 fMX = 16 MHz Note 3 VDD = 3.0 V Square wave input 0.22 1.42 Resonator connection 0.35 1.59 f MX = 10 MHz Note 3 VDD = 5.0 V Square wave input 0.19 0.92 Resonator connection 0.29 1.00 fMX = 10 MHz Note 3 VDD = 3.0 V Square wave input 0.18 0.92 Resonator connection 0.28 1.00 LS (low-speed main) Mode Note 6 fMX = 8 MHz Note 3 VDD = 3.0 V Square wave input 0.09 0.61 mA Resonator connection 0.15 0.66 fMX = 8 MHz Note 3 VDD = 2.0 V Square wave input 0.10 0.62 Resonator connection 0.15 0.67 Subsystem clock operation fSUB = 32.768 kHz Note 5 TA = -40°C Square wave input 0.32 0.69 µA Resonator connection 0.51 0.89 fSUB = 32.768 kHz Note 5 TA = +25°C Square wave input 0.41 0.82 Resonator connection 0.62 1.00 f SUB = 32.768 kHz Note 5 TA = +50°C Square wave input 0.52 1.40 Resonator connection 0.75 1.60 SUB = 32.768 kHz Note 5 TA = +70°C Square wave input 0.82 2.70 Resonator connection 1.08 2.90 fSUB = 32.768 kHz Note 5 TA = +85°C Square wave input 1.38 4.95 Resonator connection 1.62 5.15 f SUB = 38.4 kHz Note 5 TA = -40°C Square wave input 0.38 0.81 µA Resonator connection 0.60 1.04 fSUB = 38.4 kHz Note 5 TA = +25°C Square wave input 0.48 0.96 Resonator connection 0.73 1.17 fSUB = 38.4 kHz Note 5 TA = +50°C Square wave input 0.61 1.64 Resonator connection 0.88 1.88 SUB = 38.4 kHz Note 5 TA = +70°C Square wave input 0.96 3.16 Resonator connection 1.27 3.40 fSUB = 38.4 kHz Note 5 TA = +85°C Square wave input 1.62 5.80 Resonator connection 1.90 6.04 IDD3 STOP mode Note 7 TA = -40°C 0.20 0.59 µA TA = +25°C 0.26 0.72 TA = +50°C 0.33 1.30 TA = +70°C 0.53 2.60 TA = +85°C 0.93 4.85

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 95 of 143 Mar 22, 2024 Note 1. Total current flowing into VDD and AVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, LVD, I/O ports, and on-chip pull-up/pull-down resistors and the current flowing during writing to the data flash. The current flowing into AFE is not included. Note 2. During HALT instruction execution from flash memory Note 3. When the high-speed on-chip oscillator and the subsystem clock are stopped Note 4. When the high-speed system clock and the subsystem clock are stopped Note 5. When high-speed on-chip oscillator and high-speed system cl ock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). Note 6. Relationship between operation voltage width, operation frequency of CPU, and operation mode is as below. HS (high-speed main) Mode: 2.7 V ≤ VDD ≤ 5.5 V @ 1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V @ 1 MHz to 16 MHz LS (low-speed main) Mode: 1.8 V ≤ VDD ≤ 5.5 V @ 1 MHz to 8 MHz Note 7. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 96 of 143 Mar 22, 2024 (Notes and Remarks are listed on the page after the next page.)

Peripheral functions (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current I FIL Note 1 0.20 µA RTC2 operating current IRTC Notes 1, 3 fSUB = 32.768 kHz 0.02 µA 12-bit Interval timer operating current I TMKA Notes 1, 2, 4 fSUB = 38.4 kHz, fMAIN stopped 0.02 µA fSUB = 32.768 kHz, fMAIN stopped 0.02 µA 8-bit Interval timer operating current I TMRT Notes 1, 14 fSUB = 38.4 kHz, fMAIN stopped, per unit 8-bit counter mode × 2-channel operation 0.14 µA 16-bit counter mode operation 0.12 µA f SUB = 32.768 kHz, fMAIN stopped, per unit 8-bit counter mode × 2-channel operation 0.12 µA 16-bit counter mode operation 0.10 µA Watchdog timer operating current I WDT Notes 1, 5 fIL = 15 kHz 0.22 µA 10-bit A/D converter operating current I ADC Notes 1, 6 When conversion at maximum speed Normal mode, V DD = 5.0 V 1.3 1.7 mA Low-voltage mode, VDD = 3.0 V 0.5 0.7 mA Internal reference voltage (1.45 V) current I ADREF Notes 1, 7 85 µA Temperature sensor operating current I TMPS Note 1 85 µA LVD operating current ILVI Notes 1, 8 0.06 µA Self-programming operating current I FSP Notes 1, 9 2.0 12.2 mA BGO operating current IBGO Notes 1, 10 2.0 12.2 mA SNOOZE operating current I SNOZ Notes 1, 11 A/D converter operation The mode is performed 0.50 0.60 mA During A/D conversion, low-voltage mode, V DD = 3.0 V 1.20 1.44 Simplified SPI(CSI)/UART operation 0.70 0.84 DTC operation 3.1 (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 97 of 143 Mar 22, 2024 (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD operating current I LCD1 Notes 12, 13 External resistance division method f LCD = fSUB (32.768 kHz) LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 5.0 V VL4 = 5.0 V 0.04 0.20 µA fLCD = fSUB (38.4 kHz) LCD clock = 75 Hz 0.08 0.40 I LCD2 Note 12 Internal voltage boosting method f LCD = fSUB (32.768 kHz) LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 3.0 V VL4 = 3.0 V (VLCD = 04H) 0.85 2.20 µA fLCD = fSUB (38.4 kHz) LCD clock = 75 Hz 0.50 2.20 f LCD = fSUB (32.768 kHz) LCD clock = 128 Hz V DD = 5.0 V VL4 = 5.1 V (VLCD = 12H) 1.55 3.70 µA fLCD = fSUB (38.4 kHz) LCD clock = 75 Hz 0.91 3.70 ILCD3 Note 12 Capacitor split method f LCD = fSUB (32.768 kHz) LCD clock = 128 Hz 1/3 bias 4-time slice V DD = 3.0 V VL4 = 3.0 V 0.20 0.50 µA fLCD = fSUB (38.4 kHz) LCD clock = 75 Hz 0.13 0.50 Operating currents of the meter-dedicated macro I TMRJ Note 15 fSUB = 38.4 kHz, fMAIN stopped, per unit 0.10 µA IUARTMG Note 15 fSUB = 38.4 kHz, fMAIN stopped 0.12 µA ISMOTD Note 15 fSUB = 38.4 kHz, fMAIN stopped 0.10 µA IEXSD Note 15 fSUB = 38.4 kHz, fMAIN stopped 0.02 µA (2/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 98 of 143 Mar 22, 2024 Note 1. Current flowing to VDD. Note 2. When the high-speed on-chip oscillator and high-speed system clock are stopped. Note 3. Current flowing only to the real-time cl ock 2 (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 micr ocontrollers is the sum of the values of either I DD1 or IDD2, and IRTC, when the real-time clock 2 is operating in operation mo de or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2. Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supp ly current of the RL78 microcontrollers is the sum of the values of either I DD1 or IDD2, and ITMKA , when the 12-bit interval timer operates in the operating mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the 12-bit interval timer. Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and IWDT when the watchdog timer is operating. Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of I DD1 or I DD2, IADC, and IADREF when the A/D converter operates in the operating mode or the HALT mode. Note 7. Operation current flowing to the internal reference voltage. Note 8. Current flowing only to the LVD circ uit. The supply current of the RL78 microcontrollers is the sum of I DD1, IDD2, or IDD3 and ILVI when the LVD circuit operates in the operating mode, HALT mode, or STOP mode. Note 9. Current flowing during self-programming Note 10. Current flowing during writing to the data flash Note 11. For time required to shift to the SNOOZE mode, see 27.3.3 SNOOZE mode in the User’s Manual: Hardware. Note 12. Current flowing only to the LCD controller/driver (V DD pin). The current value of the RL78 microcontrollers is the sum of the LCD operating current (I LCD1, ILCD2, or ILCD3) and the supply current (I DD1 or IDD2) when the LCD controller/driver operates in the operating mode or HALT mode. Not including the current that flows through the LCD panel. Note 13. Not including the current that flows through the external divider resistor. Note 14. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microc ontrollers is the sum of the values of either I DD1 or IDD2, and IIT, when the 8-bit interval time r operates in the operating mode or HALT mode. When the low-spee d on-chip oscillator is selected, IFIL should be added. Note 15. The current value of the RL78 microcontrollers is the sum of I DD2 or I DD3 and I TMRJ, IUARTMG, ISMOTD, or I EXSD when each module operates in the sub-HALT mode or STOP mode. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. The temperature condition for the TYP . value is TA = 25°C.

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 99 of 143 Mar 22, 2024

3.4 AC Characteristics

(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock (f MAIN) operation HS (high-speed main) Mode DD ≤ 5.5 V 0.0417 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (low-speed main) Mode DD ≤ 5.5 V 0.125 1 µs Subsystem clock (f SUB) operation fXT = 38.4 kHz 1.8 V ≤ V DD ≤ 5.5 V 26.04 µs In the self- programming mode HS (high-speed main) Mode DD ≤ 5.5 V 0.0417 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (low-speed main) Mode DD ≤ 5.5 V 0.125 1 µs External system clock frequency f EX EXCLK 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz fEXT EXCLKS 32 35 kHz External system clock input high-level width, low-level width t EXH, tEXL EXCLK 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns 1.8 V ≤ VDD < 2.4 V 60 ns tEXHS, tEXLS EXCLKS 13.7 µs Timer input high-level width, low-level width t TIH, tTIL TI00 to TI07 1/fMCK + ns Timer RJ input cycle t C TRJIO0, TRJIO1 2.7 V ≤ VDD ≤ 5.5 V 100 ns 1.8 V ≤ VDD < 2.7 V 300 ns Timer RJ input high- level width, low-level width t TJIH, tTJIL TRJIO0, TRJIO1 2.7 V ≤ VDD ≤ 5.5 V 40 ns 1.8 V ≤ VDD < 2.7 V 120 ns Timer output frequency f TO TO00 to TO07 TRJIO0, TRJIO1, TRJO0, TRJO1 HS (high-speed main) Mode DD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz LS (low-speed main) Mode DD ≤ 5.5 V 4 MHz Buzzer output frequency f PCL PCLBUZ0, PCLBUZ1 HS (high-speed main) Mode DD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz LS (low-speed main) Mode DD ≤ 5.5 V 4 MHz (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 100 of 143 Mar 22, 2024 Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 7)) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Interrupt input high- level width, low-level width t INTH, tINTL INTP0 to INTP7 (when the pin on which the function is in use is multiplexed with pin functions other than P27 to P22) DD ≤ 5.5 V 1 µs INTP2 to INTP7 (when the pin on which the function is in use is multiplexed with a pin function from among P27 to P22)

1.8 V ≤ AV

DD ≤ 5.5 V 1 µs RESET low-level width tRSL 10 µs (2/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 101 of 143 Mar 22, 2024 Minimum Instruction Execution Time During Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 1.0 0.1 2.7 0.01 2.4 0.0417 0.0625 0.05 Cycle time TCY [µs] Supply voltage V DD [V] During self-programming When high-speed system clock is selected When the high-speed on-chip oscillator clock is selected

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 102 of 143 Mar 22, 2024 TCY vs VDD (LS (low-speed main) mode) 1.0 0.1 1.0 2.0 3.0 5.5 0.01 1.8 4.0 0.125 5.0 6.0 Cycle time TCY [μs] Supply voltage VDD [V] During self-programming When high-speed system clock is selected When the high-speed on-chip oscillator clock is selected

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 103 of 143 Mar 22, 2024 AC Timing Test Points External System Clock Timing TI/TO Timing VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07, TRJIO0, TRJIO1, TRJO0, TRJO1 tTJIL TRJIO0, TRJIO1 tTJIH

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 104 of 143 Mar 22, 2024 Interrupt Request Input Timing RESET Input Timing INTP0 to INTP7 tINTL tINTH tRSL RESET

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 105 of 143 Mar 22, 2024

3.5 Peripheral Functions Characteristics

3.5.1 Serial array unit

Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. The following conditions are required for low voltage interface. 2.4 V ≤ VDD < 2.7 V: MAX. 2.6 Mbps 1.8 V ≤ VDD < 2.4 V: MAX. 1.3 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Remark 1. q: UART number (q = 0 to 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) (1) During communication at same potential (UART mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Transfer rate Note 1 2.4 V ≤ VDD ≤ 5.5 V fMCK/6 Note 2 fMCK/6 Note 2 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 4.0 1.3 Mbps 1.8 V ≤ VDD ≤ 5.5 V — fMCK/6 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 — 1.3 Mbps RL78 microcontroller TxDq RxDq User’s device Rx Tx Baud rate error tolerance TxDq RxDq High-/Low-bit width 1/Transfer rate

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 106 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIMand POM number (g = 0, 1, 3, 4, 5, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) (2) During communication at same potential (Simplified SPI(CSI) mode) (master mode, SCKp... internal clock output) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 167 500 ns 2.4 V ≤ VDD ≤ 5.5 V 250 500 ns 1.8 V ≤ VDD ≤ 5.5 V — 500 ns SCKp high-/low-level width t KH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 - 18 tKCY1/2 - 50 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 - tKCY1/2 - 50 ns 1.8 V ≤ VDD ≤ 5.5 V — tKCY1/2 - 50 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 110 ns 2.7 V ≤ VDD ≤ 5.5 V 44 110 ns 2.4 V ≤ VDD ≤ 5.5 V 75 110 ns 1.8 V ≤ VDD ≤ 5.5 V — 110 ns SIp hold time (from SCKp↑) Note 2 tKSI1 2.4 V ≤ VDD ≤ 5.5 V 19 19 ns 1.8 V ≤ VDD ≤ 5.5 V — 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 25 50 ns 2.4 V ≤ VDD ≤ 5.5 V 25 50 ns 1.8 V ≤ VDD ≤ 5.5 V — 50 ns

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 107 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM number (g = 0, 1, 3, 4, 5, Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) (3) During communication at same potential (Simplified SPI(CSI) mode) (slave mode, SCKp... external clock input) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < f MCK 8/fMCK —n s fMCK ≤ 20 MHz 8/f MCK 6/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz > f MCK 8/fMCK —n s fMCK ≤ 16 MHz 6/f MCK 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/fMCK and 500 6/fMCK and 500 ns 1.8 V ≤ VDD ≤ 5.5 V — 6/fMCK and 750 ns SCKp high-/low-level width t KH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V tKCY2/2 - 7 tKCY2/2 - 7 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 - 8 tKCY2/2 - 8 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 - 18 tKCY2/2 - 18 ns 1.8 V ≤ VDD ≤ 5.5 V — tKCY2/2 - 18 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 20 1/fMCK + 30 ns 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 30 1/fMCK + 30 ns 1.8 V ≤ VDD ≤ 5.5 V — 1/fMCK + 30 ns SIp hold time (from SCKp↑) Note 2 tKSI2 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 31 1/fMCK + 31 ns 1.8 V ≤ VDD ≤ 5.5 V — 1/fMCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK + 44 2/fMCK + 110 ns 2.4 V ≤ VDD ≤ 5.5 V 2/fMCK + 75 2/fMCK + 110 ns 1.8 V ≤ VDD ≤ 5.5 V — 2/fMCK + 110 ns (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 108 of 143 Mar 22, 2024 Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 4) Simplified SPI(CSI) mode connection diagram (during communication at same potential) Simplified SPI(CSI) mode connection diagram (during communication at same potential) (Slave transmission of slave select input function (CSI00)) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) (3) During communication at same potential (Simplified SPI(CSI) mode) (slave mode, SCKp... external clock input) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SSI00 setup time tSSIK DAPmn = 0 2.7 V ≤ V DD ≤ 5.5 V 120 120 ns 2.4 V ≤ VDD ≤ 5.5 V 200 200 ns 1.8 V ≤ VDD ≤ 5.5 V — 200 ns DAPmn = 1 2.7 V ≤ V DD ≤ 5.5 V 1/f MCK + 120 1/fMCK + 120 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 200 1/fMCK + 200 ns 1.8 V ≤ VDD ≤ 5.5 V — 1/fMCK + 200 ns SSI00 hold time tKSSI DAPmn = 0 2.7 V ≤ V DD ≤ 5.5 V 1/f MCK + 120 1/fMCK + 120 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 200 1/fMCK + 200 ns 1.8 V ≤ VDD ≤ 5.5 V — 1/fMCK + 200 ns DAPmn = 1 2.7 V ≤ V DD ≤ 5.5 V 120 120 ns 2.4 V ≤ VDD ≤ 5.5 V 200 200 ns 1.8 V ≤ VDD ≤ 5.5 V — 200 ns (2/2) SCKp SOp User's device SCK SI SIp SORL78 mic roc ont roller SCK00 SO00 User's device SCK SI SI00 SO SSI00 SSO RL78 microcontroller

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 109 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) SIp SOp tKCY1, 2 Input data Output data SCKp tKL1, 2 tKH1, 2 SSI00 (CSI00 only) tSIK1, 2 tKSI1, 2 tKSO1, 2 tSSIK tKSSI Input data Output data tKCY1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 tSSIK tKSSI SIp SOp SCKp SSI00 (CSI00 only) tKL1, 2

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 110 of 143 Mar 22, 2024 Note 1. The value must be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Note 3. Condition in the HS (high-speed main) mode Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) (4) During communication at sa me potential (simplified I2C mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 400 Note 1 kHz 1.8 V (2.4 V Note 3) ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400 Note 1 400 Note 1 kHz 1.8 V (2.4 V Note 3) ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300 Note 1 300 Note 1 kHz Hold time when SCLr = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1150 ns 1.8 V (2.4 V Note 3) ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 ns 1.8 V (2.4 V Note 3) ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1150 ns 1.8 V (2.4 V Note 3) ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 ns 1.8 V (2.4 V Note 3) ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 ns Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +

85 Note 2

145 Note 2

1.8 V (2.4 V Note 3) ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 1.8 V (2.4 V Note 3) ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK +

230 Note 2

Data hold time (transmission) t HD: DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 ns 1.8 V (2.4 V Note 3) ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 ns 1.8 V (2.4 V Note 3) ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 ns

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 111 of 143 Mar 22, 2024 Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Remark 1. Rb [Ω]: Communication line (SDAr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 10, 20), g: PIM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10) RL78 microcontroller SDAr SCLr User’s device SDA SCL VDD Rb SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 112 of 143 Mar 22, 2024 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. Use it with VDD ≥ Vb Note 3. The following conditions are required for low voltage interface. 2.4 V ≤ VDD < 2.7 V: MAX. 2.6 Mbps 1.8 V ≤ VDD < 2.4 V: MAX. 1.3 Mbps Note 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) Mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) Mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) Note 5. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb [V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Transfer rate Reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 4.0 1.3 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 4.0 1.3 Mbps 1.8 V (2.4 V Note 5) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1, 2, 3 fMCK/6 Notes 1, 2, 3 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 4.0 1.3 Mbps (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 113 of 143 Mar 22, 2024 Note 1. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use it with VDD ≥ Vb (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Transfer rate Transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1 Note 1 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8 Note 2 2.8 Note 2 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3 Note 3 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2 Note 4 1.2 Note 4 Mbps 1.8 V (2.4 V Note 8) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 Notes 5, 6 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 7 0.43 Note 7 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 Vb Vb ( ) × Number of transferred bits1 Transfer rate × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 Vb Vb ( ) × Number of transferred bits1 Transfer rate × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 114 of 143 Mar 22, 2024 Note 6. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Note 8. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) (Remarks are listed on the next page.) Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 Vb Vb ( ) × Number of transferred bits1 Transfer rate × 100 [%] * This value is the theoretical value of the relati ve difference between the transmission and reception sides. RL78 microcontroller TxDq RxDq User’s device Rx Tx Vb Rb

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 115 of 143 Mar 22, 2024 UART mode bit width (during communication at different potential) (reference) Remark 1. Rb [Ω]: Communication line (TxDq) pull-up resistance, Cb [F]: Communication line (TxDq) load capacitance, Vb [V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 116 of 143 Mar 22, 2024 Note 1. Use it with VDD ≥ Vb Note 2. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) internal clock output) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 300 1150 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 500 Note 1 1150 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 1150 Note 1 1150 ns SCKp high- level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 458 tKCY1/2 - 458 ns SCKp low- level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 18 tKCY1/2 - 50 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 50 tKCY1/2 - 50 ns (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 117 of 143 Mar 22, 2024 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. Use it with VDD ≥ Vb Note 4. Condition in the HS (high-speed main) mode (Caution and remarks are listed on the next page.) internal clock output) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SIp setup time (to SCKp↓) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 81 479 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 177 479 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 479 479 ns SIp hold time (from SCKp↓) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 19 19 ns Delay time from SCKp↑ to SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 483 483 ns SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 44 110 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 44 110 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 110 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 19 19 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ 25 25 ns

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 118 of 143 Mar 22, 2024 Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Simplified SPI(CSI) mode connection diagram (during communication at different potential) Remark 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, C b [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) SCKp SOp User’s device SCK SI SIp SO Vb Rb <Master> Vb Rb RL78 mic roc ont roller

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 119 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 120 of 143 Mar 22, 2024 (Notes, Cautions, and Remarks are listed on the next page.) external clock input) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

20 MHz < fMCK 12/fMCK —n s

8 MHz < fMCK ≤ 20 MHz 10/f MCK —n s

4 MHz < fMCK ≤ 8 MHz 8/f MCK —n s

fMCK ≤ 4 MHz 6/fMCK —n s 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

20 MHz < fMCK 16/fMCK —n s

16 MHz < fMCK ≤ 20

14/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 12/f MCK —n s

4 MHz < fMCK ≤ 8 MHz 8/f MCK 16/fMCK ns

fMCK ≤ 4 MHz 6/fMCK 10/fMCK ns 1.8 V (2.4 VNote 6) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

20 MHz < fMCK 36/fMCK —n s

32/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 26/f MCK —n s

4 MHz < fMCK ≤ 8 MHz 16/f MCK 16/fMCK ns

fMCK ≤ 4 MHz 10/fMCK 10/fMCK ns SCKp high-/ low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V t KCY2/2 - tKCY2/2 - ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V t KCY2/2 - tKCY2/2 - ns 1.8 V (2.4 VNote 6) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 - tKCY2/2 - ns SIp setup time (to SCKp↑) Note 3 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/f MCK + 1/fMCK + ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/f MCK + 1/fMCK + ns 1.8 V (2.4 VNote 6) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 1/fMCK + ns SIp hold time (from SCKp↑) Note 4 tKSI2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/f MCK + 1/fMCK + ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/f MCK + 1/fMCK + ns 1.8 V (2.4 VNote 6) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 1/fMCK + ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 2/fMCK + 573 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 2/fMCK + 573 ns 1.8 V (2.4 VNote 6) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 2/fMCK + 573 ns

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 121 of 143 Mar 22, 2024 Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with VDD ≥ Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 6. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer for the SIp and SCKp pins, and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Simplified SPI(CSI) mode connection diagram (during communication at different potential) Remark 1. Rb [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 , 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) SCKp SOp User’s device SCK SI SIp SO Vb Rb <Slave> RL78 microcontroller

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 122 of 143 Mar 22, 2024 Simplified SPI(CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) Simplified SPI(CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM or POM number (g = 0, 1, 3, 4, 5, 8) SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2 Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 123 of 143 Mar 22, 2024 (8) Communication at different potentia l (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high- speed main) Mode LS (low- speed main) Mode Unit MIN. MAX. MIN. MAX. SCLr clock frequency f SCL 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 kHz 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 300 Note 1 kHz 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 400 Note 1 300 Note 1 kHz Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1550 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1550 ns 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 ns Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 245 610 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 200 610 ns 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 675 610 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 600 610 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 610 610 ns (1/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 124 of 143 Mar 22, 2024 Note 1. The value must be equal to or less than fMCK/4. Note 2. Use it with VDD ≥ Vb Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Note 4. Condition in the HS (high-speed main) mode Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by usi ng port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (8) Communication at different potentia l (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +

135 Note 3

190 Note 2

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK +

190 Note 3

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 ns 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 ns 1.8 V (2.4 VNote 4) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 ns (2/2)

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 125 of 143 Mar 22, 2024 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Remark 1. Rb [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage Remark 2. r: IIC number (r = 00, 10, 20), g: PIM, POM number (g = 0, 1, 3, 4, 5, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 2), mn = 00, 02, 10)

3.5.2 Serial Interface UARTMG

(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Transfer rate fSUB = 38.4 kHz 200 9600 bps fSUB = 38.4 kHz (when the clock doubler is in use) 200 19200 bps RL78 microcontroller SDAr SCLr User’s device SDA SCL Vb Rb Vb Rb SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 126 of 143 Mar 22, 2024

3.5.3 Serial interface IICA

Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Note 3. Condition in the HS (high-speed main) mode Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ (1) I 2C standard mode (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLA0 clock frequency f SCL Standard mode: fCLK ≥ 1 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 100 0 100 kHz 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0 100 0 100 kHz Setup time of restart condition t SU: STA 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 µs Hold time when SCLA0 = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 µs Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V 250 250 ns 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 250 250 ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 3.45 0 3.45 µs 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 0 0 3.45 µs Setup time of stop condition tSU: STO 2.7 V ≤ VDD ≤ 5.5 V 4.0 4.0 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 4.7 4.7 µs

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 127 of 143 Mar 22, 2024 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD: DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Note 3. Condition in the HS (high-speed main) mode Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ (2) I 2C fast mode (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLA0 clock frequency f SCL Fast mode: fCLK ≥ 3.5 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 400 0 400 kHz 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 04 0 004 0 0 k H z Setup time of restart condition t SU: STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 1.3 1.3 µs Hold time when SCLA0 = “H” t HIGH 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 µs Data setup time (reception) t SU: DAT 2.7 V ≤ VDD ≤ 5.5 V 100 100 ns 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 100 100 ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.9 0 0.9 µs 1.8 V (2.4 VNote 3) ≤ VDD ≤ 5.5 V 00 0 . 9 µ s Setup time of stop condition tSU: STO 2.7 V ≤ VDD ≤ 5.5 V 0.6 0.6 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 1.3 1.3 µs

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 128 of 143 Mar 22, 2024 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD: DAT is during normal transfer and a clock stretch state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing (3) I 2C fast mode plus (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLA0 clock frequency f SCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 1000 — kHz Setup time of restart condition tSU: STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 — µs Hold time Note 1 tHD: STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 — µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 — µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 — µs Data setup time (reception) tSU: DAT 2.7 V ≤ VDD ≤ 5.5 V 50 — ns Data hold time (transmission) Note 2 tHD: DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 — µs Setup time of stop condition tSU: STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 — µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 — µs tSU: DATtHD: STA Restart condition SCLn SDAn tLOW tHIGH tR tF tSU: STA tHD: STA tSU: STO Stop condition Stop condition Start condition tHD: DAT tBUF

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 129 of 143 Mar 22, 2024

3.6 Analog Characteristics

3.6.1 A/D converter Characteristics

(1) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0) , reference voltage (-) = V SS (ADREFM = 0), target pin: ANI8 to ANI10, internal reference voltage, and temperature sensor output voltage Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor/internal reference voltage output characteristics. (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = VDD, reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 81 0 bit Overall error Note 1 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution Target pin: ANI8 to ANI10 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs 1.8 V ≤ VDD ≤ 5.5 V 17 39 μs 10-bit resolution Target pin: internal reference voltage and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.5626 39 μs 1.8 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale error Notes 1, 2 EZS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Full-scale error Notes 1, 2 EFS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity error Note 1 ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±4.0 LSB Differential linearity error Note 1 DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI8 to ANI10 0 VDD V Internal reference voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 130 of 143 Mar 22, 2024 (2) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP 0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI8 to ANI10 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor/internal reference voltage output characteristics.

3.6.2 Temperature sensor/internal refe rence voltage output characteristics

(TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, reference voltage (+) = V BGRNote 3 , reference voltage (–) = VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8b it Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale error Notes 1, 2, EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(0.60+0.35) %FSR Integral linearity error Note 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(2.0+0.5) LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±(1.0+0.2) LSB Analog input voltage V AIN 0 VBGR Note 3 V (TA = -40 to +85°C, 2.4 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V, HS (high-speed main) Mode) Parameter Symbol Conditions MIN. TYP . MAX. Unit Temperature sensor output voltage VTEMP TA = +25°C 1.05 V Internal reference voltage V BGR 1.38 1.45 1.5 V Temperature coefficient F VTMPS Temperature sensor output voltage that depends on the temperature -3.6 mV/°C Operation stabilization wait time t AMP 2.4 V ≤ VDD ≤ 5.5 V 5 μs

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 131 of 143 Mar 22, 2024

3.6.3 POR circuit characteristics

Note 1. If the power supply voltage falls while the voltage detector is off, be sure to either shift to STOP mode or execute a reset by using the voltage detector or external reset pin before the power supply voltage falls below the minimum operating voltage specified in 3.4 AC Characteristics. Note 2. Minimum time required for a POR reset when V DD falls below V PDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). (TA = -40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time Note 1 1.46 1.50 1.54 V Minimum pulse width Note 2 TPW1 Other than STOP/SUB HALT/SUB RUN 300 µs TPW2 STOP/SUB HALT/SUB RUN 300 µs VDD VPDR 0.7 V VPOR TPW2 TPW1

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 132 of 143 Mar 22, 2024

3.6.4 LVD circuit characteristics

Caution Set the detection voltage (V LVD) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: V DD = 2.7 to 5.5 V @ 1 MHz to 24 MHz VDD = 2.4 to 5.5 V @ 1 MHz to 16 MHz LS (low-speed main) mode: V DD = 1.8 to 5.5 V @ 1 MHz to 8 MHz (1) LVD detection voltage in reset mode and interrupt mode (TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 Rising edge 3.98 4.06 4.14 V Falling edge 3.90 3.98 4.06 V VLVD1 Rising edge 3.68 3.75 3.82 V Falling edge 3.60 3.67 3.74 V VLVD2 Rising edge 3.07 3.13 3.19 V Falling edge 3.00 3.06 3.12 V VLVD3 Rising edge 2.96 3.02 3.08 V Falling edge 2.90 2.96 3.02 V VLVD4 Rising edge 2.86 2.92 2.97 V Falling edge 2.80 2.86 2.91 V VLVD5 Rising edge 2.76 2.81 2.87 V Falling edge 2.70 2.75 2.81 V VLVD6 Rising edge 2.66 2.71 2.76 V Falling edge 2.60 2.65 2.70 V VLVD7 Rising edge 2.56 2.61 2.66 V Falling edge 2.50 2.55 2.60 V VLVD8 Rising edge 2.45 2.50 2.55 V Falling edge 2.40 2.45 2.50 V VLVD9 Rising edge 2.05 2.09 2.13 V Falling edge 2.00 2.04 2.08 V VLVD10 Rising edge 1.94 1.98 2.02 V Falling edge 1.90 1.94 1.98 V VLVD11 Rising edge 1.84 1.88 1.91 V Falling edge 1.80 1.84 1.87 V Minimum pulse width tLW 300 µs Detection delay time 300 µs

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 133 of 143 Mar 22, 2024

3.7 Power supply voltage ri sing slope characteristics

Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 3.4 AC Characteristics. (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDB0 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V 1.80 1.84 1.87 V VLVDB1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVDB3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V (TA = -40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 134 of 143 Mar 22, 2024

3.8 LCD Characteristics

3.8.1 Resistance division method

(1) Static display mode (TA = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.0 VDD V (2) 1/2 bias method, 1/4 bias method A = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.7 VDD V (3) 1/3 bias method (TA = -40 to +85°C, VL4 (MIN.) ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.5 VDD V

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 135 of 143 Mar 22, 2024

3.8.2 Internal voltage boosting method

Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% Note 2. This is the time required to wait from when the reference vo ltage is specified by using t he VLCD register (or when the internal voltage boosting method is selected (by setting t he MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (1) 1/3 bias method (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range V L1 C1 to C4 Note 1 = 0.47 µF Note 2 VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage V L2 C1 to C4 Note 1 = 0.47 µF 2 VL1 - 0.1 2 V L1 2 VL1 V Tripler output voltage V L4 C1 to C4 Note 1 = 0.47 µF 3 VL1- 0.15 3 V L1 3 VL1 V Reference voltage setup time Note 2 tVWAIT1 5m s Voltage boost wait time Note 3 tVWAIT2 C1 to C4 Note 1 = 0.47µF 500 ms

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 136 of 143 Mar 22, 2024 Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 µF±30% Note 2. This is the time required to wait from when the reference vo ltage is specified by using t he VLCD register (or when the internal voltage boosting method is selected (by setting t he MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (2) 1/4 bias method (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range V L1 C1 to C5 Note 1 = 0.47 µF Note 2 VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V Doubler output voltage V L2 C1 to C5 Note 1 = 0.47 µF 2 VL1 - 0.08 2 V L1 2 VL1 V Tripler output voltage V L3 C1 to C5 Note 1 = 0.47 µF 3 VL1 - 0.12 3 V L1 3 VL1 V Quadruply output voltage V L4 C1 to C5 Note 1 = 0.47 µF 4 VL1 - 0.16 4 V L1 4 VL1 V Reference voltage setup time Note 2 tVWAIT1 5m s Voltage boost wait time Note 3 tVWAIT2 C1 to C5 Note 1 = 0.47µF 500 ms

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 137 of 143 Mar 22, 2024

3.8.3 Capacitor split method

Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). Note 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% (1) 1/3 bias method (TA = -40 to +85°C, 2.2 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 voltage VL4 C1 to C4 = 0.47 µF Note 2 VDD V VL2 voltage VL2 C1 to C4 = 0.47 µF Note 2 2/3 VL4 - 0.1 2/3 V L4 2/3 VL4 + 0.1 V VL1 voltage VL1 C1 to C4 = 0.47 µF Note 2 1/3 VL4 - 0.1 1/3 V L4 1/3 VL4 + 0.1 V Capacitor split wait time Note 1 tVWAIT 100 ms

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 138 of 143 Mar 22, 2024

3.9 RAM Data Retention Characteristics

Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset is effected, but RAM data is not retained when a POR reset is effected.

3.10 Flash Memory Programming Characteristics

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self-programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.

3.11 Dedicated Flash Memory Programmer Communication (UART)

(TA = -40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.46 Note 5.5 V (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 24 MHz Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years T A = 85°C 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 year T A = 25°C 1,000,000 Retained for 5 years T A = 85°C 100,000 Retained for 20 years T A = 85°C 10,000 (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention Operation mode VDDDR

RL78/H1D 3. ELECTRICAL SPECIFICATIONS (R5F11R) (D: TA = -40 to +85°C) R01DS0318EJ0111 Rev. 1.11 Page 139 of 143 Mar 22, 2024

3.12 Timing of Entry to Flash Memory Programming Modes

<1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) (TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external reset ends until the initial communication settings are specified t SUINIT POR and LVD reset must end before the external reset ends. 100 ms How long from when the TOOL0 pin is placed at the low level until an external reset ends t SU POR and LVD reset must end before the external reset ends. 10 µs How long the TOOL0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must end before the external reset ends. 1m s RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode

RL78/H1D 4. PACKAGE DRAWINGS R01DS0318EJ0111 Rev. 1.11 Page 140 of 143 Mar 22, 2024 4. PACKAGE DRAWINGS 4.1 48-pin products R5F11NGGAFB, R5F11NGFAFB

RL78/H1D 4. PACKAGE DRAWINGS R01DS0318EJ0111 Rev. 1.11 Page 141 of 143 Mar 22, 2024 4.2 64-pin products R5F11NLGAFB, R5F11NLFAFB

RL78/H1D 4. PACKAGE DRAWINGS R01DS0318EJ0111 Rev. 1.11 Page 142 of 143 Mar 22, 2024 R5F11PLGABG, R5F11PLFABG

RL78/H1D 4. PACKAGE DRAWINGS R01DS0318EJ0111 Rev. 1.11 Page 143 of 143 Mar 22, 2024 4.3 80-pin products R5F11NMGAFB, R5F11NMFAFB, R5F11NMEAFB R5F11RMGDFB MASS (Typ) [g] 0.5 Unit: mm Previous CodeRENESAS Code PLQP0080KB-B — P-LFQFP80-12x12-0.50 © 2017 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c e x y Lp 11.9 11.9 13.8 13.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 12.0 12.0 1.4 14.0 14.0 0.20 3.5・ 0.5 0.6 1.0 12.1 12.1 14.2 14.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH 2. DIMENSION “*3” DOES NOT INCLUDETRIM OFFSE T. 3. PIN 1 VISUAL INDEX FE ATURE M AY VARY, BUT MUST BE LOC ATED WITHINTHE HATCHEDAREA. 4. CHAMFERSAT CORNERSARE OPTIONAL, SIZE MAY VARY. HD D*1 4160 210 HE E NOTE 4 NOTE 3 Index area S e y S bp M F A2A1 A Lp Detail F c 0.25

Rev. Date

Description

1.00 Apr 13 2018 — First Edition issued

1.10 Apr 28 2023

The module name for CSI was changed to simplified SPI. “Wait” was modified to “clock stretch”. p.2 Addition of Note 3 in 1.1 Features Modification of Note 3 to Note 4 in 1.1 Features Modification of Note 4 to Note 5 in 1.1 Features p.5 Modification of Figure 1 - 1 in 1.2 Ordering Information p.31 Modification of Note 1 in 2.3.2 Supply current characteristics Modification of Note 4 in 2.3.2 Supply current characteristics p.33 Modification of Note 1 in 2.3.2 Supply current characteristics Modification of Note 5 in 2.3.2 Supply current characteristics Deletion of Note 6 in 2.3.2 Supply current characteristics Modification of Note 7 to Note 6 in 2.3.2 Supply current characteristics Modification of Note 8 to Note 7 in 2.3.2 Supply current characteristics Modification of Note 9 to Note 8 in 2.3.2 Supply current characteristics p.93 Modification of Note 1 in 3.3.2 Supply current characteristics Modification of Note 4 in 3.3.2 Supply current characteristics p.95 Modification of Note 1 in 3.3.2 Supply current characteristics Modification of Note 5 in 3.3.2 Supply current characteristics Deletion of Note 6 in 3.3.2 Supply current characteristics Modification of Note 7 to Note 6 in 3.3.2 Supply current characteristics Modification of Note 8 to Note 7 in 3.3.2 Supply current characteristics p.140 Replacement of PLQP0048KB-A with PLQP0048KB-B in 4.1 48-pin products p.141 Replacement of PLQP0064KB-A with PLQP0064KB-C in 4.2 64-pin products p.143 Replacement of PLQP0080KB-A with PLQP0080KB-B in 4.3 80-pin products 1.11 Mar 22 2024 p.5 Modification of table in 1.2 Ordering Information p.6 Modification of Figure 1-1 Part Number, Memory Size, and Package of RL78/H1D SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners.

REVISION HISTORY

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is ap plied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or f rom an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, im plement a system- evaluation test for the given product.

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Product Information

PTBG0064LA-A specifications and overview.

Summary

RENESAS MCU Rev. 1.11 Mar 22, 2024

Description

RENESAS MCU Rev. 1.11 Mar 22, 2024

Source title PTBG0064LA-A Datasheet(PDF) - Renesas Technology Corp

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