PTAS5805MPWPR

TAS5805M_18 TI1 | Alldatasheet

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Technical content

SCLK (BCLK) LRCLK BST_A+ OUT_A+ BST_A- OUT_A- BST_B+ OUT_B+ BST_B- OUT_B- Speaker L Channel Speaker R Channel DVDD Copyright © 2018, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS5805M SLASEH5A –MAY 2018–REVISED JULY 2018 TAS5805M23-W,Inductor-Less,DigitalInput,Stereo,Closed-LoopClass-DAudio AmplifierwithEnhancedProcessingandLowIdlePowerDissipation

1 Features

1• Supports Multiple Output Configurations – 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%) – 45 W in Mono Mode (4-Ω, 21 V, THD+N=1%)

• Excellent Audio Performance – THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V – SNR ≥ 107 dB (A-weighted), Noise Level < 40 µVRMS
• Low Quiescent Current with Hybrid Modulation – 16.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF Filter
• Flexible Power Supply Configurations – PVDD: 4.5 V to 26.4 V – DVDD and I/O: 1.8 V or 3.3 V
• Flexible Audio I/O – I2S, LJ, RJ, TDM, 3-Wire Digital Audio Interface (No MCLK Required) – Supports 32, 44.1, 48, 88.2, 96 kHz Sample Rates – SDOUT for Audio Monitoring, Sub-Channel or Echo Cancellation
• Enhanced Audio Processing – Multi-Band Advanced DRC and AGL – 2×15 BQs, Thermal Foldback, DC Blocking – Input Mixer, Output Crossbar, Level Meter – 5 BQs + 1 Band DRC +THD Manager for the Subwoofer Channel
• Integrated Self-Protection – Adjacent Pin to Pin Short Without Device Damage – Over-Current Error (OCE) – Over-Temperature Warning (OTW) – Over-Temperature Error (OTE) – Under/Over-Voltage Lock-out (UVLO/OVLO)
• Easy System Integration – I2C Software Control – Reduced Solution Size – Fewer Passives Required Compared to Open-Loop Devices – Inductor-less Operation (Ferrite Bead) for most cases where PVDD ≤ 14V

2 Applications

• LCD TV, OLED TV
• Wireless Speaker, Smart Speaker with Voice Assistant
• Soundbar, Wired Speaker , Bookshelf Stereo System
• Desktop PC, Notebook PC
• AV Receiver, Smart Home and IoT Appliance

3 Description

The TAS5805M is a high-efficiency, stereo, closed- loop Class-D amplifier offering a cost effective digital- input solution with low power dissipation and sound enrichment. The device’s integrated audio processor and 96 kHz architecture supports advanced audio process flow, including SRC, 15 BQs per channel, volume control, audio mixing, 3-band 4th order DRC, full-band AGL, THD managing and level meter. Featuring TI's proprietary Hybrid Modulation scheme, the TAS5805M consumes very-low quiescent current (<16.5 mA at 13.5V PVDD), extending battery life in portable audio applications. With advanced EMI suppression technology, designers can leverage inexpensive ferrite bead filters to reduced board space and system cost. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TAS5805M TSSOP (28) PWP 9.7 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram

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13.2 Receiving Notification of Documentation Updates 79

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2018) to Revision A Page

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5 Device Comparison Table

PVDD RANGE Audio Process Flows RDS(ON) TAS5805M 4.5 V to 26.4 V Enhanced Audio Process Flows with ROM Fixed 180 mΩ TAS5707/TAS5711 8 V to 26 V Basic Audio Process Flow with ROM Fixed 180 mΩ TAS5825M 4.5 V to 26.4 V Flexible Advanced Audio Process Flows with Smart-Amp Features 90 mΩ

6 Pin Configuration and Functions

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V) Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. DGND 1, 5 P Digital ground DVDD 2 P 3.3-V or 1.8-V digital power supply VR_DIG 4 P Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices ADR/FAULT 3 DI/O Different I2 C device address can be set by selecting different pull up resistor to DVDD, see Table 4 for details. This pin can be programed by Register 0x60h and 0x61h after Power up bit. In this mode, the ADR/FAULT Is redefined as FAULT LRCLK 6 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary. SCLK 7 DI Bit clock for the digital signal that is active on the input data line of the serial data port. SDIN 8 DI Data line to the serial data port SDOUT 9 DO Serial Audio data output. The source data can be Pre-DSP or Post DSP data, by setting the register 0x30h. SDA 10 DI/O I2C serial control data interface input/output

SLASEH5A –MAY 2018–REVISED JULY 2018 www.ti.com Product Folder Links: TAS5805M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. SCL 11 DI I2C serial control clock input PDN 12 DI Power Down, active-low.PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down Device; High, Enable Device. AVDD 13 P Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices AGND 14 P Analog ground PVDD 15,16,27,

28 P PVDD voltage input

PGND 19,24 P Ground reference for power device circuitry. Connect this pin to system ground. OUT_A+ 26 O Positive pin for differential speaker amplifier output A+ BST_A+ 25 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+ OUT_A- 23 O Negative pin for differential speaker amplifier output A- BST_A- 22 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A- BST_B- 21 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B- OUT_B- 20 O Negative pin for differential speaker amplifier output B BST_B+ 18 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+ OUT_B+ 17 O Positive pin for differential speaker amplifier output B+ PowerPAD™ P Connect to the system Ground

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SCL, SDA, SDIN,PDN

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted) (1) MIN MAX UNIT DVDD Low-voltage digital supply –0.3 3.9 V PVDD PVDD supply –0.3 30 V VI(DigIn) DVDD referenced digital inputs(2) –0.5 VDVDD + 0.5 V VI(SPK_OUTxx) Voltage at speaker output pins –0.3 32 V TA Ambient operating temperature –25 85 °C Tstg Storage temperature –40 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(POWER) Power supply inputs DVDD 1.62 3.63 V PVDD 4.5 26.4 RSPK Minimum speaker load BTL Mode (4.5V≤PVDD≤16V) 3.2 Ω BTL Mode (16V<PVDD≤24V) 4.8 Ω RSPK Minimum speaker load PBTL Mode (4.5V≤PVDD≤16V) 1.6 Ω PBLT Mode (16V<PVDD≤24V) 2.4 Ω LOUT Minimum inductor value in LC filter under short-circuit condition 1 4.7 µH (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) TAS5805M TSSOP (PWP)

28 PINS

RθJA Junction-to-ambient thermal resistance N/A 29.1 24 °C/W RθJC(top) Junction-to-case (top) thermal resistance N/A 21.8 N/A °C/W RθJB Junction-to-board thermal resistance N/A 8.2 N/A °C/W ψJT Junction-to-top characterization parameter N/A 0.3 1.5 °C/W ψJB Junction-to-board characterization parameter N/A 8.1 7.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.2 N/A °C/W

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7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL I/O |IIH| Input logic high current level for DVDD referenced digital input pins VIN(DigIn) = VDVDD 10 µA |IIL| Input logic low current level for DVDD referenced digital input pins VIN(DigIn) = 0 V –10 µA VIH(Digin) Input logic high threshold for DVDD referenced digital inputs 70% VDVDD VIL(Digin) Input logic low threshold for DVDD referenced digital inputs 30% VDVDD VOH(Digin) Output logic high voltage level IOH = 2 mA 80% VDVDD VOL(Digin) Output logic low voltage level IOH = –2 mA 20% VDVDD I2C CONTROL PORT CL(I2C) Allowable load capacitance for each I2C line 400 pF fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz SERIAL AUDIO PORT tDLY Required LRCLK/FS to SCLK rising edge delay 5 ns DSCLK Allowable SCLK duty cycle 40% 60% fS Supported input sample rates 32 96 kHz fSCLK Supported SCLK frequencies 32 64 fS fSCLK SCLK frequency 24.576 MHz SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS) Icc Quiescent supply current on DVDD PDN=2V, DVDD=3.3V, Play mode 18 mA Icc Quiescent supply current on DVDD PDN=2V, DVDD=3.3V, Sleep mode 0.75 mA Icc Quiescent supply current on DVDD PDN=2V, DVDD=3.3V, Deep Sleep mode 0.75 mA Icc Quiescent supply current on DVDD PDN=0V, DVDD=3.3V, Shutdown mode 5.5 µA Icc Quiescent supply current on PVDD PDN=2V,, PVDD=13.5V, LC filter=10uH+0.68uF, Fsw=768kHz, BD Modulation, Play mode 32.5 mA Icc Quiescent supply current on PVDD PDN=2V,, PVDD=13.5V, LC filter=22uH+0.68uF, Fsw=384kHz, Hybrid Modulation, Play mode 16.5 mA Icc Quiescent supply current on PVDD PDN=2V, PVDD=13.5V, Output Hiz Mode 10.4 mA Icc Quiescent supply current on PVDD PDN=2V, PVDD=13.5V, Sleep Mode 7.2 mA Icc Quiescent supply current on PVDD PDN=2V, PVDD=13.5V, Deep Sleep Mode 120 µA Icc Quiescent supply current on PVDD PDN=0V, PVDD=13.5V, Shutdown Mode 7.2 µA toff Turn-off Time Excluding volume ramp 10 ms AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding clipping due to lower PVDD). Measured at 0 dB input(1FS) 4.87 29.5 V ΔAV(SPK_AMP) Amplifier gain error Gain = 29.5 Vp/FS 0.5 dB fSPK_AMP Switching frequency of the speaker amplifier 384 kHz 768 kHz RDS(on) Drain-to-source on resistance of the individual output MOSFETs FET + Metallization 180 mΩ

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Free-air room temperature 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OCETHRES Over-Current Error Threshold OUTxx Overcurrent Error Threshold 5 A OVETHRES(PVDD PVDD over voltage error threshold 28 V UVETHRES(PVDD PVDD under voltage error threshold 4.2 V OTETHRES Over temperature error threshold 160 °C OTEHystersis Over temperature error hysteresis 10 °C OTWTHRES Over temperature warning level Read by register 0x73 bit3 135 °C SPEAKER AMPLIFIER (STEREO BTL) |VOS| Amplifier offset voltage Measured differentially with zero input data, programmable gain configured with 29.5 Vp gain, VPVDD = 12 V, BD Mode –6.5 6.5 mV PO(SPK) Continuous Output power (per channel) VPVDD = 21V, SPK_GAIN = 24.8 Vp/FS, RSPK = 8 Ω, f = 1 kHz, THD+N = 1%, 1SPW Mode 23 W VPVDD = 21 V, SPK_GAIN = 24.8 Vp/FS, RSPK = 8 Ω, f = 1 kHz, THD+N = 10%, 1SPW Mode 27.5 W VPVDD = 18 V, SPK_GAIN = 20.8 Vp/FS, RSPK = 6 Ω, f = 1 kHz, THD+N = 1%, BD Mode 21 W VPVDD = 18 V, SPK_GAIN = 20.8 Vp/FS, RSPK = 6 Ω, f = 1 kHz, THD+N = 10%, BD Mode 25 W VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 6 Ω, f = 1 kHz THD+N = 1%, BD Mode 9.9 W VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 6 Ω, f = 1 kHz THD+N = 10%, BD Mode 12 W VPVDD = 13.5 V, SPK_GAIN = 15.6 Vp/FS, RSPK = 6 Ω, f = 1 kHz THD+N = 1%, BD Mode 12 W VPVDD = 13.5 V, SPK_GAIN = 15.6 Vp/FS, RSPK = 6 Ω, f = 1 kHz THD+N = 10%, BD Mode 15 W THD+NSPK Total harmonic distortion and noise (PO = 1 W, f = 1 KHz, RSPK = 6 Ω) VPVDD = 12 V, Fsw=768kHz, SPK_GAIN = 13.9 Vp/FS, LC-filter, BD Mode 0.03% VPVDD = 18 V, Fsw=768kHz, SPK_GAIN = 20.8 Vp/FS, LC-filter, BD Mode 0.03% ICN(SPK) Idle channel noise(A- weighted) VPVDD = 12 V, Fsw=768kHz, LC-filter, Load=6 Ω 37 µVrms VPVDD = 18 V, Fsw=768kHz, LC-filter, Load=6 Ω 38 DR Dynamic range A-Weighted, -60 dBFS method. PVDD = 24 V, SPK_GAIN = 29.5 Vp/FS 106 dB SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N output level, PVDD=24V 111 dB A-Weighted, referenced to 1% THD+N output level, PVDD=13.5V 107.5 dB KSVR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms, PVDD = 12 V, input audio signal = digital zero 72 dB X-talkSPK Cross-talk (worst case between left-to-right and right-to-left coupling) f = 1 kHz 100 dB SPEAKER AMPLIFIER (MONO PBTL) PO(SPK) Continuous Output Power VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 4 Ω, f = 1kHz, THD+N = 1%, BD Mode 15.4 W VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 4 Ω, f = 1kHz, THD+N = 10%, BD Mode 18.5 W VPVDD = 18V, SPK_GAIN = 22.1 Vp/FS, RSPK = 4 Ω, f = 1kHz, THD+N = 1%, BD Mode 33.6 W VPVDD = 18 V, SPK_GAIN = 22.1 Vp/FS, RSPK = 4 Ω, f = 1kHz, THD+N = 10%, BD Mode 41 W

SLASEH5A –MAY 2018–REVISED JULY 2018 www.ti.com Product Folder Links: TAS5805M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Free-air room temperature 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THD+NSPK Total harmonic distortion and noise (PO = 1 W, f = 1 kHz) VPVDD = 12 V, SPK_GAIN = 16.5 Vp/FS, 4.7uH + 0.68uF filter, RSPK = 4 Ω, BD Mode 0.06% VPVDD = 24 V, SPK_GAIN = 29.5 Vp/FS, 4.7uH + 0.68uF filter, RSPK = 4 Ω, 1SPW Mode 0.07% DR Dynamic range A-Weighted, -60 dBFS method, PVDD = 24V, SPK_GAIN = 29.5 Vp/FS 106 dB SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N output level, PVDD=13.5V 107.7 dB A-Weighted, referenced to 1% THD+N output level, PVDD=24V 111 dB KSVR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms, PVDD = 19 V, input audio signal = digital zero 72 dB

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7.6 Timing Requirements

fSCLK SCLK frequency 1.024 MHz tSCLK SCLK period 40 ns tSCLKL SCLK pulse width, low 16 ns tSCLKH SCLK pulse width, high 16 ns tSL SCLK rising to LRCK/FS edge 8 ns tLS LRCK/FS Edge to SCLK rising edge 8 ns tSU Data setup time, before SCLK rising edge 8 ns tDH Data hold time, after SCLK rising edge 8 ns tDFS Data delay time from SCLK falling edge 15 ns I2C Bus Timing – Standard fSCL SCL clock frequency 100 kHz tBUF Bus free time between a STOP and START condition 4.7 µs tLOW Low period of the SCL clock 4.7 µs tHI High period of the SCL clock 4 µs tRS-SU Setup time for (repeated) START condition 4.7 µs tS-HD Hold time for (repeated) START condition 4 µs tD-SU Data setup time 250 ns tD-HD Data hold time 0 900 ns tSCL-R Rise time of SCL signal 20 + 0.1CB 1000 ns tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 1000 ns tSCL-F Fall time of SCL signal 20 + 0.1CB 1000 ns tSDA-R Rise time of SDA signal 20 + 0.1CB 1000 ns tSDA-F Fall time of SDA signal 20 + 0.1CB 1000 ns tP-SU Setup time for STOP condition 4 µs I2C Bus Timing – Fast fSCL SCL clock frequency 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tLOW Low period of the SCL clock 1.3 µs tHI High period of the SCL clock 600 ns tRS-SU Setup time for (repeated)START condition 600 ns tRS-HD Hold time for (repeated)START condition 600 ns tD-SU Data setup time 100 ns tD-HD Data hold time 0 900 ns tSCL-R Rise time of SCL signal 20 + 0.1CB 300 ns tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1CB 300 ns tSCL-F Fall time of SCL signal 20 + 0.1CB 300 ns tSDA-R Rise time of SDA signal 20 + 0.1CB 300 ns tSDA-F Fall time of SDA signal 20 + 0.1CB 300 ns tP-SU Setup time for STOP condition 600 ns tSP Pulse width of spike suppressed 50 ns

7.7 Typical Characteristics

7.7.1 Bridge Tied Load (BTL) Configuration Curves

Figure 1. THD+N vs Frequency-BTL Figure 2. THD+N vs Frequency-BTL Figure 3. THD+N vs Frequency-BTL Figure 4. THD+N vs Frequency-BTL Figure 5. THD+N vs Frequency-BTL Figure 6. THD+N vs Frequency-BTL

Figure 31. Efficiency vs Output Power-BTL

7.7.2 Bridge Tied Load (BTL) Configuration Curves

Ferrite bead + Capacitor as the output filter, BD Modulation, unless otherwise noted. Figure 32. THD+N vs Frequency-BTL Figure 33. THD+N vs Frequency-BTL Figure 34. Output Power vs Supply Voltage-BTL Figure 35. THD+N vs Output Power-BTL

Figure 36. THD+N vs Output Power-BTL Figure 37. THD+N vs Output Power-BTL Figure 38. Crosstalk Figure 39. Efficiency vs Output Power-BTL Figure 40. Efficiency vs Output Power-BTL Figure 41. Efficiency vs Output Power-BTL

7.7.3 Parallel Bridge Tied Load (PBTL) Configuration

used was 4.7 μH / 0.68 μF, unless otherwise noted.

8 Parameter Measurement Information

Figure 53. Serial Audio Port Timing in Slave Mode Figure 54. I2C Communication Port Timing Diagram

PLL & OSC LDO 1.5V ADR/ PDN FAULT SDA SCL SDIN LRCLK SCLK LDO 5V Digital to PWM Conversion H Bridge Gate Driver OC/DC Protect DVDD VR_DIG AVDD PVDD1/2/3/4 AGND PGND 1/2DGND 3.3/1.8V 4.5-26.4V BST_A+ OUT_A+ OUT_A- BST_A- BST_B- OUT_B- BST_B+ OUT_B+ Closed-Loop Feedback Closed-Loop Feedback SDOUT TAS5805M SLASEH5A –MAY 2018–REVISED JULY 2018 www.ti.com Product Folder Links: TAS5805M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TAS5805M device integrates 4 main building blocks together into a single cohesive device that maximizes sound quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:

• A stereo audio DAC.
• An Audio DSP subsystem.
• A flexible closed-loop amplifier capable of operating in stereo or mono, at different switching frequencies, and supporting a variety of output voltages and loads.
• An I2C control port for communication with the device The device requires only two power supplies for proper operation. A DVDD supply is required to power the low voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the audio amplifier. Two internal LDOs convert PVDD to 5 V for GVDD and AVDD and to 1.5V for DVDD respectively.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Power Supplies

9.3.2 Device Clocking

Figure 55. Audio Flow with Respective Clocks Figure 55 shows the basic data flow and clock distribution.

• SCLK (Bit Clock)
• LRCLK/FS (Left Right Word Clock and Frame Sync)
• SDIN (Input Data) The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP and the DAC clock. The TAS5805M device has an audio sampling rate detection circuit that automatically senses the sampling frequency. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz with ±5% tolerance are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.

9.3.3 Serial Audio Port – Clock Rates

serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

Table 1. Audio Data Formats, Bit Depths and Clock Rates device puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). When all audio clocks are within the expected ranges, the device automatically returns to the state it was in.

9.3.4 Serial Audio Port - Data Formats and Bit Depths

selected via Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length. Figure 56. Left-Justified Audio Data Format

9.3.5 Digital Audio Processing

Process Flows for details or request the PPC3 access for TAS5805M app .

9.3.6 Class D Audio Amplifier

9.3.6.1 Speaker Amplifier Gain Select

modulator to the output of the speaker amplifier power stage. Figure 61. Speaker Amplifier Gain signal is not clipped at different PVDD levels. 0dBFS output corresponds to 29.5-V peak output voltage. Table 2. Analog Gain Setting

9.4 Device Functional Modes

9.4.1 Software Control

The TAS5805M device is configured via an I2 C communication port.

are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.

9.4.2 Speaker Amplifier Operating Modes

• BTL Mode
• PBTL Mode

9.4.2.1 BTL Mode

the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.

9.4.2.2 PBTL Mode

9.4.3 Low EMI Modes

9.4.3.1 Spread Spectrum

Spectrum with triangle mode. Table 3. Triangle Mode Spread Spectrum Frequency and Range Selection

9.4.3.2 Channel to Channel Phase Shift

This device supports channel to channel 180-degree PWM phase shift to minimize the EMI.

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9.4.3.3 Multi-Devices PWM Phase Synchronization

This device supports up to 4 phases selection for the multi devices application system. For example, when a system integrated 4 pieces of TAS5805M devices, user can select phase 0/1/2/3 for each device with register PHASE_CTRL (0x6A), which means there is a 45-degree phase shift between each device to minimize the EMI. Recommend to do the Phase Synchronization with I2S clock during the Startup Phase: 1. Halt I2S clock. 2. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A = 0x03 for device 0; Register 0x6A = 0x07 for device 1; Register 0x6A = 0x0B for device 2; Register 0x6A = 0x0F for device 3. There should be a 45-degree PWM phase shift between each device to minimize the EMI. 3. Configure each device into Hi-Z mode. 4. Provide I2S to each device. Phase synchronization for all 4 devices will be automatically done by internal sequence. 5. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization). 6. Device to Device PWM phase shift should be fixed with 45 degree.

9.4.4 Device State Control

Except Shutdown Mode, TAS5805M has other 4 states with different power dissipation which listed in the Electrical Characteristics Table.

• Deep Sleep Mode. Register 0x03h -D[1:0]=00, device stays in Deep Sleep Mode. In this mode, I2C block is still working. This mode can be used to extend the battery life in some portable speaker applications. If the host processor stops playing audio for a long time, TAS5805M can be set to Deep Sleep Mode to minimize power dissipation until host processor starts playing audio again. Device returns back to Play Mode by setting Register 0x03h -D[1:0] to 11. Unlike the Shutdown Mode (Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP is kept active.
• Sleep Mode. Register 0x03h -D[1:0]=01, device stays in Sleep Mode. In this mode, I2 C block, Digital core, DSP Memory , 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit Sleep Mode, DSP is kept active.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, device stays in Hiz Mode. In this mode, only output driver is set to be Hi-Z state, all other block operate normally.
• Play Mode. Register 0x03h -D[1:0]=11, device stays in Play Mode.

9.4.5 Device Modulation

TAS5805M has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select modulation schemes for TAS5805M with Register 0x02 [1:0]-DAMP_MOD.

9.4.5.1 BD Modulation

This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load.

Figure 62. BD Mode Modulation of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses.

Figure 63. 1SPW Mode Modulation

9.4.5.3 Hybrid Modulation

22uH+0.68uF) is recommended.

9.5 Programming and Control

9.5.1 I2 C Serial Communication Bus

register 0 on each page. This register value selects the page address, from 0 to 255.

9.5.2 Slave Address

defined by ADR pin in Table 4. Table 4. I2 C Slave Address Configuration

9.5.2.1 Random Write

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer. Figure 64. Random Write Transfer

9.5.2.2 Sequential Write

responds with an acknowledge bit and the I2 subaddress is automatically incremented by one. Figure 65. Sequential Write Transfer

9.5.2.3 Random Read

condition to complete the single-byte data-read transfer. Figure 66. Random Read Transfer

9.5.2.4 Sequential Read

stop condition to complete the transfer. Figure 67. Sequential Read Transfer

9.5.2.5 DSP Memory Book, Page and BQ update

9.5.2.6 Checksum

will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.

9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum

same register locations where the CRC checksum is valid.

9.5.2.6.2 Exclusive or (XOR) Checksum

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

9.5.3 Control via Software

• Startup Procedures
• Shutdown Procedures

9.5.3.1 Startup Procedures

1. Configure ADR/FAULT pin with proper setting for I2C device address. 2. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first). 3. Once power supplies are stable, start SCLK, LRCLK. 4. Once I2S clock are stable, configure the device via the I2C control port based on the user cases (Make sure the PDN pin = HIGH before I2C control port operating). 5. The device is now in normal operation. It is important to note that I2C control port register changes should only occur when the device is placed into SLEEP. This can be accomplished by configuring Register 0x3h-D[1:0] in the control register.

9.5.3.2 Shutdown Procedures

1. The device is in normal operation. 2. Configure the Register 0x03h -D[1:0]=00 (DEEP SLEEP) via the I2C control port or Pull PDN low. 3. Pull PDN low. 4. The clocks can now be stopped and the power supplies brought down. 5. The device is now fully shutdown and powered off.

9.5.3.3 Protection and Monitoring

9.5.3.3.1 Overcurrent Shutdown (OCSD)

Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector, and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2 fault register saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output FETs, and operation returns to normal after the short is removed.

9.5.3.3.2 DC Detect

If the TAS5805M device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the OUTxx outputs transition to high impedance, signifying a fault.

9.6 Register Maps

9.6.1 CONTROL PORT Registers

Table 5 should be considered as reserved locations and the register contents should not be modified. Table 5. CONTROL PORT Registers

Table 5. CONTROL PORT Registers (continued) access types in this section. Table 6. CONTROL PORT Access Type Codes

9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 68 and described in Table 7. Figure 68. RESET_CTRL Register Table 7. RESET_CTRL Register Field Descriptions

4 RST_MOD W 0 WRITE CLEAR BIT

0 RST_CONTROL_REG W 0 WRITE CLEAR BIT

This bit resets the control port registers back to their initial values. The RAM content is not cleared.

9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 69 and described in Table 8. Figure 69. DEVICE_CTRL_1 Register Table 8. DEVICE_CTRL_1 Register Field Descriptions

7 RESERVED R/W 0 This bit is reserved

3 RESERVED R/W 0 This bit is reserved

2 DAMP_PBTL R/W 0 0: SET DAMP TO BTL MODE

9.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL_2 is shown in Figure 70 and described in Table 9. Figure 70. DEVICE_CTRL_2 Register Table 9. DEVICE_CTRL_2 Register Field Descriptions

4 DIS_DSP R/W 1 DSP reset

settled so that DMA channels do not go out of sync.

3 MUTE R/W 0 Mute Both Left /Right Channel

volume will be smoothly ramped down/up to avoid pop/click noise.

2 RESERVED R/W 0 This bit is reserved

9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 71 and described in Table 10. Figure 71. I2C_PAGE_AUTO_INC Register Table 10. I2C_PAGE_AUTO_INC Register Field Descriptions

3 PAGE_AUTOINC_REG R/W 0 Page auto increment disable

page itself like in older part.

9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 72 and described in Table 11. Figure 72. SIG_CH_CTRL Register Table 11. SIG_CH_CTRL Register Field Descriptions must be set according to the current audio sampling rate.

9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 73 and described in Table 12. Figure 73. CLOCK_DET_CTRL Register Table 12. CLOCK_DET_CTRL Register Field Descriptions

6 DIS_DET_PLL R/W 0 Ignore PLL overate Detection

ignored, a PLL overrate error will not cause a clock error.

5 DIS_DET_BCLK_RANGE R/W 0 Ignore BCK Range Detection

4 DIS_DET_FS R/W 0 Ignore FS Error Detection

3 DIS_DET_BCLK R/W 0 Ignore BCK Detection

This bit controls whether to ignore the BCK detection against LRCK.

2 DIS_DET_MISS R/W 0 Ignore BCK Missing Detection

ignored an BCK missing will not cause a clock error.

1 RESERVED R/W 0 This bit is reserved

0 RESERVED R/W 0 This bit is reserved

9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]

SDOUT_SEL is shown in Figure 74 and described in Table 13. Figure 74. SDOUT_SEL Register

Table 13. SDOUT_SEL Register Field Descriptions 0 SDOUT_SEL R 0 SDOUT Select. This bit selects what is being output as SDOUT pin.

9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 75 and described in Table 14. Figure 75. I2S_CTRL Register Table 14. I2S_CTRL Register Field Descriptions

5 BCK_INV R/W 0 BCK Polarity

the falling edge of the BCK.

9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 76 and described in Table 15. Figure 76. SAP_CTRL1 Register Table 15. SAP_CTRL1 Register Field Descriptions

7 I2S_SHIFT_MSB R/W 0 I2S Shift MSB

6 RESERVED R/W 0 This bit is reserved

mode is less than 8 cycles of SCK, these two bits need set to 01.

9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 77 and described in Table 16. Figure 77. SAP_CTRL2 Register Table 16. SAP_CTRL2 Register Field Descriptions

9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 78 and described in Table 17. Figure 78. SAP_CTRL3 Register Table 17. SAP_CTRL3 Register Field Descriptions

9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 79 and described in Table 18. Figure 79. FS_MON Register Table 18. FS_MON Register Field Descriptions 3-0 FS R 0000 These bits indicate the currently detected audio sampling rate.

9.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 80 and described in Table 19. Figure 80. BCK_MON Register Table 19. BCK_MON Register Field Descriptions BCK clocks in one audio frame.

9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 81 and described in Table 20. Figure 81. CLKDET_STATUS Register Table 20. CLKDET_STATUS Register Field Descriptions must be stable and in the range of 32-512FS to be valid. bit2: This bit indicates whether the BCK is missing or not. be reported as unlocked when it is disabled.

9.6.1.15 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL_CTL is shown in Figure 82 and described in Table 21. Figure 82. DIG_VOL_CTL Register Table 21. DIG_VOL_CTR Register Field Descriptions digital volume is 24 dB to -103 dB in -0.5 dB step.

9.6.1.16 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL2 is shown in Figure 83 and described in Table 22. Figure 83. DIG_VOL_CTRL2 Register Table 22. DIG_VOL_CTRL2 Register Field Descriptions

9.6.1.17 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL3 is shown in Figure 84 and described in Table 23. Figure 84. DIG_VOL_CTRL3 Register Table 23. DIG_VOL_CTRL3 Register Field Descriptions usually needs faster ramp down compared to normal soft mute.

9.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in Figure 85 and described in Table 24. Figure 85. AUTO_MUTE_CTRL Register Table 24. AUTO_MUTE_CTRL Register Field Descriptions 0: Auto mute left channel and right channel independently.

9.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 86 and described in Table 25. Figure 86. AUTO_MUTE_TIME Register Table 25. AUTO_MUTE_TIME Register Field Descriptions for 96 kHz sampling rate and will scale with other rates. for 96 kHz sampling rate and will scale with other rates.

9.6.1.20 ANA_CTRL Register (Offset = 53h) [reset = 0x00]

ANA_CTRL is shown in Figure 87 and described in Table 26. Figure 87. ANA_CTRL Register Table 26. ANA_CTRL Register Field Descriptions be selected for high audio performance.

9.6.1.21 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 88 and described in Table 27. Figure 88. AGAIN Register Table 27. AGAIN Register Field Descriptions This bit controls the analog gain.

9.6.1.22 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]

BQ_WR_CTRL1 is shown in Figure 89 and described in Table 28. Figure 89. BQ_WR_CTRL1 Register Table 28. BQ_WR_CTRL1 Register Field Descriptions 0 BQ_WR_FIRST_COEF R/W 0 Indicate the first coefficient of a BQ is starting to write.

9.6.1.23 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]

DAC_CTRL is shown in Figure 90 and described in Table 29. Figure 90. DAC_CTRL Register Table 29. DAC_CTRL Register Field Descriptions

9.6.1.24 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]

ADR_PIN_CTRL is shown in Figure 91 and described in Table 30. Figure 91. ADR_PIN_CTRL Register Table 30. ADR_PIN_CTRL Register Field Descriptions

0 ADR_OE R/W 0 ADR Output Enable This bit sets the direction of the ADR pin

9.6.1.25 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in Figure 92 and described in Table 31. Figure 92. ADR_PIN_CONFIG Register Table 31. ADR_PIN_CONFIG Register Field Descriptions

9.6.1.26 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in Figure 93 and described in Table 32. Figure 93. DSP_MISC Register Table 32. DSP_MISC Register Field Descriptions

9.6.1.27 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in Figure 94 and described in Table 33. Figure 94. DIE_ID Register

Table 33. DIE_ID Register Field Descriptions

9.6.1.28 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 95 and described in Table 34. Figure 95. POWER_STATE Register Table 34. POWER_STATE Register Field Descriptions

9.6.1.29 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 96 and described in Table 35. Figure 96. AUTOMUTE_STATE Register Table 35. AUTOMUTE_STATE Register Field Descriptions 1 ZERO_RIGHT_MON R 0 This bit indicates the auto mute status for right channel. 0 ZERO_LEFT_MON R 0 This bit indicates the auto mute status for left channel.

9.6.1.30 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]

PHASE_CTRL is shown in Figure 97 and described in Table 36. Figure 97. PHASE_CTR Register Table 36. PHASE_CTR Register Field Descriptions mode if this feature is needed.

1 I2S_SYNC_EN R/W 0 Use I2S to synchronize output PWM phase

0 PHASE_SYNC_EN R/W 0 0: RAMP phase sync disable

9.6.1.31 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

SS_CTRL0 is shown in Figure 98 and described in Table 37. Figure 98. SS_CTRL0 Register Table 37. SS_CTRL0 Register Field Descriptions

5 SS_PRE_DIV_SEL R/W 0 select pll clock divide 2 as source clock in manual mode

4 SS_MANUAL_MODE R/W 0 set ramp ss controller to manual mode

1 SS_RDM_EN R/W 0 random SS enable

0 SS_TRI_EN R/W 0 triangle SS enable

9.6.1.32 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 99 and described in Table 38. Figure 99. SS_CTRL1 Register Table 38. SS_CTRL1 Register Field Descriptions

9.6.1.33 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]

SS_CTRL2 is shown in Figure 100 and described in Table 39. Figure 100. SS_CTRL2 Register Table 39. SS_CTRL2 Register Field Descriptions

9.6.1.34 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 101 and described in Table 40. Figure 101. SS_CTRL3 Register Table 40. SS_CTRL3 Register Field Descriptions

9.6.1.35 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 102 and described in Table 41. Figure 102. SS_CTRL4 Register Table 41. SS_CTRL4 Register Field Descriptions

9.6.1.36 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 103 and described in Table 42. Figure 103. CHAN_FAULT Register Table 42. CHAN_FAULT Register Field Descriptions

3 CH1_DC_1 R 0 left channel DC fault

2 CH2_DC_1 R 0 right channel DC fault

1 CH1_OC_I R 0 left channel over current fault

0 CH2_OC_I R 0 right channel over current fault

9.6.1.37 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 104 and described in Table 43. Figure 104. GLOBAL_FAULT1 Register Table 43. GLOBAL_FAULT1 Register Field Descriptions 7 OTP_CRC_ERROR R 0h Indicate OTP CRC check error.

6 BQ_WR_ERROR R 0h the recent BQ is written failed

2 CLK_FAULT_I R 0h clock fault

1 PVDD_OV_I R 0h PVDD OV fault

0 PVDD_UV_I R 0h PVDD UV fault

9.6.1.38 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 105 and described in Table 44. Figure 105. GLOBAL_FAULT2 Register Table 44. GLOBAL_FAULT2 Register Field Descriptions

0 OTSD_I R 0 over temperature shut down fault

9.6.1.39 OT WARNING Register (Offset = 73h) [reset = 0x00]

OT_WARNING is shown in Figure 106 and described in Table 45. Figure 106. OT_WARNING Register Table 45. OT_WARNING Register Field Descriptions

2 OTW R 0 over temperature warning ,130C

9.6.1.40 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 107 and described in Table 46. Figure 107. PIN_CONTROL1 Register Table 46. PIN_CONTROL1 Register Field Descriptions

7 MASK_OTSD R/W 0 mask OTSD fault report

6 MASK_DVDD_UV R/W 0 mask DVDD UV fault report

5 MASK_DVDD_OV R/W 0 mask DVDD OV fault report

4 MASK_CLK_FAULT R/W 0 mask clock fault report

3 MASK_PVDD_UV R/W 0 mask PVDD UV fault report

2 MASK_PVDD_OV R/W 0 mask PVDD OV fault report

1 MASK_DC R/W 0 mask DC fault report

0 MASK_OC R/W 0 mask OC fault report

9.6.1.41 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 108 and described in Table 47. Figure 108. PIN_CONTROL2 Register Table 47. PIN_CONTROL2 Register Field Descriptions

5 CLKFLT_LATCH_EN R/W 1 enable clock fault latch

4 OTSD_LATCH_EN R/W 1 enable OTSD fault latch

3 OTW_LATCH_EN R/W 1 enable OT warning latch

2 MASK_OTW R/W 0 mask OT warning report

9.6.1.42 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 109 and described in Table 48. Figure 109. MISC_CONTROL Register Table 48. MISC_CONTROL Register Field Descriptions

7 DET_STATUS_LATCH R/W 0 1:latch clock detection status

4 OTSD_AUTO_REC_EN R/W 0 OTSD auto recovery enable

9.6.1.43 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 110 and described in Table 49. Figure 110. FAULT_CLEAR Register Table 49. FAULT_CLEAR Register Field Descriptions 7 ANALOG_FAULT_CLEAR W 0 WRITE CLEAR BIT.

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section details the information required to configure the device for several popular configurations and provides guidance on integrating the TAS5805M device into the larger system.

10.1.1 Bootstrap Capacitors

The output stage of the TAS5805M uses a high-side NMOS driver, rather than a PMOS driver. To generate the gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. Use 0.22-µF capacitors to connect the appropriate output pin (OUT_X) to the bootstrap pin (BST_X). For example, connect a 0.22-µF capacitor between OUT_A and BST_A for bootstrapping the A channel. Similarly, connect another 0.22-µF capacitor between the OUT_B and BST_B pins for the B channel inverting output.

10.1.2 Power Supply Decoupling

To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with some good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the PVDD pins of the device.

10.1.3 Output EMI Filtering

The TAS5805M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter. The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that are commonly used. In other high-power applications, large toroid inductors are required for maximum power and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon the desired load and response.

10.2 Typical Applications

10.2.1 2.0 (Stereo BTL) System In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0. Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel. While certainly the two channels can contain any two audio channels, such as two surround channels of a multi-channel speaker system, the most popular occurrence in two channels systems is a stereo pair. Figure 111 shows the 2.0 (Stereo BTL) system application.

Figure 111. 2.0 (Stereo BTL) System Application Schematic with Ferrite Bead as the output filter

Figure 112. 2.0 (Stereo BTL) System Application Schematic with Inductor as the output filter

10.2.1.1 Design Requirements

• Power supplies: – 3.3-V or 1.8-V supply – 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients The requirement for the supporting components for the TAS5805M device in a Stereo 2.0 (BTL) system is provide in Table 50 and Table 51

Table 50. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as

Table 50. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as output Output Power = 1W/4W/8W for each channel.

• Select Ferrite bead (L1~L5). The trade-off is impedance and rated current. If the rated current meet the system's requirement, larger impedance means larger EMI margin for the EMI, especially for the frequency band 5MHz~50MHz. The typical ferrite bead recommend for TAS5805M is NFZ2MSM series (Murata) and UPZ2012E series (Sunlord). 300 ohm @ 100MHz ferrite bead is a typical value which can pass EMI for most of application cases.
• Select capacitor (C15~C23). The trade-off is capacitor value and idle current. Larger capacitor means larger idle current, increase the capacitor value from 1nF to 2.2nF makes much help for frequency band 5MHz~100MHz.
• Using Ferrite bead as the output filter, recommend designer to use Fsw=384kHz with Spread spectrum enable, BD Modulation, refer to Spread Spectrum
• With Ferrite bead as the output power. In order to pass EMI (AC Conducted Emission) standard, an AC to DC adapter with EMI filter in it is needed. For most of applications (TV/Voice Control Speaker/Wireless speaker/Soundbar) which need a 110V~220V power supply usually has a EMI filter in the AC to DC adapter. Some cases use DC power supply and also need to test the DC Conducted Emission , this applications (Automotive/Industry) need a simple EMI filter on PVDD for TAS5805M. Refer to application note: AN-2162 Simple Success With Conducted EMI From DC to DC Converters.

Table 51. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Inductor as output

384kHz to 768kHz. Higher switching frequency means smaller Inductor value needed.

• With 768kHz switching frequency. Designers can select 10uH + 0.68uF or 4.7uH +0.68uF as the output filter, this will help customer to save the Inductor size with the same rated current during the inductor selection. With 4.7uH + 0.68uF, make sure PVDD ≤ 18V to avoid the large ripple current to trigger the OC threshold (5A).
• With 384kHZ switching frequency. Designers can select 22uH + 0.68uF or 15uH + 0.68uF or 10uH + 0.68uF as the output filter, this will help customer to save power dissipation for some battery power supply application. With 10uH + 0.68uF, make sure PVDD ≤ 18V to avoid the large ripple current to trigger the OC threshold (5A).

10.2.1.2 Detailed Design Procedures

Design Procedures can be used for Stereo 2.0, Mono, 2.1 system.

10.2.1.2.1 Step One: Hardware Integration

• Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Following the recommended component placement, board layout, and routing given in the example layout above, integrate the device and its supporting components into the system PCB file. – The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended. – For questions and support, go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

10.2.1.2.2 Step Two: Hardware Integration

Using the TAS5805MEVM evaluation module and the PPC3 app to configure the desired device settings.

10.2.1.2.3 Step Three: Software Integration

• Using the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

10.2.1.3 Application Curves

10.2.1.3.1 Audio Performance

Figure 113. THD+N vs Frequency (Ferrite bead as Output Figure 114. THD+N vs Frequency (Inductor as Output

10.2.1.3.2 EN55022 Conducted Emissions Results with Ferrite Bead as output filter

Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel. Figure 115. Conducted Emission with Ferrite Bead Filter - Figure 116. Conducted Emission with Ferrite Bead Filter -

10.2.1.3.3 EN55022 Radiated Emissions Results with Ferrite Bead as output filter

Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel. Figure 117. Radiated Emission with Ferrite Bead Filter - Figure 118. Radiated Emission with Ferrite Bead Filter - Radiated Emission. More data are included in the application note -TAS5805M Design Considerations for EMC.

10.2.2 MONO (PBTL) Systems

In MONO mode, TAS5805M can be used as PBTL mode to drive sub-woofer with more output power.

9 RU 9

Figure 119. Mono (PBTL) System Application Schematic

10.2.2.1 Design Requirements

• Power supplies: – 3.3-V or 1.8-V supply – 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients The requirement for the supporting components for the TAS5805M device in a MONO (PBTL) system is provide in Table 52

Table 52. Supporting Component Requirements for MONO (PBTL) system (With Inductor as output

10.2.2.2 Detailed Design Procedure

For information about the Detailed Design Procedure, see the Detailed Design Procedures section.

10.2.2.3 Application Curves

Figure 120. Efficiency vs Output Power (Inductor as Figure 121. THD+N vs Output Power (Inductor as Output 2.1 (Stereo BTL with Two TAS5805M devices) system application.

Figure 122. 2.1 (2.1 CH with Two TAS5805M Devices) Application Schematic

11 Power Supply Recommendations

I2C communication and providing stable I2S clock before enabling the device outputs. Figure 123. Power Supply Function Block Diagram

11.1 DVDD Supply

as closely as possible for proper operation and performance. Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.

11.2 PVDD Supply

voltage spikes which can damage the device.

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated PVDD Supply (continued) A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device. Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD. AVDD pin is provided for the attachment of decoupling capacitor for the TAS5805M internal circuitry. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.

SLASEH5A –MAY 2018–REVISED JULY 2018 www.ti.com Product Folder Links: TAS5805M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

12 Layout

12.1 Layout Guidelines

12.1.1 General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and the layout of the supporting components used around them. The system level performance metrics, including thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all affected by the device and supporting component layout. Ideally, the guidance provided in the applications section with regard to device and component selection can be followed by precise adherence to the layout guidance shown in the Layout Example section. These examples represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These designs can be modified slightly as needed to meet the needs of a given application. In some applications, for instance, solution size can be compromised to improve thermal performance through the use of additional contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start from the guidance shown in the Layout Example section and work with TI field application engineers or through the E2E community to modify it based upon the application specific goals.

12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5805M device deserve special attention. The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these components too far from the TAS5805M device can cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD pins than what is shown in the example layouts in the Layout Example section.

12.1.3 Optimizing Thermal Performance

Follow the layout example shown in the Figure 124 to achieve the best balance of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance can be required due to design constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device naturally travels away from the device and into the lower temperature structures around the device.

12.1.3.1 Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures. These tips should be followed to achieve that goal:

• Avoid placing other heat producing components or structures near the amplifier (including above or below in the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5805M device and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top and bottom layer.
• Place the TAS5805M device away from the edge of the PCB when possible to ensure that the heat can travel away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5805M device to the surrounding areas with traces or via strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in between the two pads, orient it so that the narrow end of the passive component is facing the TAS5805M device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane

www.ti.com SLASEH5A –MAY 2018–REVISED JULY 2018 Product Folder Links: TAS5805M Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Layout Guidelines (continued) from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

12.1.3.2 Stencil Pattern

The recommended drawings for the TAS5805M device PCB foot print and associated stencil pattern are shown at the end of this document in the package addendum. Additionally, baseline recommendations for the via arrangement under and around the device are given as a starting point for the PCB design. This guidance is provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this guidance may be too conservative and advanced PCB design techniques may be used to improve thermal performance of the system. NOTE The customer must verify that deviation from the guidance shown in the package addendum, including the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability goals.

12.1.3.2.1 PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5805M device will be soldered. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5805M device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5805M device has the largest interface possible to move heat from the device to the board. The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the Layout Example section, this interface can benefit from improved thermal performance. NOTE Vias can obstruct heat flow if they are not constructed properly. More notes on the construction and placement of vias are as follows:

• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing should be determined by the voltages present on the planes surrounding the via and minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in the Layout Example section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal layers. If needed, remove some vias that are farthest from the TAS5805M device to open up the current path to and from the device.

12.1.3.2.2 Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to

12.2 Layout Example

Figure 124. 2.0 (Stereo BTL with Ferrite Bead as Output Filter) Layout View Figure 125. 2.0 (Stereo BTL with Inductor as Output Filter) Layout View

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Device Nomenclature

The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE, and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this product and documentation, collateral, or support tools and software used with this product. For any additional questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum. Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half- bridge and the other terminal is connected to another half-bridge. DUT refers to a device under test to differentiate one device from another. Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing the output signal to the input signal and attempts to correct for non-linearities in the output. Dynamic controls are those which are changed during normal use by either the system or the end-user. GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform many functions as required by the system. Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device which serves as a central system controller, providing control information to devices connected to it as well as gathering audio source data from devices upstream from it and distributing it to other devices. This device often configures the controls of the audio processing devices (like the ) in the audio path in order to optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure level, safe operating area of the system, and user preference. Maximum continuous output power refers to the maximum output power that the amplifier can continuously deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period of time required that their temperatures reach thermal equilibrium and are no longer increasing Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half bridges placed in parallel rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier. Static controls/Static configurations are controls which do not change while the system is in normal use. Vias are copper-plated through-hole in a PCB.

13.1.2 Development Support

For RDGUI software, please consult your local field support engineer.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

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13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

13.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 17-Jul-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTAS5805MPWPR ACTIVE HTSSOP PWP 28 2000 TBD Call TI Call TI -25 to 85 TAS5805MPWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 TAS5805MA1 TAS5805MPWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 TAS5805MA1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 17-Jul-2018 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5805MPWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 Pack Materials-Page 2

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