PT7C433833A
Document overview
- Manufacturer or author: Diodes Incorporated
- PDF pages: 21
Technical content
Features
Description
Table 1. Basic functions of PT7C4338
1 Oscillator
2 Time
3 Alarm interrupt -
5 RAM 568
6 Battery backup
- No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
- See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen - and Antimony-free, "Green" and Lead-free.
- Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000 ppm
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 2 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Pin Configuration Pin Description Pin# Pin Name Type Description 1 X1 I 32.768kHz Crystal Connections. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. An external 32.768kHz oscillator can also drive the PT7C4338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
2 X2 O
6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor.
7 SQW/OUT O
Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is open drain and requires an external pull up resistor. Operates with either VCC or VBAT applied.
8 VCC P
Supply Voltage. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.
3 VBAT P
+3V Battery Input. Backup supply input for any standard 3V lithium cell or other energy source. Battery voltage must be held between the minimum and maximum limits for proper operation. If a backup supply is not required, VBAT must be grounded. UL recognized to ensure against reverse charging when used with a lithium battery.
4 GND P
Ground. DC power is provided to the device on these pins. VCC is the primary power input. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. VBAT GND VCC SQW/OUT SCL 6 4 5SDA PT7C4338 SOIC-8 MSOP-8
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 3 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Function Block
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 4 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Maximum Ratings Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit VCC Supply Voltage PT7C433833A 2.7 3.3 5.5 V VIH Logic 1 Note 2 0.7 * VCC - VCC + 0.3 VIL Logic 0 Note 2 -0.3 - +0.3 * VCC VPF Power-Fail Voltage PT7C433833A 1.5 1.75 2.0 VBAT VBAT Battery Voltage Note 2 1.3 3.0 3.7 Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground.
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 5 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85 °C, unless otherwise noted. Typical values are at V CC = 3.3V, TA = +25°C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit VBAT VBAT Battery Voltage Note 2 1.3 - 3.7 V ILI Input Leakage Note 3 -1 - 1 μA ILO I/O Leakage Note 4 -1 - 1 μA IOLSDA SDA Logic 0 Output VCC > =2V; VOL = 0.4V 3.0 - - mA VCC < 2V; VOL = 0.2 VCC 3.0 - - IOLSQW SQW/OUT Logic 0 Output VCC > =2V; VOL = 0.4V 1.0 - - mA 1.3V < VCC < 2V; VOL = 0.2 VCC 250 - - μA ICCA Active Supply Current (Note 5) PT7C433833A - 40 120 μA ICCS Standby Current (Note 6) PT7C433833A - 30 100 μA IBATLKG VBAT Leakage Current (VCC Active) - - 10 100 nA (VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0V, TA = +25°C, unless otherwise noted.) Symbol Parameter Min. Typ. Max. Unit IBATOSC1 VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT OFF (Note 7) - 350 1000 nA IBATOSC2 VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT ON (32kHz) (Note 7) - 400 1200 nA IBATDAT VBAT Data-Retention Current (OSC OFF); VBAT =3.7V (Note 7) - - 300 nA Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: SCL only. Note 4: SDA and SQW/OUT. Note 6: Specified with the I2C bus inactive. Note 7: Measured with a 32.768 kHz crystal attached to X1 and X2. Sym Description Value Unit VHM Rising and falling threshold voltage high 0.7 VCC V VHL Rising and falling threshold voltage low 0.3 VCC V Measurement Level Signal tf tr VHM VLM
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 6 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A TA = -40℃ to +85℃ (Note 1) Symbol Parameter Conditions Min. Typ. Max. Unit fSCL SCL Clock Frequency - - - 400 kHz tBUF Bus Free Time Between STOP and START condition - 1.3 - - μs tHD:STA Hold Time (Repeated) START Condition Note 2 0.6 - - μs tLOW LOW Period of SCL Clock - 1.3 - - μs tHIGH HIGH Period of SCL Clock - 0.6 - - μs tSU:STA Setup Time of Repeated START Condition - 0.6 - - μs tHD:STA Data Hold Time Note3,4 0 - 0.9 μs tSU:STA Data Setup Time Note5 100 - - ns tr Rise Time of Both SDA and SCL Signals (Note 6) Fast mode - - 300 ns Standard mode - - 1000 tf Fall Time of Both SDA and SCL Signals Note6 - - 300 ns tSU:STO Setup Time for STOP Condition - 0.6 - - μs CB Capacitance Load for Each Bus Line Note 6 - - 400 pF CI/O I/O Capacitance (SDA, SCL) Note 1 - - 10 pF tOSF Oscillator Stop Flag (OSF) Delay Note 7 - 100 - ms Note 1: Limits of full temperature are guaranteed by design not production test. Note 2: After this period, the first clock pulse is generated. A limit of min value at fast mode is 4.0us in UM10204 I2C-bus specification. Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 4: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr MAX + tSU:DAT = 1000 +250 = 1250ns before the SCL line is released. Note 7: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBAT ≤ 3.7V. Timing Diagram
Document Number DS40364 Rev 3-4 7 © 2024 Copyright Diodes Incorporated. All Rights Reserved. Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs. Figure 1. Power-Up/Power-Down Timing
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 8 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Recommended Layout for Crystal Built-in Capacitors Specifications and Recommended External Capacitors Parameter Symbol Typ Unit Build-in capacitors X1 to GND CG 20 pF X2 to GND CD 20 pF Recommended External capacitors X1 to GND C1 4 pF X2 to GND C2 4 pF Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768 KHz, C1 and C2 should meet the equation as below: Crystal Specifications Parameter Symbol Min Typ Max Unit Nominal Frequency fO - 32.768 - kHz Series Resistance ESR - - 70 k Load Capacitance CL - 12.5 - pF Note: The crystal, traces and crystal input pins should be isolated from RF generating signals.
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 9 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Function Description Overview of Functions Clock Function Programmable Square Wave Output Interface with CPU Oscillator Enable/disable Registers Allocation of registers Addr. (hex)*1 Function Register Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 Seconds (00-59) /EOSC*2 S40 S20 S10 S8 S4 S2 S1
01 Minutes (00-59) 0 M40 M20 M10 M8 M4 M2 M1
02 Hours (00-23 / 01-12) 0 12, /24 H20 or
P, /A H10 H8 H4 H2 H1
03 Days of the week (01-07) 0 0 0 0 0 W4 W2 W1
04 Dates (01-31) 0 0 D20 D10 D8 D4 D2 D1
05 Months (01-12) 0 0 0 MO10 MO8 MO4 MO2 MO1
06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
07 Control*3 OUT*4 0 OSF SQWE*5 0 0 RS1*6 RS0*6
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 10 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Control and Status Register Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
07 Control OUT 0 OSF SQWE 0 0 RS1 RS0
(default) 1 0 1 1 0 0 1 1
- OUT OUT Data Description Read / Write 0 When SQWE = 0, SQW/OUT pin output low. 1 When SQWE = 0, SQW/OUT pin output high. Default
- SQWE (Square Wave Enable)
- RS (Rate Select) RS1, RS0 Data SQW output freq. (Hz) Read / Write 00 1 01 4.096k 10 8.192k 11 32.768k Default
- OSF (Oscillator Stop Flag)
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 11 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Time Counter Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
00 Seconds /EOSC S40 S20 S10 S8 S4 S2 S1
(default) 0 0 0 0 0 0 0 0
01 Minutes 0 M40 M20 M10 M8 M4 M2 M1
(default) 0 0 0 0 0 0 0 0
02 Hours 0 12, /24 H20 or P,/A H10 H8 H4 H2 H1
(default) 0 0 0 0 0 0 0 0
- 12, /24 bit 12, /24 Data Description Read / Write 0 24-hour system 1 12-hour system 12, /24 Description Hours register 0 24-hour time display 1 12-hour time display * Be sure to select between 12-hour and 24-hour clock operation before writing the time data. 24-hour clock 12-hour clock 24-hour clock 12-hour clock 00 52 ( AM 12 ) 12 72 ( PM 12) 01 41 ( AM 01 ) 13 61 ( PM 01 ) 02 42 ( AM 02 ) 14 62 ( PM 02 ) 03 43 ( AM 03 ) 15 63 ( PM 03 ) 04 44 ( AM 04 ) 16 64 ( PM 04 ) 05 45 ( AM 05 ) 17 65 ( PM 05 ) 06 46 ( AM 06 ) 18 66 ( PM 06 ) 07 47 ( AM 07 ) 19 67 ( PM 07 ) 08 48 ( AM 08 ) 20 68 ( PM 08 ) 09 49 ( AM 09 ) 21 69 ( PM 09 ) 10 50 ( AM 10 ) 22 70 ( PM 10 ) 11 51 ( AM 11 ) 23 71 ( PM 11 )
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 12 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Days of the Week Counter Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
03 Days of the week 0 0 0 0 0 W4 W2 W1
(default) 0 0 0 0 0 0 0 1 Calendar Counter Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0
04 Dates 0 0 D20 D10 D8 D4 D2 D1
(default) 0 0 0 0 0 0 0 1
05 Months 0 0 0 M10 M8 M4 M2 M1
(default) 0 0 0 0 0 0 0 1
06 Years Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
(default) 0 0 0 0 0 0 0 0 Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
Document Number DS40364 Rev 3-4 13 © 2024 Copyright Diodes Incorporated. All Rights Reserved. Figure 2. System configuration Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
Document Number DS40364 Rev 3-4 14 © 2024 Copyright Diodes Incorporated. All Rights Reserved. Figure 3. Starting and Stopping on I2C Bus *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 15 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A b) Data Acknowledge Response (ACK Signal) Slave Address Operation Transfer data Slave address R / W bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read D1 h 1 1 0 1 0 0 0 1 (= Read) Write D0 h 0 (= Write) I2C Bus’s Basic Transfer Format SCL from Master 1 2 8 9 SDA from transmitter (sending side) SDA from receiver (receiving side) Release SDA Low active ACK signal S Start indication P Stop indication Sr Restart indication A RTC Acknowledge A Master Acknowledge
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 16 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A 1) Write via I2C Bus 2) Read via I2C Bus a) Standard Read b) Simplified Read Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. Slave address (7 bits) 1 1 0 1 0 0 0 0 write Addr. setting Slave address + write specification Address Specifies the write start address. A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit A P Write data S A A C K A C K A C K Start Stop Slave address (7 bits) 1 1 0 1 0 0 0 0 write Slave address + write specification Address Specifies the read start address. Addr. setting AS Slave address (7 bits) 1 1 0 1 0 0 0 1 Read Slave address + read specification Data read (1) Data is read from the specified start address and address auto increment. A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /A PSr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bitbit Data read (2) Address auto increment to set the address for the next data to be read. A C K N O A C K A A C K A C K A C K A Start StopRestart Data read (2) Address register auto increment to set the address for the next data to be read. Data read (1) Data is read from the address pointed by the internal address register and address auto increment. Slave address (7 bits) 1 1 0 1 0 0 0 1 Read A bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /A PS 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bitbit A C K N O A C K A C K A StopStart Slave address + read specification
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 17 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Part Marking U Package W Package ZE Package
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 18 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A Packaging Mechanical 8-SOIC (W)
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 19 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A 8-MSOP (U)
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 20 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A 8-TDFN (ZE) please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
Ordering Information
Part Number Package Code Package Description PT7C433833AWEX W 8-Pin, 150mil-Wide (SOIC) PT7C433833AUEX U 8-Pin, Mini Small Outline Package (MSOP) PT7C433833AZEEX ZE 8-Pin, 2x3 (TDFN) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. 4. E = Pb-free and Green 5. X suffix = Tape/Reel
PT7C433833A www.diodes.com May 2024 Document Number DS40364 Rev 3-4 21 © 2024 Copyright Diodes Incorporated. All Rights Reserved. PT7C433833A IMPORTANT NOTICE 1.DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2.The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes ’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any prod uct described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. 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