PT6880 PTC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 42
Technical content
Features
CMOS Technology Low Power Consumption 4-Bit or 8-Bit MPU Interface High Speed MPU Interface: 2MHz (VDD =5V) 80 x 8-Bit Display RAM (80 characters max.) Auto Reset Function 5 x 8 and 5 x 10 Dot Matrix Built-in Oscillator with External Resistors Programmable Duty Cycle: - 1/8 Duty: (1 Display Line, 5 x 8 Dots with Cursor) - 1/11 Duty: (1 Display Line, 5 x 10 Dots with Cursor) - 1/16 Duty: (2 Display Lines, 5 x 8 Dots with Cursor) 9920-Bit Character Generator ROM (CGROM) - 208 Character Fonts (5 x 8 dot matrix) - 32 Character Fonts (5 x 10 dot matrix) 64 x 8-Bit Character Generator RAM (CGRAM) - 8 Character Fonts (5 x 8 dot matrix) - 4 Character Fonts ( 5 x 10 dot matrix)
16 Common x 40 Segment OLED Drivers
Available in C.O.B. or QFP Package PT6880 pre 1.1 Page 1 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880
Applications
Cellular Phone Data Bank/Organizer Electronic Dictionary / Translator Information Appliance P.D.A. P.O.S. Car Audio Electronic Equipment with OLED Display PT6880 pre 1.1 Page 2 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Block Diagram RESET CIRCUIT OSCILLATION CIRCUIT DISB OSC1 CLOSC2 LAT COM1 SG1 COM2 SG2 COM15 SG39 REFOUT COM16 SG40 D V16 SEGG DVR BVR VDD GND RS R/WB E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 MPU INTERFACE INPUT/ OUTPUT BUFFER INSTRUCTION REGISTER INSTRUCTION DECODER ADDRESS COUNTER 40-BIT SHIFT REGISTER 40-BIT LATCH CIRCUIT 16-BIT SHIFT REGISTER SEGMENT SIGNAL DRIVER OLED DRIVE VOLTAGE COMMON SIGNAL DRIVER DISPLAY DATA RAM (DDRAM) 80x8 BITS TIMING GENERATOR DATA REGISTER CHARACTER GENERATOR RAM (CGRAM) 64 BYTES CHARACTER GENERATOR ROM (CGROM) 9920 BITS CURSOR AND BLINK CONTROLLER PARALLEL / SERIAL CONVERTER AND ATTRIBUTE CIRCUIT BUSY FLAG 408 PT6880 pre 1.1 Page 3 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Pin Configuration 1SG 29 NC SG 28 NC SG 27 SG 26 SG 25 SG 24 SG 23 SG 22 SG 19 SG 18 SG 17 SG 16 SG 15 SG 14 SG 13 SG 12 SG 11 SG 10 SG 9 NC NC NC NC NC NC SG 8 D NC RS NC R/ WB E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VS S COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 NC NC NC NC NC NC COM 9 10 10 31 100 32 99 33 98 34 97 35 96 36 95 37 94 38 93 39 92 40 91 41 90 42 89 43 88 44 87 45 86 46 85 47 84 48 83 49 82 SG7 NC SG6 SG30 SG5 SG31 SG4 SG32 SG3 SG33 SG2 SG34 SG1 SG35 SEGG SG36 REFOUT SG37 V16 SG38 VSS SG39 VSS SG40 OSC1 V16 OSC2 COM16 BVR COM15 DVR COM14 LAT COM13 CL COM12 VDD COM11 DISB COM10 SG 21 SG 20 PT6880 pre 1.1 Page 4 Mar. 2002 Pin/Pad Description
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Pin Name I/O Description Pad/Pin No. SG40 ~ SG30 SG29, SG 28 SG27 ~ SG9 SG8 ~ SG1 O Segment Driver Output Pins 89 ~ 99 1,3 5 ~ 23 30 ~ 37 SEGG - OLED Drive Power Supply (0V) 38 REFOUT O Reference Current Output Pin 39 V16 - OLED Drive Power Supply (16V) 40, 88 VSS - Ground Pin (0V) 41, 42, 65 OSC1 I Oscillator Input Pin 43 OSC2 O Oscillator Output Pin 44 BVR I Brightness Control Input Pin 45 DVR I Precharge Time Control Input Pin 46 LAT O Latch Clock Output Pin 47 CL O Shift Clock Output Pin 48 VDD - Power Supply (2.7V to 5.5V) 49 DISB O Reset Signal Output Pin 50 D O Character Pattern Data Output Pin 51 RS I Register Select Input Pin When this pin is set to "0", it is used as an Instruction Register. When this pin is set to "1", it is used for as the Data Register. R/WB I Read/Write Control Input Pin This pin is used to select either the Write or the Read Operation. If this pin is set to "0", then the Write Function is enabled. If this pin is set to "1", then the Read function is enabled. E I Data Read/Write Start Control Pin 56 DB0 ~ DB3 I/O Low Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. These 57 ~ 60 PT6880 pre 1.1 Page 5 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 pins are not used during a 4-bit operation. DB4 ~ DB7 I/O High Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. D7 can be used as a Busy Flag. 61 ~ 64 COM1 ~ COM8 COM9 ~ COM16 O Common Driver Output Pins (see Note 1) 66 ~ 73 80 ~ 87 NC - No Connection 2, 4, 24 ~ 29, 52, 54, 74 ~ 79, 100 Note: 1. COM1 to COM16 are used as the Common Output Driver Pins. However, when the pins are not in used, the respective common signals are transformed into non-selection waveforms. For example, under a 1/8 Duty Factors, the Common Driver Output Pins -- COM9 to COM16 are not used. Common Driver Output Pins -- COM12 to COM16 are not used during a 1/11 duty factor. Therefore, the common signals represented by aforementioned Unused Common Driver Output Pins are transformed into non-selection waveforms. PT6880 pre 1.1 Page 6 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Functional Description Registers PT6880 provides two types of 8-bit registers, nam ely: Instruction Register (IR) and Data Register (DR). The register is selected using the RS Pin. When the RS pin is set to "0", the Instruction Register T ype is selected. When RS pin is set to "1", the Data Register Type is selected. Please refer to the table below. RS R/WB Operation 0 0 Instruction Register Write as an Internal Operation. 0 1 Read Busy Flag (DB7) and Address Counter (DB0 to DB6) 1 0 Data Register Write as an Internal Operation (DR to DDRAM or CGRAM) 1 1 Data Register Read as an Internal Operation (DDRAM or CGRAM to DR) INSTRUCTION REGISTER (IR) The Instruction Register is used to store the inst ruction code (i.e. Display Clear , Cursor Home and others), Display Data RAM (DDRAM) Addre ss, and the Character Generator RAM (CGRAM) Address. Instruction register can only be written from the MPU. DATA REGISTER (DR) The Data Register is used as a tem porary storag e f or data that are going to be written into the DDRAM or CGRAM as well as those data that are going to be read from the DDRAM or CGRAM. BUSY FLAG (BF) The Busy Flag is used to determ ine whether PT6880 is idle or internally operating. W hen PT6880 is performing some internal operations, the Busy Flag is set to "1". Under this condition, the no other instruction will not be accepted. When RS Pin is set to "0" and R/WB Pin is set to "1", the Busy Flag will be outputted to the DB7 pin. When PT6880 is idle or has com pleted its previous internal operation, the Busy Flag is set to "0". The next instruction can now be processed or executed. PT6880 pre 1.1 Page 7 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 ADDRESS COUNTER (AC) The address counter is used to assign the Disp lay Data RAM (DDRAM) Address and the Character Generator RAM (CGRAM) Address. W hen an Addr ess inf ormation is written into the Instruction Register (IR), this Address information is sent from the Instruction Register to the Address Counter . At the same time, the nature of the Address (either CGRAM or DDRAM) is determined by the instruction. After writing into or reading from the DDRAM or CGRAM, the Address Counter is autom atically increased or decreased by 1 (for Write or Read Function). It must be noted that when the RS pin is set to "0" and R/WB is set to "1", the contents of the Address Counter are outputted to the pins -- DB0 to DB6. DISPLAY DATA RAM (DDRAM) The Display Data RAM (DDRAM) is used to store the Display Data which is represented as 8-bit character code. The Display Data RAM supports an extended capacity of 80 x 8-bits or 80 characters. The area in the DDRAM which are not used for displa y can be used as General Data RAM. For m ore details, please refer to the sections below. The Display Data RAM Address (ADD) is set in the Address Counter as a hexadecimal. High Order Bits Low Order Bits Address Counter (hexadecimal AC6 AC5 AC4 AC3 AC2 AC1 AC0 An example of a DDRAM Address = 4E is given below. DDRAM Address: 4E AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0 PT6880 pre 1.1 Page 8 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 1-LINE DISPLAY (N=0) When the number of characters displayed is less than 80, the first character is displayed at the head position. The relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position (digit) 1 2 3 4 …………. 78 79 80 DDRAM Address (hexadecimal) 00 01 02 03 … … … … . 4D 4E 4F For example, when only 8 characters are displayed in one Display Line, the relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position 1 2 3 4 5 6 7 8 DDRAM Address 00 01 02 03 04 05 06 07 Shift Left 01 02 03 04 05 06 07 08 Shift Right 4F 00 01 02 03 04 05 06 2-LINE DISPLAY (N=1) Case 1: The Number of Characters displayed is less than 40 x 2 lines When the number of characters displayed is less than 40 x 2 lines, then the first character of the first and second lines are displayed starting from the head. It is important to note that the first line end address and the second line start address are not consecutive. Please refer the figure below. Display Position 1 2 3 4 ………. 37 38 39 40 00 01 02 03 ………. 24 25 26 27 DDRAM Address (hexadecimal) 40 41 42 43 ………. 64 65 66 67 PT6880 pre 1.1 Page 9 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 To illustrate, f or 2-line x 8 characters display , the relationship between the DDRAM address and position of the OLED panel is shown below. Display Position 1 2 3 4 5 6 7 8 00 01 02 03 04 05 06 07 DDRAM Address 40 41 42 43 44 45 46 47 01 02 03 04 05 06 07 08 Shift Left 41 42 43 44 45 46 47 48 27 00 01 02 03 04 05 06 Shift Right 67 40 41 42 43 44 45 46 Case 2: 16-Character x 2 Lines Display PT6880 can be extended to display 16 characters x 2 lines by using the 40-output extension driver . When there is a Display Shift operation, the DDRAM Address is also shifted. Please refer to the example below. Display Position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4FDDRAM Address PT6880 Display Extension Driver Display 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10Shift Left 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0EShift Right 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E PT6880 pre 1.1 Page 10 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Character Generator ROM (CGROM) The Character Generator ROM (CGROM) is used to ge nerate either 5 x 8 dots or 5 x 10 dots character patterns from 8-bit character codes. It can genera te up to two hundred eight (208) 5 x 8 dot character patterns and thirty two (32) 5 x 10 dot character patte rns. For user -defined character patterns, please contact PTC. CORRESPONDENCE BETWEEN THE CHARACTER CODES AND THE CHARACTER PATTERNS UPPER BITS 0000 LOWER BITS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM CG RAM PT6880 pre 1.1 Page 11 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 CHARACTER Generator RAM (CGRAM) The Character Generator RAM (CGRAM) is used to generate either 5 x 8 dot or 5 x 10 dot character patterns. It can generate eight 5 x 8 dot character patterns and four 5 x 10 dot character patterns. The character patterns generated by the CGRAM can be rewritten. User-defined character patterns f or the CGRAM is supported. Areas in the CGRAM that are not used for display m ay be used as the General Data RAM. RELATIONSHIP BETWEEN CGRAM ADDRESS, DDRAM CHARACTER CODE AND CGRAM CHARACTER PATTERNS (FOR 5 X 8 DOT CHARACTER PATTERN) Character Codes (DDRAM Data) CGRAM Address Character Patterns (CGRAM Data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High Low High High Low 0 0 0 * * * 1 1 1 1 0 0 0 1 * * * 1 0 0 0 1 0 1 0 * * * 1 0 0 0 1 0 1 1 * * * 1 1 1 1 0 1 0 0 * * * 1 0 1 0 0 1 0 1 * * * 1 0 0 1 0 1 1 0 * * * 1 0 0 0 1 Character Pattern 1 0 0 0 0 * 0 0 0 0 0 0 1 1 1 * * * 0 0 0 0 0 Cursor Position 0 0 0 * * * 1 0 0 0 1 0 0 1 * * * 0 1 0 1 0 0 1 0 * * * 1 1 1 1 1 0 1 1 * * * 0 0 1 0 0 1 0 0 * * * 1 1 1 1 1 1 0 1 * * * 0 0 1 0 0 1 1 0 * * * 0 0 1 0 0 Character Pattern 2 0 0 0 0 * 0 0 1 0 0 1 1 1 1 * * * 0 0 0 0 0 Cursor Position 0 0 0 * * * 0 0 1 * * * 1 0 0 * * * 1 0 1 * * * 1 1 0 * * * 0 0 0 0 * 1 1 1 1 1 1 1 1 1 * * * Notes: 1. * = Not Relevant 2. The character pattern row positions correspond to the CGRAM data bits -- 0 to 4, where bit 4 is in the left position. 3. Character Code Bits 0 to 2 correspond to the CGRAM Address Bits 3 to 5 (3 bits : 8 types) 4. If the CGRAM Data is set to "1", then the selection is displayed. If the CGRAM is set to "0", there no selection is made. 5. The CGRAM Address Bits 0 to 2 are used to define the character pattern line position. The 8th line is the cursor position and its display is formed by the logical OR with the cursor. The 8th line CGRAM data bits 0 to 4 must be set to "0". If any of the 8th line CGRAM data PT6880 pre 1.1 Page 12 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. 6. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit 3 is not relevant and will not have any effect on the character display. Because of this, the first Character Pattern shown above ( R ) can be displayed when the Character Code is 00H or 08H. RELATIONSHIP BETWEEN CGRAM ADDRESS, DDRAM CHARACTER CODE AND CGRAM CHARACTER PATTERNS (FOR 5 X10 DOT CHARACTER PATTERN) Character Codes (DDRAM Data) CGRAM Address Character Patterns (CGRAM Data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High Low High Low High Low 0 0 0 0 * * * 0 0 0 0 0 0 0 0 1 * * * 0 0 0 0 0 0 0 1 0 * * * 1 0 1 1 0 0 0 1 1 * * * 1 1 0 0 1 0 1 0 0 * * * 1 0 0 0 1 0 1 0 1 * * * 1 0 0 0 1 0 1 1 0 * * * 1 1 1 1 0 0 1 1 1 * * * 1 0 0 0 0 1 0 0 0 * * * 1 0 0 0 0 1 0 0 1 * * * 1 0 0 0 0 Character Pattern 0 0 0 0 * 0 0 * 0 0 1 0 1 0 * * * 0 0 0 0 0 Cursor Position 0 0 0 0 * 1 1 * 1 1 Notes: 1. * = Not Relevant 2. The character pattern row positions corre spond to the CGRAM data bits -- 0 to 4, where bit 4 is in the left position. 3. Character Code Bits 1 and 2 correspond to the CGRAM Address Bits -- 4 and 5 respectively (2 bits : 4 types) 4. If the CGRAM Data is set to "1", then the selection is displayed. If the CGRAM is set to "0", there no selection is made. 5. The CGRAM Address Bits 0 to 3 are used to define the character pattern line position. The 11th line is the cursor position and its display is formed by the logical OR with the cursor. PT6880 pre 1.1 Page 13 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 The 11th line CGRAM data bits 0 to 4 must be set to "0". If any of the 11th line CGRAM data bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. 6. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit -- 0 and 3 are not relevant and will not have any ef fect on the character display . Because of this, the Character Pattern shown above ( P ) can be displayed when the Character Code is 00H, 01H, 08H or 09H. Timing Generation Circuit The timing signals for the internal circuit operations (i.e. DDRAM, CGRAM, and CGROM) are generated by the Timing Generation Circuit. The timing signals for the MPU internal operation and the RAM Read for Display are generated separately in order to prev ent one from interfering with the other. This means that, for example, when the data is being written into the DDRAM, there will be no unwanted interference such as flickering in areas other than the display area. OLED Driver Circuit PT6880 provides 16 Com mon Drivers and 40 Segm ent Driver Outputs. W hen a character font and the number of lines to be displayed have been selected, the corresponding Common Drivers output the drive waveform automatically. A non-selection waveform will be outputted by the rest of the Common Drivers. Serial data transm ission always begins with the disp lay data character pattern corresponding to the last Display Data RAM (DDRAM) Address. The serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register. Thus, PT6880 drives from the head display. Cursor / Blink Control Circuit The cursor or character blinking is generated by the Cursor / Blink Control Circuit.The cursor or the blinking will appear with the dig it located at the Display Data RAM (DDRAM) Address Set in the Address Counter (AC). AC6 AC5 AC4 AC3 AC2 AC1 AC0 Address Counter 0 0 0 1 0 0 0 CASE 1: FOR 1-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM PT6880 pre 1.1 Page 14 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Address 08H. Display Position 1 2 3 4 5 6 7 8 9 10 11 DDRAM Address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A Cursor Position Note: The cursor or blinking appears when th e Address Counter (AC) selects the Character Generator RAM (CGRAM). W hen the AC sel ects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position. CASE 2: FOR 2-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM Address 08H. Display Position 1 2 3 4 5 6 7 8 9 10 11 00 01 02 03 04 05 06 07 08 09 0A DDRAM Address (hexadecimal) 40 41 42 43 44 45 46 47 48 49 4A Cursor Position Note: The cursor or blinking appears when th e Address Counter (AC) selects the Character Generator RAM (CGRAM). W hen the AC sel ects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position. Reset Function INTERNAL RESET CIRCUIT INITIALIZATION When power is turned ON, PT6880 is initialized autom atically by an internal reset circuit. The following instructions are executed during the initialization. 1. Display Clear 2. Function Set: DL = "1" : 8-Bit Interface Data N = "0" : 1-Line Display F = "0": 5 x 8 Dot Character Font 3. Display ON/OFF Control: D = "0" : Display OFF PT6880 pre 1.1 Page 15 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 C = "0" : Cursor OFF B = "0" : Blinking OFF 4. Entry Mode Set: I/D = "1" : Increment by 1 S = "0" : No Shift The Busy Flag (BF) is in a busy state until the in itialization is completed (BF="1"). The busy state will be in effect 10 ms after the VDD rises to 4.5 Volts. Please note that in order for the initialization by internal reset circuit to be successf ul, the electrical characteristic conditions listed in the Electrical Characteristics Section m ust be com plied with. Otherwise, such initialization must be performed by instruction from the MPU. Instructions PT6880's Instruction Register (IR) and Data Register (DR) are the only registers that can be controlled by the MPU. Prior to the com mencement of it internal operation, PT6880 tem porarily stores the control information to its Instruction Register (IR) and Data Register (DR) in order to easily f acilitate interface with various types of MPU. The internal operati on of the PT6880 are determ ined by the signals (RS, R/WB, DB0 to DB7) that are sent from the MPU. These signals are categorized into 4 instructions types, namely: 1. Function Setting Instructions (i.e. Display, Format, Data Length etc.) 2. Internal RAM Address Setting Instructions 3. Data Transfer with Internal RAM Instructions 4. Miscellaneous Function Instructions The generally used instructions are those that execute data transfers with the internal RAM. However , when the internal RAM addresses are auto increm ented/decremented by 1 after each Data W rite, the program load of the MPU is lightened. The Display Shift Instruction can be executed at the same time as the Display Data W rite, thereby m inimizing syst em developm ent tim e with m aximum program ming efficiency. When an instruction is being executed for an in ternal operation, only the Busy Flag/Address Read Instruction can be perform ed. The other instructions are not valid. It should be noted that during the execution of an instruction, the Busy Flag is set to "1". The Busy Flag is set to "0" when the instructions are can be accepted and executed. Therefore, the Busy Flag should be checked to make certain that BF = "0" before sending another instruction from the MPU. If not, the time between the first instruction and the next instruction is longer than the time it takes to execute the instruction itself. Instruction Code
Description
Max. Execution Time when PT6880 pre 1.1 Page 16 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 R S R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 fsp or fosc = 250kHz Clear Display 0 0 0 0 0 0 0 0 0 1 Clears entire display. Sets DDRAM Address 0 into the Address Counter Return Home 0 0 0 0 0 0 0 0 1 x Sets DDRAM Address 0 into the Address Counter. Returns shifted display to original position. DDRAM contents remain unchanged. 1.52ms Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction and specifies display shift. (These operations are performed during data write and read.) 37us Display ON/OFF Control 0 0 0 0 0 0 1 D C B Sets entire Display (D) ON/OFF. Sets Cursor (C) ON/OFF. Sets Blinking(B) of Cursor Position Character. 37us Cursor/ Display Shift 0 0 0 0 0 1 S/C R/L x x Moves cursor & shifts display without changing DDRAM contents. 37us Function Set 0 0 0 0 1 DL N F x x Sets interface data length (DL). Sets number of display lines (N). Sets Character Font (F). 37us Set CGRAM Address 0 0 0 1 ACG ACG ACG ACG ACG ACG Sets CGRAM Address. CGRAM data is sent and received after this setting. 37us Set DDRAM Address 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM Address. The DDRAM data Is sent and received after this setting. 37us Read Busy Flag & Address 0 1 BF AC AC AC AC AC AC AC Reads Busy Flag (BF) indicating that internal operation is being performed. Reads Address Counter contents. 0us Write data into the CGRAM or DDRAM 1 0 Write Data Writes data into the CGRAM or DDRAM 37us tADD=4us* Read Data from the CGRAM 1 1 Read Data Read data from the CGRAM or DDRAM 37us tADD=4us* PT6880 pre 1.1 Page 17 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 or DDRAM Notes: 1. x = Not Relevant 2. * = After the CGRAM/DDRAM Read or W rite Instruction has been executed, the RAM Address Counter is incremented or decremented by 1. After the Busy Flag is turned OFF, the RAM Address is updated. 3. I/D = Increment / Decrement Bit I/D = "1" : Increment I/D = "0" : Decrement 4. S = Shift Entire Display Control Bit 5. BF = Busy Flag BF = "1" : Internal Operating in Progress BF ="0" : No Internal Operation is being executed, next instruction can be accepted. 6. R/L = Shift Right / Left R/L = "1" : Shift to the Right R/L = "0" : Shift to the Left 7. S/C = Display Shift / Cursor Move S/C = "1" : Display Shift S/C = "0" : Cursor Move 8. DDRAM = Display Data RAM 9. CGRAM = Character Generator RAM 10. ACG =CGRAM Address 11. ADD = Address Counter Address (corresponds to cursor address) 12. AC = Address Counter (used for DDRAM and CGRAM Addresses) 13. F = Character Pattern Mode F = "1" : 5 x 10 dots F = "0" : 5 x 8 dots 14. N = Number of Lines Displayed N = "1" : 2 -Line Display N = "0" : 1-Line Display 15. * = The tim e it takes to execute an instructi on changes when the frequency changes. T o illustrate an example: When fcp of fosc = 250 kHz, then the execution time = 37us x 270/250 = 40us 16. tADD is the tim e period starting when the Busy Flag is turned OFF up to the tim e the Address Counter is updated. Please refer to the diagram below. PT6880 pre 1.1 Page 18 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 BUSY STATE BUSY SIGNAL (DB7) tADD AA +1ADDRESS COUNTER (DB0 TO DB6) where 1. tADD depends on the operati on frequency and m ay be calculated using the following equation tADD = 1.5 / (fcp) seconds or tADD = 1.5 /(fosc) seconds INSTRUCTION DESCRIPTION Clear Display Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 This instruction is used to clear the Display Write Space 20H in all DDRAM Addresses. That is, the character pattern for the Character Code 20H m ust be a BLANK pattern. It then sets the DDRAM Address 0 into the Address Counter and reverts the display to its original state (if the display has been shifted). The display will be cleared and the cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display. Under the Entry Mode, this instruction also sets the I/D to 1 (Increment Mode). The S Bit of the Entry Mode does not change. Return Home Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 * Note: * = Not Relevant This instruction is used to set the DDRAM Address 0 into the Address Counter and revert the display to its original status (if the display has been shifted). The DDRAM contents do not change. The cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display. PT6880 pre 1.1 Page 19 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Entry Mode Set Instruction The Entry Mode Set Instruction has two controlling bits: I/D and S. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S I/D is the Increment / Decrement Bit. When I/D is set to "1". the DDRAM Address is incremented by "1" when a character code is written into or read from the DDRAM. An increment of 1 will move the cursor or blinking one step to the right. When the I/D is set to "0", the DDRAM is decremented by 1 when a character code is written into or read from the DDRAM. An decrement of 1 will move the cursor or blinking one step to the left. S : Shift Entire Display Control Bit This bit is used to shift the entire display. When S is set to "1", the entire display is shifted to the right (when I/D ="0") or left (when I/D ="1"). The display does not shift when reading from the DDRAM, writing into or reading from the CGRAM. When S is set to "0", the display is not shifted. Display ON / OFF Control Instruction The Display On / OFF Instruction is used to turn the display ON or OFF. The controlling bits are D, C and B. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 D C B D : Display ON /OFF Bit When D is set to "1", the display is turned ON. When D is set to "0", the display is turned OFF and the display data is stored in the DDRAM. The display data can be instantly displayed by setting D to "1". C : Cursor Display Control Bit When C is set to "1", the cursor is displayed. In a 5 x 8 dot character font, the cursor is displayed via the 5 dots in the 8th line. In a 5 x 10 dot character font , it is displayed via 5 dots in the 11th line. When C is set to "0", the cursor display is disabled. PT6880 pre 1.1 Page 20 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 During a Display Data Write, the function of the I/D and others will not be altered even if the cursor is not present. Please refer to the figure below. 5 x 8 Dot Character Font 5 x 10 Dot Character Font Cursor Æ Å Cursor B : Blinking Control Bit When B is set to ' 1", the character specified by the cursor blinks. The blinking feature is displayed by switching between the blank dots a nd the displayed character at a speed of 409.6ms intervals when the fcp or fosc is 250kHz. Please refer to the figure below. ÅÆ Figure 1 Figure 2 Note: Figure 1 and 2 are alternately displayed The cursor and the blinking can be set to disp lay at the sam e time. The blinking frequency depends on the fosc or the reciprocal of fcp. To illustrate, when fcp =270kHz, then, the blinking frequency = 409.6 x 250/270 = 379.2ms PT6880 pre 1.1 Page 21 Mar. 2002 Cursor / Display Shift Instruction
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 This instruction is used to shift the cursor or di splay position to the left or right without writing or reading the Display Data. This function is used to correct or search the display. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L * * S/C R/L Shift Function 0 0 Shifts the cursor position to the left. (AC is decremented by 1). 0 1 Shifts cursor position to the right. (AC incremented by 1). 1 0 Shifts entire display to the left. The cursor follows the display shift. 1 1 Shifts the entire display to the right. The cursor follows the display shift. In a 2-line Display, the cursor moves to the second line when it passes the 40th digit of the first line. The first and second line displays will shift at the same time. When the displayed data is shifted repeatedly , each line m oves only horizontally. The second line display does not shift into the first line position. The Address Counter (AC) contents will not change if the only action performed is a Display Shift. Function Set Instruction The Function Set Instruction has three controlling 3 bits, namely: DL, N and F. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL N F * * PT6880 pre 1.1 Page 22 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 DL : Interface Data Length Control Bit This is used to set the interface data length. When DL is set to "1", the data is sent or received in 8-bit length via the DB0 to DB7 (for an 8-Bit Data Transfer). When DL is set to "0", the data is sent or received in 4-bit length via DB4 to DB7 ( for a 4-Bit Data Transfer). When the 4-bit data length is selected, the data must be sent or received twice. N : Number of Display Line This is used to set the num ber of display lines. When N="1", the 2-line display is selected. When N is set to "0", the 1-line display is selected. F : Character Font Set This is used to set the character font set. W hen F is set to "0", the 5 x 8 dot character font is selected. When F is set to "1", the 5 x 10 dot character font is selected. It must be noted that the character font setting must be performed at the head of the program before executing any instructions other than the Busy Flag and Address Instruction. Otherwise, the Function Set Instruction cannot be executed unless the interface data length is changed. Set CGRAM Address Instruction This instruction is used to set the CGRAM A ddress binary AAAAAA into the Address Counter . Data is then written to or read from the MPU for CGRAM. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 ACG ACG ACG ACG ACG ACG Note: ACG is the CGRAM Address Set DDRAM Address Instruction This instruction is used to set the DDRAM A ddress binary AAAAAAA into the Address Counter . The data is written to or read from the MPU for the DDRAM. If 1-line display is selected (N="0"), then AAAAAAA can be 00H to 4FH. When the 2-line display is selected, then AAAAAAA can be 00H to 27H for the first line and 40H to 67H for the second line. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 ADD ADD ADD ADD ADD ADD ADD ÅHigher Order Bits Lower Order Bits Æ Note: ADD = DDRAM Address PT6880 pre 1.1 Page 23 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Read Busy Flag and Address Instruction This instruction is used to read the Busy Flag (BF) to indicate if PT6880 is internally operating on a previously received instruction. If BF is set to "1", then the internal operation is in progress and the next instruction will not be accepted. If the BF is set to "0", then the previously received instruction has been executed and the next instruction can be accepted and processed. It is im portant to check the BF status before proceeding to the next wr ite operation. The value of the Address Counter in binary AAAAAAA is simultaneously read out. This Address Counter is used by both the CGRAM and the DDRAM and its value is determined by the previous instruction. The contents of the address are the same as for the instructions -- Set CGRAM Address and Set DDRAM Address. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BF AC AC AC AC AC AC AC ÅHigher Order Bits Lower Order Bits Æ Notes: 1. BF= Busy Flag 2. AC = Address Counter Write Data to CGRAM / DDRAM Instruction This instruction writes 8-bit binary data -- DDDDDDDD to the CGRAM or the DDRAM. The previous CGRAM or DDRAM Address setting determ ines whether a data is to be written into the CGRAM or the DDRAM. After the write process is com pleted, the address is autom atically incremented or decremented by 1 in accordance with the Entry Mode instruction. It m ust be noted that the Entry Mode instruction also determines the Display Shift. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D D D D D D D D ÅHigher Order Bits Lower Order Bits Æ Read Data from the CGRAM or DDRAM Instruction This instructions reads the 8-bit binary data -- DDDDDDDD from the CGRAM or the DDRAM. The Set CGRAM Address or Set DDRAM Address Set Instruction m ust be executed before this instruction can be performed, otherwise, the first Read Data will not be valid. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D D D D D D D D ÅHigher Order Bits Lower Order Bits Æ When the Read Instruction is executed in series, the next address data is norm ally read from the Second Read. There is no need for the Address Set Instruction to be perform ed before this Read PT6880 pre 1.1 Page 24 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 instruction when using the Cursor Shif t Instruction to shift the cursor (Reading the DDRAM). The Cursor Shift Instruction has the same operation as that of the Set the DDRAM Address Instruction. After a Read instruction has been executed, the Entry Mode is autom atically increm ented or decremented by 1 . It m ust be noted that regardless of the Entry Mode, the Display Shift is not executed. After the W rite instructions to either the CGRAM or DDRAM has been perf ormed, the Address Counter is autom atically increased or decreased by 1. The RAM data selected by the Address Counter cannot be read out at this time even if the Read Instructions are executed. Therefore, in order to correctly read the data, the following procedure has suggested: 1. Execute the Address Set or Cursor Shift (only with DDRAM) Instruction 2. Just before reading the desired data, execute the Read Instruction from the second time the Read Instruction has been sent. MPU Interface PT6880 can be configured to interface with either the 4-bit or 8-bit MPU via the DB0 to DB7 pins. 8-BIT MPU INTERFACE When PT6880 interfaces with an 8-bit MPU, DB0 to DB7 are used. The 8-bit data transfer starts from the four high order bits --DB4 to DB7 followed by the four low order bits -- DB0 to DB3. An example of a Busy Flag Check Timing in an 8-Bit MPU Interface is given in the diagram below. PT6880 pre 1.1 Page 25 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 4-BIT MPU INTERFACE PT6880 can be configured to interface with a 4-bit MPU and is selected via a program. If the I/O port of the 4-Bit MPU from which PT6880 is connected to, is capable of transferring 8 bits, then an 8-bit data transf er operation is executed. Otherwise, tw o 4-bit data transfer operations are needed to satisfy one complete data transfer. Under the 4-bit data transfer, DB4 to DB7 are used as bus lines. DB0 to DB3 are disabled. The data transfer between PT6880 and MPU is com pleted after two 4-bit data have been transferred. The Busy Flag must be checked (one instruction) after completion of the data transfer (that is, 4-bit data has been transferred twice.). The Busy Flag must be checked after two 4-bits data transfer has been completed. Please refer to the diagram below for a 4-bit data transfer timing sequence. Where: 1. IR7 = Instruction Bit 7 2. IR3 = Instruction Bit 3 3. AC3 = Address Counter 3 From the above timing diagram, it is important to note that the Busy Flag Check and the data transfer are both executed twice. PT6880 pre 1.1 Page 26 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 OLED Interface PT6880 supports two display types, namely: 5 x 8 dots and 5 x 10 dots character fonts. Each of these type includes a cursor display. Up to 2 lines may be displayed in a 5x 8 dot character font type and 1 line for a 5 x 10 dots character font type. The number of lines that can be displayed as well as the type of font can be selected by using the software program. Please refer to the table below Number of Display Line Character Font Type Number of Common Signals Duty Factor 1 5 x 8 dots + cursor 8 1/8 1 5 x 10 dots + cursor 11 1/11 2 5 x 8 dots + cursor 16 1/16 As shown in the table above, three types of com mon signals are available. An exam ple of each configuration is shown in the exam ples below. It should be noted that every 5 segm ent signal lines can display one digit, therefore, PT6880 can display up to 8 digits in a 1-line display and 16 digits in a 2-line display. Example 1: An OLED and PT6880 interface with a 5 x 10 dot, 8-character x 1-line display at 1/1 1 duty cycle is given below. PT6880 pre 1.1 Page 27 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Example 2: OLED and PT6880 connection with 5 x 8 dots, 8-character x 1-line display, at 1/8 duty cycle. Example 3: OLED and PT6880 Connec tion when 5 x 8 dots, 8-character x 2-line display at 1/16 duty cycle. COM1 COM8 COM9 SG1 SG2 SG39 COM16 SG40 OLED Display Panel PT6880 PT6880 pre 1.1 Page 28 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Absolute Maximum Rating (Unless otherwise stated, Ta=25 oC) Parameter Symbol Rating Unit Power Supply Voltage 1 VDD-GND -0.3 to +5.5 V Power Supply Voltage 2 V16 -SEGG -0.3 to +18.0 V Input Voltage Vt -0.3 to VDD+0.3 V Operating Temperature Topr -30 to +85 oC Storage Temperature Tstg -55 to +125 oC (Unless otherwise stated, Ta=25oC, V16=16V) Parameter Symbol Condition Min. Typ. Max. Unit VDD All input pins and I/O pins except OSC1 VDD=3V 0.7VDD - VDD V VDD High Level Input Voltage 1 VIH1 All input pins and I/O pins except OSC1 VDD=5V 2.2 - VDD V All input pins and I/O pins except OSC1 VDD=3V -0.3 - 0.55 V Low Level Input Voltage 1 VIL1 All input pins and I/O pins except OSC1 VDD=5V -0.3 - 0.60 V OSC1 VDD=3V 0.7VDD - VDD V High Level Input Voltage 2 VIH2 OSC1 VDD=5V VDD -1.0 - VDD V OSC1 VDD=3V - - 0.2 VDD V Low Level Input Voltage 2 VIL2 OSC1 VDD=5V - - 1.0 V Applies to I/O Pins, DB0 to DB7, VDD=3V, IOH=-0.1mA 0.75VDD - - V High Level Output Voltage 1 VOH1 Applies to I/O Pins, DB0 to DB7, VDD=4.5-5.5V, IOH=-0.205mA 2.4 - - V PT6880 pre 1.1 Page 29 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Applies to I/O Pins, DB0 to DB7 VDD=3V, IOL=0.1mA - - 0.2VDD V Low Level Output Voltage 1 VOL1 Applies to I/O Pins, DB0 to DB7 VDD=4.5-5.5V, IOL=1.2mA - - 0.1VDD V All Output Pins except DB0 to DB7. VDD=3V, IOH=0.04mA 0.8VDD - - V High Level Output Voltage 2 VOH2 All Output Pins except DB0 to DB7. VDD=4.5-5.5V, IOH=0.04mA 0.9VDD - - V All Output Pins except DB0 to DB7. VDD=3V, IOL=0.04mA - - 0.2VDD V Low Level Output Voltage 2 VOL2 All Output Pins except DB0 to DB7. VDD=4.5-5.5V, IOL=0.04mA - - 0.1VDD V VDD=3V, VIN= 0 to VDD -1 - 1 uA Input Leakage Current (see Note 1) ILI VDD=5V, VIN= 0 to VDD -1 - 1 uA DB0 to DB7, RS, R/WB VIN=3.0V 10 50 120 uA Pull-up MOS Current -Ip DB0 to DB7, RS, R/WB VIN=5.0V 50 125 250 uA Rf Oscillation, External Clock VDD=3V, fosc=270kHz - - 1 mAOperating Current (see Notes 2) Icc Rf Oscillation, External Clock VDD=5V, fosc=270kHz - - 1 mA V16 - SEGG VDD=3V 9.0 - 16.0 V OLED Voltage VOLED V16 - SEGG VDD=5V 9.0 - 16.0 V High Level Segment Output Current ISEGOH VSEGOH=14V -30 - -300 uA High Level Segment Output Current Tolerance ITOL1* ISEGOH=-300uA - - ±5 % High Level Segment Output Current Tolerance ITOL2* ISEGOH=-300uA - - +1 % Low level Common Sink Current ICOMOL VCOMOL=0.4V 15 - - mA PT6880 pre 1.1 Page 30 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Notes: 1. Current flowing through pull-up MOSs, excluding output drive MOS. 2. Input/Output current is not included. W hen the input is at an interm ediate level with the CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. (Unless otherwise specified, Ta = 25oC, V16=16V) Parameter Symbol Condition Min. Typ. Max. Unit Applies only to external clock operation. (see Note 1), VDD=3V 125 250 350 kHz External Clock Frequency fcp Applies only to external clock operation. (see Note 1), VDD=5V 125 250 350 kHz Applies only to external clock operation. (see Note 1), VDD=3V - - 0.2 us External Clock Rise Time trcp Applies only to external clock operation. (see Note 1), VDD=5V - - 0.2 us Applies only to external clock operation. (see Note 1), VDD=3V - - 0.2 us External Clock Fall Time tfcp Applies only to external clock operation. (see Note 1), VDD=5V - - 0.2 us Rf=75 kΩ, (see Note 2) VDD=3V 190 270 350 kHzClock Oscillation Frequency fosc Rf=91 kΩ, (see Note 2) VDD=5V 190 270 350 kHz Notes: 1. These param eters apply only to external clock operation. Please refer to the diagram below. PT6880 pre 1.1 Page 31 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 2. This param eter applies only to the internal oscillation operation using an oscillation resistor Rf. Please refer to the diagram below. When VDD=5V, Rf= 91 kΩ + 2% The values of the Oscillation Frequency depend on the capacitance of the pins -- OS C1 and OSC2 -therefore, the wiring length of these puns must be minimized. Bus Timing Characteristics (Unless otherwise specified, Ta = -20 to +75oC, VDD=5V, V16=16V) Write Operation Timing Characteristics Parameter Symbol Condition Min. Typ. Max. Unit VDD=3V 1000 - - ns Enable Cycle Time tcycE VDD=5V 500 - - ns VDD=3V 450 - - ns Enable Pulse Width (High Level) PWEH VDD=5V 230 - - ns VDD=3V - - 25 ns Enable Rise/ Fall Time tEf, tEr VDD=5V - - 20 ns VDD=3V 60 - - ns Address Set-up Time (RS, R/WB to E) tAS VDD=5V 40 - - ns VDD=3V 20 - - ns Address Hold Time tAH VDD=5V 10 - - ns VDD=3V 195 - - ns Data Set-up Time tDSW VDD=5V 80 - - ns VDD=3V 10 - - ns Data Hold Time tH VDD=5V 10 - - ns PT6880 pre 1.1 Page 32 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Write Operation Timing Diagram VIH1 VIH1 VIH1VIH1 tcycE VIL1 VIL1 tEf tEr VIL1VIL1 VIL1VIL1 VIH1VIH1 VIL1 VIL1 VIL1 RS R/WB E DB0 ~ DB7 tAS tAH tAH tDSW tH PWEH VALID DATA PT6880 pre 1.1 Page 33 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Read Operation Timing Characteristics Parameter Symbol Condition Min. Typ. Max. Unit VDD=3V 1000 - - ns Enable Cycle Time tcycE VDD=5V 500 - - ns VDD=3V 450 - - ns Enable Pulse Width (High Level) PWEH VDD=5V 230 - - ns VDD=3V - - 25 ns Enable Rise/ Fall Time tEf, tEr VDD=5V - - 20 ns VDD=3V 60 - - ns Address Set-up Time (RS, R/WB to E) tAS VDD=5V 40 - - ns VDD=3V 20 - - ns Address Hold Time tAH VDD=5V 10 - - ns VDD=3V - - 360 ns Data Delay Time tDDR VDD=5V - - 160 ns VDD=3V 5 - - ns Data Hold Time tDHR VDD=5V 5 - - ns Read Operation Timing Diagram VIH1 VIH1 VIH1VIH1 tcycE VIL1 VIL1 tEf tEr VIL1VIL1 VOL1VOL1 * VOH1VOH1 VIL1 VIL1 VIL1 RS R/WB E DB0 ~ DB7 tAS tAH tAH tDHR tDDR PWEH VALID DATA Note: * = VOL1 is assumed to be 0.8V at 2MHz Operation. PT6880 pre 1.1 Page 34 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Interface Timing Characteristics with External Driver Parameter Symbol Condition Min. Typ. Max. Unit VDD=3V 800 - - ns High Level Clock Pulse Width tCWH VDD=5V 800 - - ns VDD=3V 800 - - ns Low Level Clock Pulse Width tCWL VDD=5V 800 - - ns VDD=3V 500 - - ns Clock Set-up Time tCSU VDD=5V 500 - - ns VDD=3V 300 - - ns Data Set-up Time tSU VDD=5V 300 - - ns VDD=3V 300 - - ns Data Hold Time tDH VDD=5V 300 - - ns VDD=3V - - 200 ns Clock Rise / Fall Time tct VDD=5V - - 100 ns Interface Timing with External Driver Diagram VOH2 VOH2 VOH2 VOH2 tct VOL2 VOL2 VOL2 tCWH tCWH tCWL tct tSU tCSU tDH LAT CL D PT6880 pre 1.1 Page 35 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Power Supply Condition for Internal Reset Circuit Parameter Symbol Condition Min. Typ. Max. Unit VDD=3V 0.1 - 10 ms Power Supply Rise Time trCC VDD=5V 0.1 - 10 ms VDD=3V 1 - - ms Power Supply OFF Time tOFF VDD=5V 1 - - ms Internal Power Supply Reset Timing Diagram Notes: 1. tOFF compensates for the power oscillation period caused by the momentary power supply oscillations. 2. Specified at 4.5V for a 5-Volt operation and at 2.7 for a 3-Volt operation. 3. If 4.5V is not reached during the 5-Volt operation, the internal reset circuit will not operate normally. Under this condition, PT6880 must be initialized using the instructions. PT6880 pre 1.1 Page 36 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Application Circuit COM1 COM2 COM15 COM16 O39 O40 O78 O79 O80 D LAT CL DISB REFOUT DI LAT CL DISB BVR REFOUT BVR DVR SEGG DVR SEGG SHL OSC1 OSC2 E R/WB RS PT6880 PT6800 OLED PANEL MCU DB0 DB1 DB6 DB7 PT6880 pre 1.1 Page 37 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880
Package Information
100 Pins, QFP Package (Body Size: 20mm x 14mm , Pitch:0.65mm) -C- SEATING PLA NE S L 0.25mm GAUGE PLANE -D- D E -A- -B- -H- e b A2 A1 A c L1 PT6880 pre 1.1 Page 38 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Symbol Min. Nom. Max c 0.11 0.23 L 0.73 0.88 1.03 L1 1.60 BSC A 3.40 A1 0.25 0.50 A2 2.50 2.70 2.90 b 0.22 0.40 D 23.20 BASIC D1 20.00 BASIC E 17.20 BASIC E1 14.00 BASIC e 0.65 BASIC S 0.2 - - R1 0.13 - - R2 0.13 - 0.30 θ 0o - 7o θ1 0o - - θ2 5o - 16o θ3 5o - 16o Notes: 1. All dimensioning and tolerancing dimension conform to ASME Y14.5M-19942. 2. Dimensions “D1” and “E1” do not include mold protrusion, allowable protrusion is 0.25 mm per side. 3. Regardless of the relative size of the upper and lower body sections, dimensions “D1” and “E1” are determined at the largest feature of the body exclusive of mold flash and gate burrs but including any mismatch between the upper and lower sections of the molded body. 4. Controlling Dimensions: Millimeters 5. Dimension “b” do not include dam bar protrusion. The dam bar protrusion(s) shall not cause the lead width to exceed “B” maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 6. Refer to JEDEC MS-022 Variation GC-1 JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. PT6880 pre 1.1 Page 39 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Pad Information Pad Configuration SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 V16 SG40 COM16 COM15 COM14 COM13 COM12 COM10 COM11 COM9 SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SEGG REFOUT V16 VSS VSS OSC1 OSC2 BVR DVR6 LAT CL VDD DISB D RS R/WB E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 chip size: 2778*3128 pad size: 90*90 ptich size: 120 P-Substrate:VSS unit: µm PT6880 pre 1.1 Page 40 Mar. 2002
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 Pad Location * * * PAD # NAME Location * * * 1 SG(29) [ 105.900, 3049.400 ] 2 NC 3 SG(28) [ 50.000, 2821.300 ] 4 NC 5 SG(27) [ 50.000, 2701.300 ] 6 SG(26) [ 50.000, 2581.300 ] 7 SG(25) [ 50.000, 2461.300 ] 8 SG(24) [ 50.000, 2341.300 ] 9 SG(23) [ 50.000, 2221.300 ] 10 SG(22) [ 50.000, 2101.300 ] 11 SG(21) [ 50.000, 1981.300 ] 12 SG(20) [ 50.000, 1861.300 ] 13 SG(19) [ 50.000, 1741.300 ] 14 SG(18) [ 50.000, 1625.600 ] 15 SG(17) [ 50.000, 1475.600 ] 16 SG(16) [ 50.000, 1325.600 ] 17 SG(15) [ 50.000, 1175.600 ] 18 SG(14) [ 50.000, 1025.600 ] 19 SG(13) [ 50.000, 875.600 ] 20 SG(12) [ 50.000, 725.600 ] 21 SG(11) [ 50.000, 575.600 ] 22 SG(10) [ 50.000, 425.600 ] 23 SG(9) [ 50.000, 275.600 ] 24 NC 25 NC 26 NC 27 NC 28 NC 29 NC 31 SG(7) [ 171.300, 50.000 ] 32 SG(6) [ 292.000, 50.000 ] 33 SG(5) [ 412.000, 50.000 ] 34 SG(4) [ 532.000, 50.000 ] 35 SG(3) [ 652.000, 50.000 ] 36 SG(2) [ 772.000, 50.000 ] 37 SG(1) [ 892.000, 50.000 ] 38 SEGG [ 1012.014, 50.000 ] 39 REFOUT [ 1153.128, 50.000 ] 40 V16 [ 1282.214, 50.000 ] 41 VSS [ 1402.200, 50.000 ] 42 VSS [ 1522.200, 50.000 ] 43 OSC1 [ 1642.200, 50.000 ] 44 OSC2 [ 1762.200, 50.000 ] 45 BVR [ 1882.200, 50.000 ] 46 DVR [ 2002.200, 50.000 ] PT6880 pre 1.1 Page 41 Mar. 2002 47 LAT [ 2122.200, 50.000 ]
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw OLED Driver/Controller IC Preliminary PT6880 48 CL [ 2242.200, 50.000 ] 49 VDD [ 2362.200, 50.000 ] 50 DISB [ 2482.200, 50.000 ] 51 D [ 2699.200, 90.500 ] 52 NC 53 RS [ 2699.200, 210.500 ] 54 NC 55 R/WB [ 2699.200, 330.500 ] 56 E [ 2699.200, 450.500 ] 57 DB(0) [ 2699.200, 570.500 ] 58 DB(1) [ 2699.200, 690.500 ] 59 DB(2) [ 2699.200, 810.500 ] 60 DB(3) [ 2699.200, 930.500 ] 61 DB(4) [ 2699.200, 1050.500 ] 62 DB(5) [ 2699.200, 1170.500 ] 63 DB(6) [ 2699.200, 1290.500 ] 64 DB(7) [ 2699.200, 1410.500 ] 65 VSS [ 2699.200, 1537.900 ] 66 COM(1) [ 2699.200, 1921.000 ] 67 COM(2) [ 2699.200, 2041.000 ] 68 COM(3) [ 2699.200, 2161.000 ] 69 COM(4) [ 2699.200, 2281.000 ] 70 COM(5) [ 2699.200, 2401.000 ] 71 COM(6) [ 2699.200, 2521.000 ] 72 COM(7) [ 2699.200, 2641.000 ] 73 COM(8) [ 2699.200, 2761.000 ] 74 NC 75 NC 76 NC 77 NC 78 NC 79 NC 80 COM(9) [ 2690.800, 3049.400 ] 81 COM(10) [ 2570.800, 3049.400 ] 82 COM(11) [ 2380.800, 3049.400 ] 83 COM(12) [ 2240.800, 3049.400 ] 84 COM(13) [ 2100.800, 3049.400 ] 85 COM(14) [ 1960.800, 3049.400 ] 86 COM(15) [ 1820.800, 3049.400 ] 87 COM(16) [ 1680.800, 3049.400 ] 88 V16 [ 1560.800, 3049.400 ] 89 SG(40) [ 1440.800, 3049.400 ] 90 SG(39) [ 1320.800, 3049.400 ] 91 SG(38) [ 1185.900, 3049.400 ] 92 SG(37) [ 1065.900, 3049.400 ] 93 SG(36) [ 945.900, 3049.400 ] 94 SG(35) [ 825.900, 3049.400 ] 95 SG(34) [ 705.900, 3049.400 ] 96 SG(33) [ 585.900, 3049.400 ] 97 SG(32) [ 465.900, 3049.400 ] 98 SG(31) [ 345.900, 3049.400 ] 99 SG(30) [ 225.900, 3049.400 ] 100 NC PT6880 pre 1.1 Page 42 Mar. 2002