PT542-1 BOURNS | Alldatasheet
Document overview
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Technical content
Features
■ For use with Globespan ADSL chipset ■ Excellent Total Harmonic Distortion (THD) Performance ■ Exceeds standards for ANSI and ETSI ■ Isolation voltages up to 2000 Vrms ■ Designed to meet UL1950 and EN60950 supplementary insulation requirements for operating voltages up to 250 Vrms ■ Operating temperature -40 °C to +85 °C ■ Lead free version available (see How to Order) ■ Lead free versions are RoHS compliant*
Applications
■ ADSL - Globespan Electrical Specifications @ 25 °C Turns OCL Primary DCR @ Ratio (1-4) with Leakage (1-3), (2-4), Isolation Insertion Longitudinal Part Chip-Line (2-3) shorted Inductance (10-8), (9-7) Voltage Loss Balance Number ( ±2 %) ( µH –10 %) ( µH max.) ( Ω max.) (Vrms) (dB max.) (dB typ.) Package PT542-1 1.4:1.4:1:1 940 10 1.2 1500 3 62 THT PT543-1 1:1:1:1 410 10 0.8 1500 3 62 THT PT544-1 1.4:1.4:1:1 940 10 1.2 3000 3 62 THT PT545-1 1:1:1:1 410 10 0.8 3000 3 62 THT SM546-1 1.4:1.4:1:1 940 10 1.2 3000 3 62 SMT SM547-1 1:1:1:1 410 10 0.8 3000 3 62 SMT Product Dimensions DATE CODE DATE CODE 19.05 (.750) 22.86 (.900) 27.05 (1.065) 3.81 (.150) 4.83 (.190) 23.24 (.915) 24.13 (.950) 1.78 (.070) 8 PLCS. 3.81 (.150) 8 PLCS. MAX. 26.67 (1.05) MAX. MIN.12.70 (.500) MAX. 1.07 (.042) X 0.38 (.015) 3.3 (.130) 20.32 (.800) TYP. 3.81 (.150) TYP. 24.13 (.950) MAX. 12.70 (.500) MAX. 0.97 (.038) 10 PLCS. 3.56 (.140) 10 PLCS. Recommended PAD layout SMT THT 0.10 (.004)
10 SURFACES
DIMENSIONS ARE: MM (INCHES) TOLERANCE: ± 0.25 (.010) Electrical Schematic PT542-1 Packaging Specifications *RoHS COMPLIANTVERSIONS AVAILABLE *RoHS Directive 2002/95/EC Jan 27 2003 including Annex Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. How to Order PT or SM5xx-1 __ Model Termination Blank = Tin-lead L = Tin only (lead free)