PT4841A

PT4840A TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

• DSL Triple Outputs (Independantly Regulated)
• Input Voltage Range: 36V to 75V
• 1500VDC Isolation
• On/Off Control
• Current Limit
• Short Circuit Protection (All Outputs)

Ordering Information

(65W) (62W) PT Series Suffix (PT1234x) Case/Pin Order Package Configuration Suffix Code Vertical N (EKD) Horizontal A (EKA) SMD C (EKC) (Reference the applicable package code drawing for the dimensions and PC layout) Typical Application PT4840 Series—48V

Description

The PT4840 Excalibur™ power modules are a series of isolated triple- output DC/DC converters that operate from a standard (–48V) central office supply. Rated for up to 65W, these regulators are appropriate for powering both analog and mixed- signal circuitry. A typical application is a chip-set for an ADSL/DSL line card. The output voltage combinations offered by the PT4840 series provide power for a low-voltage processor core, the associated digital circuitry, and analog support circuitry. The PT4840 series incorporates many features to simplify system integration. These include a flexible On/Off control, over-temperature protection, and an input under- voltage lock-out. All outputs are current limited and short-circuit protected. In addition, the low- voltage outputs for processor core and digital circuitry meet the power- up and power-down sequencing requirements of popular DSP ICs. The PT4840 series is housed in a space-saving solderable case. The module requires no external heat sink and can occupy as little as 1.97 in2 of PCB area. Cin = Optional Cout = Optional; See specifications EN1 & EN2 pins: See On/Off Enable Logic 65-W Triple Output Isolated DC/DC Converter for DSL Applications SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002 DSL/ADSL IC Chip Set +VIN –VIN +15VDC +3.3VDC +1.5VDC PT4841 15,16 22,23 18–20 12,13 Vo1 COM COM Vo2 Vo3 +VIN –VIN EN 1 Vo2adj Vo3adj Vo2 Adjust Vo3 Adjust COUT1 COUT3 COUT2 CIN

4 EN 2

• Fixed Frequency Operation
• Over-Temperature Shutdown
• Under-Voltage Lockout
• Space Saving Package: 1.9 sq. in. PCB Area (suffix N)
• Solderable Copper Case
• Safety Approvals: UL60950 CSA 22.2 950 VDE EN60950

For technical support and more information, see inside back cover or visit www.ti.com Pin Function +Vin –Vin EN 1 EN 2 TEMP Do Not Connect Do Not Connect Pin Not Present Pin Not Present PT4840 Series—48V 65-W Triple Output Isolated DC/DC Converter for DSL Applications Pin Function Pin Not Present +Vo1 COM COM Pin Not Present +Vo2 +Vo2 Vo2 adjust Pin Function COM COM COM Vo3 adjust +Vo3 +Vo3 Pin Not Present Do Not Connect Do Not Connect On/Off Enable Logic Pin Configuration Pin Descriptions Pin 3 Pin 4 Output Status Off On Off Notes: Logic 1 =Open collector Logic 0 = –Vin (pin 2) potential For positive Enable function, connect pin 3 to pin 2 and use pin 4. For negative Enable function, leave pin 4 open and use pin 3. +Vin: The positive input supply for the module with respect to –Vin. When powering the module from a –48V telecom central office supply, this input is connected to the primary system ground. –Vin: The negative input supply for the module, and the 0VDC reference for the EN 1, EN 2, and TEMP inputs. When powering the module from a +48V supply, this input is connected to the 48V(Return). EN 1: The negative logic input that activates the module output. This pin is referenced to –Vin. A low-level voltage at this pin enables the module’s outputs, and a high impedance impedance disables the module’s outputs. If not used, the pin must be connected to –Vin. EN 2: The positive logic input that activates the module output. This pin is referenced to –Vin. A high impedance at this pin enables the module’s outputs. If not used, the pin should be left open circuit. TEMP: This pin produces an output signal that tracks a temperature that is approximately the module’s metal case. The output voltage is referenced to –Vin and rises approximately 10mV/°C from an intital value of 0.1VDC at –40°C. The signal is available whenever the module is supplied with a valid input voltage, and is independant of the enable logic status. (Note: A load impedance of less than 1MΩ will adversly affect the module’s over-temperature shutdown threshold. Use a high-impedance input when monitoring this signal.) Vo 1: The highest regulated output voltage, which is referenced to the COM node. The output may be used to power analog support circuitry. Vo 2: The regulated output that is designed to power logic or I/O circuitry. It is referenced to the COM node. Vo 3: The low-voltage regulated output that provides power for a micro, processor, ASIC, or DSP core, and is referenced to the COM node. COM: The secondary return reference for the module’s three regulated output voltages. It is DC isolated from the input supply pins. Vo2 Adjust: Using a single resistor, this pin allows Vo2 to be adjusted higher or lower than the preset value. If not used, this pin should be left open circuit. Vo3 Adjust: Using a single resistor, this pin allows Vo3 to be adjusted higher or lower than the preset value. If not used, this pin should be left open circuit. Note: Shaded functions indicate those pins that are at primary-side potential. SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002 Environmental Specifications Characteristics Symbols Conditions Min Typ Max Units Operating Temperature Range Ta Over Vin Range –40 85 (i) Over-Temperature Protection OTP Case temperature 100 Solder Reflow Temperature Treflow Surface temperature of module pins or case 215 (ii) Storage Temperature Ts –40 125 Mechanical Shock Per Mil-STD-883D, Method 2002.3 1 msec, ½ Sine, mounted 500 G’s Mechanical Vibration Mil-STD-883D Method 2007.2 Suffix N 10 (iii) G’s 20-2000 Hz Suffix A, C 20 (iii) Weight Vertical/Horizontal grams Flammability Meets UL 94V-O Notes: (i) See SOA curves or consult factory for appropriate derating. (ii) During solder reflow of SMD package version do not elevate the module case, pins, or internal component temperatures above a peak of 215°C. For further guidance refer to the application note, “Reflow Soldering Requirements for Plug-in Power Surface Mount Products,” (SLTA051). (iii) Only the case pins on through-hole pin configurations (N & A) must be soldered. For more information see the applicable package outline drawing.

For technical support and more information, see inside back cover or visit www.ti.com PT4841—48V 65-W Triple Output Isolated DC/DC Converter for DSL Applications (Unless otherwise stated, the operating conditions are:- Ta =25°C, Vin =48V, and Ion =0.5Ionmax) PT4841 Characteristics Symbols Conditions Min Typ Max Units Output Power Po Each output: Vo1 ( 15V) (1) Vo2 (3.3V) (1) W Vo3 (1.5V) 10.5 (1) Total (all three outputs) (1) W Output Current Io Io1 ( 15V) 2.7 Io2 (3.3V) (2) A Io3 (1.5V) (2) Maximum (Io2 + Io3) (2) A Input Voltage Range Vin V Set-Point Voltage Vo Vo1 15.2 Vo2 3.3 V Vo3 1.5 Temperature Variation Regtemp –40°C ≤Ta ≤+85°C, Io =Iomin Vo1 ±0.5 %Vo Vo2/Vo3 ±0.8 Line Regulation Regline All outputs, Over Vin range 0.1 0.5 %Vo Load Regulation Regload All outputs, 0≤Io≤Iomax 0.2 0.5 %Vo Cross Regulation Regcross Any one output vs. other outputs 1.0 %Vo Total Output Voltage Variation ∆Vo tol Includes set-point, line, load, Vo1 15.75 (3) –40°C ≤Ta ≤+85°C Vo2 3.2 3.4 (3) V Vo3 1.45 1.55 (3) Efficiency η Po =Pomax Vo Ripple/Noise Vn Co1/Co2/Co3 =10µF Vo1 100 (4) (0 to 20MHz bandwidth) Vo2 (4) mVpp Vo3 (4) Transient Response ttr 0.1A/µs load step, 50% to 75% Iomax µSec Vos Vo over/undershoot %Vo Output Adjust Range Voadj Vo2 / Vo3 ±10 %Vo Current Limit Threshold ILIM Io1 A Io2 + Io3 Over Current Shutdown Delay tsd Time period prior to latched shutdown 200 (5) ms Switching Frequency ƒs Over Vin and Io ranges 450 500 550 kHz Under Voltage Lockout Von Vin increasing V Voff Vin decreasing Enable Control (pins 2 & 3) Referenced to –Vin (pin 2) High-Level Input Voltage VIH 4.0 70 (6) V Low-Level Input Voltage VIL –0.2 0.8 (6) Low-Level Input Current IIL Vin =75V 0.16 0.25 mA Standby Input Current Iin standby pins 2 & 4 connected 10 (3) mA Internal Input Capacitance Cint µF External Output Capacitance Co1 330 (7) Co2 5,000 (7) µF Co3 10,000 (7) Temperature Sense Vtemp Output voltage at temperatures:- –40°C 0.1 (8) V 100°C 1.5 (8) Primary/Secondary Isolation V iso 1500 V C iso 1500 pF R iso MΩ Notes: (1) The sum total power delivered from all three regulated outputs, Vo1, Vo2, and Vo3, cannot exceed 65 watts. (2) The sum-total current from outputs Vo2, and Vo3 cannot exceed 11ADC. (3) Limits are guaranteed by design. (4) The ripple and noise is measured with a 10µF tantalum capacitor across each output. (5) After latched shutdown, the module may be reset cycling the input power. (6) The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 4 open-circuit and connecting pin 3 to –Vin allows the the converter to operate when input power is applied. The maximum open-circuit voltage is 5.1V. (7) Ultra-low ESR capacitors, such as organic or polymer aluminum electrolytic types, may cause instability. For more information refer to the application note regarding capacitor selection. (8) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is the sensed temperature in degrees centigrade. See pin descriptions for more information. SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002

For technical support and more information, see inside back cover or visit www.ti.com PT4841—48V 65-W Triple Output Isolated DC/DC Converter for DSL Applications Efficiency vs Output Power PT4841 Performance Characteristics (See Note A) Typical Characteristics Power Dissipation vs Output Power Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. PT4841 SOA vs Output Load @Vin =48V PT4841 Safe Operating Areas (See Note B) PT4841 SOA vs Output Load @Vin =60V PT4841 SOA vs Output Load @Vin =36V 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow 100 100 % Load (All Outputs) Efficiency - % 36V 48V 75V VIN 100 % Load (All Outputs) Pd - Watts 75V 48V 36V VIN SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002

For technical support and more information, see inside back cover or visit www.ti.com PT4842—48V 65-W Triple Output Isolated DC/DC Converter for DSL Applications PT4842 Specifications (Unless otherwise stated, the operating conditions are:- Ta =25°C, Vin =48V, and Ion =0.5Ionmax) PT4842 Characteristics Symbols Conditions Min Typ Max Units Output Power Po Each output: Vo1 ( 12V) 32.4 (1) Vo2 (3.3V) (1) W Vo3 (1.8V) 12.6 (1) Total (all three outputs) (1) W Output Current Io Io1 ( 12V) 2.7 A Io2 (3.3V) (2) A Io3 (1.8V) (2) Maximum (Io2 + Io3) (2) A Current Limit Threshold ILIM Io1 A Io2 + Io3 Over Current Shutdown Delay (3) tsd Time period prior to latched shutdown 200 ms Input Voltage Range Vin V Under Voltage Lockout Von Vin increasing V Voff Vin decreasing Internal Input Capacitance Cint µF Output Voltage Vo Vo1 ( 12V) 11.64 12.0 12.36 Vo2 (3.3V) 3.2 3.3 3.4 V Vo3 (1.5V) 1.74 1.8 1.86 Output Adjust Range Voadj Vo2 / Vo3 ±10 %Vo Line Regulation Regline All outputs, Over Vin range 0.1 1.0 %Vo Load Regulation Regload All outputs, 0≤Io≤Iomax 0.2 1.0 %Vo Cross Regulation Regcross Any one output vs. other outputs 1.0 %Vo Vo Ripple/Noise (4) Vn Cout =10µF tantalum capacitor Vo1 ( 12V) 100 (0 to 20MHz bandwidth) Vo2 (3.3V) mVpp Vo3 (1.5V) Transient Response (5) ttr 25% load step µSec Vos Vo over/undershoot %Vo Efficiency η Po =Pomax Switching Frequency ƒs Over Vin and Io ranges 450 500 550 kHz On/Off Control On Referenced to –Vin Logic ‘0’ 0.8 Off Logic ‘1’ 2.4 (6) V Open cct. voltage Istby Input current in ‘Off’ state mA Primary/Secondary Isolation V iso 1500 V C iso 1500 pF R iso MΩ Temperature Sense (7) Vtemp Output voltage at temperatures:- –40°C 0.1 V 100°C 1.5 External Output Capacitance (8) Cout Co1 330 Co2 5,000 µF Co3 10,000 Notes: (1) The sum total power delivered from all three regulated outputs, Vo1, Vo2, and Vo3, cannot exceed 62 watts. (2) The sum-total current from outputs Vo2, and Vo3 cannot exceed 11ADC. (3) After latched shutdown, the module may be reset by cycling the input power. (4) The ripple and noise is measured with a 10µF tantalum capacitor across each output. (5) The transient response is measured with a 25% load step from Io =0.5Iomax, and di/dt =0.2A/µs. (6) Pins 3 & 4 are diode protected and can be connected to +Vin. (7) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is the sensed temperature in degrees centigrade. See pin descriptions for more information. (8) Ultra-low ESR capacitors, such as organic or polymer aluminum electrolytic types, may cause instability. For more information, refer to the application note regarding capacitor selection. SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002

For technical support and more information, see inside back cover or visit www.ti.com PT4842—48V 65-W Triple Output Isolated DC/DC Converter for DSL Applications Efficiency vs Output Power PT4842 Performance Characteristics (See Note A) Typical Characteristics Power Dissipation vs Output Power Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which internal components are at or below manufacturer’s maximum rated operating temperatures. PT4842 SOA vs Output Load @Vin =48V PT4842 Safe Operating Areas (See Note B) PT4842 SOA vs Output Load @Vin =60V PT4842 SOA vs Output Load @Vin =36V 100 100 % Load (All Outputs) Efficiency - % 36V 48V 75V VIN 100 % Load (All Outputs) Pd - Watts 75V 48V 36V VIN SLTS142C - DECEMBER 2000 -REVISED SEPTEMBER 2002 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow 100 % Load (All Outputs) Ambient Temperature (°C) 300LFM 200LFM 100LFM Nat conv Airflow

For technical support and more information, see inside back cover or visit www.ti.com PT4840 Series Operating Features of the PT4840 Triple-Output DC/DC Converters Over-Current Protection The current limit function of the PT4840 series of triple-output DC/DC converters is divided into two zones. These are the high-voltage output Vo1, and the two low-voltage outputs (combined) Vo2/Vo3. A load fault applied to Vo1 will cause this output voltage to drop. A drop in Vo1 (to less than 10V) will also cause outputs Vo2 and Vo3 to simultaneously turn off. Load faults applied to either Vo2 or Vo3 will cause both these outputs to drop, but in this case Vo1 will be unaffected. Each protection zone incorporates a latch-off time-out period of approximately 200ms. A transient or momentary fault lasting less than this period will allow the prompt recovery of all affected outputs. Faults applied for longer than this period will cause the affected zone to latch off. Faults applied to Vo2 or Vo3 results in the latch off of both these outputs; Vo1 being unaffected, whereas the latch off of Vo1 will shut down all three outputs. Recovery from a latched shutdown condition requires the removal and corresponding re-application of input power to the converter. Over-Temperature Protection The PT4840 DC/DC converter series have an internal temperature sensor, which monitors the temperature of the module’s metal case. If the case temperature exceeds a nominal 110°C the converter will shut down. The converter will automatically restart when the sensed temperature returns to about 100°C. The analog voltage generated by the sensor is also made available at the ‘TEMP’ output (pin 5), and can be monitored by the host system for diagnostic purposes. Consult the ‘Pin Descrip- tions’ section of the data sheet for more information on this feature. Under-Voltage Lock-Out The Under-Voltage Lock-Out (UVLO) circuit prevents operation of the converter whenever the input voltage to the module is insufficient to maintain output regulation. The UVLO has approximately 2V of hysterisis. This is to prevent oscillation with a slowly changing input voltage. Below the UVLO threshold the module is off and the enable control inputs, EN1 and EN2 are inoperative. Primary-Secondary Isolation The PT4840 series of DC/DC converters incorporate electrical isolation between the input terminals (primary) and the output terminals (secondary). All converters are production tested to a withstand voltage of 1500VDC. The isolation complies with UL60950 and EN60950, and the requirements for operational isolation. This allows the converter to be configured for either a positive or negative input voltage source. The regulation control circuitry for these modules is located on the secondary (output) side of the isolation barrier. Control signals are passed between the primary and secondary sides of the converter via a proprietory magnetic coupling scheme. This eliminates the use of opto-couplers. The data sheet ‘Pin Descriptions’ and ‘Pin-Out Information’ provides guidance as to which reference (primary or secondary) that must be used for each of the external control signals. Input Current Limiting The converter is not internally fused. For safety and overall system protection, the maximum input current to the converter must be limited. Active or passive current limiting can be used. Passive current limiting can be a fast acting fuse. A 125-V fuse, rated no more than 10A, is recommended. Active current limiting can be imple- mented with a current limited “Hot-Swap” controller.

required to insure dynamic response to load transients. electrical specification table on p.3. with temperature when selecting electrolytic capacitors. noise components during higher current excursions. Table 1. The table identifies vendors with acceptable of ≥40mΩ, are also recommended for Vo1. temperature range extends below 0°C. long term capacitor life cycles.

For technical support and more information, see inside back cover or visit www.ti.com Application Notes continued Table 1; Output Capacitors for Vo1 (See Note A) o d n e V r otic a p a C tn e n o p m o C s eir e S n oitc ele S s u B e g atlo V h gi H citsir etc a r a h C r otic a p a C V ytitn a u Q g nik r o W e g atlo V µ e ula V tn ela viu q E R S E e c n atsis e R s eir e S tn e rr u C elp piR x a M m rI( C la cis y h P m m e ziS o V 1 V r e b m u N r o d n e V ci n o sa n a P n u o M e c afr u S C F n u o M e c afr u S K F V V V 1.0 Ω 0.0 Ω 1.0 Ω A m A m A m 1 × 2.0 5.2 5.6 2.0 P E C F V E E Q L V C F V E E P E K F V E E n o C m e h C d eti n U Z X L Y V M V V V 0.0 Ω 0.0 Ω 1.0 Ω A m A m A m 1 × 5.2 1 × 5.2 1 × 3.0 L X M B V Z X L L X M B V Z X L P T x M C V Y V M M P n o ci h ci N V V 1.0 Ω 0.0 Ω A m A m 1 × 5.2 1 × 5 H P M E M P U H P M E M P U V S S S n o c s O R N s u B V e h t n O e s U t o N o D X V A S P T m u lat n a T R X ci m a r e C R X ci m a r e C V V V 4.0 Ω 1.0 Ω 0.0 Ω 0.0 Ω A m A m A m L 3.7 W 7.5 × 1.4 R M V S P T C d a el( A A K C R M M S T A M C :te m e K m u lat n a T ci m a r e C R X V V 2.0 Ω 0.0 Ω A m A m L 3.7 W 7.5 H 0.4 S A M X T C A R C C u g a r p S D m u lat n a T ci m a r e C R X V V 2.0 Ω 0.0 Ω A m L 2.7 × W W 1.4 T R X D Ñ A X M Y J V o d n e V r otic a p a C tn e n o p m o C s eir e S V n oitc ele S s u B e g atlo V w o L citsir etc a r a h C r otic a p a C ytitn a u Q g nik r o W e g atlo V µ ula V tn ela viu q E R S E e c n atsis e R s eir e S tn e rr u C elp piR x a M m rI( C la cis y h P m m e ziS o V 2 o V V r e b m u N r o d n e V :ci n o sa n a P n u o M e c afr u S C F )laid a R C F V V V 0.0 Ω 0.0 Ω 0.0 Ω A m A m A m 1 × 5 5.2 × 5 1 × 5.2 S V C F U E E S V C F V E E E C F U E E o C m e h C d eti n U Z F L S F X F V V V V 0.0 Ω 0.0 Ω 0.0 Ω 0.0 Ω A m A m A m A m 1 × 6 1 × 5.2 1 × 5.0 1 × 5.0 L L X M B V Z X L L L X M B V Z X L M S F M X F M P n o ci h ci N V V V 0.0 Ω 0.0 Ω 0.0 Ω A m A m A m 1 × 5 5.2 × 5 5.0 × 5 H H M V M P U H H M V M P U H H M C M P U K F ci n o sa n a P n u o M e c afr u S V V 0.0 Ω 0.0 Ω A m A m 1 × 2.0 5.2 5.3 P V K F V E E Q V K F V E E )laid a R S S n o c s O n u o M e c afr u S V S V V V 0.0 Ω 0.0 Ω 0.0 Ω A m A m A m 1 × 5.0 3.0 3.0 6.2 M S S M V S M V S m u lat n a T S P T X V A V V V 1.0 Ω 0.0 Ω 0.0 Ω A m A m A m L 3.7 W 7.5 × 1.4 R X V S P T R X V S P T R X V S P T :te m e K T T V V 0.0 Ω 0.0 Ω A m A m W 3.4 L 3.7 H 0.4 S A M X T S A M X T m u lat n a T e u g a r p S n u o M e c afr u S D V V 0.0 Ω 0.0 Ω A m A m L 2.7 × W W 1.4 T R X D T R X D Note A: N/R –Not Recommended. Ultra-low ESR capacitors are not recommended for Vo1 (+15V) output bus. Note B: The part numbers listed in Table 2 can be used for any low-output bus voltage of <5VDC. Table 2; Output Capacitors for Vo2, and Vo3 (See Note B) PT4840 Series

For technical support and more information, see inside back cover or visit www.ti.com Adjusting the Output Voltage of the PT4840 Dual Output Voltage DC/DC Converters The Vo2 and Vo3 output voltages from the PT4840 se- ries of DC/DC converters can be independantly adjusted by up to ±10% from their factory pre-set voltage. The method of adjustment uses a single external resistor. 1 The value of the resistor determines the magnitude of adustment, and the placement of the resistor determines the direction of adjustment (up or down). The resistor value can be calculated directly from a simple formula. The constants are given in Table 1. Alternatively, Table 2 provides the resistor values for a select number of output voltages. The placement of each resistor is as follows. Vo2 Adjust Up: To increase the output, add a resistor R1 between pin 17 (Vo2 Adjust) and pin 18 (COM). Vo2 Adjust Down: Add a resistor (R2), between pin 17 (Vo2 Adjust) and pin 16 (+Vo1). Vo3 Adjust Up: Add a resistor R3 between pin 21 (Vo3 Adjust) and pins 20 (COM). Vo3 Adjust Down: Add a resistor (R4) between pin 21 (Vo3 Adjust) and pin 22 (+Vo3). Refer to Figure 1 for further information on resistor placement. Figure 1 Notes: 1. Use only a single 1% resistor in either the R1 or (R2) location to adjust Vo2, and in the R3 or (R4) location to adjust Vo3. Place the resistor as close to the ISR as possible. 2. Never connect capacitors to either the Vo2 Adjust or Vo3 Adjust pins. Any capacitance added to these control pins will affect the stability of the respective regulated output. The adjust resistor values may be calculated. Use the applicable formula and select the appropriate constants from Table 1 for the output and model being adjusted. R1 or R3 Ro · Vr – Rs kΩ Va – Vo (R2) or (R4) Ro (Va – Vr ) – Rs kΩ Vo – Va Where: Vo = Original output voltage, (Vo2 or Vo3) Va = Adjusted output voltage Vr = The reference voltage from Table 1 Ro = The resistance value in Table 1 Rs = The series resistance from Table 1 PT4840 Series + V IN –V IN +Vo 1 +Vo 2 +Vo 3 PT4840 15, 16 22, 23 Vo 1 C O M C O M Vo 2 Vo 3 + V IN -V IN EN 1 Vo 2adj Vo 3adj C OUT 1 C OUT 3 C OUT 2 C IN EN 2 (R 4) Adj Down R 3 Adjust Up (R 2) Adj Down R 1 Adjust Up 12, 13 18–20 C O M

For technical support and more information, see inside back cover or visit www.ti.com Application Notes continued 3.0 (3.1) 3.05 (6.5)kΩ 3.1 (11.5)kΩ 3.15 (20.0)kΩ 3.2 (36.9)kΩ 3.25 (87.6)kΩ 3.3 3.35 309.0kΩ 3.4 151.0kΩ 3.45 98.2kΩ 3.5 71.7kΩ 3.55 55.9kΩ 3.6 45.3kΩ R1/R3 = Black, R2/R4 = (Blue) Vo2 Bus Vo3 Bus Series Pt # PT4841/42 PT4841 PT4842 Adj. Resistor R1/(R2) R3/(R4) R3/(R4) Vo(nom) 3.3V 1.5V 1.8V Va(req’d) Va(req’d) Table 1 ADJUSTMENT RANGE AND FORMULA PARAMETERS Vo2 Bus Vo3 Bus Series Pt # PT4841/42 PT4841 PT4842 Adj. Resistor R1/(R2) R3/(R4) R3/(R4) Vo(nom) 3.3V 1.5V 1.8V Va(min) 2.97V 1.35V 1.62V Va(max) 3.63V 1.65V 1.98V Vr 2.5V 1.0V TBD Ro (kΩ) 6.34 4.99 TBD Rs (kΩΩΩΩΩ) 7.5 10.0 TBD 1.35 (1.6)kΩ 1.4 (10.0)kΩ 1.45 (34.9)kΩ 1.5 1.55 89.8kΩ 1.6 39.9kΩ 1.65 23.3kΩ 1.7 1.7 1.8 1.85 1.9 1.95 2.0 Table 2 ADJUSTMENT RESISTOR VALUES PT4840 Series

For technical support and more information, see inside back cover or visit www.ti.com VDE Approved Installation Instructions (Installationsanleitung) Nennspannnug (Rated Voltage): PT4840 36 to 72 Vdc, Transient to 80Vdc Nennaufnahme (Rated Input): PT4840

2.2 Adc

Nennleistung (Rated Power):

25 Watts Maximum

PT4841, 65 Watts Maximum PT4842, 62 Watts Maximum Ausgangsspannung (Sec. Voltage): PT4840 Series Maximum total current is 13.7 Adc or 65 Watts PT4842, +12V/ +3.3V/ +1.8V, 2.7Adc/ 6Adc/ 7Adc Ausgangsstrom (Sec. Current): Maximum total current is 13.7 Adc or 62 Watts oder (or) Ausgangsleistung (Sec. Power): Angabe der Umgebungstemperatur (Information on ambient temperature): +85 °C maximum Besondere Hinweise (Special Instructions): Es ist vorzusehen, daß die Spannungsversorgung in einer Endanwendung über eine isolierte Sekundaerschaltung bereit gestellt wird. Die Eingangspannung der Spannungsversorgungsmodule muss eine verstaerkte Isolierung von der Wechselstromquelle aufweisen. Die Spannungsversorgung muss gemaess den Gehaeuse-, Montage-, Kriech- und Luftstrecken-, Markierungs- und Trennanforderungen der Endanwendung installiert werden. Bei Einsatz eines TNV-3- Einganges muss die SELV-Schaltung ordnungsgemaess geerdet werden. (The power supply is intended to be supplied by isolated secondary circuitry in an end use application. The input power to these power supplies shall have reinforced insulation from the AC mains. The power supply shall be installed in compliance with the enclosure, mounting, creepage, clearance, casualty, markings, and segregation requirements of the end-use application. When the input is TNV-3, the SELV circuitry must be reliably grounded.) Offenbach, VDE Prüf- und Zertifizierungsinstitut Abteilung / Department TD (Jürgen Bärwinkel) Ort / Place: Datum / Date: (Stempel und Unterschrift des Herstellers / Stamp and signature of the manufacturer) PT4840 Series

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2002, Texas Instruments Incorporated