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10W Stereo Integrated Audio Amplifier

DESCRIPTION

The PT2830 is an integrated audio amplifier design for the compact audio system; the maximum output power is up to 10W x 2. Utilizi ng PTC exclusive, patented Class-D modulation circuit, compare with traditional Class-AB amplifier, the PT2830 have a lot of benefit for high efficiency, low heat dissipation and very low harmonic distortion. Thanks for highly integrated design, consist a complete audio amplifier system is easy and only needs few external components, no more complex PCB wiring and saving the PCB sizes.

APPLICATIONS

  • LCD TV
  • Docking Speaker System
  • Other audio applications

FEATURES

  • 10W/8 Ω (THD=10%) × 2 output power
  • 4 stereo sources input
  • Volume, bass and treble control
  • Audio line out for second power amplifier
  • Built-in 5V regulator
  • Improved RF interference immunity
  • 4 power amplifier voltage gain selectable
  • External mute output
  • Low harmonic distortion (0.05%), superior sound quality
  • I2C bus controls
  • Over current and temperature protection
  • Low EMI emission
  • 48 Pins, E-LQFP ( thermal pad included) package BLOCK DIAGRAM I2C INPUT SEL VOLUME BASS TREBLE INPUT SEL VOLUME BASS TREBLEIN R1 IN R4 IN R2 IN R3 IN L1 IN L2 IN L3 IN L4 LB 1LB 2 LT LOUT IN LNIN LP PV DD PG ND OUTLP OUTLN IN RNIN RP PV DD PG ND OUTRP OUTRN PV DD AGND BYPASS PG ND 5VREG SDPower Managment 5V Reg SDA SCL RB1RB2 RT ROUT MUOUT DE-POP OE UV /OV/OC Thermal Protection Power Amplifier L-CH R-CH Power Amplifier

V1.0 2 July 2013 APPLICATION CIRCUIT C12 C11 C10 1uC13 C14 C15 C16 C21 820p C17 68n C18 68n 8.2K C22 820p C19 68n C20 68nR2 8.2K C24 2.2uF C23 0.47u C31 1uF C30 0.1u C29 0.1u C26 10uF C27 10uF C25 10uF C28 0.1u 0.47uF 0.47uF 0.47uF 0.47uF 22uH 22uH 22uH 22uH R-SPK L-SPK Power SD C32 470uF VDD SDA SCL U1A U1B U1C U2A OUTR+ OUTR- OUTL- OUTL+ +12V GND OUTRP 1OUTRP 2PVDD 3PGND 4AGND 55VREG 6BYPASS 7INRN 8INRP 9ROUT 10RB1 11RB2 12 RT13 INR114 INR215 INR316 INR417 OE18 INL419 INL320 INL221 INL122 LT23 LB224 LB125 LOUT26 INLP27 INLN28 DGND29 SDA30 SCL31 AGND32 MUOUT33 SD34 OUTLP35 OUTLP36 PVDD 37PGND 38PGND 39PVDD 40OUTLN 41OUTLN 42OUTRN 43OUTRN 44PVDD 45PGND 46PGND 47PVDD 48 IC1 PT2830 IN1 IN2 IN3 IN4 0.47uF 0.47uF 0.47uF 0.47uF MUTE OUT 4.7 4.7 C33 0.47u C34 0.47u

V1.0 3 July 2013 ORDER INFORMATION Valid Part Number Package Type Top Code PT2830-LQ 48 Pins, E-LQFP, 7 X 7 mm PT2830-LQ PIN CONFIGURATION OUTRP1 OUTRP2 PVDD3 PGND4 AGND5 5VREG6 BYPASS7 INRN8 INRP9 ROUT10 RB111 RB212 RT 13INR1 14INR2 15INR3 16INR4 17OE 18INL4 19INL3 20INL2 21INL1 22LT 23LB2 24 LB1 25LOUT 26INLP 27INLN 28DGND 29SDA 30SCL 31AGND 32MUOUT 33SD 34OUTLP 35OUTLP 36 PVDD37 PGND38 PGND39 PVDD40 OUTLN41 OUTLN42 OUTRN43 OUTRN44 PVDD45 PGND46 PGND47 PVDD48

V1.0 4 July 2013 PIN DESCRIPTION Pin Name I/O Description Pin No. OUTRP O Right channel output (+) 1 OUTRP O Right channel output (+) 2 PVDD Power Power supply of control circuit 3 PGND Power Ground of control circuit 4 AGND Power Ground of analog circuit 5 5VREG O Regulator bypass 6 BYPASS I Internal voltage reference bypassing 7 INRN I Power amp right channel input (-) 8 INRP I Power amp right channel input (+) 9 ROUT O Right channel line out 10 RB1 I Capacitor 1 for right channel bass controller 11 RB2 I Capacitor 2 for right channel bass controller 12 RT I Capacitor for right channel treble controller 13 INR1 I Input 1 of right channel 14 INR2 I Input 2 of right channel 15 INR3 I Input 3 of right channel 16 INR4 I Input 4 of right channel 17 OE I/O Output Enable, with internal high resistance pull-up, usually connects a cap to ground for turn-on delay. INL4 I Input 4 of left channel 19 INL3 I Input 3 of left channel 20 INL2 I Input 2 of left channel 21 INL1 I Input 1 of left channel 22 LT I Capacitor for left channel treble controller 23 LB2 I Capacitor 2 for left channel bass controller 24 LB1 I Capacitor 1 for left channel bass controller 25 LOUT O Left channel line out 26 INLP I Power amp left channel input (+) 27 INLN I Power amp left channel input (-) 28 DGND Power Digital GND for I2C Ack. 29 SDA I/O I 2C bus data Input 30 SCL I I 2C bus clock Input 31 AGND Power Ground of analog circuit 32 MUOUT O External mute output 33 SD I Shutdown. Sets to low level will turn off whole chip and pull up to High level for normal operation. OUTLP O Left channel output (+) 35 OUTLP O Left channel output (+) 36 PVDD Power Left channel power supply input 37 PGND Power Left channel power ground 38 PGND Power Left channel power ground 39 PVDD Power Left channel power supply input 40 OUTLN O Left channel output (-) 41 OUTLN O Left channel output (-) 42 OUTRN O Right channel output (-) 43 OUTRN O Right channel output (-) 44 PVDD Power Right channel power supply input 45 PGND Power Right channel power ground 46 PGND Power Right channel power ground 47 PVDD Power Right channel power supply input 48

V1.0 22 July 2013 IMPORTANT NOTICE Princeton Technology Corporation (PTC ) reserves the right to make co rrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw