PT12000

MC33PT2000_V01 NXP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 148

Technical content

Features

• Battery voltage range, 5.0 V < V BATT < 72 V
• Battery and boost voltage monitoring
• Pre-drive operating voltage up to 72 V
• Seven high-side/ eight low-side pre-drive PWM capability up to 100 kHz-30 nC
• All pre-drivers have four selectable slew rates
• Eight selectable, pre-defined V DS monitoring thresholds
• Measurement function for end of injection detection
• Encryption for microcode protection
• Integrated 1.0 MHz back-up clock 5.0 V VBOOST x3 BankVSENSEPx VSENSENx VSENSEPx VSENSENx VBAT/VBOOST VBAT VBAT VBOOST

Figure 1. PT2000 simplified application diagram

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1 Orderable parts

Table 1. Orderable part variations

1. To order parts in tape and reel, add the R2 suffix to the part number.

1.1 Cipher key

Contact a NXP sales representative to obtain devices with a specific encryption key and the associated code encryptor.

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2 Internal block diagram

Figure 2. PT2000 simplified internal block diagram

3 Pin connections

Figure 3. PT2000 pin connections Functional descriptions of many of these pins can be found in the Functional block description section beginning on page 34. Table 2. PT2000 pin definitions (2), (3), (4)

1 DRVEN Input Weak PD Driver enable input

2 RESETB Input Weak PU Reset pin

3 START1 Input/output PU/PD

4 START2 Input/output PU/PD

5 START3 Input/output PU/PD

6 START4 Input/output PU/PD

7 START5 Input/output PU/PD

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8 START6 Input/output PU/PD

9 START7 Input/output PU/PD

14 CSB Input PU SPI chip select

15 MOSI Input Weak PU SPI slave input

16 MISO Output — SPI slave output

17 SCLK Input Weak PU SPI clock

19 DBG Input/output Weak PU Debug port / Flag_bus (15)

20 DGND Ground — Digital ground

23 AGND Ground — Analog ground

24 VSENSEN4 Input/output PU/PD

25 VSENSEP4 Input/output Weak PD Current sense input comparator + /Flag(4) (general purpose I/O)

26 VSENSEN1 Input — Current sense input comparator 1 -

27 VSENSEP1 Input — Current sense input comparator 1 +

28 VSENSEN2 Input — Current sense input comparator 2 -

29 VSENSEP2 Input — Current sense input comparator 2 +

30 VSENSEN3 Input — Current sense input comparator 3 -

31 VSENSEP3 Input — Current sense input comparator 3 +

32 VSENSEN5 Input — DC-DC current sense input comparator -

33 VSENSEP5 Input — DC-DC current sense input comparator +

34 VSENSEN6 Input — DC-DC current sense input comparator -

35 VSENSEP6 Input — DC-DC current sense input comparator +

36 OA_1 Output — Analog output 1

37 OA_2 Input/output Weak PD Analog output 2/Flag_bus (14)

38 OA_3 Output — Analog output 3

39 D_LS8 Input — Drain pin low-side MOSFET for DC/DC converter

40 D_LS7 Input — Drain pin low-side MOSFET for DC/DC converter

41 D_LS6 Input — Drain pin low-side MOSFET actuator 6

42 D_LS5 Input — Drain pin low-side MOSFET actuator 5

Table 2. PT2000 pin definitions (2), (3), (4)(continued)

43 D_LS4 Input — Drain pin low-side MOSFET actuator 4

44 D_LS3 Input — Drain pin low-side MOSFET actuator 3

45 D_LS2 Input — Drain pin low-side MOSFET actuator 2

46 D_LS1 Input — Drain pin low-side MOSFET actuator 1

47 VBATT Input — Battery voltage input

49 G_LS8 Output — Gate pin low-side high speed MOSFET can be used for DC/DC converter

50 G_LS7 Output — Gate pin low-side high speed MOSFET can be used for DC/DC converter

51 G_LS6 Output — Gate pin low-side MOSFET actuator 6

52 G_LS5 Output — Gate pin low-side MOSFET actuator 5

53 G_LS4 Output — Gate pin low-side MOSFET actuator 4

54 G_LS3 Output — Gate pin low-side MOSFET actuator 3

55 G_LS2 Output — Gate pin low-side MOSFET actuator 2

56 G_LS1 Output — Gate pin low-side MOSFET actuator 1

57 VBOOST Input — Boost voltage and drain pin for boost pre-drivers

58 B_HS7 - — Bootstrap pin high-side MOSFET 7

59 G_HS7 Output — Gate pin high-side MOSFET 7

60 S_HS7 Input — Source pin high side MOSFET 7

61 B_HS6 - — Bootstrap pin Boost MOSFET 6

62 G_HS6 Output — Gate pin Boost MOSFET 6

63 S_HS6 Input — Source pin Boost MOSFET 6

64 B_HS5 - — Bootstrap pin high-side MOSFET 5

65 G_HS5 Output — Gate pin high-side MOSFET 5

66 S_HS5 Input — Source pin high side MOSFET 5

67 B_HS4 - — Bootstrap pin boost MOSFET 4

68 G_HS4 Output — Gate pin boost MOSFET 4

69 S_HS4 Input — Source pin boost MOSFET 4

70 B_HS3 - — Bootstrap pin high-side MOSFET 3

71 G_HS3 Output — Gate pin high-side MOSFET 3

72 S_HS3 Input — Source pin high-side MOSFET 3

73 B_HS2 - — Bootstrap pin boost MOSFET 2

74 G_HS2 Output — Gate pin boost MOSFET 2

75 S_HS2 Input — Source pin boost MOSFET 2

76 B_HS1 - — Bootstrap pin high-side MOSFET 1

77 G_HS1 Output — Gate pin high-side MOSFET 1

78 S_HS1 Input — Source pin high-side MOSFET 1

79 IRQB Input/output Weak PD Interrupt output/Flag_bus (13)

80 CLK Input Weak PU Clock pin (low-frequency reference for internal PLL)

Table 3. Resistor types

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1. External 7.0 V is required in case the typical battery voltage is 24 V ( See External VCCP (vccp_ext_en='1') on page 35).
2. Except for supply and ground, it is guaranteed by design unused pins can be kept open without any impact on the device.
3. Unused VSENSEPx and VSENSENx pins can both be connected to GND.

4 Functional description

4.1 Introduction

The PT2000 is a mixed signal IC for engine injector and electrical valve control, which provides a cost effective, flexible, and smart, high- side and low-side MOSFET gate driver. The device includes both individual charge pump outputs for each high-side pre-driver and high- voltage DC/DC converter pre-driver. Gate drive, diagnostics, and protection against external faults, are managed through six independent and concurrent digital microcores. Each of the three logic channels including two microcores and their own code RAM and data RAM. The internal microcode is protected against theft via encryption and corruption via check sums. Those microcores are optimized to control power MOSFET with a small latency time. The PT2000 can control three banks of two injectors each or three banks with one injector per bank for full overlap,

4.2 Features

High-side and low-side pre-drivers

• Seven high-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates
• Six low-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates
• Integrated bootstrap circuitry for each high-side pre-driver
• Integrated charge pump circuitry for each high-side pre-driver with 100% duty cycle capability
• Configurable automatic freewheeling capability between high-side and low-side DC/DC converter
• Two low-side pre-driver, for a logic level N-channel MOSFET, can be optionally dedicated to providing a boost DC-DC converter with four programmable slew rates
• Three different control modes to reduce power dissipation (manual, hysteretic, resonant) Current measurement
• Four independent current measurement blocks
• Two current measurements (channel 5 and 6) are optionally configurable to support DC/DC converters Diagnostics and monitoring
• V DS and VSRC monitoring (programmable values) for fault protection and diagnostics
• V BOOST monitoring
• V BAT monitoring
• Temperature monitoring Integrated end of injection detection
• Accurate detection of end of injection for each high-side source and low-side drain without any external component needed. Power supplies
• Integrated 7.0 V linear regulator (VCCP) for the HS/LS gate power supply (2)
• Integrated 2.5 V linear regulator (VCC2P5) for the digital core supply based on the VCC5 input supply
• External 5.0 V supply (VCC5)
• Selectable VCCIO external supply (5.0 V or 3.3 V) for digital I/O Digital block
• Six digital microcores, each with their own ALU, and full access to the system crossbar switch
• Three memory banks: 1024 x 16-bit of code RAM with built-in error detection and 64 x 16-bit of data RAM
• Memory BIST and Logic BIST activated by the SPI, with pass/fail status Control interface
• 16-bit slave SPI up to 10 MHz - two protocols - programmable slew rate
• 16 general purpose digital IOs able to sustain up to 36 V
• Independent direct pre-driver inhibition input for safety purposes

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5 Electrical characteristics

5.1 Maximum ratings

Table 4. Maximum ratings

36 V (5)

• DC voltage
• Transients t <800 ns
• Transients t <400 ns -3.0 -6.0 -8.0 V BOOSTMAX VBOOSTMAX VBOOSTMAX V (6) (6) VB_HSX B_HSx
• V BATT -VB_HSx must not exceed 40 V
• Transients t <800 ns
• Transients t <400 ns -0.3 -2.0 -4.0 VS_HSX + VBS_HSX_CL V (6) (6) VG_HSX DC voltage at G_HSx V S_HSx - 0.3 V B_HSx +0.3 V VG_LSX G_LSx
• DC voltage
• Transients t < 5.0 s; V CCP_MAX = 8.0 V; energy of pulses < 0 V or > V CCP is limited to 2.0 J due to capacitive coupling -0.3 -1.5 VCCP + 0.3 VCCP + 1.5 V — (6) VD_LSX D_LSx
• DC voltage
• Transients t < 400 ns -3.0 -8.0 V (6)

• Static at VCC5 < 10 V
• Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5, 5.25 V
• Dynamic for max 1.0 s at VCC5 < 5.25 V -1.0 -5.0 -15 1.0 5.0 V (6) (6) VVSENSEP1/2/3 DC voltage at VSENSEP1/2/3
• DC voltage at VCC5 < 10 V
• Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
• Dynamic for max 1.0 s at VCC5 < 5.25 V -2.5 -5.0 -15 2.5 5.0 V (6) (6) VVSENSEN5/6 DC voltage at VSENSEN5/6
• DC voltage at VCC5 < 10 V
• Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
• Dynamic for max 1.0 s at VCC5 < 5.25 V -3.0 -5.0 -15 1.0 5.0 V (6) (6) VVSENSEP5/6 DC voltage at VSENSEP5/6
• DC voltage at VCC5 < 10 V
• Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
• Dynamic for max 1.0 s at VCC5 < 5.25 V -4.2 -5.0 -15 2.5 5.0 V (6) (6) ESD voltage VESD-HBM1 VESD-HBM2 VESD-HBM3 VESD-CDM1 VESD-CDM2 ESD voltage
• Human body model (HBM) VBOOST, VBATT, S_HSx D_LSx All other pins
• Machine model Corner pins All other pins -4000 -8000 -2000 -750 -500 4000 8000 2000 750 500 V (7), (8) Thermal ratings TA TJ Operating temperature
• Ambient
• Junction - 40 -40 125 150 TTHRESHOLD Temperature monitoring threshold 167 187 C TSTG Storage ambient temperature -55 150 C Thermal resistance RJA Thermal resistance junction to ambient — 25.3 °C/W (9) RJCTOP Thermal resistance junction to case top — 13.2 °C/W (10) RJCBOTTOM Thermal resistance junction to case bottom — 0.8 °C/W (11) Notes 5. With series resistor of 3.3 k  at the pin 6. Guaranteed by design. 7. Human body model (HBM) per JESD22-A114 - 100 pF, 1.5 k  8. Charge device model (CDM) per JESD22-C101. 9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal 10. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012 .1). 11. Thermal resistance between the die and the solder pad on the bottom of the package based on the simulation without internal resistance

Table 4. Maximum ratings (continued)

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5.2 Power supply electrical characteristics

Table 5. PT2000 static electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• Internal VCCP regulator
• External VCCP regulator 5.0 5.0 13.5 V (12) VBATT_LOADDUMP VBATT power supply input voltage during load dump duration < 500 ms
• Internal VCCP regulator 18 — 40 V IVBATT_LEAK VBATT power supply current in reset state, VCC5 = VCCIO = 0.0 V
• V BATT = 13.5 V
• V BATT = 40 V 150 600 180 800 IVBATT_OPER VBATT power supply current in normal operation VBATT = 16 V
• DRVEN low, internal VCCP reg. off
• DRVEN low, Internal VCCP reg. on
• DRVEN high, VCCP max. load 100 mA 0.9 4.5 104.5 2.5 6.0 106 mA I VBATT_LEAK VBATT power supply current in reset state, VCC5 = VCCIO = 0.0 V
• V BATT = 13.5 V
• V BATT = 40 V 150 600 180 800 VBOOST input supply IVBOOST_LEAK Leakage current from VBOOST, during reset state with VCC5 = V CCIO = 5.0 V
• V BOOST = VBAT = 13.5 V
• V BOOST = VBAT = 40 V
• V BOOST = VBAT = 65 V Contributors (13.5 V): V BOOST volt. div.: 65 A 240 400 370 600 I VBOOST_OPER Operating current from VBOOST = 65 V — 3.9 5.75 mA VCC5 input supply VCC5 VCC5 supply input voltage 4.75 5.0 5.25 V VCC5_DIGITAL VCC5 supply input voltage for digital part functional only 4.0 5.0 5.25 V (12) IVCC5 VCC5 supply current
• f SYS = 24 MHz, 7 HS load biasing enabled, no microcore running
• f SYS = 24 MHz, 7 HS load biasing enabled, all microcores running
• LBIST running, bias disabled 66.4 81.4 mA (12) VOVVCC5 VCC5 overvoltage threshold 7.5 8.5 10 V VOVVCC5_VCCP VCC5 overvoltage threshold for VCCP shutdown 6.2 6.9 7.5 V VUVVCC5- VCC5 undervoltage low-voltage threshold 4.3 4.45 4.7 V VUVVCC5+ VCC5 undervoltage high-voltage threshold 4.35 4.5 4.75 V VUVVCC5_HYST VCC5 undervoltage hysteresis 30 50 85 mV Notes 12. Guaranteed by design.

• f SYS = 24 MHz, no microcore running
• f SYS = 24 MHz, all microcores running 1.5 mA (13) VCCP input supply VCCP VCCP output voltage, 0.0 mA < I VCCP < 100 mA 6.5 7.0 7.5 V VCCP_EXT VCCP input voltage range (VCCP externally supplied) 5.0 — 9.0 V CVCCP VCCP external output capacitor 1.0 4.7 14 F (14) VVCCP VBATT to VCCP voltage dropout
• V BATT = 5.0 V and I VCCP = -50 mA
• V BATT = 5.0 V and I VCCP = -30 mA
• V BATT = 5.0 V and I VCCP = -10 mA
• V BATT = 5.0 V and I VCCP = -100 mA 180 110 350 mV V UVVCCP- VCCP undervoltage low-voltage threshold 4.3 4.5 4.68 V VUVVCCP+ VCCP undervoltage high-voltage threshold 4.4 4.55 4.73 V VUVVCCP_HYST VCCP undervoltage hysteresis 30 50 70 mV IVCCP VCCP output current (average during PWM operation)

9.0 V < V BATT < 18 V — — 100 mA

• f SYS = 24 MHz, all microcores running — -15 -50 mA IVCC2P5_LIM VCC2P5 supply output current limit -50 93 140 mA VPORESETB- VCC2P5 voltage threshold for asserting PORESETB 2.0 2.11 2.21 V VPORESETB+ VCC2P5 voltage threshold for deasserting PORSETB 2.07 2.19 2.3 V VPORESETB_HYST PORESETB voltage hysteresis 50 75 100 mV tD_PORESETB PORESETB switching time — 0.7 1.5 s Notes 13. Guaranteed by design. 14. For VCCP: “For EMC purpose adding 1.0 F + 100 nF caps in parallel connected to PGND is recommended 15. For VCC2P5: “For EMC purpose adding 1.0 F + 100 nF caps in parallel connected to DGND is recommended

Table 5. PT2000 static electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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• DAC code = 0h — 0.0 — V VVBATT_DAC_OUT_ MAX DAC maximum output voltage
• DAC code = 3Fh — 2.461 — V VBATT VBATT measurement total error (VBATT > 5.0 V) -5.0 1.0 5.0 % tVBATT_DAC VBATT DAC settling time — — 0.9 s Boost voltage monitor VBOOSTMAX Input voltage range 0.0 — 72 V RVBOOST_IN Input impedance 400 640 — k  GVBOOST_DIV VBOOST voltage divider ratio (boost monitor mode) 1/32* 0.996 1/32 1/32* 1.004 GUV_VBOOST_DIV VBOOST voltage divider ratio (UV VBOOST mode) 1/4* 0.996 1/4 1/4* 1.004 VVBOOST_DAC_LSB DAC LSB — 9.77 — mV VBOOST VBOOST measurement total error (4.85 V to 72 V) -2.0 — 2.0 % Notes 16. This limitation is only for the V BAT ADC, if VBAT is > 36 V, then VBAT monitoring results will saturate. It means in case VBAT > 36 V, the VBAT monitoring feature will not work but device will be 100 % functional until VBAT = 72 V.

the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.3 High-side pre-driver electrical characteristics

Table 6. High-side pre-driver electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

8.0 V (17)

• V S_HSX = VBOOSTMAX
• V S_HSX = 13.5 V
• V S_HSX = 7.0 V
• V S_HSX = 4.0 V 1000 250 120 100 I S_HSX_SINK_ON S_HSx leakage current when pre-driver on (biasing switched Off)
• V S_HSX = 7.0 V — — 220 A fG_HSX_PWM PWM frequency
• Internal V CCP and VBATT 9.0 V
• Internal V CCP and 5.0 V VBATT9.0 V
• External V CCP and 9.0 V VBATT 0.0 0.0 0.0 100 100 kHz (17) DCG_HSX Duty cycle 0.0 — 100 % tON_HSX_MIN High-side driver minimum PWM on time — — 1.0 s (17) QG_HSX External high-side MOSFET effective gate charge
• f PWM 67 kHz nC IG_HSX_PWM G_HSx current (average during PWM operation) QG = QG_HSX, fPWM = 100 kHz — 4.0 5.0 mA (17) IG_HSx_SRC Peak source gate drive current — 230 — mA (17) IG_HSx_SINK Peak sink gate drive current — 440 — mA (17) High-side pre-driver dynamic tR_G_HSX Turn on rise time, 10%-90% of out voltage, VCCP = 7.0 V, at open pin 4.5 — 25 ns (17) tF_G_HSX Turn off fall time, 90%-10% of out voltage, VCCP = 7.0 V, at open pin 5.0 — 25 ns (17) SRS_HSX Max permissible slew rate at the S_HSX pin -125 — 600 V/ s (17) tDON_G_HSX_300 Turn on propagation delay at 300 V/ s slew rate 40 — 100 ns (17)(19) tDOFF_G_HSX_300 Turn off propagation delay at 300 V/ s slew rate 40 — 100 ns (17)(19) tDON_G_HSX_50 Turn on propagation delay at 50 V/ s slew rate 65 — 125 ns (17)(19) tDOFF_G_HSX_50 Turn off propagation delay at 50 V/ s slew rate 50 — 100 ns (17)(19) Notes 17. Guaranteed by design. 18. VB_HSx has to be 2.0 V above PGND for full function (switch on) of the pre-driver 19. 10% of output voltage change, C LOAD = 4.7 nF; R G = 40.2 , VCCP = 7.0 V

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5.4 Low-side (LS1-LS6) pre-driver electrical characteristics

1. 10% of output voltage change, C

Table 7. Low-side pre-driver electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• V D_LSx = 13.5 V
• V D_LSx = 40 V 110 320 fG_LSx_PWM PWM frequency
• Nominal
• Short period of switching during 50 s every 1ms 0.0 0.0 100 200 kHz (22) DCG_LSx Duty cycle 0.0 — 100 % (22) QG_LSx External low-side MOSFET effective gate charge
• f PWM 67 kHz
• f PWM 50 kHz 100 nC Notes 22. Guaranteed by design.

Table 6. High-side pre-driver electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• QG = QG_LSX; f PWM = 100 kHz — 3.0 5.0 mA (23) IG_LSx_SRC Peak source gate drive current — 230 — mA (23), (24) IG_LSx_SINK Peak sink gate drive current — 440 — mA (23), (24) Dynamic low-side pre-driver LS1-6 TR_G_LSX Turn on rise time, 10% to 90% of output voltage; VCCP = 7.0 V; at open pin 5.0 — 25 ns (23) TF_G_LSX Turn off fall time, 90% to 10% of output voltage; VCCP = 7.0 V; at open pin 5.0 — 25 ns (23) TDON_G_LSX_300 Turn on propagation delay at 300 V/ s slew rate 10 — 70 ns (23), (25) TDOFF_G_LSX_300 Turn off propagation delay at 300 V/ s slew rate 10 — 70 ns (23), (25) TDON_G_LSX_50 Turn on propagation delay at 50 V/ s slew rate 10 — 80 ns (23), (25) TDOFF_G_LSX_50 Turn off propagation delay at 50 V/ s slew rate 10 — 80 ns (23), (25) TDON_G_LSX_25 Turn on propagation delay at 25 V/ s slew rate 15 — 120 ns (23), (25) TDOFF_G_LSX_25 Turn off propagation delay at 25 V/ s slew rate 15 — 120 ns (23), (25) TDON_G_LSX_12.5 Turn on propagation delay at 12.5 V/ s slew rate 15 — 150 ns (23), (25) TDOFF_G_LSX_12.5 Turn off propagation delay at 12.5 V/ s slew rate 15 — 150 ns (23), (25) LS pre-driver safe off RPD_LSX G_LSX to PGND pull-down resistor 25 50 90 k  Low-side pre-driver LS1-6 RDS_LSX_P (00) G_LSx pMOS RDS(on) (00) 300 V/ s 7.5 14.6 31.3  RDS_LSX_N (00) G_LSx nMOS RDS(on) (00) 300 V/ s 2.5 5.9 16.5  RDS_LSX_P (01) G_LSx pMOS RDS(on)n (01) 50 V/ s 61 84 115  RDS_LSX_N (01) G_LSx nMOS RDS(on) (01) 50 V/ s2 3 3 5 5 0  RDS_LSX_P (10) G_LSx pMOS RDS(on) (10) 25 V/ s 122 170 230  RDS_LSX_N (10) G_LSx nMOS RDS(on) (10) 25 V/ s 47 69 100  RDS_LSX_P (11) G_LSx pMOS RDS(on) (11) 12.5 V/ s 245 337 460  RDS_LSX_N (11) G_LSx nMOS RDS(on) (11) 12.5 V/ s 94 138 199  Notes 23. Guaranteed by design. 24. V CCP = VGS = 7.0 V and fastest slew rate 25. 10% of output voltage change; C LOAD = 4.7 nF; R G = 40.2 ; VCCP = 7.0 V

Table 7. Low-side pre-driver electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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5.5 Low-side high-speed (LS7-LS8) pre-driver electrical characteristics

Table 8. High-speed low-side pre-driver electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• f PWM  400 kHz
• f PWM 300 kHz
• f PWM 240 kHz 100 nC I G_LS7/8_PWM G_LS7/8 current (average during PWM operation)
• f PWM = 400 kHz
• f PWM 300 kHz
• f PWM 100 kHz
• f PWM 50 kHz 9.0 3.0 1.5 22.5 7.5 3.75 mA (27) IG_LS7/8_SRC Peak source gate drive current — 680 — mA (27), (27) IG_LS7/8_SINK Peak sink gate drive current — 2200 — mA (27), (27) Dynamic low-side pre-driver L7 and 8 tR_G_LS7/8_1500 Turn on rise time
• at 1500 V/ s slew rate 10% to 90% of out voltage; VCCP =7.0 V; at the open pin 3.5 — 11 ns (27) tF_G_LS7/8_1500 Turn off fall time
• at 1500 V/ s slew rate 90% to 10% of out voltage; VCCP = 7.0 V; at the open pin 3.5 — 11 ns (27) tR_G_LS7/8 Turn on rise time
• at 300-25 V/ s slew rate 10% to 90% of out voltage; VCCP = 7.0 V; at the open pin 5.0 — 25 ns (27) tF_G_LS7/8 Turn off fall time
• at 300-25 V/ s slew rate 90% to 10% of out voltage; VCCP = 7.0 V; at the open pin 5.0 — 25 ns (27) tDON_G_LS7_1500 Turn on propagation delay
• at 1500 V/ s slew rate 10% of out voltage change 10 — 50 ns (27), (28) tDOFF_G_LS7_1500 Turn off propagation delay
• at 1500 V/ s slew rate 10% of out voltage change 10 — 50 ns (27), (28) tDON_G_LS7_300 Turn on propagation delay
• at 300 V/ s slew rate 10% of out voltage change 10 — 70 ns (27), (28) tDOFF_G_LS7_300 Turn off propagation delay
• at 300 V/ s slew rate 10% of out voltage change 10 — 70 ns (27), (28) Notes 26. Guaranteed by design. 27. At the fastest slew rate setting with minimum R G_LS8 of 2.0  and VCCP/VGS = 7.0 V 28. C LOAD = 4.7 nF; R G = 40.2  VCCP = 7.0 V

5.6 High-side VDS VSRC monitoring electrical characteristics

• at 50 V/ s slew rate 10% of out voltage change 15 — 100 ns (29), (30) tDOFF_G_LS7_50 Turn off propagation delay
• at 50 V/ s slew rate 10% of out voltage change 15 — 100 ns (29), (30) tDOFF_G_LS7_25 Turn off propagation delay
• at 25 V/ s slew rate 10% of out voltage change 15 — 120 ns (29), (30) tDOFF_G_LS7_25 Turn off propagation delay
• at 25 V/ s slew rate 10% of out voltage change 15 — 120 ns (29), (30) RPD_LS7/8 G_LS7/8 to PGND pull-down resistor 25 50 90 k  Slew rate control low-side 7 and 8 RDS_HSX_P (00) G_LS7/8 pMOS RDS(on) (00) 1500 V/ s 2.6 5.0 10.7  RDS_HSX_N (00) G_LS7/8 nMOS RDS(on) (00) 1500 V/ s 0.5 1.1 2.9  RDS_HSX_P (01) G_LS7/8 pMOS RDS(on) (01) 300 V/ s 7.5 14.6 31.3  RDS_HSX_N (01) G_LS7/8 nMOS RDS(on) (01) 300 V/ s 2.5 5.9 16.5  RDS_HSX_P (10) G_LS7/8 pMOS RDS(on) (10) 50 V/ s 61 85 115  RDS_HSX_N (10) G_LS7/8 nMOS RDS(on) (10) 50 V/ s2 3 3 5 5 0  RDS_HSX_P (11) G_LS7/8 pMOS RDS(on) (11) 25 V/ s 122 170 230  RDS_HSX_N (11) G_LS7/8 nMOS RDS(on) (11) 25 V/ s 47 69 100  Notes 29. Guaranteed by design. 30. C LOAD = 4.7 nF; R G = 40.2  VCCP = 7.0 V

Table 9. High-side VDS/SRC monitor electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• DC voltage
• Transients t < 400 ns
• Transients t < 800 ns -3.0 -6.0 -8.0 V (31) VVBATT_VDS High-side VDS/SRC monitoring functional range S_HSx
• Full functionality
• Limited functionality (V DS_HS_Th 3.5 V is at 3.0 V min) 5.5 5.0 5.5 V VVBOOST_VDS High-side VDS/SRC monitoring functional range VBOOST
• Full functionality
• Limited functionality (V DS_HS_Th 3.5 V is at 3.0 V min) 5.5 5.0 5.5 V Notes 31. Guaranteed by design.

Table 8. High-speed low-side pre-driver electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

21 NXP Semiconductors

• V VBATT_VDS = 5.5 V to 72 V, V VBOOST_VDS = 5.5 V to 72 V
• V VBATT_VDS = 5.0 V to 5.5 V, V VBOOST_VDS = 5.0 V to 5.5 V 3.23 3.00 3.45 3.45 3.67 3.67 V tTH_HSVDS High-side VDS/SRC threshold settling time — 0.4 1.0 s VSRC_HS_TH (0000) High-side VSRC threshold (0000) -0.03 0.0 0.03 V VSRC_HS_TH (1001) High-side VSRC threshold (1001) 0.07 0.10 0.13 V VSRC_HS_TH (1010) High-side VSRC threshold (1010) 0.155 0.2 0.245 V VSRC_HS_TH (1011) High-side VSRC threshold (1011) 0.25 0.3 0.35 V VSRC_HS_TH (1100) High-side VSRC threshold (1100) 0.345 0.4 0.455 V VSRC_HS_TH (0001) High-side VSRC threshold (0001) 0.44 0.5 0.56 V VSRC_HS_TH (0010) High-side VSRC threshold (0010) 0.9 1.0 1.1 V VSRC_HS_TH (0011) High-side VSRC threshold (0011) 1.35 1.5 1.65 V VSRC_HS_TH (0100) High-side VSRC threshold (0100) 1.8 2.0 2.2 V VSRC_HS_TH (0101) High-side VSRC threshold (0101) 2.38 2.55 2.72 V VSRC_HS_TH (0110) High-side VSRC threshold (0110) 2.85 3.0 3.15 V VSRC_HS_TH (0111) High-side VSRC threshold (0111) 3.33 3.5 3.68 V

Table 9. High-side VDS/SRC monitor electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.7 Low-side VDS VSRC monitoring electrical characteristics

Table 10. Low-side V DS/SRC monitor electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• DC voltage
• Transients t < 400 ns -3.0 -8.0 V V DS_LS_TH (0000) Low-side VDS threshold (0000) -0.03 0.0 0.03 V VDS_LS_TH (1001) Low-side VDS threshold (1001) 0.07 0.10 0.13 V VDS_LS_TH (1010) Low-side VDS threshold (1010) 0.155 0.2 0.245 V VDS_LS_TH (1011) Low-side VDS threshold (1011) 0.25 0.3 0.35 V VDS_LS_TH (1100) Low-side VDS threshold (1100) 0.345 0.4 0.455 V VDS_LS_TH (0001) Low-side VDS threshold (0001) 0.44 0.5 0.56 V VDS_LS_TH (0010) Low-side VDS threshold (0010) 0.9 1.0 1.1 V VDS_LS_TH (0011) Low-side VDS threshold (0011) 1.35 1.5 1.65 V VDS_LS_TH (0100) Low-side VDS threshold (0100) 1.8 2.0 2.2 V VDS_LS_TH (0101) Low-side VDS threshold (0101) 2.38 2.5 2.63 V VDS_LS_TH (0110) Low-side VDS threshold (0110) 2.85 3.0 3.15 V VDS_LS_TH (0111) Low-side VDS threshold (0111) 3.33 3.5 3.68 V tTH_LSVDS Low-side VDS threshold settling time — 0.4 1.0 s (32) Low-side VDS monitor D_ls7/D_ls8 for DC/DC VD_LSX_VDS Low-side VDS voltage range D_LSx -3.0 — 75 V VDS_LS_TH_DC (0100) Low-side VDS threshold for DC/DC (0100) 1.8 2.06 2.2 V VDS_LS_TH_DC (0101) Low-side VDS threshold for DC/DC (0101) 2.25 2.5 2.75 V tVDS_DCDC_PD Comparator propagation delay time — — 50 ns (32) RVDS_78_IN Input impedance VDS_78 200 350 — k  Notes 32. Guaranteed by design.

23 NXP Semiconductors

5.8 Load bias electrical characteristics

Table 11. Load bias electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• V BATT > 8.0 V, V CC5 > 4.75 V
• V BATT < 8.0 V, V CC5 > 4.75 V 3.8 (VBATT/2) -200 mV (VBATT/2) VCC5 (VBATT/2) 200 mV V RBIAS_LS Equivalent resistance of LS current source Notes 33. Current source can be connected to maximum two D_LSx 34. Current source can be connected to maximum three D_LSx 35. Current source can be connected to maximum five D_LSx

5.9 Current measurement electrical characteristics

5.9.1 Current measurement for positive current

• Current measurement channel 1- 4
• Differential amplifier 1- 4
• DAC 1- 4
• Comparator 1- 4
• Current measurement channel 5 - 6
• Differential amplifier 5 - 6
• DAC 5 - 6H and DAC 5 - 6L
• Comparator 5 - 6H and 5 - 6L

Table 12. Current measurement for positive currents

• at GDA_diff (00) = 5.8
• at GDA_diff (01) = 8.7
• at GDA_diff (10) = 12.6
• at GDA_diff (11) = 19.3 ±3.5 ±3.5 ±3.5 ±3.5 (36), (37) At DAC range of 25% to 75%, after analog offset compensation
• at GDA_diff (00) = 5.8
• at GDA_diff (01) = 8.7
• at GDA_diff (10) = 12.6
• at GDA_diff (11) = 19.3 ±5.3 ±5.3 ±5.3 ±5.3 (36), (37) Notes 36. Guaranteed by design. 37. The tolerance of the 10 m  shunt resistor is assumed as ±2.0% (at 4.5 ). All other input tolerances from the device specification are assumed at 6 .

Table 13. Differential amplifier 1, 2, 3, 4, 5, and 6 the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• G DA_DIFF(00) = 5.8 -25.9 — 387 mV VDA_DIFF_IN (01) Differential input voltage range (01)
• G DA_DIFF(01) = 8.7 -17.3 — 258 mV VDA_DIFF_IN (10) Differential input voltage range (10)
• G DA_DIFF(10) = 12.6 -12 — 179 mV VDA_DIFF_IN (11) Differential input voltage range (11)
• G DA_DIFF(11) = 19.3 -7.8 — 116 mV GDA_DIFF (00) Differential voltage gain (00) 5.71 5.79 5.87 GDA_DIFF (01) Differential voltage gain (01) 8.55 8.68 8.81 GDA_DIFF (10) Differential voltage gain (10) 12.32 12.53 12.74

25 NXP Semiconductors

• 1.0 V common mode voltage 10 — 26 k  RVSENSEPX_IN Input impedance VSENSEPx (x = 1…4)
• 1.0 V common mode voltage 10 — 26 k  CVSENSE Differential amplifier EMI filter C. It is recommended to place a filter C between VSENSEN and P close to the IC for EMI. — 330 — pF VDA_BIAS Output bias voltage 240 250 265 mV VDA_OUT_OFF Maximum output offset voltage error at maximum gain -140 — 220 mV VDA_OUT Differential amplifier x output voltage range 0.1 — 2.7 V DAC 1, 2, 3, 4, 5L, 5H, 6H, and 6L (8-bit) VDAC_LSB DAC LSB — 9.77 — mV VDAC_OUT_MIN DAC minimum output voltage
• DAC code = 0h — 0.0 — V VDAC_OUT_MAX DAC maximum output voltage
• DAC code = FFh — 2.49 — V DAC_DNL DAC differential linearity error -0.5 — 0.5 LSB DAC_INL DAC integral linearity error -1.0 — 1.0 LSB VDAC_OUT_OFF DAC maximum output offset 0.0 — 10 mV tDAC DAC settling time — — 0.9 s Voltage comparator 1, 2, 3, 4, 5H, 5L, 6H, and 6L VCOMP_IN Comparator input voltage 0.0 — 2.7 V VCOMP_IN_OFF Comparator input offset voltage -25 — 10 mV Current measurement channel 1, 2, 3, 4, 5, and 6 detection delays tD_CS Detection delay coming from differential amplifier and comparator at GDA_DIFF(00) = 5.8 20 500 ns (38) Notes 38. Guaranteed by design.

Table 13. Differential amplifier 1, 2, 3, 4, 5, and 6 (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.9.2 Current measurement for negative currents

• Current measurement channel 5 and 6
• Differential amplifier 5 and 6 negative
• DAC 5 and 6 negative
• Comparator 5 and 6 negative Differential amplifier 1, 2, 3, 4, 5L, 5H, 6L and 6H analog offset compensation VOFFDAC_OUT_MAX _POS VOFFDAC_OUT_MAX _NEG Offset compensation voltage range referred to amplifier output offset at maximum gain
• Offset DAC value = +31
• Offset DAC value = -31 150 -310 310 -150 mV (40) VOFFDAC_LSB Offset compensation step size referred to amplifier output offset at maximum gain 5.0 — 10 mV VCS_OFF_TEMP Differential amplifier output offset temperature drift -5.0 -50 5.0 LSB mV (39) VCS_OFF_GD Residual offset after offset compensation at diff amplifier output for path shunt  comparator output -0.61 -6.1 0.39 3.9 LSB mV (41) tOFFCOMP_STEP Offset compensation minimum step time — — 2.0 s (40) tOFFCOMP Offset compensation runtime to finish compensation — — 2.0*31 = 62 s (40)(42) Notes 39. Guaranteed by design. 40. Gain set to G DA_DIFF(11) = 19.3 41. The offset compensation algorithm is implemented so the compensation always stops when the comparator output signal is low, assuming a zero DAC gain error and INL. 42. Assuming the start from an offset compensation DAC value of 0 is worst case, it has to go to one extreme value (-31 or 31).

Table 14. PT2000 static electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• at DAC range of 75% to 100% at G DANEG_DIFF = -2.0
• at DAC range of 25% to 75% at G DANEG_DIFF = -2.0 4.4 8.9 % (43), (44) Differential amplifier 5, 6 negative VVSENSEN5/ 6_DANEG Differential amplifier 5 and 6 negative (negative currents) functional range VSENSE N5/6 -3.0 — 1.0 V (43) VVSENSEP5/ 6_DANEG Differential amplifier 5 and 6 negative (negative currents) functional range VSENSE P5/6 -4.2 — 1.0 V (43) VDANEG_DIFF_IN Differential input voltage range
• G DANEG_DIFF = -2.0 -1.125 — 0.0 V (43) GDANEG_DIFF Differential voltage gain -1.966 -2.0 -2.034 RVSENSEN5/6_IN Input impedance VSENSE N5/6
• 1.0 V common mode voltage 6.0 — 14 k 

the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

27 NXP Semiconductors

• 1.0 V common mode voltage 6.0 — 14 k  VDANEG_IN_OFF Differential amplifier maximum input offset voltage -20 — 20 mV VDANEG_BIAS Output bias voltage 240 250 265 mV VDANEG_OUT_OFF Maximum output offset voltage error, including amplifier input offset and bias voltage offset. -60 — 60 mV VDANEG_OUT Differential amplifier x output voltage range 0.0 — 2.7 V DAC 5 Neg and 6 Neg (4 Bit) VDACNEG_LSB DAC LSB — 156.3 — mV VDACNEG_OUT_MIN DAC minimum output voltage
• DAC code = 0h — 0.0 — V VDACNEG_OUT_MAX DAC maximum output voltage
• DAC code = Fh — 2.344 — V DACNEG_GAIN DAC maximum gain error
• Error of bandgap reference voltage -1.0 — 1.0 % DACNEG_DNL DAC differential linearity error -0.063 — 0.063 LSB DACNEG_INL DAC integral linearity error -0.063 — 0.063 LSB VDACNEG_OUT_OFF DAC maximum output offset 0.0 — 10 mV tDACNEG DAC settling time — — 0.9 s Voltage comparator 5 Neg and 6 Neg VCOMP_IN Comparator input voltage 0.0 — 2.7 V VCOMP_IN_OFF Comparator input offset voltage -25 — 10 mV Current measurement channel 5 Neg and 6 Neg detection delays tD_CSNEG Detection delay coming from differential amplifier and comparator
• GDANEG_DIFF = -2.0 20 — 500 ns (45) Notes 43. Guaranteed by design. 44. The tolerance of the 10 m  shunt resistor is assumed as ±2.0% (at 4.5 ). All other input tolerances from the device specification are assumed at 6  45. Guaranteed by design.

Table 14. PT2000 static electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.10 Analog output (OAx) electrical characteristics

Table 15. Analog output static electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• without series resistor, for digital function MIN = 200 
• R MIN = 100 
• R MIN = 75 
• R MIN = 50  1.0 5.0 5.0 100 pF nF nF nF nF (46) PSRROAX OAx power supply rejection — — 103 dB (46) GOAX(00) OAx output gain (00) 1.303 1.33 1.357 GOAX(01) OAx output gain (01) 1.940 2.0 2.060 GOAX(10) OAx output gain (10) 2.91 3.0 3.090 GOAX(11) OAx output gain (11) 5.17 5.33 5.49 GOAX(ADC) OAx output gain (ADC) 0.98 1.0 1.02 tOAX_GAIN OAx output gain switching time — — 2.0 s (46) VOAX_OFFSET OAx output offset voltage from OAx amplifier
• G OAx = 1.0
• G OAx = 1.33
• G OAx = 2.0
• G OAx = 3.0
• G OAx = 5.33 -14 -18 -28 -30 -53 mV R OA1/3_EN0 OA1/3 input impedance when OaENx = 0
• 2.0 V, impedance to GND — — 8000 k  ROA2_EN0 OA2 input impedance when OaENx = 0
• 2.0 V, impedance to GND 350 — 500 k  tOAX_MUX OAx multiplexer switching time — — 10 s (46) VOAX_DRIFT_ADC OAx output voltage drift of T&H in ADC mode over time
• at V OAx = 1.5 V and after 20 s -50 — 50 mV Notes 46. Guaranteed by design.

29 NXP Semiconductors

5.11 Clock / PLL electrical characteristics

Table 16. Clock / PLL electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. Divider value is changed every 10 μs
2. The following values take into account an input clock at 0.95 MHz to 1.05 MHz, a PLL multiplication factor of 47 to 49, and an output duty cycle of

Figure 4. PLL, DRAM/CRAM system clock

5.12 Digital input/output electrical characteristics

Table 17. PT2000 static electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• I OUT > -1.0 mA, no higher current at other I/Os VCCIO -0.3 — — V VOL_IO Digital pins low output voltage (IRQB, MISO, START1-7, FLAG0-3, DBG)
• I OUT < 1.0 mA, no higher current at other I/Os — — 0.3 V VOH_ START8/FLAG4 Digital pins high output voltage (Start8, Flag4)
• I OUT > -200 A VCC0 -0.6 — — V VOL_ START8/FLAG4 Digital pins low output voltage (Start8, Flag4) VOH_OA2 Digital pins high output voltage (OA2)
• G OAx = 1.33, IOUT > -1.0 mA
• G OAx = 2.0, IOUT > -1.0 mA 2.8 VCC5 -0.6 V VOL_OA2 Digital pins low output voltage (OA2), IOUT < 0.5 mA — — 0.3 V tR_XXX Digital pins output rise time (IRQB, START1-7, FLAG0-3, DBG)
• C LOAD = 30 pF, 10%-90% of out voltage 3.0 — 12 ns tF_XXX Digital pins output fall time (IRQB, START1-7, FLAG0-3, DBG)
• C LOAD = 30 pF, 90%-10% of out voltage 3.0 — 12 ns tD_XXX Digital pins output delay (IRQB, START1-7, FLAG0-3, DBG)
• C LOAD = 30 pF, 10% of out voltage 2.0 — 10 ns

31 NXP Semiconductors

• C LOAD = 30 pF with V CCIO = 3.3 V
• C LOAD = 30 pF with V CCIO = 5.0 V 1.4 2.0 s (50) tF_OA2 Digital pins output fall time (OA2), 90%-10% of out voltage
• C LOAD = 30 pF with V CCIO = 3.3 V
• C LOAD = 30 pF with V CCIO = 5.0 V 1.4 3.2 s (50) tD_OA2 Digital pins output delay (OA2), 10% of out voltage
• C LOAD = 30 pF with V CCIO = 3.3 V
• C LOAD = 30 pF with V CCIO = 5.0 V 2.7 3.0 s (50) tR_START8/FLAG4 Digital pins output rise time (START8, FLAG4)
• CLOAD = 30 pF, 10%-90% of out voltage 60 — 200 ns (50) tF_START8/FLAG4 Digital pins output fall time (START8, FLAG4)
• CLOAD = 30 pF, 90%-10% of out voltage 60 — 200 ns (50) tD_START8/FLAG4 Digital pins output delay (START8, FLAG4)
• CLOAD = 30 pF, 10% of out voltage 5.0 — 20 ns (50) CPIN_XXX Digital pins equivalent pin capacitance (IRQB, STARTx, FLAGx, DBG) — — 10 pF (50) CPIN_MISO Digital pin equivalent pin capacitance (MISO) — — 10 pF (50) CPIN_MOSI Digital pin equivalent pin capacitance (MOSI) — — 10 pF (50) Pull-up/down resistors RW_PU/PD Weak pull-up/down resistor 200 480 800 k  RPU/PD Pull-up/down resistor 50 120 200 k  Notes 50. Guaranteed by design.

Table 17. PT2000 static electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.13 Serial peripheral interface electrical characteristics

Figure 5. SPI timing Table 18. SPI electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

33 NXP Semiconductors

• CL = 30 pF
• CL = 75 pF
• CL = 150 pF ns tF_MISO_S3.3 MISO fall time slow setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF ns tR_MISO_F3.3 MISO rise time fast setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 1.5 2.7 4.4 13.4 17.1 23.9 ns tF_MISO_F3.3 MISO fall time fast setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 1.5 2.7 4.4 13.4 17.1 23.9 ns SPI MISO driver with VCCIO = 5.0 V tR_MISO_S5.0 MISO rise time slow setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 9.0 ns tF_MISO_S5.0 MISO fall time slow setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 9.0 ns tR_MISO_F5.0 MISO rise time fast setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 1.1 2.1 3.6 9.6 12.5 17.8 ns tF_MISO_F5.0 MISO fall time fast setting:
• CL = 30 pF
• CL = 75 pF
• CL = 150 pF 1.1 2.1 3.6 9.6 12.5 17.8 ns

the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6 Functional block description

6.1 Power supplies

6.1.1 VCC5

in any overvoltage condition at this pin. This is done to guarantee 36 V robustness of the VCC5 pin. microcontroller as soon as uv_vcc5 is asserted.

6.1.2 VCCIO

The interfaces toward the ECU microcontroller uses the VCCIO voltage for the output drivers and receives the same levels on its inputs. Note that the DRVEN and RESETB input pins can operate with an input level of 5.0 V, even when VCCIO is 3.3 V.

6.1.3 VCC2P5 regulator

to digital ground (DGND pin). signal (VCC2P5) is asserted to the logic core after a delay of tD_PORESETB and resets the logic core and all device internal modules. Figure 6. PORESETB

35 NXP Semiconductors

6.1.4 VCCP regulator

6.1.4.1 Internal V CCP (vccp_ext_en='0')

The voltage source at the VBATT input pin provides power for the VCCP regulator. This integrated linear regulator provides typically 7.0 V at the VCCP pin, to supply the pre-driver section of the device. The regulator uses low drop out features to extend the system's operating range when VBATT temporarily falls below its normal operating range, for example during engine crank conditions. This avoids problems caused by insufficient gate voltage, such as slow MOSFET switching and increased on-state losses. A capacitor (4.7 F recommended) is required at the VCCP pin to provide the high peak currents required when charging a MOSFET gate. At low VCC5, the regulator may be active, but with an increased dropout voltage. The low dropout mode of the regulator is active only when the voltage at VCC5 is above the VCC5 undervoltage threshold VUVVCC5+. If VCC5 is not present or low, POResetB is active and disables the VCCP regulator. VCCP during bootstrap initialization: 1. If the DBG pin is not used as a digital I/O, the DBG pin logic level is ‘1’ during reset due to the device internal weak pull-up resistor. As result, the internal VCCP regulator is switched on during the HS pre-driver bootstrap initialization phase. (refer to See Power-up sequence VCCP and bootstrap capacitors on page 58). 2. If the DBG pin is used as a digital I/O. This means the DBG pin logic level is undefined during reset and may be '0'. As resu lt, the internal VCCP regulator's On status during HS pre-driver bootstrap init phase can only be guaranteed if vccp_ext_en is set to '0'. The bit has to be configured as soon as possible during device init, to start the pre-charging of the bootstrap capacitors soon enough (refer to Table 148, Driver_config_Part 2 (1A6h)). Note that this regulator also needs a charge pump voltage coming from the VBOOST pin. Due to this, the VCCP regulator is not functional when the voltage on the VBOOST pin is below 4.7 V.

6.1.4.2 External V CCP (vccp_ext_en='1')

The VCCP can also be powered by an external voltage source connected to the VCCP pin. The internal VCCP regulator is sized for 12 V system operation, including the ISO voltage transients specified for those systems. But for 24 V system operation, the internal VCCP linear regulator dissipates too much power. In this case, the internal VCCP regulator should be switched off by setting the vccp_ext_en bit of the driver_config_part2 register (1A6h) to '1' and an external regulator needs to be used. VCCP during initialization VCCP: 1. If is not possible to turn on the internal V CCP regulator for a limited time in parallel to the external voltage source, the DBG pin has to be tied to logic level '0' and the SPI configuration bit has to stay at '1', to strictly avoid the internal regulator to be switched on at any time. The logic level of the DBG pin should be forced by a pull-down resistor towards GND. 2. On the other hand, if it is possible to switch on the internal regulator for some limited time in parallel with the external voltage supply without destroying it, no special measures have to be taken during startup. After bootstrap initialization, the vccp_ext_en bit has to be set to '1' (refer to Table 148, Driver_config_Part 2 (1A6h)).

6.1.4.3 V CCP undervoltage

VCCP voltage is internally monitored by a voltage comparator to detect if it is in the operating range. In case of an undervoltage when falling below the lower threshold, the gate driver outputs are switched off by the digital core. This prevents possible malfunctions and/or failures: in case of an undervoltage, operations are stopped before any malfunction, due to insufficient gate driver supply voltage. Moreover, in case of a battery voltage disconnection, all MOSFETs are switched off (and therefore inductive loads are disconnected) before the electrolytic capacitors on the VBATT line are completely discharged. This prevents any negative voltage on the VBATT line, which may cause failures on the VBATT, VCCP, D_HSx and B_HSx pins due to exceeding its maximum ratings.

6.1.5 Battery voltage monitor

the battery voltage measurements. The result is available both via a SPI register and the internal microcore memory map. Figure 7. Battery voltage monitoring The battery voltage threshold can be calculated using the following formula. Table 19 shows some example values.

6.1.6 Boost voltage monitor

• A high accuracy internal voltage divider dividing the voltage at the VBOOST pin to a smaller level V BOOST_DIV
• A programmable DAC (8 bits) either by the SPI (refer to Table 113. Boost_dac (17Fh)) or by microcode creating a reference voltage
• A comparator comparing the reference voltage with the V BOOST_DIV

Table 19. V BAT voltage DAC values

37 NXP Semiconductors

Figure 8. Boost voltage monitor block diagram VBOOST pin is less than its undervoltage lockout threshold, which is around 4.7 V. VBOOST pin is used to detect battery undervoltage.

6.1.6.1 Application with V BOOST voltage

The boost voltage threshold can be calculated using the following formula. Table 20 shows some example values.

• V BOOST = (DAC_VALUE * 312.5 mV) Due to the compensation, concept values below 08h should not be used. Values higher than E1h must not be used, because this results in a boost voltage higher than 72 V which destroys the device. The real maximum value for the boost set point threshold in the application is even lower due to dynamic effects like voltage drop in the boost capacitor. It is not recommendable to use a DAC value above D0h (65 V).

Table 20. Boost voltage DAC values

6.1.6.2 Application without boost voltage

For this purpose, it is possible to change the internal voltage divider ratio from 1/32 to 1/4 by setting the signal boost_mon_en high. To detect undervoltage and use the signal uv_vboost to disable the pre-drivers, the uv_vboost bit needs to be set to “1” (refer to Table 162, driver_status (1B2h)). The uv_vboost signal goes high as soon as the voltage at the VBOOST pin is below the threshold, if the VBOOST UV monitor is enabled (Vboost_disable_en = 1). The same digital filter used for the VBOOST voltage measurement is also used for the VBOOST UV monitoring mode. The DAC set point value in this mode has to be chosen to fulfill two requirements:

• The pre-drivers must not be disabled at a battery voltage above 5.0 V
• The device internal charge pump only works properly down to a battery voltage of 4.7 V The VBOOST UV threshold can be calculated using the following formula.
• V BOOST = (DAC_VALUE * 39.1 mV)

6.1.7 Charge pump

The PT2000 provides one charge pump with independent outputs for each of the seven high-side drivers. The independent outputs allow complete flexibility of the topology used, meaning all high-sides can drive MOSFETs with the drain connected to VBOOST or VBAT. But there is a limitation on the diagnostics only HS2, 4, and 6 can use the VBOOST for monitoring (for example, VBAT or VBOOST). In most operating topologies and conditions, the bootstrap is the primary source of charge for the bootstrap capacitor, and the charge pump sustains the voltage at each bootstrap capacitor when it is not being charged by low-side switching. This charge pump allows 100% duty cycle operation of the high-side MOSFETs while the bootstrap circuitry is not operating (VS_HSx voltage never goes significantly below the VCCP voltage). In this condition, the charge pump provides current maintaining each bootstrap capacitor charged via independent current sources, to guarantee a minimum VGS voltage. The charge pump, supplied by VBOOST, creates gate drive voltages of about 8.0 V greater than the voltage at VBOOST. However, their current capacity is sufficient only for low frequency switching. The charge pump is not running as long as the POResetB reset signal is active. The internal CP can be used to charge the bootstrap capacitors during init with a guaranteed current of 20 A per HS pre-driver. This current is only available if there is no leakage current from B_HSx pin. Any possible leakage current has to be subtracted from this available charge current (See Using the charge pump to charge bootstrap capacitors on page 59).

6.2 Clock subsystem

The digital logic is supplied by a clock (cksys) generated by the PLL from the 1.0 MHz clock forced externally on CLK pin. Two internal clocks are derived from the PLL:

• the main logic clock cksys
• the code RAM clock cksys_cram inverted in respect to cksys
• the Data RAM clock cksys_dram inverted in respect to cksys If an unsuitable signal is applied on the CLK pin, the device automatically switches to the internal backup clock. The PLL output frequency can be modulated for EMC purposes. Modulation activation is enabled by default, but can be disabled by the SPI. Refer to Table 151 PLL_Config (1A7h).

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6.3 High-side pre-driver

logic level MOSFETs. These pre-drivers are dedicated to load driving like injectors or solenoids, and integrate diagnostics features. is described in the next chapter, only HS2, 4, and 6 can use VBOOST voltage for diagnostics. Figure 9. High-side pre-driver block diagram

• Logic command coming from channel logic (hsx_in)
• VCCP undervoltage signals (uv_vccp) from VCCP UV monitor: in case of an undervoltage, the external MOSFET is switched off
• VCC5 undervoltage signals (uv_vcc5) from VCC5 UV monitor: in case of an undervoltage, the external MOSFET is switched off
• VBOOST undervoltage signals (uv_vboost) from boost voltage monitor: in case of an undervoltage, the external MOSFET is switched off if this feature is enabled (refer to Table 162, driver_status (1B2h)
• Signal cksys_drven coming from the clock monitoring: in case of a missing clock (PLL not locked), the external MOSFET is switched off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152, backup_clock_status (1A8h))
• At the high-side pre-driver block signal, DrvEn is added to the control signal for the driver. As long as the DrvEn signal is negated (low), the high-side pre-driver is switched off. The high-side pre-driver 5 and 7 include a feature to override the switch off path via the DrvEn signal. As long as the signal hsx_en_ovr is high (only for HS5 and HS7), the pre-driver is not influenced by DrvEn. (refer to Table 178, HSx_output_config (1DA, 1DDh, 1E0h, 1E3h, 1E6h, 1E9h))

The truth table describing the status of hsx_command signal is given in Figure 21.

• When the hsx_command is high, the G_HSx pin is driven high (pull-up to B_HSx voltage);
• When the hsx_command is low, the G_HSx pin is driven low (pull-down to S_HSx voltage).

6.3.1 High-side pre-driver slew rate control

on the used MOSFET and the additional gate circuit (refer to Slew rate high-side and low-side selection register).

6.3.2 Safe state of high-side pre-driver

RPD_HSX between G_HSx and S_HSx of about 1.0 M keeps the external MOSFET in the off state even when the bootstrap voltage is low. Table 21. High-side pre-driver truth table Table 22. Slew rate settings for HS pre-drivers

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6.3.3 High-side pre-drivers in low-side configuration

so the VDS monitoring for this low-side MOSFET is not functional. Figure 10. High-side pre-driver in low-side configuration

6.4 High-side VDS and VSRC monitor

6.4.1 HS1, 3, 5, 7 V DS monitoring

Figure 11. High-side 1, 3, 5, and 7 VDS VSRC and LS1-6 VDS monitoring monitors of HS pre-driver 1, 3, 5, and 7 is shown in Figure 11. threshold selection). Selectable values are shown in Table 23.

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6.4.2 HS2, 4, 6 V DS monitoring

Figure 12. VDS monitors and load biasing HS2, 4, and 6 DS monitors of HS pre-driver 2, 4, and 6 is shown in Figure 12. threshold selection). Selectable values are shown in Table 23. Table 23. V DS monitor threshold selection

compared to the S_HSx voltage.

6.5 Low-side pre-driver (LS1-6)

Figure 13. Low-side pre-driver block diagram power on reset state (RSTB low). MOSFET in low-side configuration. The logic command lsx_command, to switch the external MOSFET, is provided by the digital block.

• Logic command coming from channel logic (lsx_in).
• V CCP undervoltage signals (uv_vccp) from the VCCP UV monitor: In case of an undervoltage, the external MOSFET is switched off.
• V CC5 undervoltage signals (uv_vcc5) from VCC5 UV monitor: In case of an undervoltage the external MOSFET is switched off. 0100 2.0 0101 2.5 0110 3.0 0111 3.5

Table 23. V DS monitor threshold selection (continued)

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• Signal cksys_drven coming from the clock monitoring: In case of a missing clock (PLL not locked), the external MOSFET is switched off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152, backup_clock_status (1A8h)).
• For safety purpose DRV_EN is added to the control signal for the driver. As long as DRV_EN signal is negated (low) the low-sid e pre-driver is switched off. The low-side pre-driver 6 includes a feature to override the switch off path via the DRV_EN signal (refer to Table 174, LSx_output_config (1C2h, 1C5h,1C8h, 1CBh, 1CEh, 1D1h)). The truth table describing the status of lsx_command signal is given in Table 24. The pre-driver G_LSx output is set according to lsx_command:
• When lsx_cmd is high, the G_LSx pin is driven high (pull-up to V CCP voltage)
• When lsx_cmd is low, the G_LSx pin is driven low (pull-down to PGND voltage)

6.5.1 Low-side pre-driver slew rate control

used MOSFET and the additional gate circuit.(refer to Slew rate high-side and low-side selection register). Table 24. Low-side pre-driver truth table Table 25. Slew rate settings for LS pre-drivers 1-6

6.5.2 LS1 - LS6 V DS monitor

Figure 14. VDS monitoring LS1 to LS6 values are shown in Table 26. Table 26. Low-side VDS monitor threshold selection

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6.6 Low-side pre-driver for DC/DC converter (LS7 and LS8)

power MOSFETs used in low-side configurations. If no DC/DC is required, they can be used as general purpose low-side. Figure 15. Low-side pre-driver for DC/DC converter (LS7 and LS8) power on reset state (RSTB low). The low-side pre-drivers are supplied by VCCP voltage.

• Logic command coming from channel logic (ls7/8_in). CCP undervoltage signals (uv_vccp) from VCCP UV monitor: in case of undervoltage, the external MOSFET is switched off.
• V CC5 undervoltage signals (uv_vcc5) from VCC5 UV monitor: in case of undervoltage, the external MOSFET is switched off.
• Signal cksys_drven coming from the clock monitoring: in case of a missing clock (PLL not locked), the external MOSFET is switched off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high (refer to Table 152, backup_clock_status (1A8h)).
• For safety purpose DRV_EN is added to the control signal for the driver. As long as DRV_EN signal is negated (low) the low-side pre-driver is switched off. The low-side pre-driver for the DC/DC converter includes a feature to override the switch off path via signal DrvEn. As long as the signals ls7/8_en_ovr are high, the pre-driver is not influenced by DrvEn (refer to Table 175, LS7_output_config (1D4h) & LS8_output_config (1D7h)). The pre-driver is capable of PWM operation up to 400 kHz according to the following table. A maximum duty cycle of 100% is allowed during PWM operations.

Table 27. Low-side pre-driver LS7/8 PWM frequency and load

6.6.1 Low-side pre-driver slew rate control (LS7 and LS8)

in Table 28 and Table 29. These values are given as reference and are impacted by the external circuitry.

6.6.2 Low-side V DS monitor D_ls7/D_ls8 for DC/DC

Figure 16. Low-side 7 and 8 VDS monitor Table 28. Slew rate settings for LS pre-drivers 7/8 PMOS Table 29. Slew rate settings for LS pre-drivers 7/8 NMOS

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VDS monitor on page 46), and the other is a high-speed comparator used for the DC/DC resonant converter application.

• Input impedance of D_LSx has to be switched to low speed by setting l SX_VDS_HIGHSPEED_EN to “0” via the SPI register bit (refer to Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h))
• l SX_VDS_FBK is used for diagnostics
• Clamp voltage = 3.5 V Fast VDS monitoring (DC/DC resonant converter):
• Input impedance of D_LSx has to be switched to high speed by setting l SX_VDS_HIGHSPEED_EN to “1” via SPI register bit (refer to Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h))
• lsx_vds_dcdc is used for resonant detection
• VDS Threshold needs to be set to 2.5 V For more details on the DC/DC mode See DC/DC converter control (LS7/8) on page 61.

6.7 Current measurement

There are six total input pairs to measure currents with external shunt resistors in a four-wire configuration.

• Four general purpose blocks (#1, 2, 3, and 4).
• Two extended mode block for DC-DC converters (#5 and 6). The shunt resistors are used in low-side configuration with one of the shunt terminals tied to ground for all the blocks. This means the PT2000 measures a differential voltage over the two input pins.

6.7.1 General purpose current measurement block

Figure 17. General purpose current measurement block diagram Instruction Set). The differential amplifier also adds a constant offset to its output. Therefore, the output of the amplifier is always positive. voltage at the comparator input stable during the ADC conversion.

assumed to have a worst case error of 2.0%.

6.7.1.1 Current sense amplifier

VDABIAS is fixed value of 250 mV applied to the differential amplifier output. differential mode input voltages depend on the chosen gain value.

6.7.1.2 Current sense DAC

comparator (dac_value (7:0)). The current threshold can be calculated using the following formula. VDAC_LSB is the DAC resolution = 9.77 mV. runtime by the SPI (opampx_gain(1:0)). This gain can be selected using the instruction stgn. RSENSEX is the external sense resistor of the current measurement channel x. Table 30. Current sense DAC values with a 10 m Ω shunt

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6.7.1.3 Current measurement offset compensation

there is no current flow in the shunt of the related measurement channel. automatic and only the start and stop has to be handled by the microcore. to set the ck_ofscmp to a maximum of 500 kHz. each offset compensation decreases the offset of the current measurement amplifier independent of it being finished. Figure 18. Offset compensation block diagram

6.7.2 Current measurement for DC/DC

The inputs of the 5th and 6th current sense need to support a very wide range of applications. Typical applications use the 5th and 6th current sense e.g.

• Just identical to the other current sense blocks or
• To control a DC/DC converter with a low-side current measurement and concurrently provide an overcurrent supervision at the booster capacitor The two-point current control of a DC/DC converter results in challenging requirements on latency of the control loop. This means:
• The path from sense input to low-side driver output must achieve a very small delay
• There is no time to change the DAC setting after each switching event. G_LS7/8 oa_sel3(2:0) G OA_3 dacxl_value (7:0) VSENSEP5/6 VSENSEN5/6 DACxL curxl_fbk opampx_gain(1:0) oa_gain3(1:0) oa_en3 RSENSEx dacxh_value (7:0) DACxH curxh_fbk dacxneg_value (3:0) DACxNeg curxneg_fbk DCDC Current Measurement (x=5, 6) Diff Ampx Diff Ampx Comp xL Comp xH Comp xNeg MUX Filter xL Filter xH Filter xNeg MC33PT2000 VBAT VBOOST

Figure 19. DC/DC current measurement (5 & 6) block diagram a two-point current regulation using the cur5/6h_fbk and cur5/6l_fbk signals as inputs to directly control the LS7 or LS8 low-side driver.

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6.7.2.1 Negative current differential amplifier

gain. This is used to detect overcurrent when the low-side is Off. The current threshold can be calculated using the following formula. DAC_VALUE is selected and changed at runtime by the digital microcore by means of the signal dacx_value (3:0). VDAC LSB is the DAC resolution = 156.25 mV. VDA_BIAS is the fixed voltage biasing applied to the differential amplifier output = 250 mV. The Gain Value GDA_DIFF is fixed to -2.0. RSENSEX is the external sense resistor of the current measurement channel x.

6.7.2.2 Current measurement offset compensation

overcurrent, the differential amplifier 5 and 6 negative do not have offset compensation (see Figure 19).

6.8 OA_x output pins, multiplexer and T & H

6.8.1 General features

some special measurement functions. The maximum output voltage at the OA_x pins of VCC5 always has to be taken into account. and adding again to the amplified signal afterwards. check the connection between the PT2000 and the microcontroller ADC on the ECU level. Table 31. Boost overcurrent sense amplifier overall gain Table 32. OA_x amplifier gain selection and output voltage

Figure 20. OA_x multiplexer Analog output (OAx) configuration register on page 116).

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multiplexer can cause a glitch on the signal being processed.

6.8.2 OA_2 Pin digital I/O function

6.8.2.1 General requirements

how the enable signal is created. Table 33. OA_1 multiplexer logic table Table 34. OA_2 multiplexer truth table Table 35. OA_3 multiplexer truth table

6.8.2.2 OA_2 pin I/O voltage

6.8.3 OAx output offset and offset error

It is important to have a close look at the output offset of the OAx pins and the output voltage values corresponding to load current values. offset of 250 mV and a variable offset at the input of the OAx amplifier. considered in a full error calculation. Table 36. OA2 enable truth table Table 37. OA_2 amplifier gain selection (I/O voltage) Table 38. OAx input and output values

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7 Functional device operation

7.1 Power-up/down sequence

the slope of the voltage ramp up of the supply voltages (VCC5, VCCIO, VBATT) and the starting value.

7.1.1 Power-up sequence of VCC5, VCC2P5, and reset

Figure 21. Power-up diagram

7.1.2 Power-up sequence VCCP and bootstrap capacitors

7.1.2.1 Bootstrap switch control

• Hsx_bs_lowcurrent: the low-current limit (280 A), which is set only during init independently for each HS pre-driver;
• Vsrc_threshold: the V SRC thresholds of each HSx, which during init is set first to 0.5 V and after some time to 1.0 V. After init phase is finished the VSRC threshold returns to the value defined in the appropriate register (refer to Table 94, Vsrc_threshold_hs_Part2 (16Eh)).
• Ls_bias: all ls_bias are set active for all LSx outputs during init phase of any HS pre-driver, and then go back to the configuration defined in the appropriate register (refer to register Table 126, Ls_bias_config (18Ch)) when all HS pre-drivers are out of the init phase.
• Hs_bias: the hs_bias is set inactive for the HSx outputs during init and then returns to the configuration defined in the appr opriate register (refer to Table 125, Hs_bias_config (18Bh)). During the init phase of the bootstrap capacitors, the vccp_external_enable signal is affected according to what is defined in Table 150, VCCP external enable setting. In particular, as long as at least one HS pre-driver is in bootstrap init mode, the vccp_external_enable setting is set to '0' (internal regulator active), if the value of the DBG pin sampled at reset (POResetB and ResetB) was '1'. The charging of the bootstrap capacitors starts after reset is deactivated and as soon as the VCCP voltage is ramped up. As soon as the VCCP voltage is above the VCCP undervoltage threshold, a global timer for all hs pre-drivers running on cksys with an end of count value of 36 ms is started. As soon as the timer reaches the end of count value, the Vsrc_threshold is changed from 0.5 V to 1.0 V for all drivers still in init mode. At the same moment, the hsx_src_1V bit is set to '1' for all these drivers. The bootstrap init for each HS pre-driver ends if one of the following conditions is met:
• The bs ready comparator shows the B_HSx voltage is close to the V CCP voltage and at the same time the S_HSx voltage is below 0.5 V or 1.0 V,
• The clamp is activated and at the same time the S_HSx voltage is below 0.5 V or 1.0 V;
• An LS pre-driver connected to the same HS pre-driver is switched on and the corresponding hsx_lsx_act signal is set to '1';
• The connection between LS pre-drivers and HS pre-driver is disabled (hsx_ls_act_dis signal = '1'); or
• The same HS pre-driver is switched on. In applications where two HS pre-drivers are connected to the same node by their S_HSx pin directly or via a diode, care must be taken. It is not allowed in these configurations to turn on the hs_bias via the SPI register or the microcode command before all HS pre-drivers finished their bootstrap init. Otherwise an active hs_bias from one pre-driver may block the init of the other. The init mode of each HS pre- driver can be quit by setting the corresponding “hsx_ls_act_dis” bit to '1' (refer to Table 127, Bootstrap_charged (18Dh)). This should be done for each HS pre-driver not used in an application.

7.1.2.2 Using D_LSx pull-down sources to charge bootstrap capacitors

limitation of 280 A, plus the charge pump current of 20 A. Table 39. Charge times bootstrap Cs using D_LSx sources

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7.1.2.3 Using the charge pump to charge bootstrap capacitors

possible leakage current has to be subtracted from this available charge current. charge a bootstrap capacitor to 7.0 V using the charge pump current of 20 A.

7.1.2.4 Using LS MOSFETs to charge bootstrap capacitors

16 s delay), it is possible to switch on the LS MOSFETs.

1. Wait for some specific time after V CCP regulator is activated to ensure the VCCP output voltage has reached it's nominal value of

capacitor, this leads to a transfer of charge without crossing the VCCP_UV threshold again. Figure 22 shows this strategy. Table 40. Charge times bootstrap Cs using CP

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7.2 DC/DC converter control (LS7/8)

7.2.1 General description

DC/DC converter control modes (mode 2/3).

7.2.1.1 Mode 1 (manual mode)

7.2.1.2 Mode 2 (hysteretic control)

low. This mode is used for standard DC/DC control. Note that when this mode is used LS7, it should be paired with current sense 5 and LS8 with current sense 6. Figure 24. DC/DC mode 2: hysteretic control Table 41. DC/DC converter control modes

7.2.1.3 Mode 3 (LS7/8 resonant mode V DS monitoring)

small capacitor (~10 nF) CRES in parallel with the external MOSFET has to be connected, to avoid oscillation when the low-side is off. Table 116, Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h)). "VBOOST-VBAT" value, so a timeout is used to make sure the LS can be enabled again. this timeout period, the MOSFET activates directly by the timeout logic. Figure 25. DC/DC mode 3 resonant (threshold 2.5 V used)

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7.3 Device clock manager and PLL init

After 100 s the clock monitor is enabled, Table 42 shows different strategies to start the device.

• when the factor is 24, it is detected an invalid clock condition when it is possible to count more than 165 or less than 125 pll_output_clock cycles.
• when the factor is 12, it is detected an invalid clock condition when it is possible to count more than 84 or less than 61 pll_output_clock cycles. After requesting the switch back to the external clock reference the device cannot be accessed via the SPI (see Table 152, backup_clock_status (1A8h)) for about:
• 100 s if there is a valid external clock available
• 290 s (250 s+40 s re-lock time) if there is no valid input clock available and the device has to go back to the backup clock again. The SPI word transmitted to set the Switch to clock pin bit has to be the last word within a SPI burst.

Table 42. Device clock manager and PLL init

1.0 MHz clock at CLK

7.4 SW initialization flow

7.4.1 Power supply, reset, and clock

• Supply device
• The device needs 5.0 V supply voltage on the VCC5 pin and 3.3 V or 5.0 V supply voltage on the VCCIO pin
• A voltage at the VBATT and/or VBOOST pin is not mandatory for device initialization
• As soon as the device is properly supplied at the VCC5 pin, VCC2P5 regulator is started
• When V CC2P5 is above a specific threshold, the internal POResetB signal is deactivated
• After the internal POResetB signal is deactivated, it takes a maximum time of 100 s until the digital outputs of the device are functional
• Setup external reference clock of 1.0 MHz at the CLK pin
• The PLL is locked about 25 s after the external CLK is enabled
• If the external clock signal availability cannot be guaranteed within this period, it is recommended to reset the device via ResetB immediately, or switch to the external clock reference later via the SPI command
• Deactivate ResetB signal
• The external reset signal ResetB has to be deactivated if it has been active
• As soon as there is no POResetB and ResetB signal active, the internal reset RSTB is deactivated

7.4.2 SPI configuration

The whole SPI configuration can be done while the device is using the internal backup clock reference. The device registers are not locked after device reset.

• Check if device is accessible via the SPI
• Check if the device is accessible via the SPI by reading the ID/REV register
• Init the main configuration registers
• Init the main configuration registers including the Clock Prescaler, Flag pin setup,…
• If the application uses the internal V CCP regulator to supply the pre-drivers, this regulator must be switched on now
• Set code width
• If the microcode transmits using one single SPI burst, it is mandatory to write the code width register of each channel used
• If the microcode is transmitted using multiple bursts which include information about the number of words, the code width regi ster can also be written
• The code width must be set before setting the pre_flash_enable bit, because the checksum calculation information is required
• Download microcode
• Download microcode via the SPI for each channel used
• Set the CRC32 checksum
• Set the checksum_l/h register (32-bit) of each channel used
• Init diagnostics configuration registers
• Init I/O configuration registers
• Init channel configuration registers
• Init DRAM values for the first time
• Depending on the application and the microcode, it could be required to set up DRAM parameters of the channels used
• Set the lock bit in the device_lock register (optional)

7.4.3 Clock monitor, flash enable, and DrvEn

• Check if the device is running on an external reference clock
• It is recommended to verify the device is running on the external clock reference. This can be checked by reading a bit in the driver_status SPI register
• If the device is running on the backup clk, it is possible to switch the clock manager to external reference via a SPI command
• This is only mandatory if the external clock reference is not available in time and the device is running on the backup oscillator’s clock
• The clock manager is forced to try to switch back to the external reference by a SPI write to a dedicated bit
• SPI transfers have to be avoided when switching the clock reference. The SPI module is in reset as long as there is no valid c lock
• Do not switch the clock reference while the first checksum calculation is running
• Set the pre_flash_enable bit
• Set the pre_flash_enable bit of the used channel(s)
• This bit “freezes” the CRAM and enables the signature unit to perform the CRC32 check for the first time
• After the signature unit has finished the first CRC32 check successfully, it sets the flash_enable bit to start the microcore( s) of the used channel(s)
• The microcode should check for the flash_enable bit with a timeout ensuring the microcores are running
• Activate the DrvEn signal
• Depending on the application and the microcode, it could be required to activate the DrvEn signal if deactivated

7.5 BIST

The device has a built-in self test (BIST) for the memory (MBIST for CRAM and DRAM) and for the logic core (LBIST). The BIST can be started by the SPI (see Table 170, Bist_interface in write mode (1BDh)). A full LBIST check of the device digital core and MBIST check of the device memories can be required accessing the BIST_register in Write mode and writing a 16-bit password. This request is accepted only if all three CRAMs are unlocked. It is recommended to run MBIST and LBIST during the initialization phase, since the DRAM and CRAM are erased during BIST. After this request is performed, the LBIST and MBIST check starts and its evolution can be monitored accessing the same BIST_register in read mode.

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7.5.1 MBIST

The MBIST is started by writing the MBIST password (B157h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)).

• All 00, All 11
• All 55, All AA
• All 0F, All F0
• All 00, All FF
• All FF, All 00 While the MBIST is running the digital core of the device is functional. The SPI interface can be used. It is not possible to use the CRAM and DRAM.

7.5.2 LBIST

The LBIST is started by writing the LBIST password (0666h) to the BIST register (see Table 170, Bist_interface in write mode (1BDh)). The overall LBIST operation takes about 32 ms (at 24 MHz) to complete. The coverage of the LBIST is > 92%. is running. When the LBIST is finished, the IRQB signal goes high again. state. It is recommended to check if the LBIST result is reset to “00” to ensure the LBIST clear command was successful.

7.6 Reset sources

• the resetb input reset pin is driven low
• the poresetb (power on reset) signal generated by the internal voltage regulator, incase an undervoltage is detected on VCC2P5
• a SPIresetb request received through SPI, when the appropriate code is written to the “global reset registers” (refer to See SPIReset global reset register 1 and 2 on page 126). It is kept asserted for a fixed time (333 ns) then it is released. Reset source can be determined reading the Reset_source register (refer to Table 168, Reset_Source (1B7h)).

Figure 26. VCC2P5 and reset sources

As long as RSTB is asserted, the SPI module is also inactive. In order to understand when the device has gone out of reset state, the microcontroller should poll the device on the SPI. This can be done by either sending any message to the device and checking for the control pattern (A8h) on the MISO during the command word or by reading out any register with a reset value not equal to zero (e.g. ID register).

7.7 Cipher unit

This block has the function to secure the code downloaded by the microcontroller into the code RAM via the SPI. The data loaded at device startup must be encrypted with the suitable cipher. This block receives an encoded SPI stream and decodes it at runtime. The decoded microcode is then stored in the code RAM. This feature cannot be disabled. The cipher algorithm is re-initialized every time the code memory is selected by a write operation to the Selection register (3FFh).

7.8 Ground connections

The device integrates three separate ground pins: PGND, DGND, and AGND:

• PGND is the substrate connection and is only connected to the package exposed pad, to guarantee a low-impedance connection and get optimized EMC performances. PGND is the reference ground for the VCCP regulator, some analog functions, and all of the low-side pre-drivers. It is highly recommended to directly connect PGND to the ECU ground plane.
• DGND is the reference ground for the digital logic core. It is highly recommended to directly connect DGND to the ECU ground plane.The microcontroller as well as other logic devices communicating with the device should share the same reference ground connected to the ground plane to prevent noise.
• AGND is the ground for all the noise sensitive analog blocks integrated into the device. This pin should be connected to the a nalog ground of the ECU. A star connection is recommended to guarantee a clean analog signal acquisition of the OAX_x pins from the MCU. Due to their functionality, some analog functions are referred to PGND:
• VDS monitors the low-side drivers
• VSRC monitors the high-side drivers
• The load biasing S_HSX regulator and the D_LSx pull-down All the ground pins of the device should be connected to the same ground voltage. Even during transient conditions, the voltage difference between PGND, DGND, and AGND must be limited to 0.3 V. The layout of the ground connection of the ECU should be carefully designed to limit the ground noise generated as much as possible, for instance during fast switching of the external power MOSFETs. The decoupling and filter capacitors at the different supply voltage pins should be implemented as described by the following:
• VCC5 to AGND
• VCCIO to DGND
• VCC2P5 to DGND
• VCCP to PGND
• VBATT to PGND
• VBOOST to AGND or PGND

7.8.1 Detection of missing GND connections

The PT2000 can detect any single or multiple missing connection of any ground pin (PGND, DGND, AGND) of the device. At least one ground must remain connected to allow the loss of ground detection. If the ground disconnection is detected, the internal signal uv_vccp is asserted and all the pre-drivers are disabled. The ground lost detection is filtered to allow the device to work in a proper way for a time of typically tFILTER_UVVCCP via the uv_vccp signal.

7.9 Shutoff path via the DrvEn pin

The device includes a shutoff path via the DrvEn pin, which is used to safely disable the solenoid injection power stage in a fault condition of the ECU. When the DrvEn pin is negated, all pre-drivers (w/o configuration option for DrvEn) must be switched off. Status of the DRVEN pin can be read back by the SPI (refer to Table 162). The shutoff path also works in a defined way (switch off all pre-drivers) when DrvEn is negated, even when the PT2000 is stressed with a voltage of up to 36 V at the supply and/or microcore interface (SPI, Startx,…) pins. Digital interface pins of the PT2000 are self-protected against a voltage of up to 36 V: CLK, IRQB, ResetB, DrvEn, MISO, MOSI, SCLK, CSB, Dbg, Startx (7x), Flagx (4x), OA_x (3x).

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7.9.1 DrvEn shutoff path of the high-side pre-driver

of independence, because there is a direct wire from this pin to the HS pre-driver input and the failure rate of this functionally is very low.

• Missing clock signal for the device digital core
• Missing supply voltage for the device digital core
• Missing supply voltage of level shifter
• Missing supply voltage (V BS) of HS pre-driver
• Single damaged pre-driver

7.9.2 DrvEn Shutoff path of the low-side pre-driver

independence, because there is a direct wire from this pin to the HS pre-driver input and the failure rate of this functionally is very low.

• Missing clock signal for the device digital core
• Missing supply voltage for the device digital core
• Missing supply voltage VCCP of LS pre-driver
• Single damaged pre-driver

Table 43. DrvEn path for HS pre-drivers Direct wire from the DrvEn pin to the HS pre-driver input. High independence and low FIT rate. Configuration option for the DrvEn path. The signal is routed via the digital core only. Table 44. DrvEn path for LS pre-drivers Direct wire from the DrvEn pin to the LS pre-driver input. High independence and low FIT rate. Configuration option for the DrvEn path. The signal is routed via the digital core only.

8 Digital core

structures for HW configuration, and the communication interface with the ECU microcontroller. runtime of one microcore is not influenced by RAM access from the SPI or the other microcores.

8.1 Logic channels description

• Two 16-bit processing units (microcores) having a specific programming model
• One Code RAM - 1023 x 16-bit. The memory dedicated to microcode storage is shared between the two microcores of logic channel
• One Data RAM - 64 x 16-bit. The memory dedicated to variable storage is shared between the two microcores of a logic channel Figure 27 describes logic channel 1. The other channels are identical.

Figure 27. Logic channel 1 diagram

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8.1.1 Microcores

communicate with each other by a flag bus. Figure 28. Microcore block diagram For further detail on how to program the microcores, (reference Programming Guide and Instruction Set).

8.1.2 Dual microcore arbiter

• the two microcores
• the signature unit (code RAM only)
• the SPI interface

8.1.2.1 Access sequence to code RAM

When the device is operating in single microcore mode, access slots to code RAM are granted according to Table 45. in dual microcore mode, access slots to Code RAM are granted according to Table 46. the DRAM access (See Access sequence to data RAM on page 71). Table 45. Code RAM access sequence (single microcore mode) Table 46. Code RAM Access Sequence (dual microcore mode)

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8.1.2.2 Access sequence to data RAM

When the device is operating in single microcore mode, access slots to data RAM are granted according to Table 47. Note that when ck_per is equal to 1 and dual microcore mode is enabled, there are some limitations for the DRAM access. from the microcores for the SPI. can access (load, store instructions). This limit depends on the SPI frequency used in the application. As a consequence, the microcore 0 and 1 must not block the DRAM access slots for longer than the given number of ck cycles minus 1. If this limit is achieved, it automatically be reported by the NXP IDE (compiler). Table 47. Data RAM access sequence (single microcore mode) Table 48. Data RAM Access Sequence (dual microcore mode)

access, which could occur based on a given SPI baud rate.

8.1.3 Signature unit

The task of the signature unit is to compute a checksum of the CRAM to detect possible memory corruption. during the init phase through the SPI and calculated automatically by the PT2000 IDE. microcores accessing the same CRAM are disabled. checksum causes only a warning (set the appropriate bit in the flash_enable register) without disabling code execution. The signature unit works only for a code width of 3 or larger. If a shorter code of 1 to 2 words is used, the signature unit has to be disabled.

8.1.4 SPI backdoor

It is also possible to access (both to read and to write) to all the registers normally accessible through the SPI by using an SPI backdoor. be changed while the operation is in progress. “SPI data” address of the internal memory map.

• First of all, it is only possible to write to SPI registers which are not locked at the moment the write operation “wrspi” is requested.
• For some special registers there are additional limitations dependant on the configuration of the device. Table 51 shows the different limitations.

Table 49. SPI baud rate and DRAM access sequence for the ck_prescaler = “1”

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SPI address mode (set using “slsa” instruction) must not be changed while the operation is in progress.

8.1.5 CRAM

microcore1 if dual microcore mode is enabled). Table 69, uc1_entry_point (10Bh, 12Bh, 14Bh)).

8.1.6 DRAM

be accessed by the external microcontroller and both microcores. Table 50. Cycles for SPI backdoor read/write Table 51. SPI backdoor access limitation VDS and VSRC values are ignored.

8.2 Serial peripheral interface

The communication between the PT2000 and the main microcontroller is managed with a 16-bit SPI interface. This block is the module providing the SPI connection features. The block is full-duplex, so it can receive and transmit at the same time. on the MISO signal on the rising edge of the sclk clock.

16 CLK

Figure 29. SPI protocol diagram understands where these operations should start, meaning what is the first address in this burst of operations to be accessed. Table 52. SPI protocol

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8.2.1 SPI read access

transmitted via the MISO line. Table 53. SPI read access

8.2.2 SPI write access

SPI error status is transmitted via the MISO line. Table 54. SPI write access

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8.2.3 SPI protocol

8.2.3.1 Mode A

Figure 30. SPI protocol mode A CSB, MOSI, and MISO interface goes into the error state.

• If the value of channel select register is “0xxxxx001”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 1. This command is used to write the whole CRAM of channel 1 with only one command word.
• If the value of channel select register is “0xxxxx010”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 2. This command is used to write the whole CRAM of channel 2 with only one command word.
• If the value of channel select register is “0xxxxx100”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 3. This command is used to write the whole CRAM of channel 3 with only one command word.
• If the value of channel select register is “0xxxxx011”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 1. This command is used to fully write the CRAMs of channel 1 and 2 (with exactly the same code) with only one command word.
• If the value of channel select register is “0xxxxx101”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 1. This command is used to fully write the CRAMs of channel 1 and 3 (with exactly the same code) with only one command word.
• If the value of channel select register is “0xxxxx110”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 2. This command is used to fully write the CRAMs of channel 2 and 3 (with exactly the same code) with only one command word.
• If the value of channel select register is “0xxxxx111”, the protocol performs a burst of operations starting from address 0; the number of operations is specified by the value of the code_width register (refer to Table 64, status_reg_uc1 (106h, 126h, 146h)) of channel 1. This command is used to fully write the CRAMs of channel 1, 2 and 3 (with exactly the same code) with only one command word.
• If the value of channel select register is “1xxxxx000”, the protocol performs a burst of operations starting from address 0; the number of operations is 192. This command is used to fully write the DRAMs of all three channels with only one command word.
• For all the other values of channel select register, the command is neglected.

data corruption in the registers or DRAM.

• Select the communication interface as the target: this is done by writing the value 0100h at the address 3FFh. First send the data “0_1111111111_00001” (7FE1h) via the SPI. As the ASIC is in idle conditions, it uses this data as a command word. In particular, this specific command word of the example means: write (because of the initial 0) starting from address 3FFh (the ten bits immediately after) 1 word (the five bits at the end). The next data to send is 0100h. The SPI block is expecting a write to 3FFh, so write 0100h in the location 3FFh. As the number of word expected is arrived, the SPI block returns to the idle state;
• Write the value of the 24 registers: the SPI block is waiting for a command word. The correct data to send is “0_0111000000_11000”. This means write (0) starting form address 1C0h (0111000000) 24 words (11000). The next 24 words are written to the communication interface registers.

8.2.3.2 Mode B

Figure 31. SPI protocol mode B CSB, MOSI, and MISO

• the chip select is de-asserted and the number of words transferred is lower than the number parameters required by the command word,
• the number of word transferred is equal to the number parameter + 1. If the number parameter is zero, there is no check on the number of words transferred, and the length of the burst is decided only by the assertion of SPI chip select. It is not recommended to read from any register which is “reset on read” nor from any register which is located one address before such a register using a mode B burst with the number parameter set to zero. This may lead to the effect of a register reset, which is not a read out via the SPI. This problem does not occur if the number parameter is equal to the number of data words transmitted. Note: If one additional data word is sent it is detected, but also written. For example:
• SPI write access mode B, parameter number set to 3 and 3 data words written with no error
• SPI write access mode B, parameter number set to 3 and 4 data words written with a SPI frame error after the 4th data word, bu t the 4th data word is written to RAM or the register.
• SPI write access mode B, parameter number set to 3 and 6 data words written with a SPI frame error after the 4th data word, bu t the 4th data word is written to RAM or the register. 5th and 6th data words are not written to memory.

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8.3 SPI address map

Table 55. MC33PT2000 address map yes Data RAM of channel 1, private area, See DRAM on page 73... yes Data RAM of channel 2, private area, See DRAM on page 73... yes Data RAM of channel 3, private area, See DRAM on page 73...

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8.3.1 Selection register (3FFh)

code RAM is accessed or to select all the other addresses (including the 3 data RAMs and all the registers). Table 57 details the meaning of the 4 bits in this register. Not all possible values are allowed for this register. Table 56. selection_register (3FFh) Table 57. Selection register ‘0’ “000” Nothing selected. Further SPI operation, except for the one concerning this register is ignored. ‘0’ “011” Write operation affects the Code RAM of channel 1 and 2. Read operation is not possible. ‘0’ “101” Write operation affects the Code RAM of channel 1 and 3. Read operation is not possible. ‘0’ “110” Write operation affects the Code RAM of channel 2 and 3. Read operation is not possible. ‘0’ “111” Write operation affects the all three channel’s Code RAM. Read operation is not possible.

8.3.2 Configuration register

8.3.2.1 Flash_enable register

• Checksum_disable. If set, this bit disables the effects of a failed checksum, so microcore execution is not stopped
• Pre_flash_enable. This bit “freezes” the CRAM so the micro-controller cannot further modify the configuration code unless a specific unlock code is written into register unlock_reg. It enables the signature_unit (See Signature unit on page 72)
• Flash_enable. This bit enables the microcores. It can only be set by the signature_unit after a successful checksum calculatio n
• En_dual_microcore. This bit is used to enable the dual microcore mode. Note that when using dual microcore ck_per (refer to Table 136, Clock_Prescaler (1A0h)) set to lower than three, there are some limitations regarding C/DRAM access.
• Checksum_irq_en. If this bit is '1', an interrupt on the_irq_device pin is done in case a CRAM corruption detected
• Checksum_failure. This bit sets to '1' when a mismatch is found between the calculated checksum and the checksum code stored i n the appropriate registers (refer to Table 66, checksum_h (108h, 128h, 148h) and Table 67, checksum_l (109h, 129h, 149h)). This bit sets when a checksum calculation fails, even if the checksum is disabled. This bit resets each time the pre_flash_enable bit sets to '1' to lock the memory.

8.3.2.2 Control register microcore0

• Control_register: these 8 bits can be used to control the execution of the micro-program of uc0, providing control bits which can be read by the micro-program. For instance one bit could be used to enable/disable recharge pulses on the channel or to re-enable the actuation after an error condition has been detected.
• Control_register_shared: according to a configuration bit stored in the “control_register_split” register (refer to Table 77, Dac_rxtx_cr_config (112h, 132h, 152h)), these 8 bits can be used either as control (like the other 8 bits) or like status (like the status register, refer to Table 63, status_reg_uc0 (105h, 125h, 145h)and Table 64, status_reg_uc1 (106h, 126h, 146h)). In this case, they can only be read through the SPI, while they can be set by the “set control register bit” instruction.

Table 58. Flash_enable (100h, 120h, 140h) Table 59. Ctrl_reg_uc0 (101h, 121h, 141h)

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8.3.2.3 Control register microcore1

• Control register: these 8 bits can be used to control the execution of the micro-program of uc0, providing control bits which can be read by the micro-program itself. For instance one bit could be used to enable/disable recharge pulses on the channel or to re-enable the actuation after an error condition has been detected.
• Control register shared: according to a configuration bit stored in the “control register split” register (refer to Table 77, Dac_rxtx_cr_config (112h, 132h, 152h)), these 8 bits can be used either as control (like the other 8 bits) or like status (like the status register, refer to Table 63, status_reg_uc0 (105h, 125h, 145h)and Table 64, status_reg_uc1 (106h, 126h, 146h)). In this case they can only be read through the SPI, while they can be set by the “set control register bit” instruction.

8.3.2.4 Start configuration register

possible to enable a smart start mode for each microcore (reference Programming Guide and Instruction Set).

• start1_sens_uc0: This bit is '1' if the uc0_is sensitive to start1, '0' otherwise
• start2_sens_uc0: This bit is '1' if the uc0_is sensitive to start2, '0' otherwise
• start3_sens_uc0: This bit is '1' if the uc0_is sensitive to start3, '0' otherwise
• start4_sens_uc0: This bit is '1' if the uc0_is sensitive to start4, '0' otherwise
• start5_sens_uc0: This bit is '1' if the uc0_is sensitive to start5, '0' otherwise
• start6_sens_uc0: This bit is '1' if the uc0_is sensitive to start6, '0' otherwise
• start7_sens_uc0: This bit is '1' if the uc0_is sensitive to start7, '0' otherwise
• start8_sens_uc0: This bit is '1' if the uc0_is sensitive to start8, '0' otherwise
• start1_sens_uc1: This bit is '1' if the uc1_is sensitive to start1, '0' otherwise
• start2_sens_uc1: This bit is '1' if the uc1_is sensitive to start2, '0' otherwise

Table 60. ctrl_reg_uc1 (102h, 122h, 142h) Table 61. start_config_reg_Part1 (103h, 123h, 143h) Table 62. start_config_reg_Part2 (104h, 124h, 144h)

• start3_sens_uc1: This bit is '1' if the uc1_is sensitive to start3, '0' otherwise
• start4_sens_uc1: This bit is '1' if the uc1_is sensitive to start4, '0' otherwise
• start5_sens_uc1: This bit is '1' if the uc1_is sensitive to start5, '0' otherwise
• start6_sens_uc1: This bit is '1' if the uc1_is sensitive to start6, '0' otherwise
• start7_sens_uc1: This bit is '1' if the uc1_is sensitive to start7, '0' otherwise
• start8_sens_uc1: This bit is '1' if the uc1_is sensitive to start8, '0' otherwise
• smart_start_uc0: This bit is '1' if the smart start mode is enabled for uc0, '0' otherwise (reference Programming Guide and Instruction Set).
• smart_start_uc1: This bit is '1' if the smart start mode is enabled for uc1, '0' otherwise (reference Programming Guide and Instruction Set).

8.3.2.5 Status register microcore0

registers can be configured so they reset after a SPI read operation to the register (see Table 158, Reset_Behavior (1AEh)).

8.3.2.6 Status register microcore1

so they reset after a SPI read operation to the register (see Table 158, Reset_Behavior (1AEh)). Table 63. status_reg_uc0 (105h, 125h, 145h) Table 64. status_reg_uc1 (106h, 126h, 146h)

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8.3.2.7 Code_width register

• It is used by the SPI interface to determine the length of the special burst transfer used for CRAM initialization (refer to See SPI protocol on page 77).
• The signature unit computes the checksum only of the used part of the CRAM. This signature unit only works if the code with is bigger than 3 lines, if it is not the case signature unit has to be disabled (refer to Table 58, Flash_enable (100h, 120h, 140h)) This allows the application not to write all the CRAM, but only the part which is really used.

8.3.2.8 Checksum high register

unit on page 72) compares the result of its computation to this register and checksum_l.

8.3.2.9 Checksum low register

Signature unit on page 72) compares the result of its computation to checksum_h and this register. Table 65. code_width (107h, 127h, 147h) Table 66. checksum_h (108h, 128h, 148h) Table 67. checksum_l (109h, 129h, 149h)

8.3.2.10 Microcore0 entry point address register

This 10-bit register contains the CRAM address of the first instruction to be executed by microcontroller0.

8.3.2.11 Microcore1 entry point address register

in case the two entry points coincide.

8.3.2.12 Diagnostics interrupt routine address register

• diagnostics_routine_address_uc0. The complete address is “0000” & “diagnostics routine address uc0”: this is the CRAM address of the first instruction of the interrupt routine to be executed by uc0_when an automatic diagnostics exception is raised.
• diagnostics_routine_address_uc1. The complete address is “0000” & “diagnostics routine address uc1”: this is the CRAM address of the first instruction of the interrupt routine to be executed by uc1_when an automatic diagnostics exception is raised.

Table 68. uc0_entry_point (10Ah, 12Ah, 14Ah) Table 69. uc1_entry_point (10Bh, 12Bh, 14Bh) Table 70. Diag_routine_addr (10Ch, 12Ch, 14Ch)

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8.3.2.13 Driver disabled interrupt routine address register

• driver_disable_routine_address_uc0. The complete address is “0000” & “driver disable routine address uc0”: This is the CRAM address of the first instruction of the interrupt routine to be executed by uc0_when a disabled driver or cksys missing exception is raised.
• driver_disable_routine_address_uc1. The complete address is “0000” & “driver disable routine address uc1”: This is the CRAM address of the first instruction of the interrupt routine to be executed by uc1_when a disabled driver or cksys missing exception is raised. The following events can trigger this interrupt (all configurable):
• DrvEn pin going low
• UV_VCCP
• UV_VCC5
• UV_VBOOST
• cksys missing
• Overtemperature

8.3.2.14 Software interrupt routine address register

• software_interrupt_routine_address_uc0. The complete address is “0000” & “software interrupt routine address uc0”: This is the CRAM address of the first instruction of the interrupt routine to be executed by uc0_when a software interrupt is requested.
• software_interrupt_routine_address_uc1. The complete address is “0000” & “software interrupt routine address uc1”: This is the CRAM address of the first instruction of the interrupt routine to be executed by uc1_when a software interrupt is requested.
• sw_irq_rising_edge_start_uc0. When this bit is set to '1', the software interrupt 0 is generated towards microcore 0 if a risi ng edge is detected on the gen_start signal. When set to '0', no software interrupt is required.
• sw_irq_falling_edge_start_uc0. When this bit is set to '1', the software interrupt 0 is generated towards microcore 0 if a fal ling edge is detected on the gen_start signal. When set to '0', no software interrupt is required.
• sw_irq_rising_edge_start_uc1. When this bit is set to '1', the software interrupt 1 is generated towards microcore 1 if a risi ng edge is detected on the gen_start signal. When set to '0', no software interrupt is required.
• sw_irq_falling_edge_start_uc1. When this bit is set to '1', the software interrupt 1 is generated towards microcore 1 if a fal ling edge is detected on the gen_start signal. When set to '0', no software interrupt is required.

Table 71. Driver_disable_routine_addr (10Dh, 12Dh, 14Dh) Table 72. Sw_interrupt_routine_addr (10Eh, 12Eh, 14Eh)

8.3.2.15 Microcore0 interrupt status register

• Interrupt_routine_in_progress: '1' when an interrupt is being served.
• Irq_source:
• “000”: serving start rising edge interrupt
• “001”: serving driver disable interrupt request
• “010”: serving automatic diagnostics interrupt request
• “011”: serving start falling edge interrupt
• “100”: serving software interrupt request 0
• “101”: serving software interrupt request 1
• “110”: serving software interrupt request 2
• “111”: serving software interrupt request 3
• Iret_address: the value of the return address after the interrupt is served. The return address after an interrupt is always the address where the code execution would continue if no interrupt had occurred. For wait and conditional jump instructions, the address is defined considering the status of the feedback at the moment the interrupt request took place.

8.3.2.16 Microcore1 interrupt status register

• Interrupt_routine_in_progress: '1' when an interrupt is being served.
• Irq_source:
• “000”: serving start rising edge interrupt
• “001”: serving driver disable interrupt request
• “010”: serving automatic diagnostics interrupt request
• “011”: serving start falling edge interrupt
• “100”: serving software interrupt request 0
• “101”: serving software interrupt request 1
• “110”: serving software interrupt request 2
• “111”: serving software interrupt request 3
• Iret_address: the value of the return address after the interrupt is served.

Table 73. uc0_irq_status (10Fh, 12Fh, 14Fh) Table 74. uc1_irq_status (110h, 130h, 150h)

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8.3.2.17 Counter 3 and 4 prescaler register

actual ratio is according to Table 76, Counter prescaler. Table 75. Counter_34_prescaler (111h, 131h, 151h) Table 76. Counter prescaler

8.3.2.18 DAC Rxtx configuration register

channel), DACs are accessible and if DACs H and NEG of channel five or six are accessible. can be decided by register bits or microcode instruction sl56dac.

• CR_shared_uc0: if set to '0', all 16 of the bits of the control register uc0_are used as control bits. If set to '1', the 8 MSBs of the control register (control register shared) are used as status bits.
• CR_shared_uc1: if set to '0', all 16 of the bits of the control register uc1_are used as control bits. If set to '1', the 8 MSBs of the control register (control register shared) are used as status bits.
• oc_dac_sel_uc0: selects the other dac for microcore 0.
• ‘0', channel 1: ssoc refers to dac3, osoc refers to dac4 (next channel = 2)
• ‘0', channel 2: ssoc refers to dac5, osoc refers to dac6 (next channel = 3)
• ‘0', channel 3: ssoc refers to dac1, osoc refers to dac2 (next channel = 1)
• ‘1', channel 1: ssoc refers to dac5, osoc refers to dac6 (prev. channel = 3)
• ‘1', channel 2: ssoc refers to dac1, osoc refers to dac2 (prev. channel = 1)
• ‘1', channel 3: ssoc refers to dac3, osoc refers to dac4 (prev. channel = 2)
• oc_dac_sel_uc1: selects the other dac for microcore 1.
• '0', channel 1: ssoc refers to dac4, osoc refers to dac3 (next channel = 2)
• '0', channel 2: ssoc refers to dac6, osoc refers to dac5 (next channel = 3)
• '0', channel 3: ssoc refers to dac2, osoc refers to dac1 (next channel = 1)
• '1', channel 1: ssoc refers to dac6, osoc refers to dac5 (prev. channel = 3)
• '1', channel 2: ssoc refers to dac2, osoc refers to dac1 (prev. channel = 1)
• '1', channel 3: ssoc refers to dac4, osoc refers to dac3 (prev. channel = 2)
• dac56_sel_ucX: selects the dac5/6 for microcore X.
• '0': dac56h56n refers to dac5
• '1': dac56h56n refers to dac6

Table 77. Dac_rxtx_cr_config (112h, 132h, 152h) Table 78. Other dac configuration

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• rxtx_link_sel_ucX: selects the target for the channel communication register (rxtx) in the internal memory map for microcore X (can also be done using the 'stcrt instruction').
• '0': same uc same channel (sssc)
• '1': other uc same channel (ossc)
• '2': same uc next channel (ssnc)
• '3': other uc next channel (osnc)
• '4': sum of highest 4 bits of all rxtx registers (sumh)
• '5': sum of second highest 4 bits of all rxtx registers (suml)
• '6': same uc previous channel (sspc)
• '7': other uc previous channel (ospc)

8.3.2.19 Unlock word register

(binary) or “BEEF” (hexadecimal). As this is not a register, no SPI read operations can be performed at this address. Table 79. Rxtx register link configuration Table 80. Unlock_word (113h, 133h, 153h)

8.3.3 IO configuration registers

8.3.3.1 Feedback microcore sensitivities registers

sensitive to VDS errors on HS1).

8.3.3.2 Microcores output access registers

fw auto, en_halt_x), otherwise access is denied. signals in the same ck cycle, priorities are used as defined in Table 84, Out_acc_ucxchy collision handling. rights) in different ck cycles, all the requested changes are applied in sequence. Table 81. Fbk_sens_ucxchy_part1 (154h, 156h, 158h, 15Ah, 15Ch, 15Eh) Table 82. Fbk_sens_ucxchy_part2 (155h, 157h, 159h, 15Bh, 15Dh, 15Fh) Table 83. Out_acc_ucx_chy (160h, 161h, 162h, 163h, 164h, 165h)

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8.3.3.3 Microcore current sense access registers

current measure block: if the value is set to 1, the microcore can drive those input signals, otherwise access is denied. are controlled by the “acc ucX chY curr 5/6H 5/6Neg” bits. Table 84. Out_acc_ucxchy collision handling Table 85. Cur_block_access_part1 channel1 (166h) Table 86. Cur_block_access_part2 channel2 (167h)

access rights) in different ck cycles, all the requested changes are applied in sequence.

8.3.3.4 Freewheeling link register

(refer to programming guide for more details on this instruction). This configuration is done in the fw_link register.

• Ls1_fw_link: if set, the Ls1 is driven as a fw relative to Hs1, when activated via stfw instruction.
• Ls2_fw_link: if set, the Ls2 is driven as a fw relative to Hs2, when activated via stfw instruction.
• Ls3_fw_link: if set, the Ls3 is driven as a fw relative to Hs3, when activated via stfw instruction.
• Ls4_fw_link: if set, the Ls4 is driven as a fw relative to Hs4, when activated via stfw instruction.
• Ls5_fw_link: if set, the Ls5 is driven as a fw relative to Hs5, when activated via stfw instruction.
• Ls6_fw_link: if set, the Ls6 is driven as a fw relative to Hs6, when activated via stfw instruction.
• Ls7_fw_link: if set, the Ls7 is driven as a fw relative to Hs7, when activated via stfw instruction.
• Hs7_fw_link: if set, the Hs7 is driven as a fw relative to Hs1, when activated via stfw instruction.
• Flag0_fw_link: if set, the Flag0 is driven as a fw relative to Hs4, when activated via stfw instruction.
• Flag1_fw_link: if set, the Flag1 is driven as a fw relative to Hs5, when activated via stfw instruction.
• Flag2_fw_link: if set, the Flag2 is driven as a fw relative to Hs6, when activated via stfw instruction.
• Flag3_fw_link: if set, the Flag3 is driven as a fw relative to Hs7, when activated via stfw instruction.

Table 87. Cur_block_access_part3 channel3 (168h) Table 88. Fw_link (169h)

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8.3.3.5 Freewheeling external request configuration register

the corresponding bit of this register even when the microcode is not running. This can also be enabled by the stfw instruction.

• Hs1_fw_en: if set, the fw relative to Hs1 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs2_fw_en: if set, the fw relative to Hs2 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs3_fw_en: if set, the fw relative to Hs3 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs4_fw_en: if set, the fw relative to Hs4 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs5_fw_en: if set, the fw relative to Hs5 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs6_fw_en: if set, the fw relative to Hs6 is activated, otherwise the status is defined by the microcore request (see stfw instruction).
• Hs7_fw_en: if set, the fw relative to Hs7 is activated, otherwise the status is defined by the microcore request (see stfw instruction).

Figure 32. Automatic freewheeling example Table 89. Freewheeling link register Table 90. Fw_external_request (16ah)

8.3.3.6 V DS and VSRC threshold selection

of the thresholds, in particular the HSx Vsrc thresholds. (see See Bootstrap switch control on page 58). Table 91. Vds_threshold_hs_Part1 (16Bh) Table 92. Vds_threshold_hs_Part2 (16Ch) Table 93. Vsrc_threshold_hs_Part1 (16Dh) Table 94. Vsrc_threshold_hs_Part2 (16Eh)

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Table 95. Vsrc_threshold_hs and vds_threshold_hs value Table 96. Vds_threshold_ls_Part 1 (16Fh) Table 97. Vds_threshold_ls_Part 2 (170h)

8.3.3.7 Slew rate high-side and low-side selection register

164h, 165h)). Each output has the same slew rate for the rising and falling edge, save for the low-side 7 and 8. Refer to Table 22 for the slew rates values. Refer to Table 25 for slew rates values. Table 98. Vds_threshold_ls value Table 99. Hs_slewrate (171h) Table 100. Ls_slewrate_Part 1 (172h)

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Refer to Table 28 and Table 29 for slew rates values.

8.3.3.8 Offset compensation results registers

measurement block is 0) with the “stoc” instruction (refer to programming user guide). can be both positive and negative, all the values in these registers are represented as two’s complement. converted to sign-module notation before being transferred to the analog section. Table 101. Ls_slewrate_Part 2 (173h) Table 102. Offset_compensation12 (174h) Table 103. Offset_compensation34 (175h) Table 104. Offset_compensation56 (176h)

8.3.3.9 ADC conversion results registers

163h, 164h, 165h)). The DAC5L and 6L is used when performing an ADC conversion using current measurement channel 5 and 6. not possible to do ADC conversion at the same time at channel 1 and 3, on channel 2 and 4, or on channel 5 and 6. via the SPI register until the next ADC conversion is started. (Table 105, Adc12_results (177h), Table 106, Adc34_results (178h), and Table 107, Adc56_results (179h)). Table 105. Adc12_results (177h) Table 106. Adc34_results (178h) Table 107. Adc56_results (179h)

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8.3.3.10 Current filters configuration registers

The 10 current feedback are filtered before feeding them to the microcores. The filters of all the current feedback are independent. Table 108. Current_filter12 (17Ah) Table 109. Current_filter34 (17Bh) Table 110. Current_filter5l5h (17Ch) Table 111. Current_filter6l6h (17Dh) Table 112. Current_filter5neg6neg (17Eh)

• Filter_type. This 1 bit parameter selects the type of filter used for the relative current feedback:
• if 0 - Any different sample resets the filter counter
• if 1 - Any different sample decreases the filter counter
• Filter_lenght. This 5-bit parameter set the filtering time for the current feedback signal. tFTN = tCK x (Filter_length + 1)

8.3.3.11 Boost DAC configuration registers

monitoring, requiring no microcode operation.

• Boost_threshold. This 8-bit parameter is the threshold used for boost voltage monitoring.
• ucX chY acc. This 1-bit parameter (active high) grants access to the dac_boost register.
• Filter_type: This 1 bit parameter selects the type of filter used:
• if 0 - Any different sample resets the filter counter
• if 1 - Any different sample decreases the filter counter
• Boost_fbk_filter: This 12-bit parameter sets the filtering time for the output of the vboost comparator. The filtering time is: tFTN = tCK x (x_filter + 1)

Table 113. Boost_dac (17Fh) Table 114. Boost_dac_access (180h) Table 115. Boost_filter (181h)

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8.3.3.12 V DS low-side 7/8 configuration register

VDS would not fall below the VDS threshold of 2.5 V, which would not activate the MOSFET in resonant DC/DC converter mode again. Therefore this timeout is required to force the MOSFET to be switched on. The access for this register is only via the SPI.

• Vdsx_dcdc timeout: This 8 bit parameter defines the time duration of the DC/DC converter (VDS7/8 monitoring Ls7/8). It is needed only if the async_vds mode is used. Timeout is used if the VDS threshold 2.5 V is not reached.
• The timeout is: t FTN = tCK x (x_filter + 1)
• Vdsx_to_en: V DS7/8 timeout is enabled. MOSFET is activated automatically when the timeout has been exceeded
• Cur_dcdcx_fbk_sel for async_vds and async mode:
• For LS7:
• 0: selects cur5h_dcdc feedback signal
• 1: selects cur6h_dcdc feedback signal
• For LS8:
• 0: selects cur6h_dcdc feedback signal
• 1: selects cur5h_dcdc feedback signal
• Lsx_vds_highspeed_en: Enable high speed V DS comparator for DC/DC control
• 0: standard low speed V DS monitor enabled
• 1: high speed V DS monitor for DC/DC control enabled
• dcdcx_mode. This bits shows when the automatic DC/DC control feature for LS7/8 is enabled. Refer to See DC/DC converter control (LS7/8) on page 61 for the behavior of LS7/8 during this mode.

8.3.3.13 Battery monitoring results

Table 118. batt_results (184h) Table 116. Vds7_dcdc_config (182h) & Vds8_dcdc_config (183h) Table 117. DC/DC mode 01 Async mode enabled with two current thresholds. 11 Async mode enabled with one current threshold and VDS monitor.

8.3.3.14 DAC 1-6 values registers

Other than from microcores, it is possible to set the DAC for the current measure blocks by writing to these registers. Table 119. Dac12_value (185h) Table 120. Dac34_value (186h) Table 121. Dac5l5h_value (187h) Table 122. Dac5neg_value (188h) Table 123. Dac6l6h_value (189h)

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8.3.3.15 Load bias configuration register

2 and high-side 4 have two biasing structures, one identical (hsx_en_pu) to the other high-sides and one stronger (hsx_en_s_pu). 58). Low-side bias is enabled by default, and they stay ON even after boostrap charge.

8.3.3.16 Boostrap charged/timer status registers

This register reads the charge status of the HS bootstrap capacitors during initialization phase. (See Bootstrap switch control on page 58). Table 124. Dac6neg_value (18Ah) Table 125. Hs_bias_config (18Bh) Table 126. Ls_bias_config (18Ch) Table 127. Bootstrap_charged (18Dh)

• hsx_bs_charged: when '0', the bootstrap capacitor for HSx is charged
• hsx_src_1V: when '1' it was necessary for this pre-driver to switch the V SRC threshold to 1.0 V to finish the bootstrap init
• bootstrap init timer: this shows the current value of the six MSBs of the bootstrap init timer. The value is '110100' when the timer expires Table 129, Bootstrap_charged Bits shows the exact meaning of the bits hsx_bs_charged and hsx_src_1V. The bootstrap init timer value can be used, together with the other bits of the register, to identify in detail how much time has passed since VCCP voltage was stable and which threshold is used to detect the charge of the bootstrap capacitor.

Table 128. Bootstrap_timer (18Eh) Table 129. Bootstrap_charged Bits Table 130. Bootstrap init timer

000000 VCCP voltage is not stable (undervoltage)

110100 (final value) VCCP voltage is stable since at least 35.5 ms (52). Source HS voltage threshold used to detect bootstrap charge is 1.0 V.

1. PLL factor set to 1 means 24 MHz cksys. This calculation will be different if PLL factor is set to 0.

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8.3.3.17 High-side 1-7 ground reference configuration registers

These seven registers are used to configure the ground reference of the hs1 to hs7 source pins.

• hsx_ls1_act: must be set to '1' if ls1 is connected to the same load as hsx.
• hsx_ls2_act: must be set to '1' if ls2 is connected to the same load as hsx.
• hsx_ls3_act: must be set to '1' if ls3 is connected to the same load as hsx.
• hsx_ls4_act: must be set to '1' if ls4 is connected to the same load as hsx.
• hsx_ls5_act: must be set to '1' if ls5 is connected to the same load as hsx.
• hsx_ls6_act: must be set to '1' if ls6 is connected to the same load as hsx.
• hsx_ls7_act: must be set to '1' if ls7 is connected to the same load as hsx.
• hsx_ls8_act: must be set to '1' if ls8 is connected to the same load as hsx.
• hsx_ls_act_dis: set this bit to disable the link between hsx and ls pre-drivers. If this bit is set the hsx_ls_act signal is f orced to '0' regardless if an ls is active or not.

8.3.3.18 DAC settling time register

is true. This is not applicable to the VBoost Dac. Boost DAC configuration registers on page 110). Since filter configuration can be different for each DAC, the settling time is also different. Table 131. Hsx_ls_act (18Fh - 195h) Table 132. Dac_settling_time (196h)

8.3.3.19 Analog output (OAx) configuration register

These three registers configure the function of the three OA_OUTx pins.

• oa1 en: when '1', the selected source is sent to the OA_OUT1 pin, otherwise it is put in high-impedance to connect all OAx pins to the same MCU ADC.
• oa1 gain: select the gain to apply to the signal
• “00”: gain 1.33
• “01”: gain 2.0
• “10”: gain 3.0
• “11”: gain 5.33
• oa1 g1: select the gain to apply to the signal
• “0”: gain according to oa1 gain
• “1”: gain forced to 1.0
• oa_sel1: select the signal to send to the OA_OUT1 pin.
• “000”: output from current measurement block 1
• “001”: output from current measurement block 3
• “101”: 2.5 Volt
• oa2 en: when '1' the selected source is sent to OA_OUT2.
• oa2 gain: select the gain to apply to the signal.
• “00”: gain 1.33
• “01”: gain 2.0
• “10”: gain 3.0
• “11”: gain 5.33
• oa2 g1: select the gain to apply to the signal
• “0”: gain according to oa2 gain
• “1”: gain forced to 1.0
• oa_sel2: select the signal to send to the OA_OUT2 pin.
• “000”: output from current measurement block 2
• “001”: output from current measurement block 4
• “101”: 2.5 Volt

Table 133. Oa_out1_config (197h) Table 134. Oa_out2_config (198h)

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• oa3 en: when '1', the selected source is sent to the OA_OUT3 pin, otherwise it is put in high-impedance to connect all OAx pins to the same MCU ADC.
• oa3 gain: select the gain to apply to the signal
• “00”: gain 1.33
• “01”: gain 2.0
• “10”: gain 3.0
• “11”: gain 5.33
• oa3 g1: select the gain to apply to the signal.
• “0”: gain according to oa3 gain
• “1”: gain forced to 1.0
• oa_sel3: select the signal to send to the OA_OUT3 pin.
• “000”: output from current measurement block 5
• “001”: output from current measurement block 6
• “101”: 2.5 Volt
• “111”: VCCA

8.3.4 Main configuration registers

be locked. Note that the actual divider ratio is ck = cksys/(ck_per+1). Therefore setting ck_per to “000100” sets ck = cksys/ (4+1). and See Dual microcore arbiter on page 70. Table 135. Oa_out3_config (199h) Table 136. Clock_Prescaler (1A0h)

8.3.4.2 Flags direction configuration register

Table 137. Ck_per and device modes

1. Some limitations apply on the number of consecutive DRAM access and SPI frequency ( See Dual microcore arbiter on page 70).

Table 138. Flag_direction (1A1h) Table 139. Flags_source & Flags_direction registers 0 0/1 The corresponding pin is used for its non-flag function (start,_irq, analog OA2, extFWx, etc.). Flag_bus(x) is driven by int_flags(x). 1 0 The corresponding pin is used as an output flag. The device pin is driven by int_flags(x). Flag_bus(x) is driven by int_flags(x). 1 1 (reset value) The corresponding pin is used as an input flag. The Flag_bus(x) is driven by the device pin. Table 140. Flags_source & Flags_direction registers for Flag 4 and 12

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8.3.4.3 Flags polarity register

Some bits of this register are also used to set the polarity of the start pins when they are not used as flag I/O. Table 141. Flag_polarity (1A2h) Table 142. Flags_polarity Table 143. Flag_polarity register (1A2h) Table 144. Start_polarity

0 Start active high

1 Start active Low

8.3.4.4 Flags source register

8.3.4.5 Offset compensation and ADC clock (ck_ofscmp) prescaler

• Current measurement block ( See Current measurement offset compensation on page 51)
• Battery voltage measurement ( See Battery voltage monitor on page 36)
• ADC conversion ( See ADC conversion results registers on page 108) Note that the actual divider ratio is ck_ofscmp = ck_ofscmp_per + 1. Therefore setting ck_ofscmp_per to “00001000” ck_ofscmp is cksys/9. The reset value is 2.0 s (cksys at 24 MHz).

8.3.4.6 Driver interrupt configuration registers

if the interrupt request must be generated toward the microcontroller and the microcores. Table 145. Flag_source (1A3h)

4 Flag3 Flag2 Flag1 Flag0

Table 146. Ck_ofscmp_Prescaler(1A4h) Table 147. Driver_config_Part 1 (1A5h)

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• Drv_en_irq_en: if set, the drv_en generates the local interrupt
• Vboost_irq_en: if set, an undervoltage on V BOOST generates the local interrupt
• Vcc5_irq_en: if set, an undervoltage on V CC5 generates the local interrupt
• Vccp_irq_en: if set, an undervoltage on V CCP generates the local interrupt
• Overtemp_irq_en: if set, the over temperature condition generates the local interrupt If a local interrupt is generated, it is possible to propagate it to an external device (micro controller) and to the six microcores. This is done when the following bits are set:
• Irq_uc_en, for the external device using the IRQB pin
• Irq_uc0_ch1_en, for the microcore 0 of channel 1
• Irq_uc1_ch1_en, for the microcore 1 of channel 1
• Irq_uc0_ch2_en, for the microcore 0 of channel 2
• Irq_uc1_ch2_en, for the microcore 1 of channel 2
• Irq_uc0_ch3_en, for the microcore 1 of channel 3
• Irq_uc1_ch3_en, for the microcore 1 of channel 3 This register also contains some other configuration bit concerning the output drivers:
• iret_en: the driver_enable block automatically generates an iret request toward all the microcores (this request can be filter ed by microcode if not required). No iret request is generated if the interrupt was triggered by a loss of clock. It is possible to select two types of iret:
• If iret_en is set to '0', an iret request is sent to the microcores when the drivers are re-enabled after a disable condition
• If iret_en is set to '1', an iret request is sent to the microcores when the drivers_status register is cleared. For the iret to happen, either write the driver status register or to read it while the reset on read configuration is active
• Vboost_disable_en: if set, an undervoltage of V BOOST disables the output drivers
• Vboost_mon_en: this signal configures the divider on the V BOOST voltage
• If Vboost_mon_en is set to '0', V BOOST is divided by 32 and then compared with a threshold.
• If Vboost_mon_en is set to '1', V BOOST is divided by 4 and then compared with a threshold.

Table 148. Driver_config_Part 2 (1A6h) Table 149. Truth table for propagation of UV Vboost_irq

• vccp_ext_enable: if set to '0', the internal voltage regulator is enabled and the corresponding pin is used only to connect a bypass capacitor. If set to '1', the internal voltage regulator is disabled and the VCCP voltage must be supplied externally through the corresponding pin. During bootstrap switch init (See Bootstrap switch control on page 58), this setting is bypassed and the value of the vccp_ext_enable signal is set to the inverted value of the DBG pin sampled at reset (POResetB and ResetB). This is better defined in Table 150, VCCP external enable setting. This means the DBG pin, at reset, needs to be configured as an input whose value is latched at the rising edge of the POResetB and ResetB signal, and used to set the configuration of the VCCP internal regulator during the init phase of the bootstrap switch. A SPI reset leaves the latched information unchanged. The DBG pin has an internal weak pull-up resistor so its value is '1' when not connected (n.c.).

8.3.4.7 PLL factor and speed configuration register

• PLL_factor: if set to '0', the PLL multiplication factor is 12, otherwise it is 24
• PLL_spread_disable: if set to '0' the PLL output clock has a spread, otherwise it has no spread The PLL factor is changed synchronously with clock monitor cycle to avoid a clock monitor alert when changing between 12 MHz and 24 MHz. This register is reset by POReset, ResetB, and the SPI reset.

8.3.4.8 Backup clock status register

• Loss_of_clock: this read_only bit (loss_of_clock) latches the condition when the input reference is missing

Table 150. V CCP external enable setting Table 151. PLL_Config (1A7h) Table 152. backup_clock_status (1A8h)

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• Switch_to_clock_pin: this bit (active on rising edge) is used to provide a way to reset the loss of clock condition. If this bit is set during a loss of clock condition it is reset as soon as the clock manager switches the PLL input to the external reference. If this bit sets while there is no loss of clock, the bit resets immediately without any effect.
• uc_irq_en: enable the generation of an interrupt request to the external micro controller when cksys missing is detected. This interrupt is active until this register is read
• uc0_ch1_irq_en: enable the generation of an interrupt request to microcore 0 channel 1 when cksys missing is detected
• uc1_ch1_irq_en: enable the generation of an interrupt request to microcore 1 channel 1 when cksys missing is detected
• uc0_ch2_irq_en: enable the generation of an interrupt request to microcore 0 channel 2 when cksys missing is detected
• uc1_ch2_irq_en: enable the generation of an interrupt request to microcore 1 channel 2 when cksys missing is detected
• uc0_ch3_irq_en: enable the generation of an interrupt request to microcore 0 channel 3 when cksys missing is detected
• uc1_ch3_irq_en: enable the generation of an interrupt request to microcore 1 channel 3 when cksys missing is detected
• cksys_missing_disable_driver: if set, the output drivers are disabled via the signal cksys_drven as long as the cksys_missing signal is '1'. Once the loss_of_clock bit sets, it can be reset only by completing a “switch to clock” pin. For this operation to complete, it must be requested when the main clock input pin again provides a valid clock frequency. The interrupt to the external micro and to the microcores is triggered as long as the cksys_missing signal is set. The microcore is able to process the interrupt as soon as there is a clock available. It is triggered every time the clock manager switches to the internal clock reference and when the clock manager tries to switch back to the external clock reference, due to a SPI request. The interrupt can even occur multiple times during cksys_missing state.

8.3.4.9 SPI configuration register

The spi_config register (address 1A9h) is an 8-bit register storing the SPI protocol configuration and SPI diagnostics.

• Miso_slewrate: selects one of the two possible values for the slew rate of the MISO pin.
• 0 slow slew rate
• 1 fast slew rate
• Protocol_mode: select the type of burst transmission accepted by the protocol, '0' means mode A, '1' means mode B.
• irq_enable: enable the SPI interface to request an interrupt toward the microcontroller if an incorrect SPI transmission is re ceived.
• Watchdog: when using mode A, the maximum time the SPI chip select can be inactive during a burst is expressed as follows: tWATCHDOG = tCKSYS * ((watchdog + 1) x 32768) where tCKSYS is the period of the cksys internal clock. When changing the SPI protocol mode by a write access to this register, it has to be done using a SPI transmission which is compatible to mode A and B (see See Mode A on page 77 and See Mode B on page 78). This means it must not use '0' as number of operations for the SPI transmission, and must not deassert the chip select during the transmission. Changing the protocol mode can be done as often as required.

Table 153. Spi_config (1A9h)

8.3.4.10 Tracer start/stop registers

uPC value of the selected microcore reaches this address, the trace_unit goes to the next phase (post trigger phase).

8.3.4.11 Tracer configuration register

• Trace enable. When this bit is set to '1', the trace_unit starts the first phase of the trace operation. This bit can be set to '0' by the user, to immediately stop the PT2000 trace unit transmission. This bit is automatically reset after the trace operation is complete (all the four phases are finished).
• uc select. Select which is the microcore target of the trace operation:
• “000”: microcore 0, channel 1
• “001”: microcore 1, channel 1
• “010”: microcore 0, channel 2
• “011”: microcore 1, channel 2
• “100”: microcore 0, channel 3
• “101”: microcore 1, channel 3
• Post trigger length. This field selects the duration of the post trigger phase, expressed as number of ck clock cycles. Writing 255 in the post_trigger_length field of the trace_config register causes the trace unit to output a continuos stream after the stop point. With this, run the trace operation for an unlimited amount of time and simply deactivate it by writing zero in the trace_enable bit of the trace config register.

Table 154. Trace_start (1AAh) Table 155. Trace_stop (1ABh) Table 156. Trace_config (1ACh)

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8.3.4.12 Lock device register

independently lock a section of each Data RAM, the last 16 addresses. can no longer be changed by the SPI. Note that there are some bits not locked by the device lock bit, but locked by other mechanism. “unlock password” is provided, these three bit are also reset (refer to Table 80, Unlock_word (113h, 133h, 153h)).

8.3.4.13 Reset register behavior

using the SPI backdoor never reset those registers.

• Driver enable reset behavior: if set to '1' driver_status register is reset on read (refer to Table 162, driver_status (1B2h))
• Automatic diagnostics uc0_ch1 reset behavior: if set to '1' err_uc register of microcore 0 of channel 1 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Automatic diagnostics uc1_ch1 reset behavior: if set to '1' err_uc register of microcore 1 of channel 1 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Automatic diagnostics uc0_ch2 reset behavior: if set to '1' err_uc register of microcore 0 of channel 2 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Automatic diagnostics uc1_ch2 reset behavior: if set to '1' err_uc register of microcore 1 of channel 2 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Automatic diagnostics uc0_ch3 reset behavior: if set to '1' err_uc register of microcore 0 of channel 3 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Automatic diagnostics uc1_ch3 reset behavior: if set to '1' err_uc register of microcore 1 of channel 3 is reset on read ( See Automatic diagnostics error status register on page 137). The three registers are reset when the err_ucXchY_3 register is read
• Status register uc0_ch1 reset behavior: if set to '1' the status register of microcore 0 of channel 1 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92)
• Status register uc1_ch1 reset behavior: if set to '1' the status register of microcore 1 of channel 1 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92)
• Status register uc0_ch2 reset behavior: if set to '1' the status register of microcore 0 of channel 2 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92)

Table 157. Device_Lock (1ADh) Table 158. Reset_Behavior (1AEh)

• Status register uc1_ch2 reset behavior: if set to '1' the status register of microcore 1 of channel 2 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92)
• Status register uc0_ch3 reset behavior: if set to '1' the status register of microcore 0 of channel 3 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92)
• Status register uc1_ch3 reset behavior: if set to '1' the status register of microcore 1 of channel 3 is reset on read (See Status register microcore0 on page 92 and See Status register microcore1 on page 92) The reset on read feature is implemented so no data is lost when the reset of the register is requested and at the same time there is a request to set a bit in the register from the microcode. The bit sets and transmits via the SPI the next time the register is read.

8.3.4.14 Unlock device register

Writing the password 1337h in the unlock password field, resets the device_lock register (refer to Table 157, Device_Lock (1ADh)).

8.3.4.15 SPIReset global reset register 1 and 2

This 32-bit register is divided into two 16-bit slices. When the correct “global reset code” is written in this register, a SPIreset is generated. register 1 and “57A1h” for Global reset register 2. Table 159. Device_Unlock (1AFh) Table 160. Global_Reset_code_part1 (1B0h) Table 161. Global_Reset_code_part2 (1B1h)

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8.3.4.16 Driver disable status register

backup_clock_status (1A8h) and Table 147, Driver_config_Part 1 (1A5h)).

• cksys_missing: this bit is set if the cksys missing condition it disables the drivers. This condition can be configured (refer to Table 152, backup_clock_status (1A8h)).
• DrvEn_latch: this bit latches the condition when the DRVEN input pin is inactive. The bit is reset to 1. 1: DRVEN pin was NOT low since last reset of the driver_status register 0: DRVEN pin was low since the last reset of the driver_status register
• DrvEn_value: this bit is not an error condition; it is only a “living copy” of the drv_en pin. 1: DRVEN pin is high 0: DRVEN pin is low
• Overtemperature: this bit latches the condition where an over temperature is present. It is not used to disable the drivers.
• Uv_vboost: this bit is set if the undervoltage on the vboost disables the high-side drivers. This condition can be configured (refer to Table 147, Driver_config_Part 1 (1A5h)).
• Uv_Vcc5: this bit latches the undervoltage condition on Vcc5.
• Uv_vccp: this bit latches the undervoltage condition on Vccp and the error from GND loss detection. Once an error bit has been set, it can only be reset by an SPI write operation in this register (if the corresponding error is no more present). The same error bits are reset even upon SPI read operations but only when a proper enable bit is set (refer to Table 158, Reset_Behavior (1AEh)).

8.3.4.17 SPI error status register

• spi_error(2): cksys_missing error condition
• spi_error(1): frame incomplete error condition
• spi_error(0): word incomplete error condition The duty of this block is to monitor the spi_protocol and the spi_interface to find errors during the communication with the microcontroller. If an error is detected, the corresponding code is stored in the spi_error_code register. To warn the microcontroller, during the write transfer (from microcontroller to asic), the MISO signal transfers a diagnostic word: the first 13 bits of this word are constant (“1010101010101”) and are used to detect short-circuits on the MISO line. The last three bits copy the three LSBs of the spi_error register. After an error code writes in this register, the register becomes write-protected to latch the error condition and is blind to other occurring errors. This is because after one error, others are often generated: for example for an incomplete word, which can cause an incorrect interpretation of a command word and lead to a frame incomplete error.

Table 162. driver_status (1B2h) Table 163. Spi_error (1B3h)

appropriate bit in the spi_config register (refer to Table 153, Spi_config (1A9h)). of errors and their relative codes (during correct operations the value of the register is 0000h).

• cksys_missing: this error is set if a SPI transfer is required (which means if the SPI chip select CSB is pulled low) while the cksys clock is missing.
• frame_error: this error is set if the number of data words in a burst is not the expected number programmed in the command wor d:
• Mode A is selected, the slave_protocol block received a control word specifying n word transfers, but the microcontroller perf orms less operations and then ends the communication. In this case, this module provides a watchdog function if during a programmed transfer, the communication with the microcontroller is inactive for a time longer than a prefixed limit, so the transfer is considered aborted and an error is detected.
• Mode B is selected, the number parameter is not zero in the command word and the number of transferred words is different from the one programmed in the command word.
• A frame error can also occur when the access limitations to DRAM in dual sequencer mode at maximum ck are violated (refer to Table 49)
• word_error: during the transfer of a word long data, the device receives or sends an incorrect number of bits (15 or 17 instea d of 16, for example). If multiple words are being transferred in a row with the chip select always active (the fastest way), the error is detected at the end of the sequence and it is not possible to say which is the incorrect word. To be sure of the incorrect data, the chip select must be deactivated and reactivated between each word transfer.

8.3.4.18 Interruption status registers

generated by the automatic diagnostics toward the six microcores. Table 164. Interrupt_Register_Part1 (1B4h) Table 165. Interrupt_Register_Part2 (1B5h)

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Table 166. Interrupt register bit description

8.3.4.19 Interrupt subsystem overview

Figure 33 gives an overview over the handling and configuration of the different interrupt sources of the device. Figure 33. Interrupt subsystem

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8.3.4.20 Device identifier register

• Device id is a constant. It identifies the PT2000 device.
• Mask id is a version number of the mask set used for the device. Different mask sets must have a different mask id.
• Sw id is a version number related to the mask set.

8.3.4.21 Reset source status register

8.3.4.22 BIST configuration register

The BIST register is used in write mode to trigger the BIST execution. Table 167. Device_Identifier (1B6h) Table 168. Reset_Source (1B7h) Table 169. Reset Source Register Bits resetb ‘1’ if the reset pin was asserted since the last time this register was read. After POResetB this bit is in an unknown state. Table 170. Bist_interface in write mode (1BDh)

• B157h: MBIST
• 0666h: LBIST
• C1A0: Clear LBIST (need to be sent after LBIST is done) Note that after a LBIST is done a clear BIST command needs to be sent to reenable the logic. In Read mode the register shows the BIST result.
• MBIST result: set to “00” if the memory BIST was never requested
• MBIST result: set to “01” if the memory BIST operation is in progress
• MBIST result: set to “10” if the memory BIST operation was successfully completed
• MBIST result: set to “11” if the memory BIST operation has failed
• LBIST result: set to “00” if the logic BIST was never requested or a clear command has been sent
• LBIST result: set to “10” if the logic BIST operation was successfully completed
• LBIST result: set to “11” if the logic BIST operation has failed
• LBIST result: set to “01” if the logic BIST was stopped by Flag0

8.3.5 Diagnostics configuration registers

8.3.5.1 Automatic diagnostics reaction time

error routine (refer to Table 70, Diag_routine_addr (10Ch, 12Ch, 14Ch)). error routine, and one clock cycle to execute the first instruction. Figure 34. Example of VDS automatic diagnostics filtering and disable windows Table 171. Bist_interface in read mode (1BDh)

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8.3.5.2 LS1 to LS6 output/filter/diag configuration register

These registers define the automatic diagnostics parameter and output routing option from the low-side 1-6 output.

• Filter_type. This 1-bit parameter selects the type of filter used:
• if 0 - Any different sample resets the filter counter
• if 1 - Any different sample decreases the filter counter
• Filter_lenght. This 6 bits parameter set the filtering time for the input feedback signal. tFTN = tCK x (Filter_length + 1)
• Error_table. This 4-bit parameter defines the logical value of an error signal, starting from the output and the related V DS feedback signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value means there is no coherency in the check and an error signal towards the micro-microcore should be generated.
• Disable_window. This 7-bit parameter configures a time period during which any check on the LSx_Vds_feed signal is disabled af ter any change on the output_command signal. tDTL = tCK x (Disable_window + 4)
• Output_routing. This 4-bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. When an input flag pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin is selected to drive the output, it is possible to control low-sides without programming the microcore.

Table 172. LSx_diag_config1 (1C0h, 1C3h, 1C6h, 1C9h, 1CCh, 1CFh, 1D2h, 1D5h) Table 173. LSx_diag_config2 (1C1h, 1C4h, 1C7h, 1CAh, 1CDh, 1D0h, 1D3h, 1D6h) Table 174. LSx_output_config (1C2h, 1C5h,1C8h, 1CBh, 1CEh, 1D1h)

• Invert: This parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. T his affects the output command toward the pre-drivers, but the error_table of the associated feedback is not affected since diagnostics already takes into account the pre-driver status (even when the invert bit is set). The invert bit doesn't affect the polarity of the pre-driver when it is driven from a flag pin.
• LSx_ovr: if set to '1', the low-side x output driver is not influenced by the drv_en. This bit is only writeable for LS6. For all the other pre-drivers, this feature is not available. The drv_en path is always active (hard wired).

8.3.5.3 LS7 and LS8 output/filter/diag configuration register

Table 175, LS7_output_config (1D4h) & LS8_output_config (1D7h) shows the layout of the LS7/8_output_config register.

• Output_routing: This 4-bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. When an input flag pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin is selected to drive the output, it is possible to control low-sides without programming the microcore. output_routing flag (54) output_command

0 Flag0 driven from flag0

1 Flag1 driven from flag1

2 Flag2 driven from flag2

3 Flag3 driven from flag3

4 Vsense4 driven from flag4

5 Start1 driven from flag5

6 Start2 driven from flag6

7 Start3 driven from flag7

8 Start4 driven from flag8

9 Start5 driven from flag9

10 Start6 driven from flag10

11 Start7 driven from flag11

12 Start8 driven from flag12

13 Irq driven from flag13

14 OA2 driven from flag14

15 Dbg driven from flag15

1. Configuration is linked to the value of flag source register (see Table 145 ).

Table 175. LS7_output_config (1D4h) & LS8_output_config (1D7h)

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• Invert: This parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. T he invert bit doesn't affect the polarity of the pre-driver when it is driven from a flag pin.
• LSx_ovr: if set to '1', the low-side x output driver is not influenced by the drv_en.

8.3.5.4 HSx output/filter/diag configuration register

These registers define the automatic diagnostics parameter and output routing option fro the high-side X output.

1. Configuration is linked to the value of flag source register (see Table 145 ).

Table 176. HSx_diag_config1 (1D8h, 1DBh, 1DEh, 1E0h, 1E4h, 1E7h, 1EAh) Table 177. HSx_diag_config2 (1D9h, 1DCh, 1DFh, 1E2h, 1E5h, 1E8h, 1EBh)

• Error_table_vds: This 4-bit parameter defines the logical value of an error signal, starting from the output and the related VDS feedback signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value means there is no coherency in the check and then an error signal towards the micro-microcore should be generated.
• Disable_window: This 7-bit parameter configures a time period during which any check on the HSx_Vds_feed and HSx_Vsrc_feed signals is disabled after any change on the output_command signal. tDTL = tCK x (Disable_window + 4)
• Error_table_src: This 4-bit parameter defines the logical value of an error signal, starting from the output and the related VSRC feedback signal. This table defines the output of the coherency check between the driven output and the acquired feedback. A logic 1 value means there is no coherency in the check and then an error signal towards the micro-microcore should be generated.
• Filter_type. This 1 bit parameter selects the type of filter used:
• if 0 - Any different sample resets the filter counter
• if 1 - Any different sample decreases the filter counter
• Dead_time: This 5-bit register is used to store the value of the dead_time end of count used in the generation of the free wheeling output (delay between the high-side output and the free wheeling output). The FW command goes high after a programmable time (tFWDLY) with respect to the high-side falling edge. In this mode the high-side command rising edge is always delayed of the same programmable time (tFWDLY) with respect to the rising edge requested by the microcores. tFWDLY = Tck x (Dead_time + 1)
• Output_routing: This 4-bit parameter defines if the HSx output is controlled by the microcores or by an input flag pin. When a n input flag pin is selected, the signal from the flag pin and the control signal from the microcores are combined by a logic OR. When a flag pin is selected to drive the output, it is possible to control low-sides without programming the microcore.

Table 178. HSx_output_config (1DA, 1DDh, 1E0h, 1E3h, 1E6h, 1E9h)

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• Invert: This parameter inverts the polarity of the HSx output signal, with respect to the polarity defined by the microcore. T his affects the output command towards the pre-drivers, but the error_table of the associated feedback is not affected since diagnostics already takes into account the pre-driver status (even when the invert bit is set). The invert bit doesn't affect the polarity of the pre-driver when it is driven from a flag pin.
• Filter_lenght. This 6-bit parameter sets the filtering time for the input feedback signal.
• t FTN = tCK x (Filter_length + 1)
• HSx ovr: if set to '1', the high-side x output driver is not influenced by the drv_en. This bit is only writeable for HS5 and HS7. For all the other pre-drivers this feature is not available, the drv_en path is always active (hard wired).

8.3.5.5 Automatic diagnostics error status register

in the register with regards to the output commands and the related voltage (VDS and VSRC) feedback. read. Refer also to section Table 158, Reset_Behavior (1AEh). Those three registers are reset when the err_ucXchY_3 register is read. Note that automatic diagnostics are enabled using the endiag or endiaga instructions (reference Programming Guide and Instruction Set).

1. Configuration is linked to the value of flag source register (see Table 145 ).

Table 179. Err_ucxchy_part1 (1EDh, 1F0h, 1F3h, 1F6h, 1F9h, 1FCh)

8.3.5.6 Automatic diagnostics command/feedback coherency

• diag_option = 0 => coherency check between what the microcore wants to drive, using instructions like sto/stos/ldca/ldcd and t he feedback from the MOSFETS
• diag_option = 1 => coherency check between what the device is really driving, using instructions like sto/stos/ldca/ldcd, but also including the status of overtemperature/drven pin/undervoltages/etc. and the feedback from the MOSFETS For example, in case of an overtemperature/drven pin/undervoltages/etc., drivers are disabled: In case of diag_option =0 =>, automatic diagnosis coherency check fails and detects an error (microcores are trying to drive but the output does not move due to a disabled driver, VDS/VSRC feedback incoherent with driving request => fail) In case of diag_option =1 =>, automatic diagnosis coherency check does not detect anything (microcores are trying to drive, but the output does not move due to a disabled driver, VDS/VSRC feedback is in this case first compared to “no driving” => ok) To summarize if the diag_option = 0 then automatic diagnostics is able to cover all kind of faults.

Table 180. Err_ucxchy_part2 (1EEh, 1F1h, 1F4h, 1F7h, 1FAh, 1FDh) Table 181. Err_ucxchy_part3 (1EFh, 1F2h, 1F5h, 1F8h, 1FBh, 1FEh) Table 182. diagnostics_option register (1FFh)

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9 Typical applications

The PT2000 can be configured in several applications. Figure 35 and Figure 36 shows the PT2000 in a typical application.

9.1 Application diagram: 3 bank, 6 cylinder with DC/DC

6 Cylinder

3 Bank

Figure 35. Example of application circuit (6 cylinder 3 bank with DC/DC)

9.2 Application diagram: 3 bank, 3 cylinder (full overlap) with DC/DC

3 Cylinder

Figure 36. Application diagram 3 bank, 3 cylinder with synchronous rectification and DC/DC

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10 Packaging

10.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package Suffix Package outline drawing number 80-Pin LQFP AF 98ASA00505D

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11 Reference section

Table 183. PT2000 reference

Revision Date Description of changes 1.0 3/2015 • Initial release 2.0 3/2015 • Made minor corrections

• Corrected typo error on High-side V DS Threshold in Table 8
• Corrected typo error on Low-side V DS Threshold in Table 9
• Changed Current Measurement for DC/DC title to heading 3
• Updated reset value in Table 122 (low-side pull-down disable by default)
• Updated figure 35 and 36 to use current sense measurement 6 for Bank 3, recommended in order to use OA3 for Bank3 3.0
• Added Shutoff path via the DrvEn pin section.
• I VBATT_OPER value updated to fit with maximum current allowed on VCCP in Table 5
• I VCC5 updated with 6 microcores ON and biasing enabled in Table 5
• Total Error VBOOST_DAC updated in Table 5
• OAx Input impedance updated in Table 15
• LBIST clear command added in LBIST 6/2015 • Corrected Figure 20
• Added description detail to section 7.2.1.3 4.0
• Updated I VCC5 characteristic in Table 5
• Added Table 50
• Added note (18)
• Updated section 6.1.4.1
• Updated section 8.2.3.2
• Updated section 8.3.3.12
• Updated the example in section 8.3.2.17
• Corrected package suffix
• Added the VCS_OFF_GD parameter
• Corrected Table 167
• Corrected table titles for Table 172, Table 173, Table 174, Table 176, Table 177, Table 178, Table 179, Table 180, and Table 181 5.0 4/2016
• Updated the formula for calculating current threshold
• Update Figure 33
• Updated package drawing
• Updated form and style 6.0 6/2016
• Added SPI timings to Table 18
• added clarification to Section 7.1.1. Power-up sequence of VCC5, VCC2P5, and reset, page 57
• Updated Figure 21 7.0 9/2016
• Added Table 3, Resistor types
• Added Pull resistor type column to Table 2, PT2000 pin definitions (2), (3), (4)
• Added notes (3) and (4).
• Made minor correction to Section 7.2.1.3. Mode 3 (LS7/8 resonant mode VDS monitoring), page 62 8.0 4/2017
• Updated Figure 3 (replaced VSENSEN8 by VSENSEN2)
• Updated min. value for V BATT and SRVCCC5 in Table 5
• Updated typical value for I VCCIO in Table 5
• Added note (16) and (52)
• Made minor corrections to Application without boost voltage, Low-side VDS monitor D_ls7/D_ls8 for DC/DC, VDS low- side 7/8 configuration register, and DAC settling time register
• Updated Table 145 9.0 4/2017 • Deleted S RVCCC5 characteristic from Table 5

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10.0 9/2017

• Updated Figure 1
• Updated Table 126 (changed all reset values to 1)
• Updated Table 152 11.0 6/2018
• Updated Table 5 (added the Vcc5_BGmin parameter)
• Minor typo corrections in Table 11, Table 13 and Table 16
• Updated bit 5 and bit 13 values in Table 102, Table 103 and Table 104
• Updated Figure 33 (replaced 1B4h by 1B5h and 1B5h by 1B4h) 12.0 1/2019 • Changed document status from Advance information to Technical data 13.0 5/2022 CIN 202205014I Counter 3 and 4 prescaler register
• Changed Example to counter_4_per_uc1 = 0010b from counter_4_per_uc1 = 0001b Table 76
• Changed prescaler of 1100 to 13 from 14
• Changed prescaler of 1101 to 14 from 16
• Changed prescaler of 1110 to 15 from 32
• Changed prescaler of 1111 to 16 from 64 Revision Date Description of changes

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2022. Document Number: MC33PT2000 Rev. 13