PST591 MITSUMI | Alldatasheet
Document overview
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- PDF pages: 6
Technical content
Features
- Fixed delay time setting by counter timer Excellent delay time temperature characteristics ±800ppm/ ° C 2. Low operating limit voltage 0.65V typ. 3. Hysteresis voltage provided in detection voltage 50mV typ. 4. Current consumption for no-load I CCL=300µA typ. ICCH=200µA typ. 5. 5 delay time products available PST591 50mS PST594 400mS PST592 100mS PST595 800mS PST593 200mS D : 4.2V typ. I : 2.9V typ. E : 3.9V typ. J : 2.7V typ. F : 3.6V typ. K : 2.5V typ. G : 3.3V typ. Package MMP-4A (PST59 M) TO-92A (PST59 ) * contains detection voltage rank. (MMP-4A has a manual reset pin, which should be set at GND or NC during normal operation.)
Applications
- Reset circuits in microcomputers, CPUs and MPUs 2. Logic circuit reset circuits. 3. Battery voltage check circuits. 4. Back-up power supply switching circuits. 5. Level detection circuits. 6. Mechanical reset circuits
MITSUMI System Reset PST591~595 Equivalent Circuit Diagram Absolute Maximum Ratings (Ta=25° C) Pin Assignment 123 TO-92A MMP-4A
1 VCC
2 GND
3 VOUT
1 VOUT
3 VCC
4 GND
Storage temperature TSTG -40~+125 ° C Operating temperature TOPR -20~+75 ° C Power supply voltage VCC max. -0.3~10 V Manual reset input voltage VRES max. -0.3~10 V Allowable loss Pd 200 (MMP-4P) mW 300 (TO-92)
MITSUMI System Reset PST591~595 Measuring Circuit [1] [2] Electrical Characteristics (Ta=25° C) (Except where noted otherwise, resistance unit isΩ ) *2 VCC=VS min.-0.15V Note 3: VOUT pin is low when manual reset pin is high. VOUT pin is high when manual reset pin is low. Note: Input model is an example for PST591C. Item Symbol Measuring circuit Measurement conditions Min. Typ. Max. Unit C 4.3 4.5 4.7 D 4.0 4.2 4.4 E 3.7 3.9 4.1 RL=470 F 3.4 3.6 3.8 Detection voltage VS 1V OL <= 0.4V G 3.1 3.3 3.5 V VCC=H L H 2.9 3.1 3.3 I 2.75 2.90 3.05 J 2.55 2.70 2.85 K 2.35 2.50 2.65 Hysteresis voltage VS 1R L=470, VCC=L H L 30 50 100 mV Detection voltage temperature coefficient VS/ T 1 R L=470, Ta=-20° C~+75° C ±0.01 %/ ° C Low-level output voltage VOL 1 VCC=Vs min.-0.05V, RL=470 0.1 0.4 V Output leakage current IOH 1V CC=10V ±0.1 µA Circuit current while on ICCL 1V CC=Vs min.-0.05V, RL=∞ 300 600 µA Circuit current while off ICCH 1V CC=Vs typ./0.85V, RL=∞ 200 350 µA PST591 30 50 75 RL=4.7k PST592 60 100 150 "H" transport delay time tPLH 2 CL=100PF *1 PST593 120 200 300 mS PST594 240 400 600 PST595 480 800 1200 "L" transport delay time t PHL 2R L=4.7k, CL=100PF *11 0 µ S Operating power supply voltage VOPL 1R L=4.7k, VOL <= 0.4V 0.65 0.85 V Output current while on 1 IOL11 V CC=VS min.-0.05V, RL=0 8 mA Output current while on 2 IOL21 Ta=-20° C~+75° C, RL=0 *2 6m A Manual Input high voltage VRESH 2.0 V reset Input high current VRESH VRES=2V 80 µA pin Input low voltage VRESL 0.8 V
MITSUMI System Reset PST591~595 ICCH (µA) Ta (°C) -40 -20 0 20 40 60 80 180 190 200 210 220 230 ICCL (µA) Ta(°C) -40 -20 0 20 40 60 80 200 250 300 350 400 450 ICCL vs. Ta IOL (mA) Ta (°C) -40 -20 0 20 40 60 80 IOL vs. Ta tPLH (mS) Ta (°C) -40 -20 0 20 40 60 80 tPLH vs. Ta ICCH vs. Ta VOL (mV) Ta (°C) -40 -20 0 20 40 60 80 100 150 200 250 VS (mV) Ta (°C) -40 -20 0 20 40 60 80 VS vs. Ta V OL vs. Ta -40 -20 0 20 40 60 80 3.9 4.0 4.1 4.2 4.3 4.4 VS (V) Ta (°C) 123456 78 VOUT (V) VCC (V) Ta=-25°C Ta=25°C Ta=75°C VCC vs. VOUT VS vs. Ta Characteristics (Example: PST591D)
MITSUMI System Reset PST591~595 Timing Chart VCC/VOUT (V) RESET VCC VOUT VS Time ON OFF Undefined Application circuits 1. Normal hard reset Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high. tPHL (µS) Ta (°C) -40 -20 0 20 40 60 80 tPHL vs. Ta 300 200 00 25 50 75 100 125 100 Pd (mW) Ta (°C) TO92 MMP4 Pd vs. Ta
MITSUMI System Reset PST591~595 2. Manual reset VOUT pin low for manual switch ON. VOUT pin high for manual switch OFF. Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high. 3. Mute circuit Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high.