PSN54SC4T08MPWTSEP

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SN54SC4T08-SEP Radiation-Tolerant, 1.2-V to 5.5-V, Quadruple 2-Input Positive-AND Gates With Integrated Translation

1 Features

Vendor item drawing available, VID V62/xxx (TBD)
Total ionizing dose characterized at 30 krad(Si) – Total ionizing dose characterized radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad(Si)
Single-event effects (SEE) characterized: – Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg – Single event transient (SET) characterized to

43 MeV-cm2 /mg

Wide operating range of 1.2 V to 5.5 V
Single-supply translating gates at – TTL compatible inputs:
Up translation: – 1.8-V – Inputs from 1.2 V – 2.5-V – Inputs from 1.8 V – 3.3-V – Inputs from 1.8 V, 2.5 V – 5.0-V – Inputs from 2.5 V, 3.3 V
Down translation: – 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V – 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V – 2.5-V – Inputs from 3.3 V, 5.0 V – 3.3-V – Inputs from 5.0 V
5.5 V tolerant input pins
Output drive up to 25 mA at 5-V
Latch-up performance exceeds 250 mA per JESD 17
Space enhanced plastic (SEP) – Controlled baseline – Gold bondwire – NiPdAu lead finish – One assembly and test site – One fabrication site – Military (–55°C to 125°C) temperature range – Extended product life cycle – Extended product-change notification (PCN) – Product traceability – Meets NASAs ASTM E595 outgassing specification

2 Applications

Enable or disable a digital signal
Controlling an indicator LED
Translation between communication modules and system controllers

3 Description

The SN54SC4T08-SEP contains four independent 2- input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3) SN54SC4T08-SEP PW (TSSOP, 14) 5 mm × 6.4 mm 5 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. xA xB xY Simplified Logic Diagram ADVANCE INFORMATION SN54SC4T08-SEP SCLS928 – MAY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.2 Receiving Notification of Documentation Updates..19

11 Mechanical, Packaging, and Orderable

4 Revision History

May 2023 * Initial Release SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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5 Pin Configuration and Functions

Figure 5-1. PW Package, 14-Pin TSSOP (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. 1A 1 I Channel 1, Input A 1B 2 I Channel 1, Input B 1Y 3 O Channel 1, Output Y 2A 4 I Channel 2, Input A 2B 5 I Channel 2, Input B 2Y 6 O Channel 2, Output Y GND 7 G Ground 3Y 8 O Channel 3, Output Y 3A 9 I Channel 3, Input A 3B 10 I Channel 3, Input B 4Y 11 O Channel 4, Output Y 4A 12 I Channel 4, Input A 4B 13 I Channel 4, Input B VCC 14 P Positive Supply (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN54SC4T08-SEP

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 7 V VO Output voltage range(2) –0.5 VCC + 0.5 V IIK Input clamp current VI < -0.5 V -20 mA IOK Output clamp current VO < -0.5 V or VO > VCC + 0.5 V ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous output current through VCC or GND ±50 mA Tstg Storage temperature -65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION CONDITION MIN MAX UNIT VCC Supply voltage 1.2 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VIH High-level input voltage VCC = 1.2 V to 1.3 V 0.78 V VCC = 1.65 V to 2 V 1.1 VCC = 2.25 V to 2.75 V 1.28 VCC = 3 V to 3.6 V 1.45 VCC = 4.5 V to 5.5 V 2 VIL Low-Level input voltage VCC = 1.2 V to 1.3 V 0.25 V VCC = 1.65 V to 2 V 0.5 VCC = 2.25 V to 2.75 V 0.65 VCC = 3 V to 3.6 V 0.75 VCC = 4.5 V to 5.5 V 0.85 IO Output current VCC = 1.6 V to 2 V ±3 mA VCC = 2.25 V to 2.75 V ±7 VCC = 3.3 V to 3.6 V ±15 VCC = 4.5 V to 5.5 V ±25 Δt/Δv Input transition rise or fall rate VCC = 1.2 V to 5.5 V 20 ns/V TA Operating free-air temperature -55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) SN54SC4T08-SEP UNITPW (TSSOP)

14 PINS

RθJA Junction-to-ambient thermal resistance 147.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.4 °C/W RθJB Junction-to-board thermal resistance 90.9 °C/W ΨJT Junction-to-top characterization parameter 27.2 °C/W YJB Junction-to-board characterization parameter 90.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN54SC4T08-SEP

6.5 Electrical Characteristics

over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH IOH = -50 µA 1.2 V to 5.5 V VCC-0.2 V IOH = -1 mA 1.2 V 0.8 1.1(1) IOH = -2 mA 1.65 V to 2 V 1.21 1.7(1) IOH = -3 mA 2.25 V to 2.75 V 1.93 2.4(1) IOH = -5.5 mA 3 V to 3.6 V 2.49 3.08(1) IOH = -8 mA 4.5 V to 5.5 V 3.95 4.65(1) IOH= –24 mA 4.5 V to 5.5 V 3.15 VOL IOL= 50 μA 1.2 V to 5.5 V 0.1 V IOL = 1 mA 1.2 V 0.2 IOL = 2 mA 1.65 V to 2 V 0.1(1) 0.25 IOL = 3 mA 2.25 V to 2.75 V 0.1(1) 0.2 IOL = 5.5 mA 3 V to 3.6 V 0.2(1) 0.25 IOL= 8 mA 4.5 V to 5.5 V 0.3(1) 0.35 IOL= 24 mA 4.5 V to 5.5 V 0.75 II VI = 0 V or VCC 0 V to 5.5 V ±0.1 ±1 µA ICC VI = VCC or GND, IO = 0 1.2 V to 5.5 V 2 55 µA ΔICC One input at 0.3 V or 3.4 V, other inputs at 0 or VCC, IO = 0 5.5 V 1.35 1.5 mA One input at 0.3 V or 1.1 V, other inputs at 0 or VCC, IO = 0 1.8 V 5 50 µA CI VI = VCC or GND 5 V 3 5 pF CPD (2) (3) CL = 50 pF, F = 10 MHz 1.2 V to 5.5 V 11 25 pF (1) Typical value at nearest nominal voltage (1.8 V, 2.5 V, 3.3 V, and 5 V) (2) CPD is used to determine the dynamic power consumption, per channel. (3) PD= VCC 2 × FI × (CPD+ CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage.

6.6 Switching Characteristics

over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC MIN TYP MAX UNIT tPHL A or B Y CL = 15 pF 1.2 V 38.33 117.5 nS tPLH A or B Y 26.6 102.8 nS tPHL A or B Y CL = 50 pF 42.37 137.2 nS tPLH A or B Y 30.97 115.2 nS tPHL A or B Y CL = 15 pF 1.8 V 14.9 38.1 nS tPLH A or B Y 9.81 33.7 nS tPHL A or B Y CL = 50 pF 16.54 43.6 nS tPLH A or B Y 11.73 38.0 nS tPHL A or B Y CL = 15 pF 2.5 V 9.31 22.6 nS tPLH A or B Y 5.59 20.2 nS tPHL A or B Y CL = 50 pF 10.36 26.4 nS tPLH A or B Y 7.16 23.1 nS SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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6.6 Switching Characteristics (continued)

over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC MIN TYP MAX UNIT tPHL A or B Y CL = 15 pF 3.3 V 7.17 16.1 nS tPLH A or B Y 4.15 14.6 nS tPHL A or B Y CL = 50 pF 7.84 19.0 nS tPLH A or B Y 5.24 16.7 nS tPHL A or B Y CL = 15 pF 5 V 5.62 10.6 nS tPLH A or B Y 3.06 9.7 nS tPHL A or B Y CL = 50 pF 6.11 13.0 nS tPLH A or B Y 3.76 11.4 nS

6.7 Noise Characteristics

VCC = 5 V, CL = 50 pF, TA = 25°C PARAMETER DESCRIPTION MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 1 1.2 V VOL(V) Quiet output, minimum dynamic VOL -0.8 -0.3 V VOH(V) Quiet output, minimum dynamic VOH 4.4 5 V VIH(D) High-level dynamic input voltage 2.1 V VIL(D) Low-level dynamic input voltage 0.5 V www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN54SC4T08-SEP

6.8 Typical Characteristics

TA = 25°C (unless otherwise noted) VIN - Input Voltage (V) ICC - Supply Current (µA) 1.8 V 2.5 V Figure 6-1. Supply Current Across Input Voltage 1.8-V and 2.5-V Supply VIN - Input Voltage (V) ICC - Supply Current (µA) 160 240 320 400 480 560 640 720 800 3.3 V 5.0 V Figure 6-2. Supply Current Across Input Voltage 3.3-V and 5.0-V Supply V CC (V) ICC (nA) 25°C 125°C -40°C Figure 6-3. Supply Current Across Supply Voltage IOH (mA) VOH (V) 1.5 2.5 3.5 4.5 1.8 V 2.5 V 3.3 V 5.0 V Figure 6-4. Output Voltage vs Current in HIGH State IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 1.8 V 2.5 V 3.3 V 5.0 V Figure 6-5. Output Voltage vs Current in LOW State IOH (mA) VOH (V) 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 -40°C 25°C 125°C Figure 6-6. Output Voltage vs Current in HIGH State; 5-V Supply SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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6.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40°C 25°C 125°C Figure 6-7. Output Voltage vs Current in LOW State; 5-V Supply IOH (mA) VOH (V) 2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3.05 3.1 3.15 3.2 3.25 3.3 -40°C 25°C 125°C Figure 6-8. Output Voltage vs Current in HIGH State; 3.3-V Supply IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -40°C 25°C 125°C Figure 6-9. Output Voltage vs Current in LOW State; 3.3-V Supply IOH (mA) VOH (V) 1.9 1.95 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40°C 25°C 125°C Figure 6-10. Output Voltage vs Current in HIGH State; 2.5-V Supply IOL (mA) VOL (V) 0 2 4 6 8 10 12 14 16 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -40°C 25°C 125°C Figure 6-11. Output Voltage vs Current in LOW State; 2.5-V Supply IOH (mA) VOH (V) 1.4 1.425 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 1.775 1.8 -40°C 25°C 125°C Figure 6-12. Output Voltage vs Current in HIGH State; 1.8-V Supply www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN54SC4T08-SEP

TA = 25°C (unless otherwise noted) IOL (mA) VOL (V) 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 -40°C 25°C 125°C Figure 6-13. Output Voltage vs Current in LOW State; 1.8-V Supply Time (ns) Population (%) 10% 11% 12% 13% 14% 15% Figure 6-14. TPD Distribution; 1.2-V; TA = -55°C to 125°C (40 Samples) Time (ns) Population (%) 10% 12% 14% 16% 18% Figure 6-15. TPD Distribution; 1.8-V; TA = -55°C to 125°C (40 Samples) Time (ns) Population (%) 10% 12% 14% 16% 18% 20% 22% 24% 26% Figure 6-16. TPD Distribution; 2.5-V; TA = -55°C to 125°C (40 Samples) Time (ns) Population (%) 2.5% 7.5% 10% 12.5% 15% 17.5% 20% 22.5% 25% Figure 6-17. TPD Distribution; 3.3-V; TA = -55°C to 125°C (40 Samples) Time (ns) Population (%) 10% 15% 20% 25% 30% Figure 6-18. TPD Distribution; 5-V; TA = -55°C to 125°C (40 Samples) SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt< 2.5 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. CL (1) From Output Under Test Test Point (1) CL includes probe and test-fixture capacitance. Figure 7-1. Load Circuit for Push-Pull Outputs 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 7-2. Voltage Waveforms Propagation Delays VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% (1) The greater between tr and tf is the same as tt. Figure 7-3. Voltage Waveforms, Input and Output Transition Times www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN54SC4T08-SEP

8 Detailed Description

8.1 Overview

The SN54SC4T08-SEP contains four independent 2- input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected.

8.3.2 Clamp Diode Structure

As Figure 8-1 shows, the outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND LogicInput Output VCCDevice -IIK +IOK -IOK Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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8.3.3 SCxT Enhanced Input Voltage

The SN54SC4T08-SEP belongs to TI's SCxT family of logic devices with integrated voltage level translation. This family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be referenced to the supply voltage (V CC), as described in the Electrical Characteristics table. For proper functionality, input signals must remain at or below the specified V IH(MIN) level for a HIGH input state, and at or below the specified V IL(MAX) for a LOW input state. Figure 8-2 shows the typical V IH and VIL levels for the SCxT family of devices, as well as the voltage levels for standard CMOS devices for comparison. The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). The inputs require the input signals to transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and can cause oscillations. More details can be found in the Implications of Slow or Floating CMOS Inputs application report. Do not leave inputs floating at any time during operation. Unused inputs must be terminated at V CC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-k Ω resistor is recommended and will typically meet all requirements. VCC - Supply Voltage (V) VIN - Input Voltage (V) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 3.2 3.4 3.6 1.2-V CMOS 1.8-V CMOS 2.5-V CMOS 3.3-V CMOS

1.1 V (VOH)

1.45 V (VOH)

2 V (VOH)

2.4 V (VOH)

0.3 V (VOL)

0.45 V (VOL) 0.4 V (VOL) 0.4 V (VOL) VIH VIL HIGH Input LOW Input Figure 8-2. SCxT Input Voltage Levels

8.3.3.1 Down Translation

Signals can be translated down using the SN54SC4T08-SEP. The voltage applied at the V CC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately V CC in the HIGH state, and 0 V in the LOW state. Ensure that the input signals in the HIGH state are between V IH(MIN) and 5.5 V, and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 8-2. For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to match 1.8 V CMOS signals when operating from 1.8-V VCC. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN54SC4T08-SEP

Down Translation Combinations are as follows:

1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V
2.5-V VCC – Inputs from 3.3 V and 5.0 V
3.3-V VCC – Inputs from 5.0 V

8.3.3.2 Up Translation

Input signals can be up translated using the SN54SC4T08-SEP. The voltage applied at V CC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately V CC in the HIGH state, and 0 V in the LOW state. The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a V IH(MIN) of 3.5 V. For the SN54SC4T08-SEP, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical 2.5-V to 5-V signals. Ensure that the input signals in the HIGH state are above V IH(MIN) and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 8-2. Up Translation Combinations are as follows:

1.8-V VCC – Inputs from 1.2 V
2.5-V VCC – Inputs from 1.8 V
3.3-V VCC – Inputs from 1.8 V and 2.5 V
5.0-V VCC – Inputs from 2.5 V and 3.3 V

8.4 Device Functional Modes

Table 8-1 provides the functions for the SN54SC4T08-SEP. Table 8-1. Function Table INPUTS(1) OUTPUT Y (1) A B H H H L X L X L L (1) H = high voltage level, L = low voltage level, X = do not care, Z = high impedance SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in Typical Application Block Diagram . The fourth gate can be used for another application in the system, or the inputs can be grounded and the channel left unused. The SN54SC4T08-SEP is used to directly control the RESET pin of a motor controller. The controller requires four input signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes LOW. The 4-input AND gate function combines the four individual reset signals into a single active-low reset signal.

9.2 Typical Application

Figure 9-1. Typical Application Block Diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN54SC4T08-SEP plus the maximum static supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN54SC4T08-SEP plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN54SC4T08-SEP can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50 pF. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN54SC4T08-SEP

The SN54SC4T08-SEP can drive a load with total resistance described by R L ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN54SC4T08-SEP (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-k Ω resistor value is often used due to these factors. The SN54SC4T08-SEP has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. Refer to the Feature Description section for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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9.2.2 Detailed Design Procedure

Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; by design, however, the limit will optimize performance. This can be accomplished by providing short, appropriately sized traces from the SN54SC4T08-SEP to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω, which will prevent the maximum output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.

9.2.3 Application Curves

Figure 9-2. Application Timing Diagram

9.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1- μF and 1- μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example.

9.4 Layout

9.4.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN54SC4T08-SEP

9.4.2 Layout Example

0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 9-3. Example Layout for the SN54SC4T08-SEP SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN54SC4T08-SEP

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PSN54SC4T08MPWTS EP SN54SC4T08-SEP SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PSN54SC4T08MPWTSEP TSSOP PW 14 2000 364.0 364.0 27.0 www.ti.com SN54SC4T08-SEP SCLS928 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN54SC4T08-SEP

11.2 Mechanical Data

SCLS928 – MAY 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com 2-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PSN54SC4T08MPWTSEP ACTIVE TSSOP PW 14 250 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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