SN4599-Q1 TI | Alldatasheet
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Technical content
SN4599-Q1 Automotive 5V, 2:1 (SPDT), 1-Channel Analog Switch
1 Features
- AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to 125°C ambient operating temperature – Device HBM classification level H1C – Device CDM classification level C3
- Rail to rail operation
- Bidirectional signal path
- Low on-resistance: 7Ω
- Wide supply range: 2V to 5.5V
- -40°C to +125°C Operating temperature
- Break-before-make switching
2 Applications
- Analog and digital switching
- I2C and SPI bus multiplexing
- Advanced driver assistance systems (ADAS)
- Body electronics and lighting
- Infotainment and cluster
- Zonal architecture
- Body control modules
- Battery management systems
- Telematics
- Automotive head unit
3 Description
The SN4599-Q1 is a general purpose complementary metal-oxide semiconductor (CMOS) single-pole double-throw (SPDT) switch. The SN4599-Q1 switches between two source inputs based on the state of the SEL pin. Wide operating supply of 2V to 5.5V allows for use in a broad array of automotive applications. The device supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from GND to VDD.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) SN4599-Q1 DBV (SOT-23, 6) 2.9mm × 2.8mm (1) For more information, see Section 11 (2) The package size (length × width) is a nominal value and includes pins, where applicable. Inverting Input Output Unity Gain R R Control D SEL Application Example SEL D Block Diagram ADVANCE INFORMATION SN4599-Q1 SCDS475 – APRIL 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
11 Mechanical, Packaging, and Orderable
4 Pin Configuration and Functions
Figure 4-1. DBV Package 6-Pin SOT-23 (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. SEL 1 I Select pin: controls state of the switch according to Table 7-1. (Logic Low = S1 to D, Logic High = S2 to D) VDD 2 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND. GND 3 P Ground (0V) reference S1 4 I/O Source pin 1. Can be an input or output. D 5 I/O Drain pin. Can be an input or output. S2 6 I/O Source pin 2. Can be an input or output. (1) I = input, O = output, I/O = input and output, P = power SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage -0.5 6 V VIN Control input voltage(2) -0.5 6 V VI/O Voltage range applied to any output in the high- impedance or power-off state(2) (3) -0.5 VDD + 0.5 V IIK Control input clamp current VIN < 0 -50 mA II/O I/O port diode current VI/O < 0 or VI/O > VDD -50 50 mA II/O On-state switch current(4) VI/O = 0 to VDD IDC ± 10 %(7) IDC ± 10 %(7) mA Ptot Total power dissipation 300 mW Tj Junction temperature 150 C Storage temperature, Tstg -65 150 C (1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltages are with respect to ground unless otherwise specified. (3) VI, VO, VA, and VBn are used to denote specific conditions for VI/O. (4) II, IO, IA, and IBn are used to denote specific conditions for II/O. (5) Refer to Source or Drain Current table for IDC specifications.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-002 specification.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2 5.5 V VI/O Switch input or output voltage (Max of VDD) 0 VDD V VIN Control input voltage 0 5.5 V VIH High-level input voltage VDD = 2V to 2.29V VDD x 0.75 V VDD = 2.3V to 5.5V VDD x 0.7 VIL Low-level input voltage VDD = 2V to 2.29V VDD x 0.25 VVDD = 2.3V to 2.9V VDD x 0.3 VDD = 3V to 5V 0.85 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN4599-Q1
5.4 Thermal Information
THERMAL METRIC(1) SN4599-Q1 UNITDBV (SOT-23)
6 PINS
RθJA Junction-to-ambient thermal resistance 212.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 156.7 °C/W RθJB Junction-to-board thermal resistance 96.5 °C/W ΨJT Junction-to-top characterization parameter 80.7 °C/W ΨJB Junction-to-board characterization parameter 96. °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
5.5 Source or Drain Current through Switch
Switch TJ = 25°C TJ = 85°C TJ = 125°C TJ = 130°C UNIT IDC (1) 150 120 60 50 mA Ipeak (2) 300 300 180 160 mA (1) See Thermal Information section for more details (2) Pulse current of 1ms with 10% Duty Cycle SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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5.6 Electrical Characteristics
Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SN4599-Q1 VDD V VI/o V IO mA TA rON ON-state switch resistance VI = 0V IO = 4mA 25°C 11 Ω –40°C to +85°C 20 –40°C to +125°C 20 VI = 1.65 IO = -4mA 25°C 15 –40°C to +85°C 50 –40°C to +125°C 50 2.3V VI = 0V IO = 8mA 25°C 8 –40°C to +85°C 12 –40°C to +125°C 12 VI = 2.3V IO = -8mA 25°C 11 –40°C to +85°C 30 –40°C to +125°C 30 VI = 0V IO = 24mA 25°C 7 –40°C to +85°C 9 –40°C to +125°C 9 VI = 3V IO = -24mA 25°C 9 –40°C to +85°C 20 –40°C to +125°C 20 4.5V VI = 0V IO = 30mA 25°C 6 –40°C to +85°C 7 –40°C to +125°C 7 VI = 2.4V IO = 30mA 25°C 7 –40°C to +85°C 12 –40°C to +125°C 12 VI = 4.5V IO = -30mA 25°C 7 –40°C to +85°C 15 –40°C to +125°C 15 rrange ON-state switch resistance over signal range 0 ≤ VSn ≤ VDD ID = -4mA 25°C 210 Ω –40°C to +85°C 210 –40°C to +125°C 210 2.3V ID = -8mA 25°C 85 –40°C to +85°C 85 –40°C to +125°C 85 3V ID = -24mA 25°C 30 –40°C to +85°C 30 –40°C to +125°C 30 4.5V ID = -30mA 25°C 18 –40°C to +85°C 18 –40°C to +125°C 18 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN4599-Q1
5.6 Electrical Characteristics (continued)
Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔrON Maximum ON resistance between any two channels 2V VSn = 1.15V ID = -4mA 25°C 0.5 Ω –40°C to +85°C 0.5 2.3V VSn = 1.6V ID = -8mA 25°C 0.1 –40°C to +85°C 0.1 3V VSn = 2.1V ID = -24mA 25°C 0.1 –40°C to +85°C 0.1 4.5V VSn = 3.15V ID = -30mA 25°C 0.1 –40°C to +85°C 0.1 ron(flat) ON resistance flatness 0 ≤ VSn ≤ VDD ID = -4mA 25°C 110 Ω –40°C to +85°C 110 –40°C to +125°C 110 2.3V ID = -8mA 25°C 26 –40°C to +85°C 26 –40°C to +125°C 40 3V ID = -24mA 25°C 9 –40°C to +85°C 9 –40°C to +125°C 10 4.5V ID = -30mA 25°C 4 –40°C to +85°C 4 –40°C to +125°C 5 Ioff Switch OFF leakage current 2V VS = 1V / 1.62V VD = 1.62V / 1V 25°C ±5 nA –40°C to +85°C ±25 –40°C to +125°C ±100 5.5V VS = 4.5V / 1.5V VD = 1.5V / 4.5V 25°C ±5 –40°C to +85°C ±25 –40°C to +125°C ±100 IS(on) ON-state switch leakage current 5.5 VI = VDD or GND, VO = Open 25°C ±15 nA–40°C to +85°C ±50 –40°C to +125°C ±100 IIN Control input current 0V to 5.5V 0 ≤ VIN ≤ VDD 25°C ±0.05 ±0.1 µA–40°C to +85°C ±1 –40°C to +125°C ±1 IDD Supply current 5.5V SEL = VDD or GND 25°C 1 µA–40°C to +85°C 10 –40°C to +125°C 35 CI Control input capacitance 5V SEL (VDD/2) 25°C 2.7 pF–40°C to +85°C 2.7 SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Cio(off) Switch input/output capacitance 5V Sn (VDD/2) 25°C 5.2 pF–40°C to +85°C 5.2 Cio(on) Switch input/output capacitance Sn (VDD/2) 25°C 21 pF –40°C to +85°C 21 –40°C to +125°C 21 D (VDD/2) 25°C 21 –40°C to +85°C 21 –40°C to +125°C 21 (1) TA = 25C
5.7 Analog Channel Specifications
over operating free-air temperature range (unless otherwise noted) Parameter FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VDD MIN NOM MAX UNIT Frequency response (switch on) D or Sn Sn or D RL = 50Ω, fin = sine wave 2V 250 MHz 2.3V 250 3V 250 4.5V 250 Crosstalk (between switches) S1 or S2 S2 or S1 RL = 50Ω, fin = 1MHz sine wave 2V -54 dB 2.3V -54 3V -54 4.5V -54 Feed through attenuation (switch off) D or Sn Sn or D CL = 5pF, RL = 50Ω, fin = 1MHz (sine wave) 2V -57 dB 2.3V -57 3V -57 4.5V -57 Charge injection SEL (Vs = VDD/2) D CL = 0.1nF, RL = 1MΩ 3.3V 3 pC 5V 7 Total harmonic distortion D or Sn Sn or D VI = 4.0Vp-p, Vbias = VDD/2, RL = 10kΩ, fin = 600Hz to 20kHz (sine wave) 4.5V 0.01 % www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN4599-Q1
5.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) Parameter FROM (INPUT) TO (OUTPUT) VDD MIN NOM MAX UNIT ttran RL = 200Ω, CL = 15pF, VS = 1V D or Sn Sn or D 2V ± 0.15V ns44 RL = 200Ω, CL = 15pF, VS = 2V D or Sn Sn or D 3.3V ± 0.3V ns20 RL = 200Ω, CL = 15pF, VS = 3V D or Sn Sn or D 5V ± 0.5V ns18 TB-M Break before make time 2V ± 0.15V 0.5 ns 2.5V ± 0.2V 0.5 3.3V ± 0.3V 0.5 5V ± 0.5V 0.5 SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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5.9 Typical Characteristics
at TA = 25°C, VDD = 5V (unless otherwise noted) Logic Voltage (V) Supply Current (PA) 100 200 300 400 500 VDD = 5 VVDD = 3.3 V D003 TA = 25°C Figure 5-1. Supply Current vs Logic Voltage VDD - Supply Voltage (V) Time (ns) Rising Falling D004 TA = 25°C Figure 5-2. Ttransition vs Supply Voltage Frequency (Hz) Magnitude (dB) -90 -80 -70 -60 -50 -40 -30 -20 -10 100k 1M 10M 100M D005 TA = 25°C Figure 5-3. Crosstalk and Off-Isolation vs Frequency Frequency (Hz) Gain (dB) 1M 10M 100M D006 TA = 25°C Figure 5-4. Frequency Response www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN4599-Q1
6 Parameter Measurement Information
6.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote on-resistance. The measurement setup used to measure R ON is shown in Figure 6-1. Voltage (V) and current (ISD) are measured using this setup, and RON is computed with RON = V / ISD: V D VS ISD Sx Figure 6-1. On-Resistance Measurement Setup
6.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). The setup used to measure off-leakage current is shown in Figure 6-2. VDD VDD GND VS D VD A Is (OFF) Figure 6-2. Off-Leakage Measurement Setup
6.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 6-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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D VD ID (ON) VDD VDD GND VS D Vs A IS (ON) N.C. N.C.A Figure 6-3. On-Leakage Measurement Setup
6.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the logic control signal has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 6-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION. VIH VIL tTRANSITION 10% 90% OUTPUT 0 V Logic Control (VSEL) VDD tTRANSITION VS OUTPUT RL CL SEL D GND VSEL 0 V tr < 5ns tf < 5ns VDD VDD 0.1 F Figure 6-4. Transition-Time Measurement Setup
6.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is switching. The output first breaks from the on-state switch before making the connection with the next on-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 6-5 shows the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN4599-Q1
90% Output 0 V tOPEN (BBM) = min ( tBBM 1, tBBM 2) tBBM 2 Logic Control (VSEL) tr < 5ns tf < 5ns VS OUTPUT RL CL SEL D GND VSEL VDD VDD 0.1 F Figure 6-5. Break-Before-Make Delay Measurement Setup
6.6 Charge Injection
The SN4599-Q1 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QC. Figure 6-6 shows the setup used to measure charge injection from Drain (D) to Source (Sx). VDD VDD VSS VSS OUTPUT CL SEL D GND 0.1 F 0.1 F VOUT Output VS QC = CL × VOUT VOUT VSEL VD N.C. 0 V VDD VSEL Figure 6-6. Charge-Injection Measurement Setup
6.7 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 6-7 shows the setup used to measure, and the equation used to calculate off isolation. SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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S D 50Q VSIG RL 50QSX RL 50Q VS VDD 0.1µF Figure 6-7. Off Isolation Measurement Setup O f f I s ol at i on = 20 × L og V OU T V S (1)
6.8 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. Figure 6-8 shows the setup used to measure, and the equation used to calculate crosstalk. NETWORK ANALYZER GND VSIG 50Q VOUT RL 50Q RL D 50Q VS VDD 0.1µF Figure 6-8. Crosstalk Measurement Setup C ℎ an n el − t o − C ℎ ann el C r os t al k = 20 × L o g V O UT V S (2)
6.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 6-9 shows the setup used to measure bandwidth. www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN4599-Q1
S D 50Q VSIG RL 50Q VS VDD 0.1µF SX RL 50Q Figure 6-9. Bandwidth Measurement Setup SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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7 Detailed Description
7.1 Functional Block Diagram
The SN4599-Q1 is an 2:1 (SPDT), 1-channel switch where the input is controlled with a single select (SEL) control pin. SEL D Figure 7-1. SN4599-Q1 Functional Block Diagram
7.2 Feature Description
7.2.1 Bidirectional Operation
The SN4599-Q1 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). The device has very similar characteristics in both directions and supports both analog and digital signals.
7.2.2 Rail to Rail Operation
The valid signal path input/output voltage for SN4599-Q1 ranges from GND to VDD.
7.2.3 Fail-Safe Logic
The SN4599-Q1 supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5V, regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the select pin of the SN4599-Q1 to be ramped to 5.5V while V DD = 0V. Additionally, the feature enables operation of the SN4599-Q1 with VDD = 2V while allowing the select pin to interface with a logic level of another device up to 5.5V.
7.3 Device Functional Modes
The select (SEL) pin of the SN4599-Q1 controls which source channel is connected to the drain of the device. When a signal path is not selected, that source pin is in high impedance mode (HI-Z). The control pin can be as high as 5.5V.
7.4 Truth Tables
Table 7-1. SN4599-Q1 Truth Table CONTROL LOGIC (SEL) Selected Source (Sx) Connected To Drain (D) Pin 0 S1 1 S2 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN4599-Q1
8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
SN4599-Q1 offers good system performance across a wide operating supply (2V to 5.5V). Additionally, the control input pin supports Fail-Safe Logic which allows for operation up to 5.5V, regardless of the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These features of the SN4599-Q1 general purpose multiplexer, reduce system complexity, board size, and overall system cost.
8.2 Typical Application
8.2.1 Switchable Operational Amplifier Gain Setting
One example application of the SN4599-Q1 is to change an Op Amp from unity gain setting to an inverting amplifier configuration. Utilizing a switch allows a system to have a configurable gain and allows the same architecture to be utilized across the board for various inputs to the system. Figure 8-1 shows the SN4599-Q1 configured for gain setting application. TLV9001Inverting Input OutputUnity Gain R R SN4599-Q1 D SEL Figure 8-1. Switchable Op Amp Gain Setting
8.2.1.1 Design Requirements
This design example uses the parameters listed in Table 8-1. Table 8-1. Design Parameters PARAMETERS VALUES Input Signal 0V to 3.3V Mux Supply (VDD) 3.3V Op Amp Supply (V+/ V-) ±3.3V Mux I/O signal range 0V to VDD (Rail to Rail) Control logic thresholds 2.31V up to 5.5V
8.2.1.2 Detailed Design Procedure
The application shown in Figure 8-1 demonstrates how to use a single control input and toggle between gain settings of -1 and +1. If switching between inverting and unity gain is not required, then the SN4599-Q1 can be utilized in the feedback path to select different feedback resistors and provide scalable gain settings for configurable signal conditioning. SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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The SN4599-Q1 can operate without any external components except for the supply decoupling capacitors. It is recommended to have a weak pull-down or pull-up resistor so that the input of the select pin is in a known state. All inputs to the switch must fall within the recommend operating conditions of the SN4599-Q1 including signal range and continuous current. For this design with a supply of 3.3V, the signal range can be 0V to 3.3V and the maximum continuous current can be 30mA.
8.2.1.3 Application Curve
VS or VD - Source or Drain Voltage (V) On Resistance (:) 0 1 2 3 4 5 5.5 VDD = 5.5 V VDD = 4.5 V VDD = 3.63 V VDD = 3 V D001 TA = 25°C Figure 8-2. On-Resistance vs Source or Drain Voltage
8.2.2 Input Control for Power Amplifier
Another application of the SN4599-Q1 is for input control of a power amplifier. Utilizing a switch allows a system to control when the DAC is connected to the power amplifier, and can stop biasing the power amplifier by switching the gate to GND. Figure 8-3 shows the SN4599-Q1 configured for control of the power amplifier. RF Output SN4599-Q1 SEL DAC RF Input Figure 8-3. Input Control of Power Amplifier
8.2.2.1 Design Requirements
This design example uses the parameters listed in Table 8-1. Table 8-2. Design Parameters PARAMETERS VALUES Supply (VDD) 5V Mux I/O signal range 0V to VDD (Rail to Rail) Control logic thresholds Up to 5.5V www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN4599-Q1
8.2.2.2 Detailed Design Procedure
The application shown in Figure 8-3 demonstrates how to toggle between the DAC output and GND to control a power amplifier using a single control input. The DAC output is utilized to bias the gate of the power amplifier and can be disconnected from the circuit using the select pin of the switch. The SN4599-Q1 can operate without any external components except for the supply decoupling capacitors. It is recommended to have a weak pull-down or pull-up resistor so that the input of the select pin is in a known state. All inputs to the switch must fall within the recommend operating conditions of the SN4599-Q1 including signal range and continuous current. For this design with a supply of 5V, the signal range can be 0V to 5V and the maximum continuous current can be 30mA.
8.2.2.3 Application Curve
A key parameter for this application is the transition time of the device. Faster transition time allows the system to toggle between input sources at a faster rate and allows the output to settle to the final value. The SN4599-Q1 has a transition time that varies with supply voltage and is shown in Figure 8-4 VDD - Supply Voltage (V) Time (ns) Rising Falling D004 TA = 25°C Figure 8-4. Ttransition vs Supply Voltage
8.3 Power Supply Recommendations
The SN4599-Q1 operates across a wide supply range of 2V to 5.5V. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices. Power-supply bypassing improves noise margin and prevents switching noise propagation from the V DD supply to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from V DD to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes.
8.4 Layout
8.4.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 8-5 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
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1W min. W Figure 8-5. Trace Example Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 8-6 shows an example of a PCB layout with the SN4599-Q1. Some key considerations are:
- Decouple the VDD pin with a 0.1µF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the VDD supply.
- Keep the input lines as short as possible.
- Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
8.4.2 Layout Example
Wide (low inductance) trace for power SN4599-Q1 Figure 8-6. SN4599-Q1 Layout Example www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN4599-Q1
9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
- Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
- Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES April 2024 * Initial Release
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN4599-Q1
11.1 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SN4599DBVRQ1 SOT-23 DBV 6 3000 178 9 2.4 2.5 1.2 4 8 Q3 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN4599-Q1
TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN4599DBVRQ1 SOT-23 DBV 6 3000 180 180 18 SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN4599-Q1
11.2 Mechanical Data
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50 0.25 0.6
0.3 TYP
0 TYP
1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.
0.2 C A B
0.1 C SCALE 4.000 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: SN4599-Q1
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/C 06/2021 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL SN4599-Q1 SCDS475 – APRIL 2024 www.ti.com ADVANCE INFORMATION
24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN4599-Q1
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4 www.ti.com SN4599-Q1 SCDS475 – APRIL 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: SN4599-Q1
www.ti.com 1-May-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PSN4599DBVRQ1 ACTIVE SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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