PSN3257QDYYRQ1

SN3257-Q1_V01 TI1 | Alldatasheet

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ADVANCE□INFORMATION SN3257-Q1 SEL S1A D1 S1B S2A S2B S3A S3B S4A S4B EN LOGIC CONTROL* *Internal 6MOPull-Down on Logic Pins Processor GND VDD VDDVI/O 1.8V Logic I/O SEL GND JTAG DEBUG, SPI, GPIO RAM CPU Peripherals 0.1µF EN S1B S2B S3B S4B SPI / JTAG / UART Device #2 MISO / TDI / GPIO MOSI / TDO / GPIO SCLK / TCK / GPIO SS / TMS / GPIO S1A S2A S3A S4A SPI / JTAG / UART Device #1 MISO / TDI / GPIO MOSI / TDO / GPIO SCLK / TCK / GPIO SS / TMS / GPIO Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. SN3257-Q1 SCDS411A –JULY 2019–REVISED AUGUST 2016 SN3257-Q15-V,LowPropagationDelay,2:1(SPDT),4-ChannelSwitchwith1.8VLogic

1 Features

1• AEC-Q100 qualified for automotive application – Temperature grade 1: -40°C to +125°C, TA

• Wide supply range: 1.5 V to 5.5 V
• High bandwidth: 900 MHz
• Low propagation delay: 70 ps
• Low on-resistance: 5 Ω
• Break-before-make switching
• Bidirectional Signal Path
• Supports Input Voltage Beyond Supply
• 1.8 V Logic Compatible
• Integrated Pull Down Resistor on Logic Pins
• Fail-Safe Logic
• Powered-off Protection up to 3.6 V Signals

2 Applications

• SPI multiplexing
• I2S multiplexing
• Flash memory sharing
• Automotive head unit
• Infotainment & cluster
• Battery management system (BMS)
• ADAS domain controller
• Head-up display
• Surround view system ECU
• Rear seat entertainment
• Digital cockpit processing unit
• Automotive navigation
• Automotive lighting
• On-board (OBC) & wireless charger

3 Description

The SN3257-Q1 is an automotive grade complementary metal-oxide semiconductor (CMOS) switch that supports high speed signals with low prop delay. The SN3257-Q1 offers a 2:1 (SPDT) switch configuration with 4-channels making it ideal for various protocols such as SPI and I2S. The device supports bidirectional analog and digital signals on the source (SxA, SxB) and drain (Dx) pins and can pass signals above supply up to VDD x 2, with a maximum input/output voltage of 5.5 V. The SN3257-Q1 has an active low EN pin that is used to enable/disable all channels simultaneously. When the EN pin is LOW, one of the two switch inputs is selected based on the state of SEL pin. Powered-off protection up to 3.6 V on the signal path of the SN3257-Q1 provides isolation when the supply voltage is removed (VDD = 0 V). Without this protection feature, switches can back-power the supply rail through an internal ESD diode and cause potential damage to the system. Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pin, protecting the device from potential damage. Both logic control inputs have 1.8 V logic compatible thresholds, ensuring both TTL and CMOS logic compatibility. Integrated pull down resistor on the logic pins removes external components to reduce system size and cost. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN3257-Q1 TSSOP (16) 5.00 mm × 4.40 mm SOT-23-THIN (16) 4.20 mm x 2.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Application Example Block Diagram

ADVANCE□INFORMATION SN3257-Q1 SCDS411A –JULY 2019–REVISED AUGUST 2016 www.ti.com Product Folder Links: SN3257-Q1 Submit Documentation Feedback Copyright © 2019–2016, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 25

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2019) to Revision A Page

ADVANCE□INFORMATION 1SEL 16 VDD 2S1A 15 EN 3S1B 14 S4A 4D1 13 S4B 5S2A 12 D4 6S2B 11 S3A 7D2 10 S3B 8GND 9 D3 Not to scale 1SEL 16 VDD 2S1A 15 EN 3S1B 14 S4A 4D1 13 S4B 5S2A 12 D4 6S2B 11 S3A 7D2 10 S3B 8GND 9 D3 Not to scale SN3257-Q1 www.ti.com SCDS411A –JULY 2019–REVISED AUGUST 2016 Product Folder Links: SN3257-Q1 Submit Documentation FeedbackCopyright © 2019–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

(1) I = input, O = output, I/O = input and output, P = power (2) Refer to Device Functional Modes for what to do with unused pins. Pin Functions PIN TYPE(1) DESCRIPTION(2) NAME NO. SEL 1 I Select pin: controls state of switches according to Table 1. Internal 6 MΩ pull-down to GND. S1A 2 I/O Source pin 1A. Can be an input or output. S1B 3 I/O Source pin 1B. Can be an input or output. D1 4 I/O Drain pin 1. Can be an input or output. S2A 5 I/O Source pin 2A. Can be an input or output. S2B 6 I/O Source pin 2B. Can be an input or output. D2 7 I/O Drain pin 2. Can be an input or output. GND 8 P Ground (0 V) reference D3 9 I/O Drain pin 3. Can be an input or output. S3B 10 I/O Source pin 3B. Can be an input or output. S3A 11 I/O Source pin 3A. Can be an input or output. D4 12 I/O Drain pin 4. Can be an input or output. S4B 13 I/O Source pin 4B. Can be an input or output. S4A 14 I/O Source pin 4A. Can be an input or output. EN 15 I Active low enable: When this pin is high, all switches are turned off. When this pin is low, SEL pin controls the signal path selection. Internal 6 MΩ pull-down to GND. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.

ADVANCE□INFORMATION SN3257-Q1 SCDS411A –JULY 2019–REVISED AUGUST 2016 www.ti.com Product Folder Links: SN3257-Q1 Submit Documentation Feedback Copyright © 2019–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to ground, unless otherwise specified.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) MIN MAX UNIT VDD Supply voltage –0.5 6 V VSEL or VEN Logic control input pin voltage (SEL or EN) –0.5 6 V ISEL or IEN Logic control input pin current (SEL or EN) –30 30 mA VS or VD Source or drain pin voltage –0.5 6 V IS or ID (CONT) Source and drain pin continuous current: (SxA, SxB, Dx) –25 25 mA Tstg Storage temperature –65 150 °C TJ Junction temperature 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 ±2000 V Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B ±750 (1) Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 5.5 V. (2) VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V.

6.3 Recommended Operating Conditions

VDD Supply voltage 1.5 5.5 V VS or VD Signal path input/output voltage (source or drain pin), VDD ≥ 1.5 V(1) 0 VDD x 2 V VS_off or VD_off Signal path input/output voltage (source or drain pin), VDD < 1.5 V(2) 0 3.6 V VSEL or VEN Logic control input voltage (EN, SEL) 0 5.5 V TA Ambient temperature –40 125 ºC (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) DEVICE DEVICE UNITPW (TSSOP) DYY (SOT-23)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 117.4 123.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.9 70.5 °C/W RθJB Junction-to-board thermal resistance 63.7 50.4 °C/W ΨJT Junction-to-top characterization parameter 6.9 5.0 °C/W ΨJB Junction-to-board characterization parameter 63.1 50.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

ADVANCE□INFORMATION SN3257-Q1 www.ti.com SCDS411A –JULY 2019–REVISED AUGUST 2016 Product Folder Links: SN3257-Q1 Submit Documentation FeedbackCopyright © 2019–2016, Texas Instruments Incorporated

6.5 Electrical Characteristics

VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VDD Power supply voltage 1.5 5.5 V IDD Active supply current VSEL = 0 V, 1.4V or VDD VS = 0 V to 5.5 V 40 68 μA IDD_STANDBY Supply current when disabled VEN = 1.4V or VDD VS = 0 V to 5.5 V 7.5 15 µA DC CHARACTERISTICS RON On-resistance VS = 0 V to VDD*2 VS(max) = 5.5 V ISD = 8 mA Refer to ON-State Resistance Figure 2 5 Ω ΔRON On-resistance match between channels VS = VDD ISD = 8 mA Refer to ON-State Resistance Figure 0.07 0.8 Ω RON (FLAT) On-resistance flatness VS = 0 V to VDD ISD = 8 mA Refer to ON-State Resistance Figure 1 2.5 Ω IPOFF Powered-off I/O pin leakage current VDD = 0 V VS = 0 V to 3.6 V VD = 0 V Refer to Ipoff Leakage Figure –8 0.01 8 µA IS(OFF) ID(OFF) OFF leakage current Switch Off VD = 0.8*VDD / 0.2*VDD VS = 0.2*VDD / 0.8*VDD Refer to Off Leakage Figure –900 0.03 900 nA ID(ON) IS(ON) ON leakage current Switch On VD = 0.8*VDD / 0.2*VDD, S pins floating or VS = 0.8*VDD / 0.2*VDD, D pins floating Refer to On Leakage Figure –900 0.01 900 nA LOGIC INPUTS VIH Input logic high 1.2 5.5 V VIL Input logic low 0 0.45 V IIH Input high leakage current VSEL = 1.8 V, VDD 1 ±2 μA IIL Input low leakage current VSEL = 0 V 0.2 ±2 μA RPD Internal pull-down resistor on logic pins 6 MΩ CI Logic input capacitance VSEL = 0 V, 1.8 V or VDD f = 1 MHz 3 pF

ADVANCE□INFORMATION SN3257-Q1 SCDS411A –JULY 2019–REVISED AUGUST 2016 www.ti.com Product Folder Links: SN3257-Q1 Submit Documentation Feedback Copyright © 2019–2016, Texas Instruments Incorporated

6.6 Dynamic Characteristics

VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COFF Source and drain off capacitance VS = 2.5 V VSEL= 0 V f = 1 MHz Refer to Capacitance Figure Switch OFF 4 pF CON Source and drain on capacitance VS = 2.5 V VSEL= 0 V f = 1 MHz Refer to Capacitance Figure Switch ON 8 pF QC Charge Injection VS = VDD/2 RS = 0 Ω, CL =1 nF Refer to Charge Injection Figure Switch ON 3.5 pC OISO Off isolation RL = 50 Ω f = 100 kHz Refer to Off Isolation Figure Switch OFF –90 dB RL = 50 Ω f = 1 MHz Refer to Off Isolation Figure Switch OFF –75 dB XTALK Channel to Channel crosstalk RL = 50 Ω f = 100 kHz Refer to Crosstalk Figure Switch ON –90 dB BW Bandwidth RL = 50 Ω Refer to Bandwidth Figure Switch ON 900 MHz ILOSS Insertion loss RL = 50 Ω f = 1 MHz Refer to Bandwidth Figure Switch ON –0.12 dB

ADVANCE□INFORMATION SN3257-Q1 www.ti.com SCDS411A –JULY 2019–REVISED AUGUST 2016 Product Folder Links: SN3257-Q1 Submit Documentation FeedbackCopyright © 2019–2016, Texas Instruments Incorporated

6.7 Timing Requirements

VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tTRAN Transition time from control input VDD = 2.5 V to 5.5 V VS = VDD RL = 200 Ω, CL = 15pF Refer to Transition Timing Figure 160 350 ns tTRAN Transition time from control input VDD < 2.5 V VS = VDD RL = 200 Ω, CL = 15pF Refer to Transition Timing Figure 180 580 ns tON(EN) Device turn on time from enable pin VS = VDD RL = 200 Ω, CL = 15pF Refer to Ton(EN) & Toff(EN) Figure 12 35 µs tOFF(EN) Device turn off time from enable pin VS = VDD RL = 200 Ω, CL = 15pF Refer to Ton(EN) & Toff(EN) Figure 50 95 ns tON(VDD) Device turn on time (VDD to output) VS = 3.6 V VDD rise time = 1us RL = 200 Ω, CL = 15pF Refer to Ton(vdd) & Toff(vdd) Figure 20 60 µs tOFF(VDD) Device turn off time (VDD to output) VS = 3.6 V VDD fall time = 1us RL = 200 Ω, CL = 15pF Refer to Ton(vdd) & Toff(vdd) Figure 1.2 2.7 µs tOPEN (BBM) Break before make time VS = 1 V RL = 200 Ω, CL = 15pF Refer to Topen(BBM) Figure 0.5 ns tSK(P) Inter - channel skew - SOT-23 (DYY) Refer to Tsk Figure 10 ps tSK(P) Inter - channel skew - TSSOP (PW) Refer to Tsk Figure 18 ps tPD Propagation delay - SOT-23 (DYY) Refer to Tpd Figure 70 ps tPD Propagation delay - TSSOP (PW) Refer to Tpd Figure 95 ps

6.8 Typical Characteristics

Figure 1. On-Resistance vs Source or Drain Voltage Figure 2. On-Resistance vs Source or Drain Voltage Figure 3. On-Resistance vs Source or Drain Voltage Figure 4. Supply Current vs Logic Voltage Figure 5. IPOFF Leakage vs Source or Drain Voltage Figure 6. IPOFF Leakage vs Temperature

7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance. Figure 10. On-Resistance Measurement Setup

7.2 Off-Leakage Current

off. This current is denoted by the symbol IS (OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID (OFF). The setup used to measure both off-leakage currents is shown in Figure 11. Figure 11. Off-Leakage Measurement Setup

7.3 On-Leakage Current

is on. This current is denoted by the symbol IS (ON). on. This current is denoted by the symbol ID (ON). measuring the on-leakage current, denoted by IS(ON) or ID(ON). Figure 12. On-Leakage Measurement Setup

7.4 IPOFF Leakage Current

powered off. This current is denoted by the symbol IPOFF. The setup used to measure both IPOFF leakage current is shown in Figure 13. Figure 13. IPOFF Leakage Measurement Setup

7.5 Transition Time

Figure 14. Transition-Time Measurement Setup system. Figure 15 shows the setup used to measure the enable time, denoted by the symbol tON (EN). system. Figure 15 shows the setup used to measure enable time, denoted by the symbol tOFF (EN). Figure 15. tON (EN) and tOFF (EN) Time Measurement Setup

the system. Figure 16 shows the setup used to measure turn on time, denoted by the symbol tON (VDD). system. Figure 16 shows the setup used to measure turn off time, denoted by the symbol tOFF (VDD). Figure 16. tON (VDD) and tOFF (VDD)Time Measurement Setup

7.8 Break-Before-Make Delay

the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). Figure 17. Break-Before-Make Delay Measurement Setup

7.9 Propagation Delay

Figure 18. Propagation Delay Measurement Setup

7.10 Skew

used to measure skew, denoted by the symbol tSK. Figure 19. Skew Measurement Setup

1 MHz

7.11 Charge Injection

measure charge injection from source (Sx) to drain (Dx). Figure 20. Charge-Injection Measurement Setup

7.12 Capacitance

shows the setup used to measure capacitance. Figure 21. Capacitance Measurement Setup

7.13 Off Isolation

shows the setup used to measure off isolation. Use off isolation equation to compute off isolation. Figure 22. Off Isolation Measurement Setup

7.14 Channel-to-Channel Crosstalk

at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. Figure 23 shows the setup used to measure, and the equation used to compute crosstalk. Figure 23. Channel-to-Channel Crosstalk Measurement Setup

7.15 Bandwidth

Figure 24. Bandwidth Measurement Setup

8 Detailed Description

8.1 Overview

The SN3257-Q1 is an automotive qualified 2:1 (SPDT) 4-channel switch with powered-off protection up to 3.6 V. the valid supply voltage range. through an internal ESD diode and cause potential damage to the system.

8.2 Functional Block Diagram

Figure 25. SN3257-Q1 Functional Block Diagram

8.3 Feature Description

8.3.1 Bidirectional Operation

8.3.2 Beyond Supply Operation

GND to VDD x 2, with a maximum input/output voltage of 5.5 V. Example 1: If the SN3257-Q1 is powered at 1.5 V, the signal range is 0 V to 3 V. Example 2: If the SN3257-Q1 is powered at 3 V, the signal range is 0 V to 5.5 V. Example 2: If the SN3257-Q1 is powered at 3.6 V, the signal range is 0 V to 5.5 V. Example 3: If the SN3257-Q1 is powered at 5.5 V, the signal range is 0 V to 5.5 V. voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.

ADVANCE□INFORMATION SN3257-Q1 www.ti.com SCDS411A –JULY 2019–REVISED AUGUST 2016 Product Folder Links: SN3257-Q1 Submit Documentation FeedbackCopyright © 2019–2016, Texas Instruments Incorporated Feature Description (continued) 8.3.3 1.8 V Logic Compatible Inputs The SN3257-Q1 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input thresholds remain fixed, allowing a 1.8-V processor GPIO to control the SN3257-Q1 without the need for an external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Powered-off Protection

Powered-off protection up to 3.6 V on the signal path of the SN3257-Q1 provides isolation when the supply voltage is removed (VDD = 0 V). When the SN3257-Q1 is powered-off, the I/Os of the device remain in a high-Z state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing on the signal path. The device performance remains within the leakage performance mentioned in the Electrical Specifications. For more information on powered-off protection, refer to Eliminate Power Sequencing with Powered-off Protection Signal Switches.

8.3.5 Fail-Safe Logic

The SN3257-Q1 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the select pins of the SN3257-Q1 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature enables operation of the SN3257-Q1 with VDD = 1.5 V while allowing the select pins to interface with a logic level of another device up to 5.5 V.

8.3.6 Low Capacitance

The SN3257-Q1 has low capacitance in both the ON and OFF states on the source and drain pins. Low capacitance helps to reduce large overshoots and ringing of an amplifier circuit when the switch is connected to the feedback network. Additionally, low capacitance improves system settling time by reducing the switch time constant formed by the On-resistance and On-capacitance. For more information on the benefits of low capacitance refer to Improve Stability Issues with Low CON Multiplexers.

8.3.7 Integrated Pull-Down Resistors

The SN3257-Q1 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left floating. This feature integrates up to four external components and reduces system size and cost.

8.4 Device Functional Modes

to GND so that it powers-on in a known state. The SN3257-Q1 can be operated without any external components except for the supply decoupling capacitors. (SxA, SxB, or Dx) should be connected to GND.

8.4.1 Truth Tables

Table 1. SN3257-Q1 Truth Table

1 X(1) Hi-Z (OFF)

Figure 26. SN3257-Q1 Functional Block Diagram

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

to 3.6 V. These features reduce system complexity, board size, and overall system cost.

9.2 Typical Application

to minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications. Figure 27. Multiplexing Flash Memory

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 2. Table 2. Design Parameters

9.2.2 Detailed Design Procedure

The SN3257-Q1 can be operated without any external components except for the supply decoupling capacitors. feature and the inputs can range from 0 V to 3.6 V when VDD = 0 V. The max continuous current can be 25 mA.

9.2.3 Application Curves

Figure 28. Propagation Delay and Skew Measurement

10 Power Supply Recommendations

ratings because stresses beyond the listed ratings can cause permanent damage to the devices. supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground. inductance and is beneficial for connections to ground planes.

11 Layout

11.1 Layout Guidelines

maintains constant trace width and minimizes reflections. Figure 29. Trace Example hole pins are not recommended at high frequencies. regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals. Avoid stubs on the high-speed signals traces because they cause signal reflections. Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits. signal layers separated by a ground and power layer as shown in Figure 30. Figure 30. Example Layout number of signal vias reduces EMI by reducing inductance at high frequencies.

capacitor voltage rating is sufficient for the VDD supply. High-speed switches require proper layout and design procedures for optimum performance. Keep the input lines as short as possible. Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup. possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

Figure 31. Example Layout

ADVANCE□INFORMATION SN3257-Q1 www.ti.com SCDS411A –JULY 2019–REVISED AUGUST 2016 Product Folder Links: SN3257-Q1 Submit Documentation FeedbackCopyright © 2019–2016, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

Texas Instruments, Improve Stability Issues with Low CON Multiplexers. Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches. Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches. Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers. Texas Instruments, High-Speed Interface Layout Guidelines. Texas Instruments, High-Speed Layout Guidelines. Texas Instruments, QFN/SON PCB Attachment. Texas Instruments, Quad Flatpack No-Lead Logic Packages.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 29-Aug-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PSN3257QDYYRQ1 ACTIVE SOT-23-THN DYY 16 3000 TBD Call TI Call TI -40 to 125 PSN3257QPWRQ1 ACTIVE TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 SN3257QDYYRQ1 PREVIEW SOT-23-THN DYY 16 3000 TBD Call TI Call TI -40 to 125 SN3257QPWRQ1 PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 29-Aug-2019 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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