PSMN005-75B

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N-channel enhancement mode ﬁeld-effect transistor Rev. 01 — 26 April 2002 Product data 1. Description N-channel logic level ﬁeld-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PSMN005-75P in SOT78 (TO-220AB) PSMN005-75B in SOT404 (D2-PAK). 2. Features ■ Low on-state resistance ■ Fast switching. 3. Applications ■ High frequency computer motherboard DC to DC converters ■ OR-ing applications. 4. Pinning information [1] It is not possible to make connection to pin 2 of the SOT404 package. Table 1: Pinning - SOT78 and SOT404, simpliﬁed outline and symbol Pin Description Simpliﬁed outline Symbol 1 gate (g) SOT78 (TO-220AB) SOT404 (D2-PAK) 2 drain (d) [1] 3 source (s) mb drain (d) MBK106 mb MBK116 mb s d g MBB076

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 2 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 5. Quick reference data 6. Limiting values Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 75 V ID drain current (DC) T mb =2 5°C; VGS =1 0V - 7 5 A Ptot total power dissipation T mb =2 5°C - 230 W Tj junction temperature - 175 °C R DSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj=2 5°C 4.3 5.0 m Ω Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 75 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 175 °C; RGS =2 0kΩ -7 5 V VGS gate-source voltage (DC) - ±20 V VGSM gate-source voltage t p ≤ 50 µs; pulsed; duty cycle 25%; Tj≤ 150 °C - ±30 V ID drain current (DC) T mb =2 5°C; VGS =1 0V ;Figure 2and 3 -7 5 A Tmb = 100°C; VGS =1 0V ;Figure 2 -7 5 A IDM peak drain current T mb =2 5°C; pulsed; tp ≤ 10 µs;Figure 3 - 400 A Ptot total power dissipation T mb =2 5°C; Figure 1 - 230 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode I S source (diode forward) current (DC) Tmb =2 5°C - 75 A ISM peak source (diode forward) current Tmb =2 5°C; pulsed; tp ≤ 10 µs - 400 A Avalanche ruggedness E DS(AL)S non-repetitive avalanche energy unclamped inductive load; ID =7 5A ;tp = 0.1 ms; VDD =1 5V ; R GS =5 0Ω ; VGS = 10 V; starting Tj=2 5°C - 500 mJ IDS(AL)S non-repetitive avalanche current unclamped inductive load; VDD =1 5V ;RGS =5 0Ω ; VGS =1 0V ; starting Tj=2 5°C -7 5 A

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 3 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. Tmb =2 5°C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa16 120 0 50 100 150 200 Tmb (°C) Pder (%) 03ah89 100 120 0 30 60 90 120 150 180 T mb (ºC) Ider (%) P der P tot P tot 25 C°() ID I D2 5C°() 03ah91 102 103 1 10 10 2 VDS (V) ID (A) DC 100 ms 10 ms Limit RDSon = VDS /ID 1 ms tp = 10 µs 100 µs

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 4 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 7. Thermal characteristics

7.1 Transient thermal impedance

Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting baseFigure 4 - - 0.65 K/W R th(j-a) thermal resistance from junction to ambient SOT78 vertical in still air - 60 - K/W SOT404 mounted on a printed circuit board; minimum footprint - 50 - K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 03af48 10-3 10-2 10-1 10-6 10-5 10-4 10-3 10-2 10-1 1 10tp (s) Zth(j-mb) (K/W) single pulse δ = 0.5 0.2 0.1 0.05 0.02 tp tp T P t Tδ =

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 6 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Tj=2 5°CT j=2 5°C and 175°C; VDS >ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Tj=2 5°C Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 03ah92 100 200 300 0 0.5 1 1.5 2 V DS (V) ID (A) 5.5 V 6 V Tj = 25 ºC 20 V 5 V 6.5 V 8 V 7.5 V 10 V 7 V VGS = 4.5 V 03ah94 100 0123456 V GS (V) ID (A) VDS > ID x RDSon Tj = 175 ºC 25 ºC 03ah93 0.005 0.01 0.015 0 100 200 300 ID (A) R DSon (Ω ) VGS = 20 V Tj = 25 ºC

7 V8 V

6.5 V 5.5 V 6 V 5 V 10 V 03aj03 0.5 1.5 2.5 -60 0 60 120 180 Tj (ºC) a a R DSon R DSon 25 C°()

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 7 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. VGS =0V ;f=1M H z Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa32 -60 0 60 120 180 T j ( o VGS(th) (V) max min typ 03aa35 10-6 10-5 10-4 10-3 10-2 10-1 0246 VGS (V) ID (A) maxtypmin 03ah97 102 103 104 105 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 8 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Tj=2 5°C and 175°C; VGS =0V I D = 75 A; VDD = 60 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. 03ah96 100 0.0 0.5 1.0 1.5 V SD (V) IS (A) Tj = 25 ºC 175 ºC VGS = 0 V 03ah98 0 50 100 150 200 Q G (nC) VGS (V) ID = 75 A Tj = 25 ºC VDD = 60 V

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 9 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9. Package outline Fig 14. SOT78 (TO-220AB). REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT78 SC-46 3-lead TO-220AB D D 1 q p L 123 L1(1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e p mm 2.54 qQA b Dc L2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1(1)E L 00-09-07 01-02-16 mounting base

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 10 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Fig 15. SOT404 (D2-PAK) UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm A 1 D 1 D max. E eL p H D Qc 2.54 2.60 2.20 15.80 14.80 2.90 2.1011 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b DIMENSIONS (mm are the original dimensions) SOT404 0 2.5 5 mm scale Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 e e E b D 1 H D D Q Lp c A mounting base 99-06-25 01-02-12

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor Product data Rev. 01 — 26 April 2002 11 of 13 9397 750 09743 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 10. Revision history Table 6: Revision history Rev Date CPCN Description 01 20020426 - Product data; initial version

Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 26 April 2002 12 of 13 9397 750 09743 Philips Semiconductors PSMN005-75P/75B N-channel enhancement mode ﬁeld-effect transistor © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 26 April 2002 12 of 13 Contact information For additional information, please visithttp://www.semiconductors.philips.com. 11. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Deﬁnitions Short-form speciﬁcation —The data in a short-form speciﬁcation is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. 13. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speciﬁed. 14. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Data sheet status[1] Product status[2] Deﬁnition Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure SNW-SQ-650A.

© Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 April 2002 Document order number: 9397 750 09743

PSMN005-75B specifications and overview.

Summary

N-channel logic level field-effect power transistor in a plastic package using TrenchMOS technology. Rev. 01-26 April 2002

Description

N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology.

Source title PSMN005-75B Datasheet(PDF) - NXP Semiconductors

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