PSD913F1-20JI

PSD913F2 STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Packages

i PSD9XX Family PSD913F2 PSD934F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com

PSD913F2 PSD934F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com

For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com PSD9XX Family PSD913F2 PSD934F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents

1.0 Introduction Preliminary Information PSD913F2, PSD934F2, PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers The PSD9XX family of Programmable System Devices (for 8-bit microcontrollers) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD9XX devices combine many of the peripheral functions found in MCU based applications:

• Up to 2 Mbit of Flash memory
• A secondary 256 Kbit Flash memory
• Over 2,000 gates of Flash programmable logic
• Up to 256 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.

PSD9XX Family Preliminary Information 1.0 Introduction (Cont.) The PSD9XX family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. J In-System Programming (ISP) JTAG An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even while completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as:

• First time programming – How do I get firmware into the flash the very first time? JTAG is the answer, program the PSD while blank with no MCU involvement.
• Inventory build-up of pre-programmed devices – How do I maintain an accurate count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory.
• Expensive sockets – How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. J In-Application Programming (IAP) Two independent flash memory arrays are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems:
• Simultaneous read and write to flash memory – How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two flash memories concurrently, reading code from one while erasing and programming the other during IAP.
• Complex memory mapping – I have only a 64K-byte address space to start with. How can I map these two memories efficiently? A Programmable Decode PLD is the answer. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the 64K-byte address limit.
• Separate program and data space – How can I write to flash memory while it resides in “program” space during field firmware updates, my MCU won’t allow it! The flash PSD provides means to “reclassify” flash memory as “data” space during IAP, then back to “program” space when complete. PSDsoft Express – ST’s software development tool – guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express will take you through the remainder of the design with point and click entry, covering...PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code gener- ation for your MCU, and merging your MCU firmware with the PSD design. When com- plete, two different device programmers are supported directly from PSDsoft – FlashLINK (JTAG) and PSDpro. The PSD9XX is available in 52-pin PLCC and PQFP packages as well as a 64-pin TQFP package.

Preliminary Information PSD9XX Family J A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of the MCU families supported include:

• Intel 8031, 80196, 80186, 80C251
• Motorola 68HC11, 68HC16, 68HC12, and 683XX
• Philips 8031 and 8051XA
• Zilog Z80, Z8, and Z180 J Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into eight equal-sized blocks that can be accessed with user-specified addresses. J Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. J 16, 64 or 256 Kbit SRAM. The SRAM’s contents can be protected from a power failure by connecting an external battery. J General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement external chip selects or combinatorial logic function. J Decode PLD (DPLD) that decodes address for selection of internal memory blocks. J 27 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• 16 of the I/O ports may be configured as open-drain outputs. J Standby current as low as 50 µA for 5 V devices. J Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. J Internal page register that can be used to expand the microcontroller address space by a factor of 256. J Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD9XX into Power Down Mode. J Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
• Data Retention: 15 years 2.0 Key Features

1 OR 2 MBIT MAIN FLASH

8 SECTORS

256 KBIT SECONDARY

4 SECTORS

Figure 1. PSD9XX Block Diagram

and 27 I/O pins. The following table summarizes all the devices in the PSD9XX family. Additional devices will be introduced. Table 1. PSD9XX Product Matrix

5.1 Memory

• A 1 or 2 Mbit Flash
• A secondary 256 Kbit Flash memory
• 16, 64 or 256 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 1 or 2 Mbit Flash is the main memory of the PSD9XX. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. This memory can hold boot code or data. The SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD9XX’s Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.

5.2 Page Register

5.3 PLDs

optimizes cost/performance, and eases design entry. Table 2. PLD I/O Table

5.4 I/O Ports

microcontrollers using multiplexed address/data busses. The JTAG pins can be enabled on Port C for In-System Programming (ISP). Port A can also be configured as a data port for a non-multiplexed bus.

5.5 Microcontroller Bus Interface

9.3.5 contains microcontroller interface examples.

5.6 JTAG Port

Table 3. JTAG Signals on Port C

5.7 In-System Programming

functional blocks of the PSD9XX. Table 4. Methods of Programming Different Functional Blocks of the PSD9XX

5.8 Power Management Unit

the PLD will latch its outputs and go to sleep until the next transition on its inputs. entering the PLD to reduce power consumption. See section 9.5.

Figure 2. PSDsoft Development Tools site (www.psdst.com) or the Literature CD. supported by third party device programmers, see web site for current list.

PSD9XX Family Preliminary Information The following table describes the pin names and pin functions of the PSD9XX. Pins that have multiple names and/or functions are defined using PSDsoft. 7.0 Table 5. PSD9XX Pin Descriptions Pin Name Pin* Type Description (PLCC) ADIO0-7 30-37 I/O This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD[0:7] to this port. 2. If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 in page mode, connect A[0:7] to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. ADIO8-15 39-46 I/O This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A[8:15] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[8:15] to this port. 3. If you are using an 80C251 in page mode, connect AD[8:15] to this port. 4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. CNTL0 47 I The following control signals can be connected to this port, based on your MCU: 1. WR — active-low write input. 2. R_W — active-high read/active low write input. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL1 50 I The following control signals can be connected to this port, based on your MCU: 1. RD — active-low read input. 2. E — E clock input. 3. DS — active-low data strobe input. 4. PSEN — connect PSEN to this port when it is being used as an active-low read signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the read signal. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations.

Preliminary Information PSD9XX Family Pin Name Pin* Type Description (PLCC) CNTL2 49 I This pin can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Reset 48 I Active low reset input. Resets I/O Ports and some of the configuration registers. Must be active at power up. PA0 29 I/O These pins make up Port A. These port pins are configurable PA1 28 and can have the following functions: PA2 27 1. MCU I/O — write to or read from a standard output or PA3 25 input port. PA4 24 2. General Purpose PLD outputs. PA5 23 3. Inputs to the PLDs. PA6 22 4. Latched address outputs (see Table 6). PA7 21 5. Address inputs. For example, PA0-3 could be used for A[0:3] when using an 80C51XA in burst mode. 6. As the data bus inputs D[0:7] for non-multiplexed address/data bus MCUs. 7. D0/A16-D3/A19 in M37702M2 mode. Note: PA0-3 can only output CMOS signals with an option for high slew rate. However, PA4-7 can be configured as CMOS or Open Drain Outputs. PB0 7 I/O These pins make up Port B. These port pins are configurable PB1 6 and can have the following functions: PB2 5 1. MCU I/O — write to or read from a standard output or PB3 4 input port. PB4 3 2. General Purpose PLD outputs. PB5 2 3. Inputs to the PLDs. PB6 52 4. Latched address outputs (see Table 6). PB7 51 Note: PB0-3 can only output CMOS signals with an option for high slew rate. However, PB4-7 can be configured as CMOS or Open Drain Outputs. PC0 20 I/O PC0 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TMS Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC1 19 I/O PC1 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TCK Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. Table 5. PSD9XX Pin Descriptions (cont.)

PSD9XX Family Preliminary Information Table 5. PSD9XX Pin Descriptions (cont.) Pin Name Pin* Type Description (PLCC) PC2 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. Vstby — SRAM standby voltage input for SRAM battery backup. This pin can be configured as a CMOS or Open Drain output. PC3 17 I/O PC3 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TSTAT output for the JTAG interface. 4. Rdy/Bsy output for in-system parallel programming. This pin can be configured as a CMOS or Open Drain output. PC4 14 I/O PC4 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TERR output for the JTAG interface. 4. Vbaton — battery backup indicator output. Goes high when power is being drawn from an external battery. This pin can be configured as a CMOS or Open Drain output. PC5 13 I/O PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDI input for the JTAG interface. This pin can be configured as a CMOS or Open Drain output. PC6 12 I/O PC6 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDO output for the JTAG interface. This pin can be configured as a CMOS or Open Drain output.

1. MCU I/O — write to or read from a standard output or
2. DBE — active-low Data Byte Enable input from 68HC912

This pin can be configured as a CMOS or Open Drain output.

1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
3. General Purpose PLD output.
4. MCU I/O — write to or read from a standard output or
5. General Purpose PLD output
6. CLKIN — clock input to the automatic power-down

unit’s power-down counter, and the PLD AND array.

1. MCU I/O — write to or read from a standard output or
2. General Purpose PLD output.
3. CSI — chip select input. When low, the MCU can access

blocks are disabled to conserve power. Table 6. I/O Port Latched Address Output Assignments* **Refer to the I/O Port Section on how to enable the Latched Address Output function. numbers on other package types.

PSD9XX Family Preliminary Information Table 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD9XX registers. Table 7 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9. 8.0 PSD9XX Register

Description

Register Name Port A Port B Port C Port D Other* Description Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode Control 02 03 Selects mode between MCU I/O or Address Out Stores data for output Data Out 04 05 12 13 to Port pins, MCU I/O output mode Direction 06 07 14 15 Configures Port pin as input or output Configures Port pins as either CMOS or Open Drive Select 08 09 16 17 Drain on some pins, while selecting high slew rate on other pins. Flash Protection C0 Read only – Flash Sector Protection Secondary Flash Read only – PSD Security Protection C2 and Secondary Flash Sector Protection PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register Places PSD memory VM E2 areas in Program and/or Data space on an individual basis. Table 7. Register Address Offset *Other registers that are not part of the I/O ports.

perform multiple functions, and are user configurable.

9.1 Memory Blocks

• The main Flash memory
• Secondary Flash memory
• SRAM. The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 8 summarizes which versions of the PSD9XX contain which memory blocks. Main Flash Secondary Flash Block Device Flash Size Sector Size Block Size Sector Size SRAM PSD913F2 128KB 16KB 32KB 8KB 2KB PSD934F2 256KB 32KB 32KB 8KB 8KB PSD954F2 256KB 32KB 32KB 8KB 32KB

Table 8. Memory Blocks

9.1.1 Main Flash and Secondary Flash Memory Description

can be separately protected from program and erase operations. Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte. and then resumed after reading. C3. This pin is set up using PSDsoft.

PSD9XX Family Preliminary Information

9.1.1.1 Memory Block Selects

The decode PLD in the PSD9XX generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up to three product terms. Having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. When using a microcontroller with separate Program and Data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other when used with the VM Register (see section 9.1.3.1).

9.1.1.2 The Ready/Busy Pin (PC3)

Pin PC3 can be used to output the Ready/Busy status of the PSD9XX. The output on the pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase operation is in progress.

9.1.1.3 Memory Operation

The main Flash and secondary Flash memories are addressed through the microcontroller interface on the PSD9XX device. The microcontroller can access these memories in one of two ways: J The microcontroller can execute a typical bus write or read operationjust as it would if accessing a RAM or ROM device using standard bus cycles. J The microcontroller can execute a specific instructionthat consists of several write and read operations. This involves writing specific data patterns to special addresses within the Flash to invoke an embedded algorithm. These instructions are summarized in Table 9. Typically, Flash memory can be read by the microcontroller using read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. This status test is achieved by a read operation or polling the Rdy/Busy pin (PC3). The Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). The PSD9XX Functional Blocks (cont.)

Preliminary Information PSD9XX Family The PSD9XX Functional Blocks (cont.)

9.1.1.3.1 Instructions

An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include read operations after the initial write operations. The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). The PSD9XX main Flash and Secondary Flash support these instructions (see Table 9): J Erase memory by chip or sector J Suspend or resume sector erase J Program a byte J Reset to read array mode J Read Main Flash Identifier value J Read sector protection status J Bypass Instruction (PSD934F2 and PSD954F2 only) These instructions are detailed in Table 9. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address lines A15-A12 are don’t care during the instruction write cycles. However, the appropriate sector select signal (FSi or CSBOOTi) must be selected. The main Flash and the Secondary Flash Block have the same set of instructions (except Read main Flash ID). The chip selects of the Flash memory will determine which Flash will receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.

Table 9. Instructions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse. erased must be active (high).

1. All bus cycles are write bus cycle except the ones with the “read” label.
2. All values are in hexadecimal.
3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4. Only Address bits A11-A0 are used in Instruction decoding. A15-12 (or A16-A12) are don’t care.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status

or if DQ5 (error flag) goes high.

1. Additional sectors to be erased must be entered within 80µs.
2. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip

select is active and (A1 = 1, A0 = 0).

1. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
2. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
3. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
4. The Erase Resume command is valid only during the Erase Suspend mode.
5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the

Sector Protection Status of the main Flash.

1. Available to PSD934F2 and PSD954F2 devices only.

9.1.1.4 Power-Up Condition

9.1.1.5 Read

special data from these memories. The following sections describe these read functions.

9.1.1.5.1 Read the Contents of Memory

time the read operation is not part of an instruction sequence.

9.1.1.5.2 Read the Main Flash Memory Identifier

9.1.1.5.3 Read the Flash Memory Sector Protection Status

9.1.1.5.4 Read the Erase/Program Status Bits

in Table 10. The status bits can be read as many times as needed. Table 10. Status Bits NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.

1. DQ7-DQ0 represent the Data Bus bits, D7-D0.
2. FSi/CSBOOTi are active high.

bits while an erase or program instruction is being executed by the embedded algorithm. See section 9.1.1.7 for details.

(cont.)

9.1.1.5.5 Data Polling Flag DQ7

When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Write operation is completed, the true logic value is read on DQ7 (in a Read operation). Flash memory specific features: J Data Polling is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. J During an Erase instruction, DQ7 outputs a ‘0’. After completion of the instruction, DQ7 will output the last bit programmed (it is a ‘1’ after erasing). J If the byte to be programmed is in a protected Flash sector, the instruction is ignored. J If all the Flash sectors to be erased are protected, DQ7 will be set to ‘0’ for about 100 µs, and then return to the previous addressed byte. No erasure will be performed.

9.1.1.5.6 Toggle Flag DQ6

The PSD9XX offers another way for determining when the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or CSBOOTi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling will stop and the data read on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features: J The Toggle bit is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). J If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored. J If all the Flash sectors selected for erasure are protected, DQ6 will toggle to ‘0’ for about 100 µs and then return to the previous addressed byte.

9.1.1.5.7 Error Flag DQ5

During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when there is a failure during Flash byte programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit indicates the attempt to program a Flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a byte. In case of an error in Flash sector erase or byte program, the Flash sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset instruction.

9.1.1.5.8 Erase Time-out Flag DQ3

The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to ‘1’. PSD9XX Family Preliminary Information

Preliminary Information PSD9XX Family

9.1.1.6 Programming Flash Memory

Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector basis, programming Flash memory occurs on a byte basis. The PSD9XX main Flash and Secondary Flash memories require the MCU to send an instruction to program a byte or perform an erase function (see Table 9). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD9XX support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.

9.1.1.6.1 Data Polling

Polling on DQ7 is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 3 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD9XX begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the original data byte to be programmed. The MCU continues to poll this location, comparing DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original data, and the Error bit at DQ5 remains ‘0’, then the embedded algorithm is complete. If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 again since DQ7 may have changed simultaneously with DQ5 (see Figure 3). The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a ‘1’ to a bit that was not erased (not erased is logic ‘0’). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with the byte that was intended to be written. When using the Data Polling method after an erase instruction, Figure 3 still applies. However, DQ7 will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 will indicate a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any location within the sector being erased to get DQ7 and DQ5. PSDsoft will generate ANSI C code functions which implement these Data Polling algorithms. The PSD9XX Functional Blocks (cont.)

Figure 3. Data Polling Flow Chart

9.1.1.6.2 Data Toggle

DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 4). that was not erased (not erased is logic ‘0’).

the byte that was intended to be written. sector being erased to get DQ6 and DQ5. Figure 4. Data Toggle Flow Chart

PSD9XX Family Preliminary Information The PSD9XX Functional Blocks (cont.)

9.1.1.7 Unlock Bypass Instruction (PSD934F2 and PSD954F2 only)

The unlock bypass feature allows the system to program bytes to the flash memories faster than using the standard program instruction. The unlock bypass instruction is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h (see Table 9). The flash memory then enters the unlock bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the unlock bypass programm command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles requiredc in the standard program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The falsh memory then returns to reading array data mode.

9.1.1.8 Erasing Flash Memory

The Flash Bulk Erase instruction uses six write operations followed by a Read operation of the status register, as described in Table 9. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.6. The Error bit (DQ5) returns a ‘1’ if there has been an Erase Failure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD9XX will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions.

9.1.1.8.2 Flash Sector Erase Instruction

The Sector Erase instruction uses six write operations, as described in Table 9. Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 µs. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (Erase time-out bit). If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is counting. If DQ3 is ‘1’, the timeout has expired and the PSD9XX is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode. It is not necessary to program the Flash sector with 00h as the PSD9XX will do this automatically before erasing (byte=FFh). During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.6. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed.

Preliminary Information PSD9XX Family The PSD9XX Functional Blocks (cont.)

9.1.1.8.3 Flash Erase Suspend Instruction

When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any address when an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD9XX internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. The Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend instruction has been executed. The PSD9XX will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply:

• Attempting to read from a Flash sector that was being erased will output invalid data.
• Reading from a Flash sector that was not being erased is valid.
• The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (read is an operation and is OK).
• If a Reset instruction is received, data in the Flash sector that was being erased will be invalid.

9.1.1.8.4 Flash Erase Resume Instruction

If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9.)

9.1.1.9 Specific Features

9.1.1.9.1 Flash and Secondary Flash Sector Protect

Each Flash and Secondary Flash sector can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Configuration program. This will automatically protect selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The microcontroller can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash sector will be ignored by the device. The Verify operation will result in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash protection and Secondary Flash protection registers (CSIOP). See Table 11.

9.1.1.9.2 Reset Instruction – PSD913F2

1. Reading the Flash Protection status or Flash ID
2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase

memory up to few msec to complete the reset cycle. erase cycle and return the Flash to normal Read Mode in up to few msec.

9.1.1.9.3 Reset Instruction – PSD934F2, PSD954F2

1. Reading the Flash Protection status or Flash ID
2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase

Mode in 25 µsec after the Reset instruction is issued. Flash memory to normal Read Mode in 25 µsec. Sec<i>_Prot 1 = Main Flash Sector <i> is write protected. Sec<i>_Prot 0 = Main Flash Sector <i> is not write protected. Sec<i>_Prot 1 = Secondary Flash Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. Table 11. Sector Protection/Security Bit Definition

Preliminary Information PSD9XX Family The PSD9XX Functional Blocks (cont.)

9.1.1.9.4 Reset Pin Input – PSD934F2, PSD954F2

The reset pulse input from the pin will abort any operation in progress and reset the Flash memory to Read Mode. When the reset occurs during a programming or erase cycle, the Flash memory will take up to 25 µsec to return to Read Mode. It is recommended that the reset pulse (except power on reset, see Reset Section) be at least 25 µSec such that the Flash memory will always be ready for the MCU to fetch the boot codes after reset is over.

9.1.2 SRAM

The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high. RS0 can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PC2). If you have an external battery connected to the PSD9XX, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. Pin PC4 can be configured as an output that indicates when power is being drawn from the external battery. This Vbaton signal will be high with the supply voltage falls below the bat- tery voltage and the battery on PC2 is supplying power to the internal SRAM. The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using PSDsoft.

9.1.3 Memory Select Signals

The main Flash (FSi), Secondary Flash (CSBOOTi), and SRAM (RS0) memory select signals are all outputs of the DPLD. They are setup by entering equations for them in PSDsoft. The following rules apply to the equations for the internal chip select signals: 1. Main Flash memory and Secondary Flash memory sector select signals must not be larger than the physical sector size. 2. Any main Flash memory sector must not be mapped in the same memory space as another Main Flash sector. 3. A Secondary Flash memory sector must not be mapped in the same memory space as another Secondary Flash sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A Secondary Flash memory sector may overlap a main Flash memory sector. In case of overlap, priority will be given to the Secondary Flash sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority will be given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) will automatically address Boot memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 5 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.

Figure 5. Priority Level of Memory and I/O Components manipulation of the VM register that resides in the PSD’s CSIOP space. changed by the microcontroller so that memory mapping can be changed on-the-fly. troller change it when desired. Table 13 describes the VM Register. Table 13. VM Register NOTE: Bits 5-7 are not used, should set to “0”.

Figure 6. 8031 Memory Modes – Separate Space Mode Figure 7. 80C31 Memory Mode – Combined Space Mode

9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces

9.1.3.2.1 Separate Space Modes

requires the VM register to be set to 0Ch. See Application Note for examples.

Figure 8. Page Register

9.1.4 Page Register

factor of up to 256. The contents of the register can also be read by the microcontroller. included in the Flash Memory, Secondary Flash Block, and SRAM chip select equations. internal data bus D0-D7. The microcontroller can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.

9.2 PLDs

device and available upon power-up. registers, and I/O port selects. The GPLD can be used to generate external chip selects, control signals or logic functions. The GPLD has 19 outputs that are connected to Ports A, B and D. Table 15. DPLD and GPLD Inputs NOTE: The address inputs are A[19:4] in 80C51XA mode. consumption. Refer to the Power Management Unit section on how to set the Turbo Bit. these MCU control signals are not used in PLD logic equations.

57 PLD OUT 8

Figure 9. PLD Block Diagrams

8 FLASH MEMORY

4 SECONDARY

Figure 10. DPLD Logic Array *NOTE: The address inputs are A[19:4] in 80C51XA mode.

9.2.1 Decode PLD (DPLD)

• 8 sector selects for the main Flash memory (three product terms each)
• 4 sector selects for the Secondary Flash memory (three product terms each)
• 1 internal SRAM select (two product terms)
• 1 internal CSIOP select (select PSD registers, one product term) Inputs to the DPLD chip selects may include address inputs, Page Register inputs and other user defined external inputs from Ports A, B, C or D.

9.2.2 General Purpose PLD (GPLD)

pin can be configured to perform other I/O functions. logic function or chip selects. The outputs can be configured as active high or low outputs. configured as the Data Port and the GPLD outputs will not be available. Table 16. GPLD Output Product Term

Figure 11. General Purpose PLD and I/O Port

9.3 Microcontroller Bus Interface

Table 17. Microcontrollers and their Control Signals **configured for other I/O functions. B, C, or D may be used for additional address inputs.

Preliminary Information PSD9XX Family The PSD9XX Functional Blocks (cont.)

9.3.3 Microcontroller Interface Examples

Figures 14 through 18 show examples of the basic connections between the PSD9XX and some popular microcontrollers. The PSD9XX Control input pins are labeled as to the microcontroller function for which they are configured. The MCU interface is specified using the PSDsoft. 9.3.3.1 80C31 Figure 14 shows the interface to the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. 9.3.3.2 80C251 The Intel 80C251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in Table 19. Configuration 1 is 80C31 compatible, and the bus interface to the PSD9XX is identical to that shown in Figure 14. Configurations 2 and 3 have the same bus connection as shown in Figure 15. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD9XX. The A16 connection to the PA0 pin allows for a larger address input to the PSD9XX. Configuration 4 is shown in Figure 16. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2. The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0] are changing. The PSD9XX supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time and setup time with respect to ALE is not required. The PSD access time is measured from address A[7:0] valid to data in valid.

1 RD CNTL1 A [7:0]multiplex with D[7:0}

2 WR CNTL0 Non-Page Mode

3 WR CNTL0 Page Mode

4 WR CNTL0 Page Mode

Table 19. 80C251 Configurations The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 17). and hold time with respect to ALE does not apply. signals for external devices.

Figure 18. Interfacing the PSD9XX with a 68HC11 (Muxed Address/Data Bus)

PSD9XX Family Preliminary Information The PSD9XX Functional Blocks (cont.)

9.4 I/O Ports

There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the microcontroller writing to on-chip registers in the CSIOP address space. The topics discussed in this section are:

• General Port Architecture
• Port Operating Modes
• Port Configuration Registers
• Port Data Registers
• Individual Port Functionality.

9.4.1 General Port Architecture

The general architecture of the I/O Port is shown in Figure 19. Individual Port architectures are shown in Figures 20 through 22. In general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. Exceptions will be noted. As shown in Figure 19, the ports contain an output multiplexer whose selects are driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft. Inputs to the multiplexer include the following: J Output data from the Data Out Register J Latched address outputs J General Purpose PLD (GPLD) outputs (external chip selects) The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The PDB is connected to the Internal Data Bus for feedback and can be read by the microcontroller. The Data Out, Direction and Control Registers, and port pin input are all connected to the PDB. The contents of these registers can be altered by the microcontroller. The PDB feedback path allows the microcontroller to check the contents of the registers.

Figure 19. General I/O Port ArchitectureThe

9.4.2 Port Operating Modes

programmed into the device and cannot be changed unless the device is reprogrammed. microcontroller at run-time. in the following subsections. Table 20. Port Operating Modes

Table 21. Port Operating Mode Settings

9.4.2.1 MCU I/O Mode

microcontroller address space. The addresses of the ports are listed in Table 7. input through the Data In buffer. See Figure 19. can be used for PLD I/O if they are specified in PSDsoft.

9.4.2.2 PLD I/O Mode

declaring the port pins, and then specifying an equation in PSDsoft.

9.4.2.4 Address In Mode

Flash, or SRAM is considered to be an address input.

9.4.2.5 Data Port Mode

general I/O functions are disabled in Port A if the port is configured as a Data Port.

9.4.2.6 JTAG ISP

information on the JTAG Port, refer to section 9.6.

9.4.2.3 Address Out Mode

Ports A and B for various MCUs. PSD memory so the Direction and Control register bits can be set. Table 22. I/O Port Latched Address Output Assignments

9.4.3.1 Control Register

have an associated Control Register.

9.4.3.2 Direction Register

set to ‘0’ will cause it to be an input. The default mode for all port pins is input. Figures 20 and 22 show the Port Architecture diagrams for Ports A, B and C, respectively. The direction of data flow for Ports A, B, and C are controlled by the direction register. the Direction Register for Port D has only the three least significant bits active.

0 Input

1 Output

Table 24. Port Pin Direction Control Table 26. Port Direction Assignment Example

9.4.3 Port Configuration Registers (PCRs)

for each register in Table 23 is 00h. Table 23. Port Configuration Registers *NOTE: See Table 27 for Drive Register bit definition.

Table 27. Drive Register Pin Assignment

9.4.3.3 Drive Select Register

be used for pins configured as Open Drain. is set to a ‘1’. The default pin drive is CMOS. operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’. The default rate is slow slew. be configured as Open Drain outputs and which pins the slew rate can be set for.

9.4.5 Ports A and B – Functionality and Structure

J GPLD Output – Combinatorial PLD outputs can be connected to Port A or Port B. J PLD Input – Input to the PLDs. J Latched Address output – Provide latched address output per Table 30. J Address In – Additional high address inputs, may be latched by ALE. J Data Port – Port A only, connect to non-multiplexed 8-bit data bus.

9.4.4 Port Data Registers

9.4.4.1 Data In

is read through the Data In buffer.

9.4.4.2 Data Out Register

Table 28. Port Data Registers

Figure 20. Ports A and B Structure

Preliminary Information PSD9XX Family The PSD9XX Functional Blocks (cont.)

9.4.6 Port C – Functionality and Structure

Port C can be configured to perform one or more of the following functions (see Figure 21): J MCU I/O Mode J PLD Input – Input to the PLDs. J Address In – Additional high address inputs using the Input Micro⇔ Cells. J In-System Programming – JTAG port can be enabled for programming/erase of the PSD9XX device. (See Section 9.6 for more information on JTAG programming.) Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O functions. J Open Drain – Port C pins can be configured in Open Drain Mode J Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin. PC4 can be configured as a Battery On Indicator output pin, indicating when Vcc is less than Vbat. Port C does not support Address Out mode, and therefore no Control Register is required. Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.

9.4.7 Port D – Functionality and Structure

Port D has three I/O pins. See Figure 22. This port does not support Address Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions: J MCU I/O Mode J GPLD Output – Combinatorial PLD output (external chip selects) J PLD Input – direct input to PLDs J Slew rate – pins can be set up for fast slew rate Port D pins can be configured in PSDsoft as input pins for other dedicated functions: J PD0 – ALE, as address strobe input J PD1 – CLKIN, as clock input to the PLD and APD counter J PD2 – CSI, as active low chip select input. A high input will disable the Flash/SRAM and CSIOP.

*JTAG ISP or battery back-up. Figure 21. Port C Structure *JTAG ISP or battery back-up.

Figure 22. Port D Structure

PSD9XX Family Preliminary Information

9.5 Power Management

The PSD9XX offers configurable power saving options. These options may be used individually or in combinations, as follows: J All memory types in a PSD (Flash, Secondary Flash Block, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing—it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, see PMMR registers below. J Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to reduce to standby current automatically. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD9XX devices. The APD unit is described in more detail in section 9.5.1. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals (not MCU address) that are changing states keeps the PLD out of standby mode, but not the memories. J The PSD Chip Select Input (CSI) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. J The PMMR registers can be written by the MCU at run-time to manage power. All PSD devices support “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 26). Significant power savings can be achieved by blocking signals that are not used in PLD equations. The PSD9XX devices have a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely, when the Turbo Mode is enabled, there is a significant DC current component and the AC component is higher.

9.5.1 Automatic Power Down (APD) Unit and Power Down Mode

The APD Unit, shown in Figure 23, puts the PSD into Power Down Mode by monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. If the address strobe remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal becomes active, and the PSD will enter into Power Down Mode, discussed next. The PSD9XX Functional Blocks (cont.)

Table 30. PSD9XX Timing and Standby Current During Power mode is based only on the Turbo Bit.

1. Typical current consumption assuming no PLD inputs are changing state and

Table 29. Power Down Mode’s Effect on By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. for fifteen CLKIN (pin PD1) clock periods.

• If the address strobe starts pulsing again, the PSD will return to normal operation. The PSD will also return to normal operation if either the CSI input returns low or the Reset input returns high.
• The MCU address/data bus is blocked from all memories and PLDs.
• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from the PLDs will not block CLKIN from the APD unit.
• All PSD memories enter Standby Mode and are drawing standby current. However, the PLDs and I/O ports do not go into Standby Mode because you don’t want to have to wait for the logic and I/O to “wake-up” before their outputs can change. See table 29 for Power Down Mode effects on PSD ports.
• Typical standby current is in µA for 5 V parts. This standby current value assumes that there are no transitions on any PLD input. HC11 (or compatible) Users Note The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power Down, you must not connect the E clock to the CLKIN input (PD1). You should instead connect an independent clock signal to the CLKIN input. The clock frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD9XX will keep going into Power Down Mode.

Bit 1 0 = Automatic Power Down (APD) is disabled. 1 = Automatic Power Down (APD) is enabled. 1 = PLD Turbo is off, saving power. Bit 4 0 = CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. Table 31. Power Management Mode Registers (PMMR0, PMMR2)** ***Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1. ***The PMMR0, and PMMR2 register bits are cleared to zero following power up. ***Subsequent reset pulses will not clear the registers. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to PLD AND array is disconnected, saving power. Bit 5 0 = ALE input to the PLD AND array is connected. 1 = ALE input to PLD AND array is disconnected, saving power. Bit 6 0 = DBE input to the PLD AND array is connected. 1 = DBE input to PLD AND array is disconnected, saving power. **Unused bits should be set to 0. **Refer to Table 17 the signals that are blocked on pins CNTL0-2.

0 X X Not Counting

1 X Pulsing Not Counting

Table 32. APD Counter OperationThe

9.5.2 Other Power Saving Options

enabled by setting bits in the PMMR0 and PMMR2 registers.

9.5.2.1 Zero Power PLD

The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. D.C. power, AC power, and propagation delay.

9.5.2.2 SRAM Standby Mode (Battery Backup)

below the Vstby voltage, and that the SRAM is running on battery power.

9.5.2.3 The CSI Input

9.5.2.4 Input Clock

used as part of the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be disconnected from the PLD AND array setting bit 4 to a “1” in PMMR0.

9.5.2.5 MCU Control Signals

from reaching the memory and I/O sections of the chip.

9.5.3 Reset and Power On Requirement

9.5.3.1 Power On Reset

nanoseconds before the first memory access is allowed.

9.5.3.2 Warm Reset

after warm reset. Figure 25 shows the timing of the power on and warm reset. Figure 25. Power On and Warm Reset Timing

9.5.3.3 I/O Pin, Register and PLD Status at Reset

is active, the state of the outputs are determined by the PLD equations.

Table 34. JTAG Port Signals

9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2)

9.6 Programming In-Circuit using the JTAG Interface

board and programmed using JTAG. *SR_cod bit in the VM Register are always cleared to zero on power on or warm reset. Table 33. Status During Power On Reset, Warm Reset and Power Down Mode Configuration Menu. Configuration Menu. are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note 54 for more details on JTAG In-System-Programming.

Preliminary Information PSD9XX Family

9.6.1 Standard JTAG Signals

The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is received from the external JTAG controller, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR. The PSD9XX supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. ST’s PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISC commands.

9.6.2 JTAG Extensions

TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed programming and erase functions by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note 54. TERR will indicate if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal will go low (active) when an error condition occurs, and stay low until a special JTAG command is executed or a chip reset pulse is received after an “ISC-DISABLE” command. TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD9XX device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Secondary Flash Block. TSTAT and TERR can be configured as open-drain type signals with a JTAG command.

9.6.3 Security and Flash Memories Protection

When the security bit is set, the device cannot be read on a device programmer or through the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed. All other program/erase/verify commands are blocked. Full chip erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft. All Flash Memory and Boot sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft. The PSD9XX Functional Blocks (cont.)

Range Temperature V CC Tolerance Commercial 0 ° C to +70°C + 5 V ± 10% Industrial –40° C to +85°C + 5 V ± 10% Commercial 0 ° C to +70°C 3.0 V to 3.6 V Industrial –40° C to +85°C 3.0 V to 3.6 V PSD9XX Family Preliminary Information Symbol Parameter Condition Min Max Unit TSTG Storage Temperature PLDCC – 65 + 125 °C Commercial 0 + 70 °C Operating TemperatureIndustrial – 40 + 85 °C Voltage on any Pin With Respect to GND – 0.6 + 7 V VPP Device Programmer Supply Voltage With Respect to GND – 0.6 + 14 V VCC Supply Voltage With Respect to GND – 0.6 + 7 V ESD Protection >2000 V Absolute Maximum Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Symbol Parameter Condition Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VCC Supply Voltage V-Versions All Speeds 3.0 V to 3.6 V 3.6 V Recommended Operating Conditions Operating Range

• PLD Timing – Combinatorial Timing
• Microcontroller Timing – Read Timing – Write Timing – Power Down and Reset Timing Following are issues concerning the parameters presented: J In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD9XX is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". J The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 26 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. J In the PLD timing parameters, add the required delay when Turbo bit is "OFF".

Figure 26. PLD ICC /FrequencyConsumption (VCC = 5 V ± 10%)

PSD9XX Family Preliminary Information Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power Down Mode = 90% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/153 = 29.4% Turbo Mode = ON Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 µA/PT = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz +2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 µA + 0.1 x 42.9 = 45 µA + 4.29 mA = 4.34 mA This is the operating power with no Flash writes or erases. Calculation is based on I OUT = 0 mA. Example of PSD9XX Typical Power Calculation at VCC = 5.0 V AC/DC Parameters (cont.) Figure 26a. PLD ICC /Frequency Consumption (PSD9XXFV Versions, VCC = 3 V) V CC = 3V 01 0 1 5 5 20 25 ICC – (mA) TURBO ON (100%) TURBO ON (25%) TURBO OFF TURBO OFF HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PT 100% PT 25%

Preliminary Information PSD9XX Family Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power Down Mode = 90% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/153 = 29.4% Turbo Mode = Off Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45 µA + 0.1 x 32.9 = 45 µA + 3.29 mA = 3.34 mA This is the operating power with no Flash writes or erases. Calculation is based on I OUT = 0 mA. Example of Typical Power Calculation at VCC = 5.0 V in Turbo Off ModeAC/DC Parameters (cont.)

PSD9XX Family Preliminary Information 2. CSI deselected or internal Power Down mode is active. 3. PLD is in non-turbo mode and none of the inputs are switching 4. Refer to Figure 32 for PLD current calculation. 5. I OUT = 0 mA Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VIH High Level Input Voltage 4.5 V < V CC < 5.5 V 2 V CC +.5 V VIL Low Level Input Voltage 4.5 V < V CC < 5.5 V –.5 0.8 V VIH1 Reset High Level Input Voltage (Note 1) .8 V CC VCC +.5 V VIL1 Reset Low Level Input Voltage (Note 1) –.5 .2 V CC –.1 V VHYS Reset Pin Hysteresis 0.3 V VLKO VCC Min for Flash Erase and Program 2.5 4.2 V VOL Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V IOL = 8 mA, VCC = 4.5 V 0.25 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20 µA, VCC = 4.5 V 4.4 4.49 V IOH = –2 mA, VCC = 4.5 V 2.4 3.9 V VOH 1 Output High Voltage VSTBY On I OH 1 = 1 µA V SBY – 0.8 V VSBY SRAM Standby Voltage 2.0 V CC V ISBY SRAM Standby Current (VSTBY Pin) V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB Standby Supply Current for Power CSI > VCC –0.3 V 75 200 µADown Mode (Notes 2 and 3) ILI Input Leakage Current V SS < VIN < VCC –1 ±.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ±5 10 µA PLD_TURBO = OFF, 0m Af = 0 MHz (Note 5) PLD PLD_TURBO = ON, f = 0 MHz 400 700 µA/PT ICC (DC) Operating Supply During Flash Write/Erase(Note 5) Current Flash Only 15 30 mA Read Only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA PLD AC Adder Fig. 26 ICC (AC) (Note 4) (Note 5) FLASH AC Adder 2.5 3.5 mA/MHz SRAM AC Adder 1.5 3.0 mA/MHz PSD9XX DC Characteristics (5 V ± 10% Versions)

Preliminary Information PSD9XX Family AC Symbols for PLD Timing. Example: tAVLX – Time from Address Valid to ALE Invalid. Signal Letters A – Address Input C – CEout Output D – Input Data E – E Input L – ALE Input N – Reset Input or Output P – Port Signal Output Q – Output Data R – WR, UDS, LDS, DS, IORD, PSEN Inputs S – Chip Select Input T – R/W Input W – Internal PDN Signal B – Vstby Output Signal Behavior t – Time L – Logic Level Low or ALE H – Logic Level High V – Valid X – No Longer a Valid Logic Level Z – Float PW – Pulse Width Microcontroller Interface – AC/DC Parameters (5V ± 10% Versions)

PSD9XX Family Preliminary Information NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. RD and PSEN have the same timing. 3. Any input used to select an internal PSD9XX function. 4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 5. RD timing has the same timing as DS, LDS, and UDS signals. -70 -90 -15 Turbo Symbol Parameter Conditions Min Max Min Max Min Max Off Unit tLVLX ALE or AS Pulse Width 15 20 28 ns tAVLX Address Setup Time (Note 3) 4 6 10 ns tLXAX Address Hold Time (Note 3) 7 8 11 ns tAVQV Address Valid to Data Valid (Note 3) 70 90 150 Add 10 ns tSLQV CS Valid to Data Valid 75 100 150 ns RD to Data Valid 8-Bit Bus (Note 5) 24 32 40 ns t RLQV RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 (Note 2) 31 38 45 ns tRHQX RD Data Hold Time (Note 1) 0 0 0 ns tRLRH RD Pulse Width (Note 1) 27 32 38 ns tRHQZ RD to Data High-Z (Note 1) 20 25 30 ns tEHEL E Pulse Width 27 32 38 ns tTHEH R/W Setup Time to Enable 6 10 18 ns tELTL R/W Hold Time After Enable 0 0 0 ns tAVPV Address Input Valid to Address (Note 4) 20 25 30 ns Output Delay Read Timing (5 V ± 10% Versions) Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions)

Preliminary Information PSD9XX Family -70 -90 -15 Symbol Parameter Conditions Min Max Min Max Min Max Unit tLVLX ALE or AS Pulse Width 15 20 28 tAVLX Address Setup Time (Note 1) 4 6 10 ns tLXAX Address Hold Time (Note 1) 7 8 11 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 8 15 20 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 12 15 20 ns tDVWH WR Data Setup Time (Note 3) 25 35 45 ns tWHDX WR Data Hold Time (Note 3) 4 5 5 ns tWLWH WR Pulse Width (Note 3) 31 35 45 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 6 8 10 ns tWHAX2 Trailing Edge of WR to DPLD Address Input Invalid (Note 3 and 4) 0 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register (Note 3) 27 30 38 ns tAVPV Address Input Valid to Address (Note 2) 20 25 30 nsOutput Delay Write Timing (5 V ± 10% Versions) Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) NOTES: 1. Any input used to select an internal PSD9XX function. 2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. -70 -90 -15 Fast Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Min Max Aloc OFF (Note 1) Unit tPD PLD Input Pin/Feedback to PLD Combinatorial 20 25 32 Add 2 Add 10 Sub 2 ns Output tARD PLD Array Delay Any 11 16 22 Add 2 nsMicro⇔ Cell PLD Combinatorial Timing (5 V ± 10%) NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].

PSD9XX Family Preliminary Information Symbol Parameter Conditions Min Typ Max Unit tNLNH Warm RESET Active Low Time (Note 1) 150 ns tOPR RESET High to Operational Device 120 ns tNLNH-PO Power On Reset Active Low Time 1 ms Warm Reset, will abort and reset Flash t NLNH-A programming/erase cycles to Read mode. 25 µs (Note 2) Reset Pin Timing (5 V ± 10%) Symbol Parameter Conditions Min Typ Max Unit tBVBH Vstby Detection to Vstbyon Output High (Note 1) 20 µs tBXBL VstbyOff Detection to Vstbyon Output Low (Note 1) 20 µs Vstbyon Timing (5 V ± 10%) NOTE: 1. RESET will not reset Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. For PSD934F2 and PSD954F2 only. NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms. NOTE: 1. tCLCL is the CLKIN clock period. Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) -70 -90 -15 Symbol Parameter Conditions Min Max Min Max Min Max Unit tLVDV ALE Access Time from Power Down 80 90 150 ns Maximum Delay from APD tCLWH Enable to Internal PDN Using 15 *tCLCL (µs) (Note 1) µs Valid Signal CLKIN Input Power Down Timing (5 V ± 10%)

Preliminary Information PSD9XX Family Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) -70 -90 -15 Symbol Parameter Conditions Min Max Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 20 18 14 MHz tISCCH TCK Clock High Time (Note 1) 23 26 31 ns tISCCL TCK Clock Low Time (Note 1) 23 26 31 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 2 MHz tISCCH-P TCK Clock High Time(for PLD only) (Note 2) 240 240 240 ns tISCCL-P TCK Clock Low Time(for PLD only) (Note 2) 240 240 240 ns tISCPSU ISC Port Set Up Time 7 8 10 ns tISCPH ISC Port Hold Up Time 5 5 5 ns tISCPCO ISC Port Clock to Output 21 23 25 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 25 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 25 ns ISC Timing (5 V ± 10%) NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. Symbol Parameter Min Typ Max Unit Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase (Not Preprogrammed) 5 sec tWHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase (Not Preprogrammed) 2.2 sec tWHQV1 Byte Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles t WHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 30 ns Flash Program, Write and Erase Times (5 V ± 10%) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading.

PSD9XX Family Preliminary Information Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 3.0 3.6 V VIH High Level Input Voltage 3.0 V < V CC < 3.6 V .7 V CC VCC +.5 V VIL Low Level Input Voltage 3.0 V < V CC < 3.6 V –.5 0.8 V VIH1 Reset High Level Input Voltage (Note 1) .8 V CC VCC +.5 V VIL1 Reset Low Level Input Voltage (Note 1) –.5 .2 V CC –.1 V VHYS Reset Pin Hysteresis 0.3 V VLKO VCC Min for Flash Erase and Program 1.5 2.2 V VOL Output Low Voltage IOL = 20 µA, VCC = 3.0 V 0.01 0.1 V IOL = 4 mA, VCC = 3.0 V 0.15 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20 µA, VCC = 3.0 V 2.9 2.99 V IOH = –1 mA, VCC = 3.0 V 2.7 2.8 V VOH 1 Output High Voltage VSTBY On I OH 1 = –1 µA V SBY – 0.8 V VSBY SRAM Standby Voltage 2.0 V CC V ISBY SRAM Standby Current (VSTBY Pin) V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB Standby Supply Current CSI >V CC –0.3 V 25 100 µAfor Power Down Mode (Notes 2 and 3) ILI Input Leakage Current V SS < VIN < VCC –1 ±.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ±5 10 µA PLD_TURBO = OFF, f = 0 MHz (Note 3) 0m A PLD Only PLD_TURBO = ON, ICC (DC) Operating f = 0 MHz 200 400 µA/PT (Note 5) Supply Current During FLASH or FLASH Write/Erase Only 10 25 mA Read Only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA PLD AC Adder (Note 4) Figure26a ICC (AC) FLASH (Note 5) AC Adder 1.5 2.0 mA/MHz SRAM AC Adder 0.8 1.5 mA/MHz PSD9XXFV DC Characteristics (3.0 V to 3.6 V Versions) Advance Information 2. CSI deselected or internal PD is active. 3. PLD is in non-turbo mode and none of the inputs are switching. 4. Refer to Figure 26a for PLD current calculation. 5. I OUT = 0 mA.

Preliminary Information PSD9XX Family -12 -15 -20 Turbo Symbol Parameter Conditions Min Max Min Max Min Max Off Unit tLVLX ALE or AS Pulse Width 26 26 30 ns tAVLX Address Setup Time (Note 3) 9 10 12 ns tLXAX Address Hold Time (Note 3) 9 12 14 ns tAVQV Address Valid to Data Valid (Note 3) 120 150 200 Add 20 ns tSLQV CS Valid to Data Valid 120 150 200 ns RD to Data Valid 8-Bit Bus (Note 5) 35 35 40 ns t RLQV RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 (Note 2) 45 50 55 ns tRHQX RD Data Hold Time (Note 1) 0 0 0 ns tRLRH RD Pulse Width (Note 1) 38 40 45 ns tRHQZ RD to Data High-Z (Note 1) 38 40 45 ns tEHEL E Pulse Width 40 45 52 ns tTHEH R/W Setup Time to Enable 15 18 20 ns tELTL R/W Hold Time After Enable 0 0 0 ns tAVPV Address Input Valid to (Note 4) 33 35 40 ns Address Output Delay Read Timing (3 V Versions) Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. RD and PSEN have the same timing for 8031. 3. Any input used to select an internal PSD813F function. 4. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 5. RD timing has the same timing as DS, LDS, and UDS signals.

PSD9XX Family Preliminary Information NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0]. -12 -15 -20 Symbol Parameter Conditions Min Max Min Max Min Max Unit tLVLX ALE or AS Pulse Width 26 26 30 tAVLX Address Setup Time (Note 1) 9 10 12 ns tLXAX Address Hold Time (Note 1) 9 12 14 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 17 20 25 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 17 20 25 ns tDVWH WR Data Setup Time (Note 3) 45 45 50 ns tWHDX WR Data Hold Time (Note 3) 7 8 10 ns tWLWH WR Pulse Width (Note 3) 46 48 53 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 10 12 17 ns tWHAX2 Trailing Edge of WR to DPLD Address (Notes 3 and 4) 0 0 0 nsInput Invalid tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register (Note 3) 33 35 40 ns tAVPV Address Input Valid to Address (Note 2) 33 35 40 nsOutput Delay Write Timing (3 V Versions) NOTES: 1. Any input used to select an internal PSD813F function. 2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory. Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) -12 -15 -20 Fast Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Min Max Aloc OFF (Note 1) Unit tPD PLD Input Pin/Feedback to PLD Combinatorial 40 45 50 Add 4 Add 20 Sub 6 ns Output tARD PLD Array Delay Any 25 29 33 Add 4 nsMicro⇔ Cell PLD Combinatorial Timing (3 V Versions)

Preliminary Information PSD9XX Family Symbol Parameter Conditions Min Typ Max Unit tNLNH Warm RESET Active Low Time (Note 1) 300 ns tOPR RESET High to Operational Device 300 ns tNLNH-PO Power On Reset Active Low Time 1 ms Warm Reset, will abort and reset Flash t NLNH-A programming/erase cycles to Read 25 µs mode. For PSD9X4FV only. Reset Pin Timing (3 V Versions) Symbol Parameter Conditions Min Typ Max Unit tBVBH VstbyDetection to VstbyonOutput High (Note 1) 20 µs tBXBL VstbyOff Detection to Vstbyon Output Low (Note 1) 20 µs Vstbyon Timing (3 V Versions) NOTE: 1. RESET will not reset Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms. -12 -15 -20 Symbol Parameter Conditions Min Max Min Max Min Max Unit tLVDV ALE Access Time from Power Down 145 150 200 ns Maximum Delay from APD Enable UsingtCLWH to Internal PDN Valid Signal CLKIN Input 15 *tCLCL (µs) (Note 1) µs Power Down Timing (3 V Versions) NOTE: 1. tCLCL is the CLKIN clock period. Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions)

PSD9XX Family Preliminary Information -12 -15 -20 Symbol Parameter Conditions Min Max Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 12 10 9 MHz tISCCH TCK Clock High Time (Note 1) 40 45 51 ns tISCCL TCK Clock Low Time (Note 1) 40 45 51 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 2 MHz tISCCH-P TCK Clock High Time (for PLD only) (Note 2) 240 240 240 ns tISCCL-P TCK Clock Low Time (for PLD only) (Note 2) 240 240 240 ns tISCPSU ISC Port Set Up Time 12 13 15 ns tISCPH ISC Port Hold Up Time 5 5 5 ns tISCPCO ISC Port Clock to Output 30 36 40 ns tISCPZV ISC Port High-Impedance to Valid Output 30 36 40 ns tISCPVZ ISC Port Valid Output to High-Impedance 30 36 40 ns ISC Timing (3 V Versions) NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. Symbol Parameter Min Typ Max Unit Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase (Not Preprogrammed) 5 sec tWHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase (Not Preprogrammed) 2.2 sec tWHQV1 Byte Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles t WHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 30 ns Flash Program, Write and Erase Times (3 V Versions) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading. Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions)

Figure 27. Read Timing *tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

Figure 28. Write Timing

PSD9XX Family Preliminary Information PSD9XX Pin Assignments Pin No. Pin Assignments Pin No. Pin Assignments

1 GND 27 PA2

2 PB5 28 PA1

3 PB4 29 PA0

4 PB3 30 AD0

5 PB2 31 AD1

6 PB1 32 AD2

7 PB0 33 AD3

8 PD2 34 AD4

9 PD1 35 AD5

10 PD0 36 AD6

11 PC7 37 AD7

12 PC6 38 V

13 PC5 39 AD8

14 PC4 40 AD9

16 GND 42 AD11

17 PC3 43 AD12

18 PC2 (VSTBY) 44 AD13

19 PC1 45 AD14

20 PC0 46 AD15

21 PA7 47 CNTL0

22 PA6 48 RESET

23 PA5 49 CNTL2

24 PA4 50 CNTL1

25 PA3 51 PB7

26 GND 52 PB6

52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J)

Pin No. Pin Assignments Pin No. Pin Assignments

1 PD2 27 AD4

2 PD1 28 AD5

3 PD0 29 AD6

4 PC7 30 AD7

5 PC6 31 VCC

6 PC5 32 AD8

7 PC4 33 AD9

8 VCC 34 AD10

9 GND 35 AD11

10 PC3 36 AD12

11 PC2 37 AD13

12 PC1 38 AD14

13 PC0 39 AD15

14 PA7 40 CNTL0

15 PA6 41 RESET

16 PA5 42 CNTL2

17 PA4 43 CNTL1

18 PA3 44 PB7

19 GND 45 PB6

20 PA2 46 GND

21 PA1 47 PB5

22 PA0 48 PB4

23 AD0 49 PB3

24 AD1 50 PB2

25 AD2 51 PB1

26 AD3 52 PB0

Preliminary Information PSD9XX Family PSD9XX Pin Assignments (cont.) 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)

Preliminary Information PSD9XX Family Family: Plastic Leaded Chip Carrier Millimeters Inches Symbol Min Max Notes Min Max Notes A 4.19 4.57 0.165 0.180 A1 2.54 2.79 0.100 0.110 A2 3.66 3.86 0.144 0.152 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.246 0.261 0.0097 0.0103 D 19.94 20.19 0.785 0.795 D1 19.05 19.15 0.750 0.754 D2 17.53 18.54 0.690 0.730 D3 15.24 Reference 0.600 Reference E 19.94 20.19 0.785 0.795 E1 19.05 19.15 0.750 0.754 E2 17.53 18.54 0.690 0.730 E3 15.24 Reference 0.600 Reference e1 1.27 Reference 0.050 Reference N5 2 5 2 020197R1 Figure 35A. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J) E1 E 52 51123 D View A R.025 .045 B A1 A C View A

PSD9XX Family Preliminary Information Figure 36A. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M) D E3 E1 E Index Mark Standoff: 0.05 mm Min. Lead Coplanarity: 0.1mm Max. L C B A α Family: Plastic Quad Flatpack (PQFP) Millimeters Inches Symbol Min Max Notes Min Max Notes α 0° 7° 0° 7° A – 2.35 – 0.093 A2 1.95 2.10 0.077 0.083 B 0.22 0.38 Reference 0.009 0.015 C 0.23 0.009 D 12.95 13.45 0.510 0.530 D1 9.90 10.10 0.390 0.398 D3 7.80 Reference 0.307 Reference E 12.95 13.45 0.510 0.530 E1 9.90 10.10 0.390 0.398 E3 7.80 Reference 0.307 Reference e1 0.65 Reference 0.026 Reference L 0.73 1.03 0.029 0.041 N5 2 5 2 060198R0

Preliminary Information PSD9XX Family Legend: PSDV = Zero Power version available at 2.7 V to 5.5 V VCC . Part # MCU PLDs/Decoders I/O Memory PSD PSD Data Path PLD Inputs Ports Main Flash Boot Flash SRAM @ @ Input Macrocells

5 V 3 V Output Macrocells

Page Reg. PSD913F1 PSD913F1V 9 57 19 8-Bit 27 1024Kb 16Kb PSD913F2 PSD913F2V 9 57 19 8-Bit 27 1024Kb 256Kb 16Kb PSD934F2 PSD934F2V 9 57 19 8-Bit 27 2048Kb 256Kb 64Kb PSD954F2 PSD954F2V 9 57 19 8-Bit 27 2048Kb 256Kb 256Kb Selector Guide – PSD9XXF FamilySelector Guide Part Number Construction I/O COUNT & OTHER NVM SIZE SRAM SIZE FAMILY/SERIES PSD BRAND NAME PSD = Standard Low Power Device 8 = Flash PSD for 8-bit MCUs 9 = Flash PSD for 8-bit MCUs with Combinatorial PLD 0 = 0Kb 1 = 16Kb 2 = 32Kb 3 = 64Kb 4 = 128Kb 5 = 256Kb 1 = 256Kb 2 = 512Kb 3 = 1Mb 4 = 2Mb REVISION "Blank" = no rev. - A = Rev. A SPEED - 90 = 90ns - 15 = 150ns - 20 = 200ns PACKAGE TYPE J = PLCC U = TQFP (not available on some) M = PQFP TEMP RANGE "Blank" = 0°C to +70°C (Commercial) I = –40°C to +85°C (Industrial) 2ND NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 3 = No 2nd Array V cc VOLTAGE "blank" = 5 Volt V = 3.0 Volt F = 27 I/O Flash PSD Part Number Construction I I I I I I I I I I I I I I I I I I CHARACTER # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PART NUMBER PS D 813 F2 A 15 J ––

PSD9XX Family Preliminary Information Operating Speed Temperature Part Number (ns) Package Type Range PSD913F2-70J 70 52 Pin PLCC Comm’l PSD913F2-70M 70 52 Pin PQFP Comm’l PSD913F2-90J 90 52 Pin PLCC Comm’l PSD913F2-90M 90 52 Pin PQFP Comm’l PSD913F2-90JI 90 52 Pin PLCC Industrial PSD913F2-90MI 90 52 Pin PQFP Industrial PSD934F2-70J 70 52 Pin PLCC Comm’l PSD934F2-70M 70 52 Pin PQFP Comm’l PSD934F2-90J 90 52 Pin PLCC Comm’l PSD934F2-90M 90 52 Pin PQFP Comm’l PSD934F2-90JI 90 52 Pin PLCC Industrial PSD934F2-90MI 90 52 Pin PQFP Industrial PSD954F2-70J 70 52 Pin PLCC Comm’l PSD954F2-70M 70 52 Pin PQFP Comm’l PSD954F2-90JI 90 52 Pin PLCC Industrial PSD954F2-90MI 90 52 Pin PQFP Industrial PSD913F2V-15J 150 52 Pin PLCC Comm’l PSD913F2V-15M 150 52 Pin PQFP Comm’l PSD913F2V-20JI 200 52 Pin PLCC Industrial PSD913F2V-20MI 200 52 Pin PQFP Industrial PSD934F2V-15J 150 52 Pin PLCC Comm’l PSD934F2V-15M 150 52 Pin PQFP Comm’l PSD934F2V-20JI 200 52 Pin PLCC Industrial PSD934F2V-20MI 200 52 Pin PQFP Industrial PSD954F2V-90J 90 52 Pin PLCC Comm’l PSD954F2V-90M 90 52 Pin PQFP Comm’l PSD954F2V-12JI 120 52 Pin PLCC Industrial PSD954F2V-12MI 120 52 Pin PQFP Industrial Ordering Information

PSD913F2, PSD934F2, PSD954F2

REVISION HISTORY

Table 1. Document Revision History

PSD913F2, PSD934F2, PSD954F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.