PSD813F2 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Packages
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 TABLE OF CONTENTS
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
and dramatically lowers the cost of field upgrades. – Simultaneous read and write to the device. Table 1. Product Range
- SRAM may be backed up using an external battery.
4 Sectors)
Figure 2. PQFP52 Connections
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
30 AD7
29 AD6
28 AD5
27 AD4
Figure 3. PLCC52 Connections
Figure 4. TQFP64 Connections
48 CNTL0
47 AD15
46 AD14
45 AD13
44 AD12
43 AD11
42 AD10
41 AD9
40 AD8
39 VCC
38 VCC
37 AD7
36 AD6
35 AD5
34 AD4
33 AD3
Table 2. Pin Description (for the PLCC52 package - Note 1) lower address bits, connect AD0-AD7 to this port. in page mode, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. If you are using an 80C251 in page mode, connect AD8-AD15 to this port. – active Low Write Strobe input. R_W – active High READ/active Low write input. RD – active Low Read Strobe input. DS – active Low Data Strobe input. PSEN – connect PSEN to this port when it is being used as an active Low READ signal.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Reset 48 I Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low at Power-up. PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I/O These pins make up Port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellAB0-7) outputs. Inputs to the PLDs. Latched address outputs (see Table 6). Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in burst mode. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs. D0/A16-D3/A19 in M37702M2 mode. Peripheral I/O mode. Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However, PA4-PA7 can be configured as CMOS or Open Drain Outputs. PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 I/O These pins make up Port B. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs. Inputs to the PLDs. Latched address outputs (see Table 6). Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However, PB4-PB7 can be configured as CMOS or Open Drain Outputs. PC0 20 I/O PC0 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC0) output. Input to the PLDs. TMS Input 2 for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC1 19 I/O PC1 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC1) output. Input to the PLDs. TCK Input2 for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. Pin Name Pin Type Description
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PC2 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC2) output. Input to the PLDs. V STBY – SRAM stand-by voltage input for SRAM battery backup. This pin can be configured as a CMOS or Open Drain output. PC3 17 I/O PC3 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC3) output. Input to the PLDs. TSTAT output2 for the JTAG Serial Interface. Ready/Busy output for parallel In-System Programming (ISP). This pin can be configured as a CMOS or Open Drain output. PC4 14 I/O PC4 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC4) output. Input to the PLDs. TERR output2 for the JTAG Serial Interface. Battery-on Indicator (VBATON ). Goes High when power is being drawn from the external battery. This pin can be configured as a CMOS or Open Drain output. PC5 13 I/O PC5 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC5) output. Input to the PLDs. TDI input2 for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC6 12 I/O PC6 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC6) output. Input to the PLDs. TDO output2 for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. Pin Name Pin Type Description
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 74., page 102 onwards, for pin numbers on other package types. 2. These functions can be multiplexed with other functions. PC7 11 I/O PC7 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC7) output. Input to the PLDs. DBE – active Low Data Byte Enable input from 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 10 I/O PD0 pin of Port D. This port pin can be configured to have the following functions: ALE/AS input latches address output from the MCU. MCU I/O – write or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). PD1 9 I/O PD1 pin of Port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. PD2 8 I/O PD2 pin of Port D. This port pin can be configured to have the following functions: MCU I/O - write to or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). PSD Chip Select Input (CSI ). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. VCC 15, 38 Supply Voltage GND 1, 16,
26 Ground pins
Pin Name Pin Type Description
Figure 5. PSD Block Diagram
1 OR 2 MBIT PRIMARY
8 SECTORS
3 EXT CS TO PORT D
24 INPUT MACROCELLS
256 KBIT SECONDARY
4 SECTORS
256 KBIT BATTERY
16 OUTPUT MACROCELLS
memory is divided into 4 equally-sized sectors. Each sector is individually selectable. address latching and DPLD decoding time. in Table 3, each optimized for a different function. Macrocells (OMC) and 3 combinatorial outputs. number of product terms, and macrocells. port for a non-multiplexed bus. Table 3. PLD I/O
functional blocks based on system requirements. mode that helps reduce power consumption. goes to sleep until the next transition on its inputs. Table 4. JTAG SIgnals on Port C Table 5. Methods of Programming Different Functional Blocks of the PSD
PSD pin functions and memory map information. sheet) or other distribution channels. Figure 6. PSDsoft Express Development Tool
located by the user to the internal PSD registers. Table 6. I/O Port Latched Address Output Assignments (Note1) Note: 1. See the section entitled I/O PORTS, page 51, on how to enable the Latched Address Output function. Table 7. Register Address Offset Note: 1. Other registers that are not part of the I/O ports.
1 Description
Data space on an individual basis.
multiple functions, and are user configurable. Table 8. Memory Block Size and Organization
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sec- tor basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configu- ration. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see the section entitled PLDS, page 33). Each of the eight sectors of the primary Flash memory has a Select signal (FS0- FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0- CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in differ- ent areas of system memory. When using a MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other. Ready/Busy (PC3).This signal can be used to output the Ready/Busy status of the PSD. The out- put on Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress. Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can ac- cess these memories in one of two ways: – The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles. – The MCU can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 9., page 21. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM de- vice. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte di- rectly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). Flash memory can also be read by using special instructions to retrieve particular Flash device in- formation (sector protect status and ID).
Table 9. Instructions
- All values are in hexadecimal:
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. erased, or verified, must be Active (High).
- Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.
- Only address bits A11-A0 are used in instruction decoding.
- No Unlock or instruction cycles are required when the device is in the READ Mode
- The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag Bit (DQ5/DQ13) goes High.
- Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
- The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
- The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
- The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
- The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
- The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
- The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
of the primary Flash memory.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly re- ceived and the time between two consecutive bytes is shorter than the time-out period. Some in- structions are structured to include READ opera- tions after the initial WRITE operations. The instruction must be followed exactly. Any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 9., page 21: Flash memory: ■ Erase memory by chip or sector ■ Suspend or resume sector erase ■ Program a Byte ■ Reset to READ Mode ■ Read primary Flash Identifier value ■ Read Sector Protection Status ■ Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2) These instructions are detailed in Table 9., page 21. For efficient decoding of the instruc- tions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles con- sist of writing the data AAh to address X555h dur- ing the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cy- cles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be se- lected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals deter- mine which Flash memory is to receive and exe- cute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0- CSBOOT3) is High. Power-up Mode The PSD internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR , CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is be- low VLKO . READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. Read Memory Contents Primary Flash memory and secondary Flash memory are placed in the READ Mode after Pow- er-up, chip reset, or a Reset Flash instruction (see Table 9., page 21). The MCU can read the memo- ry contents of the primary Flash memory or the secondary Flash memory by using READ opera- tions any time the READ operation is not part of an instruction. Read Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Ta- ble 9., page 21). During the READ operation, ad- dress bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be High. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. Read Memory Sector Protection Status The primary Flash memory Sector Protection Sta- tus is read with an instruction composed of 4 oper- ations: 3 specific WRITE operations and a READ operation (see Table 9., page 21). During the READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash mem- ory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See the section entitled Flash Memory Sector Protect, page 28 for register definitions.
forming these tasks and are defined in Table 10. Table 10. Status Bit
- DQ7-DQ0 represent the Data Bus bits, D7-D0.
- FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Data Polling Flag (DQ7) When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the com- plement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruc- tion or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7, in a READ operation). – Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. – During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). – If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. – If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed. Toggle Flag (DQ6) The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when ei- ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. – The Toggle Flag Bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). – If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. – If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte. Error Flag (DQ5) During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when there is a failure during Flash memory Byte Pro- gram, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Er- ror Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, ’0,’ to the erased state, '1,' which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction. Erase Time-out Flag (DQ3) The Erase Time-out Flag Bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. Af- ter this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3) is set to '1.'
(DQ6) and monitoring the Error Flag Bit (DQ5). Flag Bit (DQ5, see Figure 8). erased (not erased is logic '0'). byte that was intended to be written. Bit (DQ6) toggles until the Erase cycle is complete. (DQ6) and the Error Flag Bit (DQ5). 20h (as shown in Table 9., page 21). ond cycle contains the program address and data. Figure 8. Data Toggle Flowchart
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ERASING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 9., page 21. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled PRO- GRAMMING FLASH MEMORY, page 25 . The Er- ror Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this be- fore erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase The Sector Erase instruction uses six WRITE op- erations, as described in Table 9., page 21. Addi- tional Flash Sector Erase codes and Flash memory sector addresses can be written subse- quently to erase other Flash memory sectors in parallel, without further coded cycles, if the addi- tional bytes are transmitted in a shorter time than the time-out period of about 100µs. The input of a new Sector Erase code restarts the time-out peri- od. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’ the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time- out, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and re- set the device to READ Mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing (byte = FFh). During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled PRO- GRAMMING FLASH MEMORY, page 25 . During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then re- sumed. Suspend Sector Erase When a Sector Erase cycle is in progress, the Sus- pend Sector Erase instruction can be used to sus- pend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 9., page 21). This allows reading of data from an- other Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ Mode. A Suspend Sector Erase instruc- tion executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ Mode. If an Suspend Sector Erase instruction was exe- cuted, the following rules apply: – Attempting to read from a Flash memory sector that was being erased outputs invalid data. – Reading from a Flash sector that was not being erased is valid. – The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). – If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase If a Suspend Sector Erase instruction was previ- ously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase in- struction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 9., page 21.)
the JTAG Port or a Device Programmer. operation results in a READ of the protected data. PSD/EE protection registers (in the CSIOP block). a few milliseconds to complete the Reset cycle. Program or Bulk Erase cycle of the Flash memory. to the normal READ Mode within 25µs. tions after the Reset cycle is complete. Table 11. Sector Protection/Security Bit Definition – Flash Protection Register Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected. Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand-by (VSTBY , PC2). If you have an external battery connected to the PSD, the con- tents of the SRAM are retained in the event of a power loss. The contents of the SRAM are re- tained so long as the battery voltage remains at 2 V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PC4 can be configured as an output that indicates when power is being drawn from the external bat- tery. Battery-on Indicator (VBATON, PC4) is High with the supply voltage falls below the battery volt- age and the battery on Voltage Stand-by (V STBY , PC2) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY , PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configu- ration.
13., page 34 shows the configuration of the PLDs. The AND Array is used to form product terms. These product terms are specified using PSDabel. to the PLDs. The signals are shown in Table 14. changed for an extended time of about 70ns. block MCU control signals from entering the PLDs. Table 14. DPLD and CPLD Inputs Note: 1. The address inputs are A19-A4 in 80C51XA mode.
Figure 13. PLD Diagram
24 INPUT MACROCELL
16 OUTPUT
3 PORT D INPUTS
Figure 14. DPLD Logic Array
8 PRIMARY FLASH
lect (ECS0-ECS2), routed to Port D. the Input and Output Macrocells (IMC and OMC). standard PLD macrocell architectures. Figure 15. Macrocell and I/O Port
ing the flip-flop element, or combinatorial logic. (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 15. Output Macrocell Port and Data Bit Assignments
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ■ McellAB0-McellAB7 all have three native product terms and may borrow up to six more ■ McellBC0-McellBC3 all have four native product terms and may borrow up to five more ■ McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms al- ready in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then “external” product terms are required, which consume other Output Macro- cells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see the section enti- tled I/O PORTS, page 51). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be over- ridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailbox- es, and handshaking protocols. Data can be loaded to the Output Macrocells (OMC) on the trailing edge of Write Strobe (WR CNTL0) (edge loading) or during the time that Write Strobe (WR , CNTL0) is active (level load- ing). The method of loading is specified in PSDsoft Express Configuration. The OMC Mask Register There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked from writing to the as- sociated Output Macrocells (OMC). For example, suppose McellAB0-McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask Reg- ister for McellAB (Mask Macrocell AB) with the val- ue 0Fh. The Output Enable of the OMC The Output Macrocells (OMC) block can be con- nected to an I/O port pin as a PLD output. The out- put enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is en- abled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD out- put in PSDsoft Express. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array.
Figure 16. CPLD Output Macrocell
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure 17., page 41. The Input Macrocells (IMC) are indi- vidually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be con- trolled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by equations written in PSDabel (see Ap- plication Note AN1171 ). Outputs of the Input Mac- rocells (IMC) can be read by the MCU via the IMC buffer. See the section entitled I/O PORTS, page 51. Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input Macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 18., page 42 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output enable product term. The Slave can also write to the Port A Input Mac- rocells (IMC) and the Master can then read the In- put Macrocells (IMC) directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD , CNTL1), Write Strobe (WR, CNTL0), and Slave_CS.
Figure 17. Input Macrocell
Figure 18. Handshaking Communication Using Input Macrocells
- The interface type is specified using the PSD-
Table 16. MCUs and their Control Signals
- ALE/AS input is optional for MCUs with a non-multiplexed bus
urations, as shown in Table 18., page 48. ) connected to CNTL1 on the PSD. (PSEN ) is connected to CNTL2. Figure 22. Interfacing the PSD with the 80C251, with One READ Input Note: 1. The A16 and A17 connections are optional.
- In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs Table 18. 80C251 Configurations
are multiplexed with data bits (D7-D0). eight-bit data mode (as shown in Figure 24). the A3-A0 signals to fetch up to 16 bytes of code. Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 I/O PORTS There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Ex- press Configuration or by the MCU writing to on- chip registers in the CSIOP space. The topics discussed in this section are: ■ General Port architecture ■ Port operating modes ■ Port Configuration Registers (PCR) ■ Port Data Registers ■ Individual Port functionality. General Port Architecture The general architecture of the I/O Port block is shown in Figure 26., page 52. Individual Port ar- chitectures are shown in Figure 28., page 58 to Figure 31., page 61. In general, once the purpose for a port pin has been defined, that pin is no long- er available for other purposes. Exceptions are noted. As shown in Figure 26., page 52, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Reg- isters (Ports A and B only) and PSDsoft Express Configuration. Inputs to the multiplexer include the following: ■ Output data from the Data Out register ■ Latched address outputs ■ CPLD macrocell output ■ External Chip Select (ECS0-ECS2) from the CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direc- tion and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB). The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macro- cells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section en- titled Input Macrocell, page 41. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDabel, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Express must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Ap- plication Note AN1171 for more detail. Table 19., page 53 summarizes which modes are available on each port. Table 22., page 56 shows how and where the different modes are config- ured. Each of the port operating modes are de- scribed in the following sections.
Figure 26. General I/O Port Architecture
the ports are listed in Table 7., page 18. Register, or by the output enable product term. can read the port input through the Data In buffer. put from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a control signal. Table 19. Port Operating Modes Note: 1. Can be multiplexed with other I/O functions.
Table 20. Port Operating Mode Settings
- The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
- Any of these three methods enables the JTAG pins on Port C.
Table 21. I/O Port Latched Address Output Assignments Note: 1. N/A = Not Applicable.
Data Port is connected to the data bus of the MCU. the port is configured as a Data Port. when PSEL0 or PSEL1 is not active. Figure 27. Peripheral I/O Mode
each bit in the register controls its respective pin. each register in Table 22 is 00h. has sole control of a given pin’s direction. has only the three least significant bits active. ’1.’ The default pin drive is CMOS. ister is set to ’1.’ The default rate is slow slew. pins the slew rate can be set for. Table 22. Port Configuration Registers (PCR) Note: 1. See Table 26., page 57 for Drive Register bit definition. Table 23. Port Pin Direction Control, Output Table 24. Port Pin Direction Control, Output Table 25. Port Direction Assignment Example
0 Input
1 Output
Table 26. Drive Register Pin Assignment Note: 1. NA = Not Applicable. tion entitled PLDS, page 33. default value is 0 or unblocked. Table 27. Port Data Registers
The Enable Out register can be read by the MCU. ■ CPLD Input – Via the Input Macrocells (IMC). address output as per Table 21., page 54. using the Input Macrocells (IMC). configured to Open Drain Mode. types of MCU bus interfaces. Figure 28. Port A and Port B Structure
can be connected to Port B or Port C. using the Input Macrocells (IMC). therefore no Control Register is required. Figure 29. Port C Structure
Figure 30. Port D Structure
term that can be configured active High or Low. Figure 31. Port D External Chip Select Signals
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ■ All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing— it happens automatically. The PLD sections can also achieve Stand-by mode when its inputs are not changing, as described in the sections on the Power Management Mode Registers (PMMR). ■ As with the Power Management mode, the Automatic Power Down (APD) block allows the PSD to reduce to stand-by current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. This feature is available on all the devices of the PSD family. The APD Unit is described in more detail in the sections entitled Automatic Power-down (APD) Unit and Power-down Mode, page 63. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching PSD memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in standby mode even if the address/ data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Stand-by mode, but not the memories. ■ PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select Input (CSI , PD2) makes its initial transition from deselected to selected. ■ The PMMRs can be written by the MCU at run- time to manage power. All PSD supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 35 and Figure 36., page 72). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher.
fifteen periods of CLKIN (PD1). control signals and the common CLKIN (PD1). for Power-down mode effects on PSD ports. Table 28. Power-down Mode’s Effect on Ports Figure 32. APD Unit Table 29. PSD Timing and Stand-by Current during Power-down Mode Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
- Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
The HC11 turns off its E clock when it sleeps. abled by setting bits in PMMR0 and PMMR2. Figure 33. Enable Power-down Flow Chart AC power, and propagation delay. CC has dropped below VSTBY .
Table 30. Power Management Mode Registers PMMR0 (Note 1) Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. Table 31. Power Management Mode Registers PMMR2 (Note 1) Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. Bit 0 X 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled. Bit 2 X 0 Not used, and should be set to zero. 1 = off PLD Turbo mode is off, saving power. 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on Cntl0 input to the PLD AND Array is connected. 1 = off Cntl0 input to PLD AND Array is disconnected, saving power. 0 = on Cntl1 input to the PLD AND Array is connected. 1 = off Cntl1 input to PLD AND Array is disconnected, saving power. 0 = on Cntl2 input to the PLD AND Array is connected. 1 = off Cntl2 input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 = on DBE input to the PLD AND Array is connected. 1 = off DBE input to PLD AND Array is disconnected, saving power. Bit 7 X 0 Not used, and should be set to zero.
(PD1) to the PLD to save AC power consumption. the Output Macrocells (OMC). the clock should be disabled to save AC power. trol signals should be disabled to save AC power. by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2. Table 32. APD Counter Operation
0 X X Not Counting
1 X Pulsing Not Counting
and sets the Flash memory into Operating mode. automatically when VCC is below VLKO . the timing of the Power-up and warm reset. the Read Mode within a period of tNLNH-A . Figure 34. Reset (RESET) Timing
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface block can be enabled on Port C (see Table 34., page 70). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration Register bits may be programmed through the JTAG Serial In- terface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. By default, on a blank PSD (as shipped from the factory or after erasure), four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note AN1153 for more details on JTAG In-System Programming (ISP). Standard JTAG Signals The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different con- ditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a JTAG serial command from an external JTAG con- troller device (such as FlashLINK or Automated Test Equipment). When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG sig- nals, TSTAT and TERR. The following symbolic logic equation specifies the conditions enabling the four basic JTAG signals (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Express Configuration utility. This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1 */ Microcontroller_enabled + /* The microcontroller can set a bit at run-time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table 35., page 71 for bit definition. */ PSD_product_term_enabled; /* A dedicated product term (PT) inside the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the Port C JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 1153 for details. */ The state of the PSD Reset (RESET ) signal does not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However, Reset (RE- SET ) will prevent or interrupt JTAG operations if the JTAG enable register is used to enable the JTAG pins. The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PS- Dsoft Express software tool and FlashLINK JTAG programming cable implement the JTAG In-Sys- tem-Configuration (ISC) commands. A definition of these JTAG In-System-Configuration (ISC) commands and sequences is defined in a supple- mental document available from ST. This docu- ment is needed only as a reference for designers who use a FlashLINK to program their PSD.
ten to the secondary Flash memory. Chip Erase command is allowed. set in PSDsoft Express Configuration. Table 34. JTAG Port Signals
ming the device is available directly from ST. Please contact your local sales representative. Table 35. JTAG Enable Register used to enable the JTAG signals. 0 = off JTAG port is disabled. 1 = on JTAG port is enabled. Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. Bit 3 X 0 Not used, and should be set to zero. Bit 4 X 0 Not used, and should be set to zero. Bit 5 X 0 Not used, and should be set to zero. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.
Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)
Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)
Table 38. Absolute Maximum Ratings
Table 39. Operating Conditions (5V devices) Table 40. Operating Conditions (3V devices) Table 41. AC Signal Letters for PLD Timing Note: Example: tAVLX = Time from Address Valid to ALE Invalid. Table 42. AC Signal Behavior Symbols for PLD Note: Example: tAVLX = Time from Address Valid to ALE Invalid. Table 43. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 45. DC Characteristics (5V devices)
- CSI deselected or internal Power-down mode is active.
- PLD is in non-Turbo mode, and none of the inputs are switching.
- Please see Figure 35., page 72 for the PLD current calculation.
Table 46. DC Characteristics (3V devices)
- CSI deselected or internal PD is active.
- PLD is in non-Turbo mode, and none of the inputs are switching.
- Please see Figure 36., page 72 for the PLD current calculation.
Figure 40. Input to Output Disable / Enable Table 47. CPLD Combinatorial Timing (5V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Table 48. CPLD Combinatorial Timing (3V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Figure 41. Synchronous Clock Mode Timing – PLD Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
- CLKIN (PD1) tCLCL = tCH + tCL .
Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
- CLKIN (PD1) tCLCL = tCH + tCL .
Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
Figure 44. Input Macrocell Timing (product term clock) Table 53. Input Macrocell Timing (5V devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX . Table 54. Input Macrocell Timing (3V devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX .
Figure 45. READ Timing Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
Table 55. READ Timing (5V devices) Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
- RD and PSEN have the same timing.
- Any input used to select an internal PSD function.
- In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
- RD timing has the same timing as DS, LDS, and UDS signals.
Table 56. READ Timing (3V devices) Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
- RD and PSEN have the same timing for 8031.
- Any input used to select an internal PSD function.
- In multiplexed mode latched address generated from ADIO delay to address output on any Port.
- RD timing has the same timing as DS, LDS, and UDS signals.
Figure 46. WRITE Timing
Table 57. WRITE Timing (5V devices) Note: 1. Any input used to select an internal PSD function.
- In multiplexed mode, latched address generated from ADIO delay to address output on any port.
- WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
- Assuming data is stable before active WRITE signal.
- Assuming WRITE is active before data becomes valid.
- TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 58. WRITE Timing (3V devices) Note: 1. Any input used to select an internal PSD function.
- In multiplexed mode, latched address generated from ADIO delay to address output on any port.
has the same timing as E, LDS, UDS, WRL, and WRH signals.
- Assuming data is stable before active WRITE signal.
- Assuming WRITE is active before data becomes valid.
- TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Program, WRITE and Erase Times (5V devices) Note: 1. Programmed to all zero before erase.
- The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Table 60. Program, WRITE and Erase Times (3V devices) Note: 1. Programmed to all zero before erase.
- The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Figure 47. Peripheral I/O READ Timing Table 61. Port A Peripheral Data Mode READ Timing (5V devices)
Table 62. Port A Peripheral Data Mode READ Timing (3V devices) Figure 48. Peripheral I/O WRITE Timing Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices) Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
- WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
- Any input used to select Port A Data Peripheral mode.
- Data is already stable on Port A.
- Data stable on ADIO pins to data on Port A.
Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices) Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
- WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
- Any input used to select Port A Data Peripheral mode.
- Data is already stable on Port A.
- Data stable on ADIO pins to data on Port A.
Figure 49. Reset (RESET) Timing Table 65. Reset (RESET ) Timing (5V devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
- Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 66. Reset (RESET ) Timing (3V devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
- Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 67. VSTBYON Timing (5V devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms. Table 68. VSTBYON Timing (3V devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Figure 50. ISC Timing Table 69. ISC Timing (5V devices) Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
- For Program or Erase PLD only.
Table 70. ISC Timing (3V devices) Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
- For Program or Erase PLD only.
Table 71. Power-down Timing (5V devices) Note: 1. tCLCL is the period of CLKIN (PD1). Table 72. Power-down Timing (3V devices) Note: 1. tCLCL is the period of CLKIN (PD1).
Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing Note: Drawing is not to scale.
Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing Note: Drawing is not to scale. Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions
Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline Note: Drawing is not to scale.
Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data
Table 76. Ordering Information Scheme please contact your nearest ST Sales Office.
Table 77. PQFP52 Connections (Figure 2)
10 PC3
11 PC2
12 PC1
13 PC0
14 PA7
15 PA6
16 PA5
17 PA4
18 PA3
19 GND
20 PA2
21 PA1
22 PA0
23 AD0
24 AD1
25 AD2
26 AD3
40 CNTL0
41 RESET
42 CNTL2
43 CNTL1
44 PB7
45 PB6
46 GND
47 PB5
48 PB4
49 PB3
50 PB2
51 PB1
52 PB0
Table 78. PLCC52 Connections (Figure 3)
10 PD0
11 PC7
12 PC6
13 PC5
14 PC4
16 GND
17 PC3
18 PC2 (VSTBY )
19 PC1
20 PC0
21 PA7
22 PA6
23 PA5
24 PA4
25 PA3
26 GND
27 PA2
28 PA1
29 PA0
30 AD0
31 AD1
32 AD2
39 AD8
40 AD9
41 AD10
42 AD11
43 AD12
44 AD13
45 AD14
46 AD15
47 CNTL0
48 RESET
49 CNTL2
50 CNTL1
51 PB7
52 PB6
Table 79. TQFP64 Connections (Figure 4)
8 VCC
9 VCC
10 GND
11 GND
12 PC3
13 PC2
14 PC1
15 PC0
19 PA7
20 PA6
21 PA5
22 PA4
23 PA3
24 GND
25 GND
26 PA2
27 PA1
28 PA0
29 AD0
30 AD1
31 N/D
50 RESET
51 CNTL2
52 CNTL1
53 PB7
54 PB6
55 GND
56 GND
57 PB5
58 PB4
59 PB3
60 PB2
61 PB1
62 PB0
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
REVISION HISTORY
Table 80. Document Revision History
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States