PSD8131A-12J1T

PSD813F1A STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 111

Technical content

This is information on a product still in production but not recommended for new designs. Figure 1. Packages

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A TABLE OF CONTENTS

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A SUMMARY DESCRIPTION The PSD family of Programmable Microcontroller (MCU) Peripherals brings In-System Programma- bility (ISP) to Flash me mory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate an optimized “microcon- troller macrocell” logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct con- nection between the system address/data bus and the internal PSD registers to simplify communica- tion between the MCU and other supporting devic- es. The PSD family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG interf ace is in- cluded on the PSD enabling the entire device (Flash memory, EEPROM, the PLD, and all con- figuration) to be rapidly programmed while sol- dered to the circuit board. This requires no MCU participation, which means the PSD can be pro- grammed anytime, even while completely blank. The innovative JTAG interface to Flash memories is an industry first, so lving key problems faced by designers and manufacturing houses, such as: First time programming. How do I get firmware into the Flash the very first time? JTAG is the an- swer, program the PSD while blank with no MCU involvement. Inventory build-up of pre-programmed devic- es. How do I maintain an ac curate count of pre- programmed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. In-Application Programming (IAP) Two independent memory arrays (Flash and EE- PROM) are included so the MCU can execute code from one memory while erasing and pro- gramming the other. Robust product firmware up- dates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc.) using this unique architecture. De- signers are relieved of these problems: Simultaneous read and write to Flash memo- ry. How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two memories concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. I have only a 64K- byte address space to start with. How can I map these two memories efficiently? A Programmable Decode PLD is the answer. The concurrent PSD memories can be mapped anywhere in MCU ad- dress space, segment by segment with extremely high address resolution. As an option, the second- ary Flash memory can be swapped out of the sys- tem memory map when IAP is complete. A built-in page register breaks the 64K-byte address limit. Separate program and data space. How can I write to Flash or EEPROM memory while it resides in “program” space during field firmware updates, my MCU won’t allow it! The Flash PSD provides means to “reclassify” Flash or EEPROM memory as “data” space during IAP, then back to “program” space when complete. PSDsoft Express PSDsoft Express, a software development tool from ST, guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and out- puts, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft Express: FlashLINK (JTAG) and PSDpro.

Figure 2. PQFP52 Connections

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

32 AD8

31 VCC

30 AD7

29 AD6

28 AD5

27 AD4

Figure 3. PLCC52 Connections

Figure 4. TQFP64 Connections

48 CNTL0

47 AD15

46 AD14

45 AD13

44 AD12

43 AD11

42 AD10

41 AD9

40 AD8

39 VCC

38 VCC

37 AD7

36 AD6

35 AD5

34 AD4

33 AD3

Table 1. Pin Description (for the PLCC52 package)

1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect AD0-AD7 to this port.

1. If your MCU does not have a multiplexed address/data bus, or you are using an

80C251 in page mode, connect A0-A7 to this port.

1. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
2. If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect A8-A15 to this port.

1. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
2. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this

– active Low Write Strobe input.

1. R_W – active High READ/active Low write input.
2. RD – active Low Read Strobe input.
3. DS – active Low Data Strobe input.
4. PSEN – connect PSEN to this port when it is being used as an active Low READ

Registers. Must be Low at Power-up.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I/O These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellAB0-7) outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 5). 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in burst mode. 6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs. 7. D0/A16-D3/A19 in M37702M2 mode. 8. Peripheral I/O mode. Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However, PA4-PA7 can be configured as CMOS or Open Drain Outputs. PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 I/O These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 5). Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However, PB4-PB7 can be configured as CMOS or Open Drain Outputs. PC0 20 I/O PC0 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC0) output. 3. Input to the PLDs. 4. TMS Input 2 for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC1 19 I/O PC1 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC1) output. 3. Input to the PLDs. 4. TCK Input2 for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC2 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC2) output. 3. Input to the PLDs. This pin can be configured as a CMOS or Open Drain output. PC3 17 I/O PC3 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC3) output. 3. Input to the PLDs. 4. TSTAT output2 for the JTAG Serial Interface. 5. Ready/Busy output for In-System parallel programming. This pin can be configured as a CMOS or Open Drain output. PC4 14 I/O PC4 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC4) output. 3. Input to the PLDs. 4. TERR output2 for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. Pin Name Pin Type Description(1)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Note: 1. The pin numbers in this table are for the PLCC package only. See the Figure 2., page 7, for pin numbers on other package type. 2. These functions can be multiplexed with other functions. PC5 13 I/O PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC5) output. 3. Input to the PLDs. 4. TDI input2 for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC6 12 I/O PC6 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC6) output. 3. Input to the PLDs. 4. TDO output2 for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC7 11 I/O PC7 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. CPLD macrocell (McellBC7) output. 3. Input to the PLDs. 4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 10 I/O PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input latches address output from the MCU. 2. MCU I/O – write or read from a standard output or input port. 3. Input to the PLDs. 4. CPLD output (External Chip Select). PD1 9 I/O PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. Input to the PLDs. 3. CPLD output (External Chip Select). 4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. PD2 8 I/O PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read fr om a standard output or input port. 2. Input to the PLDs. 3. CPLD output (External Chip Select). 4. PSD Chip Select Input (CSI ). When Low, the MCU can access the PSD memory and I/ O. When High, the PSD memory blocks are disabled to conserve power. VCC 15, 38 Supply Voltage GND 1, 16,

26 Ground pins

Pin Name Pin Type Description(1)

Figure 5. Block Diagram

1 MBIT MAIN

8 SECTORS

3 EXT CS TO PORT D

24 INPUT MACROCELLS

256 KBIT SECONDARY

4 SECTORS

16 KBIT SRAM

16 OUTPUT MACROCELLS

that are individually selectable. address latching and DPLD decoding time. mized for a different function, as shown in Table 2. Product Terms, and macrocells. Table 2. PLD I/O

JTAG signals pin assignments. range of the microcontroller by up to 256 times. memory spaces for in-circuit programming. MANAGEMENT, page 64 for more details. Table 3. JTAG SIgnals on Port C Table 4. Methods of Programming Different Functional Blocks of the PSD

PSD pin functions and memory map information. vice programmers, see web site for current list. Figure 6. PSDsoft Express Development Tool

located by the user to the internal PSD registers. Table 5. I/O Port Latched Address Output Assignments Note: 1. See the section entitled I/O PORTS, page 52, on how to enable the Latched Address Output function. Table 6. Register Address Offset Note: 1. Other registers that are not part of the I/O ports. space on an individual basis.

multiple functions, and are user configurable. ry is divided into four sectors of eight KBytes each. protected from Program and Erase operations. set up using PSDsoft Express Configuration. FS7) which can contain up to three product terms. sectors from one space to the other. when the Flash memory block is being erased. erase operation is in progress. Table 7. Memory Blocks

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Memory Operation The main Flash and EEPR OM memory are ad- dressed through the microcontroller interface on the PSD device. The microcontroller can access these memories in one of two ways: – The microcontroller can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles. – The microcontroller can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash or EEPROM to invoke an embedded algorithm. These instructions are summarized in Table 8., page 20. Typically, Flash memory can be read by the micro- controller using READ operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific in- structions. For example, the microcontroller can- not write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must exe- cute a program instruction sequence, then test the status of the programming event. This status test is achieved by a READ operation or polling the Ready/Busy pin (PC3). The Flash memory can also be read by using spe- cial instructions to retrieve particular Flash device information (sector protect status and ID). The EEPROM is a bit different. Data can be written to EEPROM memory using write operations, like writing to a RAM device, but the status of each WRITE event must be checked by the microcon- troller. A WRITE event can be one to 64 contigu- ous bytes. The status test is very similar to that used for Flash memory (READ operation or Ready/Busy ). Optionally, the EEPROM memory may be put into a Software Data Protect (SDP) mode where it requires instructions, rather than operations, to alter its contents. SDP mode makes writing to EEPROM much like writing to Flash memory.

Table 8. Instructions Note: 1. Additional sectors to be erased must be entered within 80 µs. A Sector Address is any address within the Sector.

1. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don’t cares in Instruction Bus Cycles.
2. The Reset instruction is required to return to the normal READ mode if DQ5 goes high or after reading the Flash Identifier or Pro-
3. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other

memory when these instructions are performed.

1. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended.

The MCU must operate from some other memory when these instructions are executed.

1. Writing to OTP Row is allowed on ly when SDP mode is disabled.

01 AAh@

10 AAh@

10 F0h@

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A INSTRUCTIONS An instruction is defined as a sequence of specific operations. Each received byte is sequentially de- coded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include READ operations after the initial WRITE operations. The sequencing of any instruction must be fol- lowed exactly. Any invalid combination of instruc- tion bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into READ mode (Flash memory reads like a ROM device). An invalid combination or time-out while addre ssing the EEPROM block will cause the offending byte to be interpreted as a single operation. The PSD supports these instructions (see Table 8., page 20): Flash memory: ■ Erase memory by chip or sector ■ Suspend or resume sector erase ■ Program a Byte ■ Reset to READ mode ■ Read Flash Identifier value ■ Read Sector Protection Status EEPROM: ■ Write data to OTP Row ■ Read data from OTP Row ■ Power down memory ■ Enable Software Data Protect (SDP) ■ Disable SDP ■ Return from read OTP Row read mode or power down mode. These instructions are detailed in Table 8., page 20. For efficient decoding of the instruc- tions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. T he coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address lines A15-A12 are don’t cares during the instruct ion WRITE cycles. How- ever, the appropriate sector select signal (FSi or EESi) must be selected. Power-down Instruction and Power-up Mode EEPROM Power Down Instruction. The EE- PROM can enter power down mode with the help of the EEPROM power down instruction (see Ta- ble 8., page 20). Once the EEPROM power down instruction is decoded, the EEPROM memory can- not be accessed unless a Return instruction (also in Table 8., page 20) is decoded. Alternately, this power down mode will automatically occur when the APD circuit is triggered (see section entitled Automatic Power-down (APD) Unit and Power- down Mode, page 65 ). Therefore, this instruction is not required if the APD circuit is used. Power-up Mode. The PSD internal logic is reset upon power-up to the READ mode. Any write op- eration to the EEPROM is inhibited during the first 5ms following power-up. The FSi and EESi select signals, along with the write strobe signal, must be in the false state during power-up for maximum se- curity of the data contents and to remove the pos- sibility of a byte being written on the first edge of a write strobe signal. Any write cycle initiation is locked when V CC is below VLKO.

operations just as it would a ROM or RAM device. tions describe these READ functions. Reset Flash instruction (see Table 8., page 20 ). the sector is not protected. PSD/EE Protection registers in PSD I/O space. Protect, page 30 for register definitions. status bits can be read as many times as needed. MEMORY, page 27 for details. titled Writing to the EEPROM, page 24 for details. Table 9. Status Bit Note: 1. X = not guaranteed value, can be read either 1 or 0.

1. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
2. FSi and EESi are active High.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Data Polling Flag (DQ7) When Erasing or Programming the Flash memory (or when Writing into th e EEPROM memory), bit DQ7 outputs the complement of the bit being en- tered for Programming/Writing on DQ7. Once the Program instruction or the WRITE operation is completed, the true logic value is read on DQ7 (in a Read operation). Flash memory specific fea- tures: – Data Polling is effective after the fourth WRITE pulse (for programming) or after the sixth WRITE pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. – During an Erase instruction, DQ7 outputs a ‘0.’ After completion of the instruction, DQ7 will output the last bit programmed (it is a ‘1’ after erasing). – If the byte to be programmed is in a protected Flash sector, the instruction is ignored. – If all the Flash sectors to be erased are protected, DQ7 will be set to ‘0’ for about 100µs, and then return to the previous addressed byte. No erasure will be performed. Toggle Flag (DQ6) The PSD offers another way for determining when the EEPROM write or the Flash memory Program instruction is complete d. During the internal WRITE operation and when either the FSi or EESi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling will stop and the data re ad on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features: ■ The Toggle bit is effective after the fourth WRITE pulse (for programming) or after the sixth WRITE pulse (for Erase). ■ If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored. ■ If all the Flash sectors selected for erasure are protected, DQ6 will toggle to ‘0’ for about 100 µs and then return to the previous addressed byte. Error Flag (DQ5) During a correct Program or Erase, the Error bit will set to ‘0.’ This bit is set to ‘1’ when there is a failure during Flash byte programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit in- dicates the attempt to program a Flash bit(s) from the programmed state ('0') to the erased state ('1'), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a byte. In case of an error in Flash sector erase or byte program, the Flash sector in which the error oc- curred or to which the programmed byte belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset in- struction. Erase Time-out Flag DQ3 (Flash Memory only) The Erase Timer bit reflects the time-out period al- lowed between two consecutive Sector Erase in- structions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time period of 100µs + 20% unless an additional Sector Erase instruc- tion is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to ‘1.’

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Writing to the EEPROM Data may be written a byte at a time to the EE- PROM using simple writ e operations, much like writing to an SRAM. Unlike SRAM though, the completion of each byte write must be checked be- fore the next byte is written. To speed up this pro- cess, the PSD offers a Page write feature to allow writing of several bytes before checking status. To prevent inadvertent writes to EEPROM, the PSD offers a Software Da ta Protect (SDP) mode. Once enabled, SDP forces the MCU to “unlock” the EEPROM before altering its contents, much like Flash memory programming. Writing a Byte to EEPROM. A write operation is initiated when an EEPROM select signal (EESi) is true and the write strobe signal (WR ) into the PSD is true. If the PSD detects no additional writes with- in 120µsec, an internal storage operation is initiat- ed. Internal storage to EEPROM memory technology typically takes a few milliseconds to complete. The status of the write operation is obtained by the MCU reading the Data Polli ng or Toggle bits (as detailed in section entitled READ, page 22), or the Ready/Busy output pin (section Ready/Busy Pin (PC3), page 18). Keep in mind that the MCU does not need to erase a location in EEPROM before writing it. Erasure is performed automatically as an internal process. Writing a Page to EEPROM. Writing data to EE- PROM using page mode is more efficient than writing one byte at a time. The PSD EEPROM has a 64 byte volatile buffer that the MCU may fill be- fore an internal EEPROM storage operation is ini- tiated. Page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. To invoke page mode, the MCU must write to EE- PROM locations within a single page, with no more than 120µs between individual byte writes. A single page means that address lines A14 to A6 must remain constant. The MCU may write to the 64 locations on a page in any order, which is de- termined by address lines A5 to A0. As soon as 120µs have expired after the last page write, the internal EEPROM storage process begins and the MCU checks programming status. Status is checked the same way it is for byte writes, de- scribed above. Note: Be aware that if the upper address bits (A14 to A6) change during page write operations, loss of data may occur. Ensure that all bytes for a given page have been successfully stored in the EE- PROM before proceeding to the next page. Cor- rect management of MCU interrupts during EEPROM page write operations is essential. EEPROM Software Data Protect (SDP). The SDP feature is useful for protecting the contents of EEPROM from inadvertent write cycles that may occur during uncontrolled MCU bus conditions. These may happen if the application software gets lost or when VCC is not within normal operating range. Instructions from the MCU are used to enable and disable SDP mode (see Table 8., page 20). Once enabled, the MCU must write an instruction se- quence to EEPROM before writing data (much like writing to Flash memory). SDP mode can be used for both byte and page writes to EEPROM. The device will remain in SDP mode until the MCU is- sues a valid SDP disable instruction. PSD devices are shipped with SDP mode dis- abled. However, within PSDsoft Express, SDP mode may be enabled as part of programming the device with a device programmer (PSDpro). To enable SDP mode at run time, the MCU must write three specific data bytes at three specific memory locations, as shown in Figure 7., page 25. Any further writes to EEPROM when SDP is set will require this same se quence, followed by the byte(s) to write. The first SDP enable sequence can be followed directly by the byte(s) to be writ- ten. To disable SDP mode, the MCU must write specif- ic bytes to six specific locations, as shown in Fig- ure 8., page 26. The MCU must not be executing code from EE- PROM when these instructions are invoked. The MCU must be operating from some other memory when enabling or disabling SDP mode. The state of SDP mode is not changed by power on/off sequences (nonvolatile). When either the SDP enable or SDP disable instructions are is- sued from the MCU, the MCU must use the Toggle bit (status bit DQ6) or the Ready/Busy output pin to check programming status. The Ready/Busy output is driven low from the first write of AAh @ 555h until the completion of the internal storage sequence. Data Polling (status bit DQ7) is not sup- ported when issuing the SDP enable or SDP dis- able commands. Note: Using the SDP sequence (enabling, dis- abling, or writing data) is initiated when specific bytes are written to addresses on specific “pages” of EEPROM memory, with no more than 120µs between WRITES. The addresses 555h and AAAh are located on different pages of EEPROM. This is how the PSD distinguishes these instruc- tion sequences from ordinary writes to EEPROM, which are expected to be within a single EEPROM page.

stored in the OTP row (refer to Table 8., page 20). Figure 7. EEPROM SDP Enable Flowcharts

Figure 8. Software Data Protection Disable Flowchart

the embedded algorithm within the PSD begins. ously with DQ5 (see Figure 9). erased (not erased is logic ‘0’). Figure 9. Data Polling Flowchart

10 shows the Data Toggle algorithm. the embedded algorithm within the PSD begins. erased (not erased is logic ‘0’). Figure 10. Data Toggle Flowchart

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A ERASING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six write op- erations followed by a Read operation of the status register, as described in Table 8., page 20. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is re- set to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section entitled PROGRAM- MING FLASH MEMORY, page 27 . The Error bit (DQ5) returns a ‘1’ if there has been an Erase Fail- ure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions. Flash Sector Erase. The Sector Erase instruc- tion uses six write operations, as described in Ta- ble 8., page 20 . Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 µs. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (Erase time-out bit). If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is counting. If DQ3 is ‘1’, the timeout has expired and the PSD is busy eras- ing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to READ mode. It is not neces- sary to program the Flash sector with 00h as the PSD will do this automati cally before erasing (byte=FFh). During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section entitled PROGRAM- MING FLASH MEMORY, page 27. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from an- other Flash sector, and then resumed. Flash Erase Suspend When a Flash Sector Erase operation is in prog- ress, the Erase Suspe nd instruction will suspend the operation by writing 0B0h to any address when an appropriate Chip Select (FSi) is true. (See Ta- ble 8., page 20). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execu- tion and defaults to READ mode. An Erase Sus- pend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. Th e Toggle Bit will stop tog- gling between 0.1 µs and 15 µs after the Erase Suspend instruction has been executed. The PSD will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply: ■ Attempting to read from a Flash sector that was being erased will output invalid data. ■ Reading from a Flash sector that was not being erased is valid. ■ The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (READ is an operation and is OK). ■ If a Reset instruction is received, data in the Flash sector that was being erased will be invalid. Flash Erase Resume If an Erase Suspend instruction was previously ex- ecuted, the erase operation may be resumed by this instruction. The Er ase Resume instruction consists of writing 030h to any address while an appropriate Chip Select (FSi) is true. (See Table 8., page 20.)

ly protected against Program and Erase functions. JTAG Port or a Device Programmer. change) the sector protection bits. or EEPROM sector will be ignored by the device. tention of the Protection status. protection registers (CSIOP). See Table 10. write operations (refer to Table 8., page 20). Table 10. Sector Protection/Security Bit Definition – Flash Protection Register Sec<i>_Prot 1 = Flash <i> is write protected. Sec<i>_Prot 0 = Flash <i> is not write protected. Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection Register Sec<i>_Prot 1 = EEPROM Boot Sector <i> is write protected. Sec<i>_Prot 0 = EEPROM Boot Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set.

CODE PLD (DPLD) and COMPLEX PLD (CPLD). used to generate external chip selects. The AND array is used to form product terms. These product terms are specified using PSDabel. to the PLDs. The signals are shown in Table 13. changed for an extended time of about 70ns. are not used in PLD logic equations. Table 13. DPLD and CPLD Inputs Note: 1. The address inputs are A19-A4 in 80C51XA mode.

Figure 15. PLD Diagram

24 INPUT MACROCELL

16 OUTPUT

3 PORT D INPUTS

Figure 16. DPLD Logic Array Note: 1. The address inputs are A19-A4 in 80C51XA mode.

8 FLASH MEMORY

most standard PLD macrocell architectures. Figure 17. Macrocell and I/O Port

the product term is controlled by the XOR gate. using the flip-flop element, or combinatorial logic. input can use up to two product terms. Table 14. Output Macrocell Port and Data Bit Assignments

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ■ McellAB0-McellAB7 all have three native product terms and may borrow up to six more ■ McellBC0-McellBC3 all have four native product terms and may borrow up to five more ■ McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms al- ready in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then “external” product terms are required, which will consume other Output Macrocells (OMC). If external product terms are used, extra delay will be added for th e equation that required the extra product terms. This is called product term expansion. PSDsoft Express will perform this expansion as needed. Loading and Reading the Output Macrocells (OMC). The OMCs occupy a memory location in the MCU address space, as defined by the CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority over internal func- tions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-fl ops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the OMCs on the trailing edge of the WR signal (edge loading) or during the time that the WR signal is active (level loading). The method of loading is specified in PSDsoft Ex- press Configuration. The OMC Mask Register There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers can be used to block the loading of data to individual OMCs. The default value for the Mask Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask Register is set to a ‘1’, the MCU will be blocked from writing to the associated OMC. For example, suppose McellAB0-3 are be- ing used for a state machine. You would not want a MCU write to McellAB to overwrite the state ma- chine registers. Therefore, you would want to load the Mask Register for McellAB (Mask Macrocell AB) with the value 0Fh. The Output Enable of the OMC The OMC can be connected to an I/O port pin as a PLD output. The output enable of each Port pin driver is controlled by a single product term from the AND array, ORed with the Direction Register output. The pin is enabled upon power up if no out- put enable equation is defined and if the pin is de- clared as a PLD output in PSDsoft Express. If the OMC output is declared as an internal node and not as a Port pin output in the PSDabel file, then the Port pin can be used for other I/O func- tions. The internal node feedback can be routed as an input to the AND array.

Figure 18. CPLD Output Macrocell

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A Input Macrocells (IMC) The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC is shown in Figure 19., page 42. The IMCs are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the IMCs can be read by the microcontroller through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each product term output is used to latch or clock four IMCs. Port in- puts 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by equa- tions written in PSDabel (see Application Note 55). Outputs of the IMCs can be read by the MCU via the IMC buffer. See the I/O Port section on how to read the IMCs. IMCs can use the address strobe to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. IMCs are particularly useful with handshaking communication applications where two proces- sors pass data back and forth through a common mailbox. Figure 20., page 43 shows a typical con- figuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the “Slave- Read” output enable product term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs directly. Note that the “Slave-Read” and “Slave-wr” signals are product terms that are derived from the Slave MCU inputs RD , WR, and Slave_CS.

Figure 19. Input Macrocell

Figure 20. Handshaking Communication Using Input Macrocells

Table 15. MCUs and their Control Signals

1. ALE/AS input is optional for MCUs with a non-multiplexed bus

rations, as shown in Table 18., page 49. dress byte, and ALE is active in every bus cycle. address A[7:0] valid to data in valid. Table 17. Interfacing the PSD with the 80C251, with One READ Input Note: 1. The A16 and A17 connections are optional.

1. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.

Figure 24. Interfacing the PSD with the 80C251, with RD and PSEN Inputs Table 18. 80C251 Configurations

A4) are multiplexed with data bits (D7-D0). eight-bit data mode. (shown in Figure 25). time with respect to ALE does not apply. Figure 25. Interfacing the PSD with the 80C51X, 8-bit Data Bus

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A I/O PORTS There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Ex- press Configuration or by the MCU writing to on- chip registers in the CSIOP address space. The topics discussed in this section are: ■ General Port architecture ■ Port Operating Modes ■ Port Configuration Registers (PCR) ■ Port Data Registers ■ Individual Port Functionality. General Port Architecture The general architecture of the I/O Port is shown in Figure 27., page 53 . Individual Port architec- tures are shown in Figure 29., page 60 to Figure 32., page 63. In general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. Exceptions will be noted. As shown in Figure 27., page 53, the ports contain an output multiplexer whose selects are driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft Express Config- uration. Inputs to the multiplexer include the fol- lowing: ■ Output data from the Data Out Register ■ Latched address outputs ■ CPLD Macrocell output ■ External Chip Select from CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The PDB is connected to the Internal Data Bus for feedback and can be read by the microcontroller. The Data Out and Macrocell outputs, Direction and Control Registers, and port pin input are all connected to the PDB. The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND array enable product term and the Direction Register. If the enable product term of any of the array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the microcontroller. The PDB feedback path al- lows the microcontroller to check the contents of the registers. Ports A, B, and C have embedded Input Macro- cells (IMCs). The IMCs can be configured as latch- es, registers, or direct inputs to the PLDs. The latches and registers are clocked by the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from the IMCs drive the PLD input bus and can be read by the microcon- troller. See the section entitled Input Macrocell, page 42. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDabel, some by the microcontroller writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Ex- press must be programmed into the device and cannot be changed unless the device is repro- grammed. The modes that can be changed by the microcontroller can be done so dynamically at run- time. The PLD I/O, Data Port, Address Input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other modes can be changed by the microcon- troller at run-time. Table 19., page 54 summarizes which modes are available on each port. Table 22., page 57 shows how and where the different modes are config- ured. Each of the port operating modes are de- scribed in the following subsections.

Figure 27. General I/O Port Architecture

mapped into the microcontroller address space. Register, or by the output enable product term. In buffer. See Figure 27., page 53. the pin is defined as a PLD input pin in PSDabel. assigning the PLD I/O to a port. ments on Ports A and B for various MCUs. rection and Control register bits can be set. Table 19. Port Operating Modes Note: 1. Can be multiplexed with other I/O functions.

Table 20. Port Operating Mode Settings

1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

1. Any of these three methods enables the JTAG pins on Port C.

Table 21. I/O Port Latched Address Output Assignments Note: 1. N/A = Not Applicable.

the base of the CSIOP register. each bit in the register controls its respective pin. each register in Table 22 is 00h. Table 22. Port Configuration Registers (PCR) Note: 1. See Table 26., page 58 for Drive Register bit definition.

has sole control of a given pin’s direction. has only the three least significant bits active. ‘1.’ The default pin drive is CMOS. ister is set to ‘1.’ The default rate is slow slew. Table 23. Port Pin Direction Control, Output Table 24. Port Pin Direction Control, Output Table 25. Port Direction Assignment Example Table 26. Drive Register Pin Assignment Note: 1. NA = Not Applicable.

0 Input

1 Output

microcontroller can read the output of the OMCs. flip flops. See the section entitled PLD’S, page 34. default value is “0” or unblocked. PLD’S, page 34 for a detailed description. Table 27. Port Data Registers

■ CPLD Input – Via the Input Macrocells (IMC). address output as per Table 21., page 55. using the Input Macrocells (IMC). configured to Open Drain Mode. types of MCU bus interfaces. Figure 29. Port A and Port B Structure

can be connected to Port B or Port C. using the Input Macrocells (IMC). therefore no Control Register is required. Figure 30. Port C Structure

Figure 31. Port D Structure

term that can be configured active High or Low. Figure 32. Port D External Chip Select Signals

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A POWER MANAGEMENT The PSD offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: – All memory types in a PSD (Flash, EEPROM, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing— it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, as de- scribed in the section entitled PLD Power Management, page 66. – Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to reduce to standby current automatically. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD devices. The APD Unit is described in more detail in the sections entitled Automatic Power-down (APD) Unit and Power-down Mode, page 65. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of standby mode, but not the memories. – The PSD Chip Select Input (CSI ) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. – The PMMR registers can be written by the MCU at run-time to manage power. PSD supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 36., page 73 and Figure 37., page 73). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. The PSD has a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled. When the Turbo Mode is enabled, there is a significant DC current component and the AC component is higher.

PLDs will not block CLKIN from the APD unit. Down Mode effects on PSD ports. transitions on any PLD input. Table 28. Power-down Mode’s Effect on Ports Figure 33. APD Unit Table 29. PSD Timing and Standby Current during Power-down Mode Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.

1. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.

The HC11 turns off its E clock when it sleeps. setting bits in the PMMR0 and PMMR2 registers. and speed. The Turbo bit affects the PLD’s D.C. power, AC power, and propagation delay. SLQV in Table 63., page 95 or Table 64., page 95. input to the PLD to save AC power consumption. Macrocells by setting bits 4 or 5 to a ‘1’ in PMMR0. Figure 34. Enable Power-down Flow Chart

Table 30. Power Management Mode Registers PMMR0 (Note 1) Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET ) pulses do not clear the registers. Table 31. Power Management Mode Registers PMMR2 (Note 1) Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET ) pulses do not clear the registers. Bit 0 X 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled. Bit 2 X 0 Not used, and should be set to zero. 1 = off PLD Turbo mode is off, saving power. (PD1) Powers-up the PLD when Turbo bit is 0. 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on Cntl0 input to the PLD AND Array is connected. 1 = off Cntl0 input to PLD AND Array is disconnected, saving power. 0 = on Cntl1 input to the PLD AND Array is connected. 1 = off Cntl1 input to PLD AND Array is disconnected, saving power. 0 = on Cntl2 input to the PLD AND Array is connected. 1 = off Cntl2 input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 = on DBE input to the PLD AND Array is connected. 1 = off DBE input to PLD AND Array is disconnected, saving power. Bit 7 X 0 Not used, and should be set to zero.

DBE) to the PLD to save AC power consumption. Table 32. APD Counter Operation

0 X X Not Counting

1 X Pulsing Not Counting

first memory access is allowed. prevented automatically when VCC is below VLKO. Figure 35. Reset (RESET

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to ‘0’ on Power-On Reset or Warm Reset.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG interface on the PSD can be enabled on Port C (see Table 34., page 72 ). All memory (Flash and EEPROM), PLD logic, and PSD config- uration bits may be programmed through the JTAG interface. A blank part can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG sig nals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and erase operations. Note: By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. Standard JTAG Signals The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different con- ditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is re- ceived from the external JTAG controller, TDO be- comes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally en- able the two additional JTAG pins, TSTAT and TERR. The following symbolic logic equation specifies the conditions enabling the four basic JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Express Configuration utility. This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1) */ Microcontroller_enabled + /* The microcontroller can set a bit at run- time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table 35., page 72 for bit definition. */ PSD_product_term_enabled; /* A dedicated product term (PT) inside the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the Port C JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\\ signal on the Flashlink cable when multiplexing JTAG signals. (AN1153) The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. A defi- nition of these JTAG-ISC commands and se- quences are defined in a supplemental document available from ST. ST’s PSDsoft Express software tool and FlashLink JTAG programming cable im- plement these JTAG-ISC commands. This docu- ment is needed only as a reference for designers who use a FlashLink to program their PSD.

ally using the standard JTAG channel. Table 34. JTAG Port Signals ming the device is available directly from ST. Please contact your local sales representative. Table 35. JTAG Enable Register 0 = off JTAG port is disabled. 1 = on JTAG port is enabled. Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. Bit 3 X 0 Not used, and should be set to zero. Bit 4 X 0 Not used, and should be set to zero. Bit 5 X 0 Not used, and should be set to zero. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)

Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)

Table 38. Absolute Maximum Ratings

Table 39. Operating Conditions (5V devices) Table 40. Operating Conditions (3V devices) Table 41. AC Signal Letters for PLD Timings Note: Example: t AVLX = Time from Address Valid to ALE Invalid. Table 42. AC Signal Behavior Symbols for PLD Note: Example: t AVLX = Time from Address Valid to ALE Invalid. Table 43. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

1. CSI deselected or internal Power-down mode is active.
2. PLD is in non-Turbo mode, and none of the inputs are switching.
3. Please see Figure 36., page 73 for the PLD current calculation.

Table 46. DC Characteristics (3V devices)

1. CSI deselected or internal PD is active.

Figure 41. Input to Output Disable / Enable

Figure 42. Combinatorial Timing PLD Table 47. CPLD Combinatorial Timing (5V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 48. CPLD Combinatorial Timing (3V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Figure 43. Synchronous Clock Mode Timing – PLD

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

1. CLKIN (PD1) t CLCL = tCH + tCL.

Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Note: 1. ZPSD versions only.

Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) Note: 1. ZPSD Versions only.

Figure 46. Input Macrocell Timing (product term clock) Table 53. Input Macrocell Timing (5V devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t AVLX and tLXAX. Table 54. Input Macrocell Timing (3V Devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t AVLX and tLXAX.

Figure 47. READ Timing Note: 1. t AVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

Table 55. READ Timing (5V devices) Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

1. RD and PSEN have the same timing.
2. Any input used to select an internal PSD function.
3. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

timing has the same timing as DS, LDS, and UDS signals.

1. In Turbo Off mode, add 10ns to t AVQV.

Table 56. READ Timing (3V devices) Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

1. RD and PSEN have the same timing for 8031.
2. Any input used to select an internal PSD function.
3. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
4. RD timing has the same timing as DS, LDS, and UDS signals.
5. In Turbo Off mode, add 20ns to t AVQV.

Figure 48. WRITE Timing

Table 57. WRITE, Erase and Program Timing (5V devices) Note: 1. Any input used to select an internal PSD function.

1. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

has the same timing as E, LDS, UDS, WRL, and WRH signals.

1. Assuming data is stable before active WRITE signal.
2. Assuming WRITE is active before data becomes valid.

WHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Table 58. WRITE Timing (3V devices) Note: 1. Any input used to select an internal PSD function.

1. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

has the same timing as E, LDS, UDS, WRL, and WRH signals.

1. Assuming data is stable before active WRITE signal.
2. Assuming WRITE is active before data becomes valid.
3. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Table 59. Flash Program, WRITE and Erase Times (5V devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid t Q7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 60. Flash Program, WRITE and Erase Times (3V devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid t Q7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 61. EEPROM WRITE Times (5V devices) cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.

1. These specifications are for writing a page to EEPROM cells.

Table 62. EEPROM WRITE Times (3V devices) cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.

1. These specifications are for writing a page to EEPROM cells.

Figure 49. Peripheral I/O Read Timing Table 63. Port A Peripheral Data Mode READ Timing (5V devices) Table 64. Port A Peripheral Data Mode READ Timing (3V devices)

Figure 50. Peripheral I/O WRITE Timing Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices) Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Any input used to select Port A Data Peripheral mode.
3. Data is already stable on Port A.
4. Data stable on ADIO pins to data on Port A.

Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices) Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.

1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Any input used to select Port A Data Peripheral mode.
3. Data is already stable on Port A.
4. Data stable on ADIO pins to data on Port A.

Figure 51. Reset (RESET) Timing Table 67. Reset (RESET) Timing (5V devices) Note: 1. Reset (RESET ) does not reset Flash memory Program or Erase cycles.

1. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 68. Reset (RESET) Timing (3V devices) Note: 1. Reset (RESET ) does not reset Flash memory Program or Erase cycles.

1. t NLNH-PO is 10ms for devices manufactured before the rev.A.

Figure 52. ISC Timing Table 69. ISC Timing (5V devices) Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

1. For Program or Erase PLD only.

Table 70. ISC Timing (3V devices) Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

1. For Program or Erase PLD only.

Table 71. Power-down Timing (5V devices) Note: 1. t CLCL is the period of CLKIN (PD1). Table 72. Power-down Timing (3V devices) Note: 1. t CLCL is the period of CLKIN (PD1).

offers these devices in ECOPACK ® packages. tions are also marked on the inner box label. fications are available at: www.st.com. Figure 53. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing Note: Drawing is not to scale.

Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions

Figure 54. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing Note: Drawing is not to scale. Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions

Figure 55. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline Note: Drawing is not to scale.

Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data

Table 76. Ordering Information Scheme

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.

Table 77. PQFP52 Connections (Figure 2)

10 PC3

11 PC2

12 PC1

13 PC0

14 PA7

15 PA6

16 PA5

17 PA4

18 PA3

19 GND

20 PA2

21 PA1

22 PA0

23 AD0

24 AD1

25 AD2

26 AD3

40 CNTL0

41 RESET

42 CNTL2

43 CNTL1

44 PB7

45 PB6

46 GND

47 PB5

48 PB4

49 PB3

50 PB2

51 PB1

52 PB0

Table 78. PLCC52 Connections (Figure 3)

2 PB5

3 PB4

4 PB3

5 PB2

6 PB1

7 PB0

10 PD0

11 PC7

12 PC6

13 PC5

14 PC4

16 GND

17 PC3

18 PC2

19 PC1

20 PC0

21 PA7

22 PA6

23 PA5

24 PA4

25 PA3

26 GND

27 PA2

28 PA1

29 PA0

30 AD0

31 AD1

32 AD2

39 AD8

40 AD9

41 AD10

42 AD11

43 AD12

44 AD13

45 AD14

46 AD15

47 CNTL0

48 RESET

49 CNTL2

50 CNTL1

51 PB7

52 PB6

Table 79. TQFP64 Connections (Figure 4)

7 PC4

9 VCC

10 GND

11 GND

12 PC3

13 PC2

14 PC1

15 PC0

19 PA7

20 PA6

21 PA5

22 PA4

23 PA3

24 GND

25 GND

26 PA2

27 PA1

28 PA0

29 AD0

30 AD1

31 N/D

50 RESET

51 CNTL2

52 CNTL1

53 PB7

54 PB6

55 GND

56 GND

57 PB5

58 PB4

59 PB3

60 PB2

61 PB1

62 PB0

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD813F1A

REVISION HISTORY

Table 80. Document Revision History August-2000 1.0 Document written in WSI format. 06-Dec-03 2.0 Document converted to ST fo rmat. Package references corrected (Figure 1). Part number changed to PSD813F1A. Added ECOPACK text in cover page and in section PACKAGE MECHANICAL, page 100. Updated datasheet status to “not for new design”. Added 15ns speed in Table 76 Ordering information scheme.