PSD4135F1-20UI

PSD4135G2 STMICROELECTRONICS | Alldatasheet

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Packages

i PSD4000 Series PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs Table of Contents

Flash In-System-Programmable Peripherals for 16-Bit MCUs Table of Contents

1.0 Introduction Preliminary Information PSD4000 Series PSD4135G2 Configurable Memory System on a Chip for 16-Bit Microcontrollers The PSD4000 series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD4000 devices combine many of the peripheral functions found in MCU based applications:

• 4 Mbit of Flash memory
• A secondary Flash memory for boot or data
• Over 3,000 gates of Flash programmable logic
• 64 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.

PSD4000 Series Preliminary Information 1.0 Introduction (Cont.) Please refer to the revision block at the end of this document for updated information. The PSD4135G2 device offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. J In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even while completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as:

• First time programming – How do I get firmware into the flash the very first time? JTAG is the answer, program the PSD while blank with no MCU involvement.
• Inventory build-up of pre-programmed devices – How do I maintain an accurate count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory.
• Expensive sockets – How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. J In-Application re-Programming (IAP) Two independent flash memory arrays are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems:
• Simultaneous read and write to flash memory – How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two flash memories concurrently, reading code from one while erasing and programming the other during IAP.
• Complex memory mapping – How can I map these two memories efficiently? A Programmable Decode PLD is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit.
• Separate program and data space – How can I write to flash memory while it resides in “program” space during field firmware updates, my 80C51XA won’t allow it The flash PSD provides means to “reclassify” flash memory as “data” space during IAP, then back to “program” space when complete. PSDsoft – ST’s software development tool – guides you through the design process step- by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft will take you through the remainder of the design with point and click entry, covering...PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft – FlashLINK (JTAG) and PSDpro. The PSD4135G2 is available in an 80-pin TQFP package.

• Intel 80196, 80296, 80186, and 80386EX
• Motorola 68HC16, 68HC12, 683XX, and MC2001
• Philips 80C51XA
• Infineon C16X devices
• Hitachi H8 J 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight equal-sized blocks that can be accessed with user-specified addresses. J Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. J 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by connecting an external battery. J General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement external chip selects or combinatorial logic function. J Decode PLD (DPLD) that decodes address for selection of internal memory blocks. J 52 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• I/O ports may be configured as open-drain outputs. J Standby current as low as 50 µA for 5 V devices. J Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. J Internal page register that can be used to expand the microcontroller address space by a factor of 256. J Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD4000 into Power Down Mode. J Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
• 15 year data retention 2.0 Key Features

3.0 PSD4000

Table 1. PSD4000 Product Matrix

4 MBIT MAIN FLASH

8 SECTORS

256 KBIT SECONDARY

4 SECTORS

64 KBIT BATTERY

Figure 1. PSD4000 Block Diagram *Additional address lines can be brought into PSD via Port A, B, C, D, or F.

4.1 Memory

• 4 Mbit Flash
• A secondary 256 Kbit Flash memory for boot or data
• 64 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 4 Mbit Flash is the main memory of the PSD4000. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD4000’s Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.

4.2 PLDs

Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry.

4.3 I/O Ports

The PSD4000 has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). multiplexed address/data busses. G can also be configured as a data port for a non-multiplexed bus.

4.4 Microcontroller Bus Interface

9.3.5 contains microcontroller interface examples. Table 2. PLD I/O Table

4.5 ISP via JTAG Port

4.6 In-System Programming (ISP)

device can be programmed or erased without the use of the microcontroller. Table 3. JTAG Signals on Port E

4.7 In-Application re-Programming (IAP)

executing the programming algorithms out of the secondary Flash memory, or SRAM. functional blocks of the PSD4000. Table 4. Methods of Programming Different Functional Blocks of the PSD4000

4.8 Page Register

4.9 Power Management Unit

and the GPLD will latch its outputs and go to standby until the next transition on its inputs. entering the GPLD to reduce power consumption. See section 9.5.

Figure 2. PSDsoft Development Tool (www.psdst.com) or other distribution channels. supported by third party device programmers, see web site for current list.

PSD4000 Series Preliminary Information The following table describes the pin names and pin functions of the PSD4000. Pins that have multiple names and/or functions are defined using PSDsoft. 6.0 Table 5. PSD4000 Pin Descriptions Pin* (TQFP Pin Name Pkg.) Type Description ADIO0-7 3-7 I/O This is the lower Address/Data port. Connect your MCU 10-12 address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD[0:7] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[0:7] to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. ADIO8-15 13-20 I/O This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the upper address bits, connect AD[8:15] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[8:15] to this port. 3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. CNTL0 59 I The following control signals can be connected to this port, based on your MCU: 1. WR — active-low write input. 2. R_W — active-high read/active low write input. 3. WRL — Write to low byte, active low This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL1 60 I The following control signals can be connected to this port, based on your MCU: 1. RD — active-low read input. 2. E — E clock input. 3. DS — active-low data strobe input. 4. LDS — Strobe for low data byte, active low. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL2 40 I Read or other Control input pin with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN — Program Select enable, active low in code fetch bus cycle (80C51XA mode) 2. BHE — High byte enable. 3. UDS — Strobe for high data byte, 16-bit data bus mode, active low. 4. SIZ0 — Byte enable input. 5. LSTRB — Low strobe input. This pin is also connected to PLD as input.

Preliminary Information PSD4000 Series Pin* (TQFP Pin Name Pkg.) Type Description Reset 39 I Active low input. Resets I/O Ports, PLD Micro ⇔ Cells, some of the configuration registers and JTAG registers. Must be active at power up. Reset also aborts the Flash programming/erase cycle that is in progress. PA0-PA7 51-58 I/O Port A, PA0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port Drain 2. GPLD output. 3. Input to the PLD (can also be PLD input for address A16 and above). PB0-PB7 61-68 I/O Port B, PB0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. GPLD output. 3. Input to the PLD (can also be PLD input for address A16 and above). PC0-PC7 41-48 I/O Port C, PC0-7. This port is pin configurable and has multiple CMOS functions: or Slew 1. MCU I/O — standard output or input port. Rate 2. External chip select (ECS0-7) output. 3. Input to the PLD (can also be PLD input for address A16 and above). PD0 79 I/O Port D pin PD0 can be configured as: CMOS 1. ALE or AS input — latches addresses on ADIO0-15 pins or Open 2. AS input — latches addresses on ADIO0-15 pins on the Drain rising edge. 3. Input to the PLD (can also be PLD input for address A16 and above). PD1 80 I/O Port D pin PD1 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD (can also be PLD input for address A16 Drain and above). 3. CLKIN clock input — clock input to the GPLD Micro⇔ Cells, the APD power down counter and GPLD AND Array. PD2 1 I/O Port D pin PD2 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD (can also be PLD input for address A16 Drain and above). 3. CSI input — chip select input. When low, the CSI enables the internal PSD memories and I/O. When high, the internal memories are disabled to conserve power. CSI trailing edge can get the part out of power-down mode. PD3 2 I/O Port D pin PD3 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD (can also be PLD input for address A16 Drain and above). 3. WRH — for 16-bit data bus, write to high byte, active low. PE0 71 I/O Port E, PE0. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TMS input for JTAG/ISP interface. Table 5. PSD4000 Pin Descriptions (cont.)

PSD4000 Series Preliminary Information Pin* (TQFP Pin Name Pkg.) Type Description PE1 72 I/O Port E, PE1. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TCK input for JTAG/ISP interface (Schmidt Trigger). PE2 73 I/O Port E, PE2. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TDI input for JTAG/ISP interface. PE3 74 I/O Port E, PE3. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TDO output for JTAG/ISP interface. PE4 75 I/O Port E, PE4. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TSTAT output for the ISP interface. 4. Rdy/Bsy — for in-circuit Parallel Programming. PE5 76 I/O Port E, PE5. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TERR active low output for ISP interface. PE6 77 I/O Port E, PE6. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. Vstby — SRAM standby voltage input for battery backup SRAM PE7 78 I/O Port E, PE7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. Vbaton — battery backup indicator output. Goes high when power is drawn from an external battery. PF0-PF7 31-38 I/O Port F, PF0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Input to the PLD. 3. Latched address outputs. 4. As address A1-3 inputs in 80C51XA mode (PF0 is grounded) 5. As data bus port (D0-7) in non-multiplexed bus configuration 6. MCU reset mode. PG0-PG7 21-28 I/O Port G, PG0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address outputs. 3. As data bus port (D8-15) in non-multiplexed bus configuration. 4. MCU reset mode. GND 8,30, 49,50, V CC 9,29, Table 5. PSD4000 Pin Descriptions (cont.)

space. For a more detailed description, refer to section 9.

7.0 PSD4000

Table 6. Register Address Offset

PSD4000 Series Preliminary Information Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Data In Registers – Port A, B, C, D, E, F and G 8.0 Register Bit Definition All the registers in the PSD4000 are included here for reference. Detail description of the registers are found in the Functional Block section of the Data Sheet. Bit definitions: Read only registers, read Port pin status when Port is in MCU I/O input Mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Data Out Registers – Port A, B, C, D, E, F and G Bit definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Direction Registers – Port A, B, C, D, E, F and G Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in Input mode (default). Set Register Bit to 1 = configure corresponding Port pin in Output mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Control Registers – Ports E, F and G Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in MCU I/O mode (default). Set Register Bit to 1 = configure corresponding Port pin in Latched Address Out mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Drive Registers – Ports A, B, D, E, and G Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in CMOS output driver (default). Set Register Bit to 1 = configure corresponding Port pin in Open Drain output driver. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0 Drive Registers – Ports C and F Bit definitions: Set Register Bit to 0 = configure corresponding Port pin as CMOS output driver (default). Set Register Bit to 1 = configure corresponding Port pin in Slew Rate mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Flash Protection Register Bit definitions: Read Only Register Sec<i>_Prot 1 = Flash Sector <i> is write protected. Sec<i>_Prot 0 = Flash Sector <i> is not write protected.

Preliminary Information PSD4000 Series 8.0 Register Bit Definition (cont.) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Security_Bit * Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Flash Boot Protection Register Bit definitions: Sec<i>_Prot 1 = Boot Block Sector <i> is write protected. Sec<i>_Prot 0 = Boot Block Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pgr7 Pgr6 Pgr5 Pgr4 Pgr3 Pgr2 Pgr1 Pgr0 Page Register Bit definitions: Configure Page input to PLD. Default Pgr[7:0] = 00. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD PLD PLD * APD * Mcells clk array-clk Turbo enable PMMR0 Register Bit definitions: (default is 0) Bit 1 0 = Automatic Power Down (APD) is disabled. 1 = Automatic Power Down (APD) is enabled. Bit 3 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. Bit 4 0 = CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. Bit 5 0 = CLKIN input to the PLD Micro⇔ Cells is connected. 1 = CLKIN input to the PLD Micro⇔ Cells is disconnected, saving power. *Not used bit should be set to zero. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 * PLD PLD PLD PLD PLD ** array WRh array Ale array Cntl2 array Cntl1 array Cntl0 PMMR2 Register Bit definitions (defauld is 0): Bit 0 0 = Address A[7:0] are connected into the PLD array. 1 = Address A[7:0] are blocked from the PLD array, saving power. Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to the PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to the PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to the PLD AND array is disconnected, saving power. Bit 5 0 = Ale input to the PLD AND array is connected. 1 = Ale input to the PLD AND array is disconnected, saving power. Bit 6 0 = WRh/DBE input to the PLD AND array is connected. 1 = WRh/DBE input to the PLD AND array is disconnected, saving power. *Not used bit should be set to zero.

PSD4000 Series Preliminary Information 8.0 Register Bit Definition (cont.) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ** * FL_data Boot_data FL_code Boot_code SR_code VM Register Bit definitions: Bit 0 0 = PSEN can’t access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Bit 1 0 = PSEN can’t access Boot in 80C51XA modes. 1 = PSEN can access Boot in 80C51XA modes. Bit 2 0 = PSEN can’t access main Flash in 80C51XA modes. 1 = PSEN can access main Flash in 80C51XA modes. Bit 3 0 = RD can’t access Boot in 80C51XA modes. 1 = RD can access Boot in 80C51XA modes. Bit 4 0 = RD can’t access main Flash in 80C51XA modes. 1 = RD can access main Flash in 80C51XA modes. Note: Upon reset, Bit1-Bit4 are loaded to configurations selected by the user in PSDsoft. Bit 0 is always cleared by reset. Bit 0 to Bit 4 are active only when the device is configured in Philips 80C51XA mode. Not used bit should be set to zero. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0 Memory_ID0 Register Bit definitions: F_size[3:0] = 4h, main Flash size is 2M bit. F_size[3:0] = 5h, main Flash size is 8M bit. S_size[3:0] = 0h, SRAM size is 0K bit. S_size[3:0] = 1h, SRAM size is 16K bit. S_size[3:0] = 3h, SRAM size is 64K bit. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ** B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0 Memory_ID1 Register Bit definitions: B_size[3:0] = 0h, Boot block size is 0K bit. B_size[3:0] = 2h, Boot block size is 256K bit. B_type[1:0] = 0h, Boot block is Flash memory. Not used bit should be set to zero.

perform multiple functions, and are user configurable.

9.1 Memory Blocks

• The main Flash memory
• Secondary Flash memory
• SRAM. The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 7 summarizes which versions of the PSD4000 contain which memory blocks. Main Flash Secondary Flash Device Flash Size Sector Size Block Size Sector Size SRAM PSD4135G2 512KB 64KB 32KB 8KB 8KB

Table 7. Memory Blocks

9.1.1 Main Flash and Secondary Flash Memory Description

can be separately protected from program and erase operations. Flash memory may be erased on a sector-by-sector basis and programmed word-by-word. and then resumed after reading. PE4. This pin is set up using PSDsoft.

9.1.1.1 Memory Block Selects

9.1.1.2 The Ready/Busy Pin (PE4)

PSD4000 Series Preliminary Information

9.1.1.3 Memory Operation

The main Flash and secondary Flash memories are addressed through the microcontroller interface on the PSD4000 device. The microcontroller can access these memories in one of two ways: J The microcontroller can execute a typical bus write or read operationjust as it would if accessing a RAM or ROM device using standard bus cycles. J The microcontroller can execute a specific instructionthat consists of several write and read operations. This involves writing specific data patterns to special addresses within the Flash to invoke an embedded algorithm. These instructions are summarized in Table 8. Typically, Flash memory can be read by the microcontroller using read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single word directly to Flash memory as one would write a word to RAM. To program a word into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. This status test is achieved by a read operation or polling the Rdy/Busy pin (PE4). The Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID).

9.1.1.3.1 Instructions

An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include read operations after the initial write operations. The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). The PSD4000 main Flash and secondary Flash support these instructions (see Table 8): J Erase memory by chip or sector J Suspend or resume sector erase J Program a word J Reset to read array mode J Read Main Flash Identifier value J Read sector protection status J Bypass Instruction These instructions are detailed in Table 8. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. The coded cycles consist of writing the data byte AAh to address XAAAh during the first cycle and data byte 55h to address X554h during the second cycle don’t care during the instruction write cycles. However, the appropriate sector select signal (FSi or CSBOOTi) must be selected. The main Flash and the secondary Flash Block have the same set of instructions (except Read main Flash ID). The chip selects of the Flash memory will determine which Flash will receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active. The PSD4000 Functional Blocks (cont.)

Table 8. Instructions X = Don’t Care. “xxxh” address in the above table must be an even address. RA = Address of the memory location to be read. RD = Data read from location RA during read operation. (CNTL0) pulse. PA is an even address for PSD in word programming mode. PD = Data (word) to be programmed at location PA. Data is latched on the rising edge of WR# (CNTL0) pulse. erased must be active (high).

1. All bus cycles are write bus cycle except the ones with the “read” label.
2. All values are in hexadecimal.
3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4. Only Address bits A11-A0 are used in Instruction decoding.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
7. Additional sectors to be erased must be entered within 80µs.
8. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip

select is active and (A1 = 1, A0 = 0).

1. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
2. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
3. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
4. The Erase Resume command is valid only during the Erase Suspend mode.
5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the

reading the Sector Protection Status of the main Flash.

1. All write bus cycles in an instruction are byte write to even address (XA4Ah or X554h). Flash Programming

bys cycle is writing a word to even address.

9.1.1.4 Power-Up Condition

9.1.1.5 Read

special data from these memories. The following sections describe these read functions.

9.1.1.5.1 Read the Contents of Memory

time the read operation is not part of an instruction sequence.

9.1.1.5.2 Read the Main Flash Memory Identifier

memory ID is E8h. The Secondary Flash does not support this instruction.

9.1.1.5.3 Read the Flash Memory Sector Protection Status

9.1.1.5.4 Read the Erase/Program Status Bits

needed. Please note DQ15-8 is even byte for Motorola MCUs with 16 bit data bus. Table 9. Status Bits NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.

1. DQ15-DQ0 represent the Data Bus bits, D15-D0.
2. FSi/CSBOOTi are active high.

bits while an erase or program instruction is being executed by the embedded algorithm. See section 9.1.1.6 for details.

Preliminary Information PSD4000 Series The PSD4000 Functional Blocks (cont.)

9.1.1.5.5 Data Polling Flag DQ7 (DQ15 for Motorola)

When Erasing or Programming the Flash memory bit DQ7 (DQ15) outputs the complement of the bit being entered for Programming/Writing on DQ7 (DQ15). Once the Program instruction or the Write operation is completed, the true logic value is read on DQ7 (DQ15) (in a Read operation). Flash memory specific features: J Data Polling is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. J During an Erase instruction, DQ7 (DQ15) outputs a ‘0’. After completion of the instruction, DQ7 (DQ15) will output the last bit programmed (it is a ‘1’ after erasing). J If the location to be programmed is in a protected Flash sector, the instruction is ignored. J If all the Flash sectors to be erased are protected, DQ7 (DQ15) will be set to ‘0’ for about 100 µs, and then return to the previous addressed location. No erasure will be performed.

9.1.1.5.6 Toggle Flag DQ6 (DQ14 for Motorola)

The PSD4000 offers another way for determining when the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or CSBOOTi is true, the DQ6 (DQ14) will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling will stop and the data read on the Data Bus is the addressed memory location. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features: J The Toggle bit is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). J If the location to be programmed belongs to a protected Flash sector, the instruction is ignored. J If all the Flash sectors selected for erasure are protected, DQ6 (DQ14) will toggle to ‘0’ for about 100 µs and then return to the previous addressed location.

9.1.1.5.7 Error Flag DQ5 (DQ14 for Motorola)

During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when there is a failure during Flash programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit indicates the attempt to program a Flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a word. In case of an error in Flash sector erase or word program, the Flash sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset instruction. A reset instruction is required after detecting the error bit.

9.1.1.5.8 Erase Time-out Flag DQ3 (DQ11 for Motorola)

The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 (DQ11) is set to ‘1’. A reset instruction is required after detecting the erase timer bit.

PSD4000 Series Preliminary Information

9.1.1.6 Programming Flash Memory

Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Flash memory sector erases to all logic ones, and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector or chip basis, programming Flash memory occurs on a word basis. The PSD4000 main Flash and secondary Flash memories require the MCU to send an instruction to program a word or perform an erase function (see Table 8). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD4000 support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.

9.1.1.6.1 Data Polling

Polling on DQ7 (DQ15) is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 3 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD4000 begins. The MCU then reads the location of the word to be programmed in Flash to check status. Data bit DQ7 (DQ15) of this location becomes the compliment of data bit 7of the original data word to be programmed. The MCU continues to poll this location, comparing DQ7 (DQ15) and monitoring the Error bit on DQ5 (DQ13). When the DQ7 (DQ15) matches data bit 7 of the original data, and the Error bit at DQ5 (DQ13) remains ‘0’, then the embedded algorithm is complete. If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 (DQ15) again since DQ7 (DQ15) may have changed simultaneously with DQ5 (DQ13) (see Figure 3). The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a ‘1’ to a bit that was not erased (not erased is logic ‘0’). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with the word that was intended to be written. When using the Data Polling method after an erase instruction, Figure 3 still applies. However, DQ7 (DQ15) will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 (DQ13) will indicate a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any location within the sector being erased to get DQ7 (DQ15) and DQ5 (DQ13) . PSDsoft generates ANSI C code functions which implement these Data Polling algorithms. The PSD4000 Functional Blocks (cont.)

Figure 3. Data Polling Flow Chart

9.1.1.6.2 Data Toggle

changed simultaneously with DQ5 (DQ13) (see Figure 4). bit that was not erased (not erased is logic ‘0’).

the word that was intended to be written. even location within the sector being erased to get DQ6 (DQ14) and DQ5 (DQ13) . Figure 4. Data Toggle Flow Chart

Preliminary Information PSD4000 Series The PSD4000 Functional Blocks (cont.)

9.1.1.7 Unlock Bypass Instruction

The unlock bypass feature allows the system to program words to the flash memories faster than using the standard program instruction. The unlock bypass instruction is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h (see Table 8). The flash memory then enters the unlock bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the unlock bypass programm command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program instruction, resulting in faster total pro- gramming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The flash memory then returns to reading array data mode.

9.1.1.8 Erasing Flash Memory

The Flash Bulk Erase instruction uses six write operations followed by a Read operation of the status register, as described in Table 8. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6. The Error bit (returns a ‘1’ if there has been an Erase Failure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD4000 will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions.

9.1.1.8.2 Flash Sector Erase Instruction

The Sector Erase instruction uses six write operations, as described in Table 8. Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 µs. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (DQ11) (Erase time-out bit). If DQ3 (DQ11) is ‘0’, the Sector Erase instruction has been received and the timeout is counting. If DQ3 (DQ11) is ‘1’, the timeout has expired and the PSD4000 is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode. It is not necessary to program the Flash sector with 00h as the PSD4000 will do this automatically before erasing. During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed.

PSD4000 Series Preliminary Information The PSD4000 Functional Blocks (cont.)

9.1.1.8.3 Flash Erase Suspend Instruction

When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any even address when an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 8). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD4000 internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. The Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend instruction has been executed. The PSD4000 will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply:

• Attempting to read from a Flash sector that was being erased will output invalid data.
• Reading from a Flash sector that was not being erased is valid.
• The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (read is an operation and is OK).
• If a Reset instruction is received, data in the Flash sector that was being erased will be invalid.

9.1.1.8.4 Flash Erase Resume Instruction

If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any even address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 8.)

9.1.1.9 Specific Features

9.1.1.9.1 Main Flash and Secondary Flash Sector Protect

Each sector of Main Flash and Secondary Flash memory can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft program. This will automatically protect selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The microcontroller can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash sector will be ignored by the device. The Verify operation will result in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can either be read by the MCU through the Flash protection and secondary Flash protection registers (CSIOP), or use the Read Sector Protection instruction (Table 8).

9.1.1.9.2 Reset Instruction

1. Reading the Flash Protection status or Flash ID using the Flash instruction.
2. When an error condition occurs (DQ5 (DQ13) goes high) during a Flash programming

Read Mode in 25 µSeconds after the Reset instruction is issued. Flash memory to normal Read Mode in 25 µSeconds.

9.1.1.9.3 Reset Pin Input

Sec<i>_Prot 1 = Main Flash Sector <i> is write protected. Sec<i>_Prot 0 = Main Flash Sector <i> is not write protected. Sec<i>_Prot 1 = Flash Boot Sector <i> is write protected. Sec<i>_Prot 0 = Flash Boot Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. Table 10. Sector Protection/Security Bit Definition

PSD4000 Series Preliminary Information The PSD4000 Functional Blocks (cont.)

9.1.2 SRAM

The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high. RS0 can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PE6). If you have an external battery connected to the PSD4000, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. Pin PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Vbaton signal will be high with the supply voltage falls below the bat- tery voltage and the battery on PE6 is supplying power to the internal SRAM. The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using PSDsoft.

9.1.3 Memory Select Signals

The main Flash (FSi), secondary Flash (CSBOOTi), and SRAM (RS0) memory select signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules apply to the equations for the internal chip select signals: 1. Main Flash memory and secondary Flash memory sector select signals must not be larger than the physical sector size. 2. Any main Flash memory sector must not be mapped in the same memory space as another Main Flash sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another Flash Boot sector. 4. SRAMand I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a main Flash memory sector. In case of overlap, priority will be given to the Flash Boot sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority will be given to the SRAM, and I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) will automatically address Boot memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 5 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.

Figure 5. Priority Level of Memory and I/O Components changed by the microcontroller so that memory mapping can be changed on-the-fly. boot up and having the microcontroller change it when desired. Table 11 describes the VM Register. Table 11. VM Register NOTE: Bits 6-5 are not used.

Figure 6. 80C51XA Memory Modes – Separate Space Mode Figure 7. 80C51XA Memory Mode – Combined Space Mode

9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces

9.1.3.2.1 Separate Space Modes

signal is used to access data from the secondary Flash memory, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. and 4 of the VM register are set to “1”. See Application Notes for examples.

Figure 8. Page Register

9.1.4 Page Register

factor of up to 256. The contents of the register can also be read by the microcontroller. Page Register can be accessed at address location CSIOP + E0h.

PSD4000 Series Preliminary Information The PSD4000 Functional Blocks (cont.)

9.1.5 Memory ID Registers

The 8-bit read only memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers are defined as follow: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0 Memory_ID0 Register Main Flash Size F_size3 F_size2 F_size1 F_size0 (Bit) 0 0 0 0 none 0 0 0 1 256K 0 0 1 0 512K 0011 1 M 0100 2 M 0101 4 M 0110 8 M Bit Definition SRAM Size S_size3 S_size2 S_size1 S_size0 (Bit) 0 0 0 0 none 0001 1 6 K 0010 3 2 K 0011 6 4 K Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ** B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0 Memory_ID1 Register *Not used bit should be set to zero. Boot Block Size B_size3 B_size2 B_size1 B_size0 (Bit) 0 0 0 0 none 0 0 0 1 128K 0 0 1 0 256K 0 0 1 1 512K Bit Definition B_type1 B_type0 Boot Block Type 0 0 Flash 0 1 EEPROM

9.2 PLDs

registers, and I/O port selects. The GPLD can be used to generate external chip selects, control signals or logic functions. The GPLD has 24 outputs that are connected to Port A, B and C. Table 12. DPLD and GPLD Inputs NOTE: The address inputs are A[19:4] in 80C51XA mode. these MCU control signals are not used in PLD logic equations.

Figure 9. PLD Block Diagram

9.2.1 Decode PLD (DPLD)

The DPLD, shown in Figure 10, is used for decoding the address for internal components.

• 8 sector selects for the main Flash memory (three product terms each)
• 4 sector selects for the Secondary Flash memory (three product terms each)
• 1 internal SRAM select (three product terms)
• 1 internal CSIOP select (select PSD registers, one product term) Inputs to the DPLD chip selects may include address inputs, Page Register inputs and other user defined external inputs from Ports A, B, C, D or F.

9.2.2 General Purpose PLD (GPLD)

pin can be configured to perform other I/O functions. available to implement logic for that pin. number of native PTs for complicated logic. Table 13. GPLD Product Term Availability

8 FLASH MEMORY

4 SECONDARY

Figure 10. DPLD Logic Array *NOTES: 1. The address inputs are A[19:4] in 80C51XA mode.

1. Additional address lines can be brought into PSD via Port A, B, C, C or F.

Figure 11. The Micro⇔ Cell and I/O Port

80196 WR RD BHE * ALE A0 *

80186 WR RD BHE * ALE A0 *

9.3 Microcontroller Bus Interface

specified using the PSDsoft. Table 14. Microcontrollers and their Control Signals ***configured for other I/O functions. ***ALE/AS input is optional for microcontrollers with a non-multiplexed bus. ***This configuration is for 68C812A4_EC at 5MHz, 3V only. sixteen bits, Ports A, B or C may be used for additional address inputs.

9.3.3 Data Byte Enable Reference

9.3.4 Microcontroller Interface Examples

PSDsoft. The PE6 pin should be grounded if Vstby is not used. inputs (A16-A19) can be routed to Port A, B or C as inputs to the PLD. The AMD 80186 family has the same bus connection to the PSD as the 80C196. Table 15. 16-Bit Data Bus with BHE Table 16. 16-Bit Data Bus with WRH and WRL Table 17. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU) Table 18. 16-Bit Data Bus with UDS, LDS (Motorola MCU)

Preliminary Information PSD4000 Series The PSD4000 Functional Blocks (cont.)

9.3.4.2 MC683XX and 68HC16

Figure 15 shows a Motorola MC68331 with non-multiplexed sixteen-bit data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/W, DS and SIZ0 are connected to the CNTL0-2 pins. The 68HC16 and other members of the 683XX family have the same connection as the 68331 shown in Figure 15. 9.3.4.3 80C51XA The Philips 80C51XA microcontroller has a 16-bit multiplexed bus with burst cycles. Address bits A[3:1] are not multiplexed while A[19:4] are multiplexed with data bits D[15:0]. The PSD4135G2 supports the 80C51XA burst mode. The WRH signal is connected to the PD3 and the WRL is connected to CNTL0 pin. The RD and PSEN signal is connected to CNTL1-2 pins. Figure 15 shows the XA schematic. The 80C51XA improves bus throughput and performance by issuing Burst cycles to fetch codes from memory. In Burst cycles, addresses A19-4 are latched internally by the PSD, while the 80C51XA drives the A3-1 lines to sequentially fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in Burst cycle is identical to the normal bus cycle except the address set up or hold time with respect to ALE is not required.

9.3.4.4 H8/300

Figure 16 shows a Hitachi H8/2350 with non-multiplexed sixteen-bit data bus and 24-bit address bus. The H8 data bus is connected to Port F (D0-7) and Port G (D8-15). The WRL, WRH and RD signals are connected to the CNTL0, PD3 and CNTL1 pins respectively. The AS connection is optional and is required if the address are to be latched.

9.3.4.5 MMC2001

The Motorola MCORE MMC2001 microcontroller has a MOD input pin that selects internal or external boot ROM. The PSD4000 can be configured as the external flash boot ROM or as extension to the internal ROM. The MMC2001 has a 16-bit external data bus and 20 address lines with external Chip Select signals. The Chip Select Control Registers allow the user to customize the bus interface and timing to fit the individual system requirement. A typical interface configura- tion to the PSD4000 is shown in Figure 18. The MMC2001’s R/W signal is connected to the cntl0 pin, while EB0 and EB1 (enable byte0 and byte1) are connected to the cntl1 (UDS) and cntl2 (LDS) pins. The WEN bit in the Chip Select Control Register should set to 1 to terminate the EB[0:1] earlier to provide the write data hold time for the PSD. The WSC and WWS bits in the Control Register are set to wait states that meet the PSD access time requirement. Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case the PSD4000 control setting will be: OE, WRL, WRH where OE is the read signal from the MMC2001.

9.3.4.6 C16X Family

The PSD4000 supports Infineon’s C16X family of microcontrollers (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In Figure 19 the C167CR is shown connected to the PSD4000 in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE and are routed to the corresponding PSD pins. The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported by the PSD4000.

Figure 14. Interfacing the PSD4135G2 with an 80C196

Figure 15. Interfacing the PSD4135G2 with an MC68331

Figure 16. Interfacing the PSD4135G2 with a 80C51XA-G3

Figure 17. Interfacing a PSD4135G2 with a H83/2350

Figure 18. Interfacing a PSD4135G2 with a MMC2001

Figure 19. Interfacing a PSD4135G2 with a C167R

PSD4000 Series Preliminary Information The PSD4000 Functional Blocks (cont.)

9.4 I/O Ports

There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the microcontroller writing to on-chip registers in the CSIOP address space. The topics discussed in this section are:

• General Port Architecture
• Port Operating Modes
• Port Configuration Registers
• Port Data Registers
• Individual Port Functionality.

9.4.1 General Port Architecture

The general architecture of the I/O Port is shown in Figure 20. Individual Port architectures are shown in Figures 21 through 23. In general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. Exceptions will be noted. As shown in Figure 20, the ports contain an output multiplexer whose selects are driven by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft Configuration. Inputs to the multiplexer include the following: J Output data from the Data Out Register J Latched address outputs J GPLD outputs (External Chip Selects) The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The PDB is connected to the Internal Data Bus for feedback and can be read by the microcontroller. The Data Out and Micro⇔ Cell outputs, Direction and Control Registers, and port pin input are all connected to the PDB. The contents of these registers can be altered by the microcontroller. The PDB feedback path allows the microcontroller to check the contents of the registers.

9.4.2 Port Operating Modes

The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the microcontroller writing to the Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the microcontroller can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and MCU Reset modes are the only modes that must be defined before programming the device. All other modes can be changed by the microcontroller at run-time. Table 16 summarizes which modes are available on each port. Table 19 shows how and where the different modes are configured. Each of the port operating modes are described in the following subsections.

Figure 20. General I/O Port Architecture Table 16. Port Operating Modes *Available to Motorola 16-bit 683XX and HC16family of MCUs.

Table 17. Port Operating Mode Settings NOTE: 1. Control Register setting is not applicable to Ports A, B and C.

9.4.2.1 MCU I/O Mode

microcontroller address space. The addresses of the ports are listed in Table 6. microcontroller can read the port input through the Data In buffer. See Figure 20. Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if they are specified in PSDsoft.

9.4.2.2 PLD I/O Mode

in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.

9.4.2.4 Address In Mode

9.4.2.5 Data Port Mode

general I/O functions are disabled in Port F and G if the ports are configured as Data Port.

9.4.2.6 JTAG ISP

Port E is JTAG compliant, and can be used for In-System Programming (ISP).

9.4.2.7 MCU Reset Mode

the data bus lines to the desired logic level. pattern onto the MCU Data Bus when reset is active and there is no ongoing bus cycle. After reset, Port F and G return to the normal Data Port Mode. level (data pattern) that will be driven out from Port F and G during reset.

9.4.2.3 Address Out Mode

Ports E, F and F for various MCUs. PSD memory so the Direction and Control register bits can be set. Table 18. I/O Port Latched Address Output Assignments

9.4.3 Port Configuration Registers (PCRs)

for each register in Table 22 is 00h. Table 19. Port Configuration Registers *NOTE: See Table 22 for Drive Register bit definition.

9.4.3.1 Control Register

G have an associated Control Register.

9.4.3.2 Direction Register

to ‘0’ will cause it to be an input. The default mode for all port pins is input. the Direction Register for Port D has only the four least significant bits active.

0 Input

1 Output

Table 20. Port Pin Direction Control Table 21. Port Direction Assignment Example

Table 22. Drive Register Pin Assignment

9.4.3.3 Drive Select Register

be used for pins configured as Open Drain. is set to a ‘1’. The default pin drive is CMOS. operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’. The default rate is slow slew. pins can be configured as Open Drain outputs and which pins the slew rate can be set for.

9.4.4 Port Data Registers

9.4.4.1 Data In

is read through the Data In buffer.

9.4.4.2 Data Out Register

Table 27. Port Data Registers

9.4.5 Ports A, B and C – Functionality and Structure

J GPLD Output – Combinatorial PLD outputs. J PLD Input – Input to the PLDs. J Address In – Additional high address inputs may be latched by ALE. Figure 21. Port A, B and C

9.4.6 Port D – Functionality and Structure

9.4.7 Port E – Functionality and Structure

J Battery Backup features – PE6 can be configured as a Battery Input (Vstby) pin. pin, indicating when Vcc is less than Vbat. Figure 22. Port D Structure

Figure 23. Ports E, F and G Structure

9.4.8 Port F – Functionality and Structure

J PLD Input – as direct input ot the PLD array. J Address In – additional high address inputs. Direct input to the PLD array. J Latched Address Out – Provide latched address out per Table 29. J Slew Rate – pins can be set up for fast slew rate. J MCU Reset Mode – for 16-bit Motorola 683XX and HC16 microcontrollers.

9.4.9 Port G – Functionality and Structure

J Latched Address Out – provide latched address out per Table 29.

Preliminary Information PSD4000 Series

9.5 Power Management

The PSD4000 offers configurable power saving options. These options may be used individually or in combinations, as follows: J All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing— it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, see PMMR registers below. J Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to reduce to standby current automatically. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD4000 devices. The APD unit is described in more detail in section 9.5.1. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of standby mode, but not the memories. J The PSD Chip Select Input (CSI) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. J The PMMR registers can be written by the MCU at run-time to manage power. All PSD devices support “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figures 27 and 27a). Significant power savings can be achieved by blocking signals that are not used in PLD logic equations at run time. PSDsoft creates a fuse map that automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-2, ALE and WRH/DBE) if none of these signals are used in PLD logic equations. The PSD4000 devices have a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely, when the Turbo Mode is enabled, there is a significant DC current component and the AC component is higher.

9.5.1 Automatic Power Down (APD) Unit and Power Down Mode

The APD Unit, shown in Figure 24, puts the PSD into Power Down Mode by monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. If the address strobe remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal becomes active, and the PSD will enter into Power Down Mode, discussed next. The PSD4000 Functional Blocks (cont.)

Table 25. PSD4000 Timing and Standby Current During Power mode is based only on the Turbo Bit.

1. Typical current consumption assuming no PLD inputs are changing state and

Table 24. Power Down Mode’s Effect on By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. for fifteen CLKIN (pin PD1) clock periods.

• If the address strobe starts pulsing again, the PSD will return to normal operation. The PSD will also return to normal operation if either the CSI input returns low or the Reset input returns high.
• The MCU address/data bus is blocked from all memories and PLDs.
• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from the PLDs will not block CLKIN from the APD unit.
• All PSD memories enter Standby Mode and are drawing standby current. However, the PLDs and I/O ports do not go into Standby Mode because you don’t want to have to wait for the logic and I/O to “wake-up” before their outputs can change. See Table 24 for Power Down Mode effects on PSD ports.
• Typical standby current is 50 µA for 5 V parts. This standby current value assumes that there are no transitions on any PLD input.

Bit 1 0 = Automatic Power Down (APD) is disabled. 1 = Automatic Power Down (APD) is enabled. 1 = PLD Turbo is off, saving power. Bit 4 0 = CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. Table 26. Power Management Mode Registers (PMMR0, PMMR2)** ***Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1. ***The PMMR0, and PMMR2 register bits are cleared to zero following power up. ***Subsequent reset pulses will not clear the registers. WRH/DBE ALE CNTL2 CNTL1 CNTL0 Addr. Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected. 1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power. Note:In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0]. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to PLD AND array is disconnected, saving power. Bit 5 0 = ALE input to the PLD AND array is connected. 1 = ALE input to PLD AND array is disconnected, saving power. Bit 6 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to PLD AND array is disconnected, saving power. **Unused bits should be set to 0. **Refer to Table 14 the signals that are blocked on pins CNTL0-2.

0 X X Not Counting

1 X Pulsing Not Counting

Table 27. APD Counter OperationThe

9.5.2 Other Power Saving Options

enabled by setting bits in the PMMR0 and PMMR2 registers.

9.5.2.1 Zero Power PLD

The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C. power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.

9.5.2.2 SRAM Standby Mode (Battery Backup)

below the Vstby voltage and that the SRAM is running on battery power.

9.5.2.3 The CSI Input

9.5.2.4 Input Clock

9.5.2.5 MCU Control Signals

9.5.3 Reset and Power On Requirement

9.5.3.1 Power On Reset

nanoseconds before the first memory access is allowed.

9.5.3.2 Warm Reset

after warm reset. Figure 26 shows the timing of the power on and warm reset. Figure 26. Power On and Warm Reset Timing

9.5.3.3 I/O Pin, Register and PLD Status at Reset

is active, the state of the outputs are determined by the equations specified in PSDsoft.

9.5.3.4 Reset of Flash Erase and Programming Cycles

9.6 Programming In-Circuit using the JTAG-ISP Interface

circuit board and programmed using JTAG-ISP. Table 29. JTAG Port Signals *SR_cod bit in the VM Register are always cleared to zero on power on or warm reset. Table 28. Status During Power On Reset, Warm Reset and Power Down Mode Configuration Menu. Configuration Menu. are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note 54 for more details on JTAG In-System-Programming.

PSD4000 Series Preliminary Information

9.6.1 Standard JTAG Signals

The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is received from the external JTAG controller, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR. The PSD4000 supports JTAG ISP commands, but not Boundary Scan. ST’s PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISP commands.

9.6.2 JTAG Extensions

TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed programming and erase functions by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note 54. TERR will indicate if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal will go low (active) when an error condition occurs, and stay low until a special JTAG command is executed or a chip reset pulse is received after an “ISC-DISABLE” command. TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD4000 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Secondary Flash Block. TSTAT and TERR can be configured as open-drain type signals with a JTAG command.

9.6.3 Security and Flash Memories Protection

When the security bit is set, the device cannot be read on a device programmer or through the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed. All other program/erase/verify commands are blocked. Full chip erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft. All Flash Memory and Boot sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft. The PSD4000 Functional Blocks (cont.)

Preliminary Information PSD4000 Series Range Temperature V CC Tolerance Commercial 0 ° C to +70°C + 5 V ± 10% Industrial –40° C to +85°C + 5 V ± 10% Commercial 0 ° C to +70°C 3.0 V to 3.6 V Industrial –40° C to +85°C 3.0 V to 3.6 V Symbol Parameter Condition Min Max Unit TSTG Storage Temperature PLDCC – 65 + 125 °C Commercial 0 + 70 °C Operating TemperatureIndustrial – 40 + 85 °C Voltage on any Pin With Respect to GND – 0.6 + 7 V VPP Device Programmer Supply Voltage With Respect to GND – 0.6 + 14 V VCC Supply Voltage With Respect to GND – 0.6 + 7 V ESD Protection >2000 V 10.0 Absolute Maximum Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Symbol Parameter Condition Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VCC Supply Voltage V-Versions All Speeds 3.0 3.6 V 12.0 Recommended Operating Conditions 11.0 Operating Range

• PLD Timing – Combinatorial Timing
• Microcontroller Timing – Read Timing – Write Timing – Power Down and Reset Timing Following are issues concerning the parameters presented: J In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD4000 is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". J The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures 27 and 27a show the PLD mA/MHz as a function of the number of Product Terms (PT) used. J In the PLD timing parameters, add the required delay when Turbo bit is "OFF".

Figure 27. PLD ICC /FrequencyConsumption (VCC = 5 V ± 10%)

Preliminary Information PSD4000 Series Figure 27a. PLD ICC /Frequency Consumption (PSD4135G2V Versions, VCC = 3 V) V CC = 3V 01 0 1 5 5 20 25 ICC – (mA) TURBO ON (100%) TURBO ON (25%) TURBO OFF TURBO OFF HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PT 100% PT 25% Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power Down Mode = 90% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/176 = 25.5% Turbo Mode = ON Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 µA/PT = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz +2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 µA + 0.1 x 42.9 = 45 µA + 4.29 mA = 4.34 mA This is the operating power with no Flash writes or erases. Calculation is based on I OUT = 0 mA. Example of PSD4000 Typical Power Calculation at VCC = 5.0 V AC/DC Parameters (cont.)

PSD4000 Series Preliminary Information Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power Down Mode = 90% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/176 = 25.5% Turbo Mode = Off Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45 µA + 0.1 x 32.9 = 45 µA + 3.29 mA = 3.34 mA This is the operating power with no Flash writes or erases. Calculation is based on I OUT = 0 mA. Example of Typical Power Calculation at VCC = 5.0 V in Turbo Off ModeAC/DC Parameters (cont.)

Preliminary Information PSD4000 Series 2. CSI deselected or internal Power Down mode is active. 3. PLD is in non-turbo mode and none of the inputs are switching 4. Refer to Figure 32 for PLD current calculation. 5. I O = 0 mA Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VIH High Level Input Voltage 4.5 V < V CC < 5.5 V 2 V CC +.5 V VIL Low Level Input Voltage 4.5 V < V CC < 5.5 V –.5 0.8 V VIH1 Reset High Level Input Voltage (Note 1) .8 V CC VCC +.5 V VIL1 Reset Low Level Input Voltage (Note 1) –.5 .2 V CC –.1 V VHYS Reset Pin Hysteresis 0.3 V VLKO VCC Min for Flash Erase and Program 2.5 4.2 V VOL Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V IOL = 8 mA, VCC = 4.5 V 0.25 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20 µA, VCC = 4.5 V 4.4 4.49 V IOH = –2 mA, VCC = 4.5 V 2.4 3.9 V VOH 1 Output High Voltage VSTBY On I OH 1 = –1 µA V SBY – 0.8 V VSBY SRAM Standby Voltage 2.0 V CC V ISBY SRAM Standby Current (VSTBY Pin) V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB Standby Supply Current for Power CSI > VCC –0.3 V 100 200 µADown Mode (Notes 2, 3 and 5) ILI Input Leakage Current V SS < VIN < VCC –1 ±.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ±5 10 µA IO Output Current Refer to IOL and IOH in the VOL and VOH row PLD_TURBO = OFF, 0m Af = 0 MHz (Note 3) PLD Only PLD_TURBO = ON, f = 0 MHz 400 700 µA/PT ICC (DC) Operating Supply During Flash Write/Erase(Note 5) Current Flash Only 15 30 mA Read Only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA PLD AC Base Fig. 27 ICC (AC) (Note 4) (Note 5) FLASH AC Adder 2.5 3.5 mA/MHz SRAM AC Adder 1.5 3.0 mA/MHz PSD4000 DC Characteristics (5 V ± 10% Versions)

PSD4000 Series Preliminary Information AC Symbols for PLD Timing. Example: tAVLX – Time from Address Valid to ALE Invalid. Signal Letters A – Address Input C – CEout Output D – Input Data E – E Input I – Interrupt Input L – ALE Input N – Reset Input or Output P – Port Signal Output R – UDS, LDS, DS, RD, PSEN Inputs S – Chip Select Input T– R/W Input W– WR Input B– Vstby Output M – Output Micro⇔ Cell Signal Behavior t – Time L – Logic Level Low or ALE H – Logic Level High V – Valid X – No Longer a Valid Logic Level Z – Float PW – Pulse Width Microcontroller Interface – AC/DC Parameters (5V ± 10% Versions)

Preliminary Information PSD4000 Series NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. RD and PSEN have the same timing. 3. Any input used to select an internal PSD4000 function. 4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 5. RD timing has the same timing as DS, LDS, and UDS signals. -70 -90 Turbo Symbol Parameter Conditions Min Max Min Max Off Unit tLVLX ALE or AS Pulse Width 15 20 ns tAVLX Address Setup Time (Note 3) 4 6 ns tLXAX Address Hold Time (Note 3) 7 8 ns tAVQV Address Valid to Data Valid (Note 3) 70 90 Add 12** ns tSLQV CS Valid to Data Valid 75 100 ns RD to Data Valid (Note 5) 24 32 ns t RLQV RD or PSEN to Data Valid, 80C51XA Mode (Note 2) 31 38 ns tRHQX RD Data Hold Time (Note 1) 0 0 ns tRLRH RD Pulse Width (Note 1) 27 32 ns tRHQZ RD to Data High-Z (Note 1) 20 25 ns tEHEL E Pulse Width 27 32 ns tTHEH R/W Setup Time to Enable 6 10 ns tELTL R/W Hold Time After Enable 0 0 ns tAVPV Address Input Valid to Address (Note 4) 20 25 nsOutput Delay Read Timing (5 V ± 10% Versions) Microcontroller Interface – PSD4000 AC/DC Parameters (5V ± 10% Versions)

PSD4000 Series Preliminary Information -70 -90 Symbol Parameter Conditions Min Max Min Max Unit tLVLX ALE or AS Pulse Width 15 20 tAVLX Address Setup Time (Note 1) 4 6 ns tLXAX Address Hold Time (Note 1) 7 8 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 8 15 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 12 15 ns tDVWH WR Data Setup Time (Note 3) 25 35 ns tWHDX WR Data Hold Time (Note 3) 4 5 ns tWLWH WR Pulse Width (Note 3) 28 35 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 6 8 ns tWHAX2 Trailing Edge of WR to DPLD Address Input Invalid (Note 3 and 4) 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register (Note 3) 27 30 ns tAVPV Address Input Valid to Address (Note 2) 20 25 nsOutput Delay Write Timing (5 V ± 10% Versions) NOTES: 1. Any input used to select an internal PSD4000 function. 2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. tWHAX2 is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. Microcontroller Interface – PSD4000 AC/DC Parameters (5V ± 10% Versions) -70 -90 Slew TURBO Rate Symbol Parameter Conditions Min Max Min Max OFF (Note 1) Unit tPD PLD Input Pin/Feedback to 20 25 Add 12 Sub 2 nsPLD Combinatorial Output tARD PLD Array Delay 11 16 ns PLD Combinatorial Timing (5 V ± 10%) NOTE: 1. Fast Slew Rate output available on Port C and F.

Preliminary Information PSD4000 Series Symbol Parameter Conditions Min Typ Max Unit tNLNH Warm RESET Active Low Time (Note 1) 150 ns tOPR RESET High to Operational Device 120 ns tNLNH-PO Power On Reset Active Low Time 1 ms tNLNH-A Warm RESET Active Low Time (Note 2) 25 µs Reset Pin Timing (5 V ± 10%) NOTE: 1. tCLCL is the CLKIN clock period. Microcontroller Interface – PSD4000 AC/DC Parameters (5V ± 10% Versions) Symbol Parameter Conditions Min Typ Max Unit tBVBH Vstby Detection to Vstbyon Output High (Note 1) 20 µs tBXBL VstbyOff Detection to Vstbyon Output Low (Note 1) 20 µs Vstbyon Timing (5 V ± 10%) -70 -90 Symbol Parameter Conditions Min Max Min Max Unit tLVDV ALE Access Time from Power Down 80 90 ns Maximum Delay from APD Enable Using CLKIN Input 15 *tCLCL (µs) (Note 1) µstCLWH to Internal PDN Valid Signal Power Down Timing (5 V ± 10%) NOTE: 1. RESET will not abort Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

PSD4000 Series Preliminary Information -70 -90 Symbol Parameter Conditions Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 20 18 MHz tISCCH TCK Clock High Time (Note 1) 23 26 ns tISCCL TCK Clock Low Time (Note 1) 23 26 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 MHz tISCCH-P TCK Clock High Time (for PLD only) (Note 2) 240 240 ns tISCCL-P TCK Clock Low Time (for PLD only) (Note 2) 240 240 ns tISCPSU ISC Port Set Up Time 6 8 ns tISCPH ISC Port Hold Up Time 5 5 ns tISCPCO ISC Port Clock to Output 21 23 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 ns ISC Timing (5 V ± 10%) Microcontroller Interface – PSD4000 AC/DC Parameters (5V ± 10% Versions) Symbol Parameter Min Typ Max Unit Flash Program 8.5 sec Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase 10 sec t WHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase 2.2 sec tWHQV1 Word Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles t WHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output Valid (Data Polling) (Notes 2 and 3) 30 ns Flash Program, Write and Erase Times (5 V ± 10%) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only.

Preliminary Information PSD4000 Series Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 3.0 3.6 V VIH High Level Input Voltage 3.0 V < V CC < 3.6 V .7 V CC VCC +.5 V VIL Low Level Input Voltage 3.0 V < V CC < 3.6 V –.5 0.8 V VIH1 Reset High Level Input Voltage (Note 1) .8 V CC VCC +.5 V VIL1 Reset Low Level Input Voltage (Note 1) –.5 .2 V CC –.1 V VHYS Reset Pin Hysteresis 0.3 V VLKO VCC Min for Flash Erase and Program 1.5 2.3 V VOL Output Low Voltage IOL = 20 µA, VCC = 3.0 V 0.01 0.1 V IOL = 4 mA, VCC = 3.0 V 0.15 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20 µA, VCC = 3.0 V 2.9 2.99 V IOH = –1 mA, VCC = 3.0 V 2.7 2.8 V VOH 1 Output High Voltage VSTBY On I OH 1 = –1 µA V SBY – 0.8 V VSBY SRAM Standby Voltage 2.0 V CC V ISBY SRAM Standby Current (VSTBY Pin) V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB Standby Supply Current CSI >V CC –0.3 V 50 100 µAfor Power Down Mode (Notes 2 and 3) ILI Input Leakage Current V SS < VIN < VCC –1 ±.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ±5 10 µA IO Output Current Refer to IOL and IOH in the VOL and VOH row PLD_TURBO = OFF, f = 0 MHz (Note 3) 0m A PLD Only PLD_TURBO = ON, ICC (DC) Operating f = 0 MHz 200 400 µA/PT (Note 5) Supply Current During FLASH FLASH Write/Erase Only 10 25 mA Read Only, f = 0 MHz 0 0 mA SRAM f = 0 MHz 0 0 mA PLD AC Base (Note 4) Figure 27a ICC (AC) FLASH (Note 5) AC Adder 1.5 2.0 mA/MHz SRAM AC Adder 0.8 1.5 mA/MHz PSD4000 DC Characteristics (3.0 V to 3.6 V Versions) Advance Information 2. CSI deselected or internal PD mode is active. 3. PLD is in non-turbo mode and none of the inputs are switching. 4. Refer to Figure 31a for PLD current calculation. 5. I O = 0 mA.

PSD4000 Series Preliminary Information AC Symbols for PLD Timing. Example: tAVLX – Time from Address Valid to ALE Invalid. Signal Letters A – Address Input C – CEout Output D – Input Data E – E Input L – ALE Input N – Reset Input or Output P – Port Signal Output Q – Output Data R – WR, UDS, LDS, DS, IORD, PSEN Inputs S – Chip Select Input T– R/W Input W– Internal PDN Signal B– Vstby Output Signal Behavior t – Time L – Logic Level Low or ALE H – Logic Level High V – Valid X – No Longer a Valid Logic Level Z – Float PW – Pulse Width Microcontroller Interface – PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions)

Preliminary Information PSD4000 Series -90 -12 Turbo Symbol Parameter Conditions Min Max Min Max Off Unit tLVLX ALE or AS Pulse Width 22 24 ns tAVLX Address Setup Time (Note 3) 7 9 ns tLXAX Address Hold Time (Note 3) 8 10 ns tAVQV Address Valid to Data Valid (Note 3) 90 120 Add 20** ns tSLQV CS Valid to Data Valid 90 120 ns RD to Data Valid (Note 5) 35 35 ns t RLQV RD or PSEN to Data Valid, 80C51XA Mode (Note 2) 45 48 ns tRHQX RD Data Hold Time (Note 1) 0 0 ns tRLRH RD Pulse Width (Note 1) 36 40 ns tRHQZ RD to Data High-Z (Note 1) 38 40 ns tEHEL E Pulse Width 38 42 ns tTHEH R/W Setup Time to Enable 10 16 ns tELTL R/W Hold Time After Enable 0 0 ns tAVPV Address Input Valid to (Note 4) 30 35 nsAddress Output Delay Read Timing (3.0 V to 3.6 V Versions) Microcontroller Interface – PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. RD and PSEN have the same timing for 80C51XA. 3. Any input used to select an internal PSD4135G2V function. 4. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 5. RD timing has the same timing as DS, LDS, and UDS signals.

PSD4000 Series Preliminary Information -90 -12 Slew TURBO Rate Symbol Parameter Conditions Min Max Min Max OFF (Note 1) Unit tPD PLD Input Pin/Feedback to 38 43 Add 20 Sub 6 nsPLD Combinatorial Output tARD PLD Array Delay 23 27 ns PLD Combinatorial Timing (3.0 V to 3.6 V Versions) NOTE: 1. Fast Slew Rate output available on Port C and F. -90 -12 Symbol Parameter Conditions Min Max Min Max Unit tLVLX ALE or AS Pulse Width 22 24 tAVLX Address Setup Time (Note 1) 7 9 ns tLXAX Address Hold Time (Note 1) 8 10 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 15 18 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 15 18 ns tDVWH WR Data Setup Time (Note 3) 40 45 ns tWHDX WR Data Hold Time (Note 3) 5 8 ns tWLWH WR Pulse Width (Note 3) 40 45 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 8 10 ns tWHAX2 Trailing Edge of WR to DPLD Address (Notes 3 and 4) 0 0 nsInput Invalid tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register (Note 3) 33 33 ns tAVPV Address Input Valid to Address (Note 2) 30 35 nsOutput Delay Write Timing (3.0 V to 3.6 V Versions) NOTES: 1. Any input used to select an internal PSD4000 function. 2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. 4. t WHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory. Microcontroller Interface – PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions)

Preliminary Information PSD4000 Series -90 -12 Symbol Parameter Conditions Min Max Min Max Unit tLVDV ALE Access Time from Power Down 128 135 ns Maximum Delay from APD EnabletCLWH to Internal PDN Valid Signal Using CLKIN Input 15 *tCLCL (µs) (Note 1) µs Power Down Timing (3.0 V to 3.6 V Versions) Symbol Parameter Conditions Min Typ Max Unit tNLNH Warm RESET Active Low Time (Note 1) 300 ns tOPR RESET High to Operational Device 300 ns tNLNH-PO Power On Reset Active Low Time 1 ms Warm RESETActive Low Timet NLNH-A (Note 2) 25 µs Reset Pin Timing (3.0 V to 3.6 V Versions) NOTE: 1. tCLCL is the CLKIN clock period. Microcontroller Interface – PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Symbol Parameter Conditions Min Typ Max Unit tBVBH VstbyDetection to VstbyonOutput High (Note 1) 20 µs tBXBL VstbyOff Detection to Vstbyon Output Low (Note 1) 20 µs Vstbyon Timing (3.0 V to 3.6 V Versions) NOTE: 1. RESET will not abort Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

PSD4000 Series Preliminary Information Microcontroller Interface – PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Symbol Parameter Min Typ Max Unit Flash Program 8.5 sec Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase 10 sec t WHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase 2.2 sec tWHQV1 Word Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles t WHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output Valid (Data Polling) 30 ns(Notes 2 and 3) Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions) -90 -12 Symbol Parameter Conditions Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 15 12 MHz tISCCH TCK Clock High Time (Note 1) 30 40 ns tISCCL TCK Clock Low Time (Note 1) 30 40 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 MHz tISCCH-P TCK Clock High Time (for PLD only) (Note 2) 240 240 ns tISCCL-P TCK Clock Low Time (for PLD only) (Note 2) 240 240 ns tISCPSU ISC Port Set Up Time 11 12 ns tISCPH ISC Port Hold Up Time 5 5 ns tISCPCO ISC Port Clock to Output 26 32 ns tISCPZV ISC Port High-Impedance to Valid Output 26 32 ns tISCPVZ ISC Port Valid Output to High-Impedance 26 32 ns ISC Timing (3.0 V to 3.6 V Versions) NOTES: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only.

Figure 28. Read Timing *tAVLX and tLXAX are not required 80C51XA in Burst Mode.

Figure 29. Write Timing

PSD4000 Series Preliminary Information 18.0 PSD4000 Pin Assignments Pin No. Pin Assignments Pin No. Pin Assignments

1 PD2 41 PC0

2 PD3 42 PC1

3 AD0 43 PC2

4 AD1 44 PC3

5 AD2 45 PC4

6 AD3 46 PC5

7 AD4 47 PC6

8 GND 48 PC7

10 AD5 50 GND

11 AD6 51 PA0

12 AD7 52 PA1

13 AD8 53 PA2

14 AD9 54 PA3

15 AD10 55 PA4

16 AD11 56 PA5

17 AD12 57 PA6

18 AD13 58 PA7

19 AD14 59 CNTL0

20 AD15 60 CNTL1

21 PG0 61 PB0

22 PG1 62 PB1

23 PG2 63 PB2

24 PG3 64 PB3

25 PG4 65 PB4

26 PG5 66 PB5

27 PG6 67 PB6

28 PG7 68 PB7

30 GND 70 GND

31 PF0 71 PE0

32 PF1 72 PE1

33 PF2 73 PE2

34 PF3 74 PE3

35 PF4 75 PE4

36 PF5 76 PE5

37 PF6 77 PE6

38 PF7 78 PE7

39 RESET 79 PD0

40 CNTL2 80 PD1

80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U)

60 CNTL1

59 CNTL0

58 PA7

57 PA6

56 PA5

55 PA4

54 PA3

53 PA2

52 PA1

51 PA0

50 GND

49 GND

48 PC7

47 PC6

46 PC5

45 PC4

44 PC3

43 PC2

42 PC1

41 PC0

Figure 36. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP)

PSD4000 Series Preliminary Information Figure 36A. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) D E3 E1 E Index Mark Standoff: 0.05 mm Min. Load Coplanarity: 0.102 mm Max. L C Be 1 A2 AA1 α Family: Plastic Thin Quad Flatpack (TQFP) Millimeters Inches Symbol Min Max Notes Min Max Notes α 0° 7° 0° 8° A – 1.20 – 0.047 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 Reference 0.007 0.011 C 0.20 0.008 D 13.95 14.05 0.512 0.551 D1 11.95 12.05 0.433 0.472 D3 9.5 Reference 0.374 Reference E 13.95 14.05 0.512 0.551 E1 11.95 12.05 0.433 0.472 E3 9.5 Reference 0.374 Reference e1 0.50 Reference 0.019 Reference L 0.45 0.75 0.018 0.030 N8 0 8 0 060198R0

Preliminary Information PSD4000 Series 20.0 Selector Guide Part # MCU PLDs/Decoders I/O Memory Other Software

5 Data Inputs Input Macrocells Ports Flash Program Store ISP via JTAG PSDsoft

Volts Path Output Macrocells 2nd Flash Array IAP via MCU Express Outputs EEPROM Zero Power PSDsoft Page SRAM Per. Mode 2000 Reg. w/BB Security PMU APD PSD4135G2 16 57 – – 24 8-bit 52 4096Kb 256Kb – 64Kb X X X – X X X X X PSD4235G2 16 57 24 16 24 8-bit 52 4096Kb 256Kb – 64Kb X X X – X X X X Selector Guide – PSD4000 Series

PSD4000 Series Preliminary Information 21.0 Part Number Construction 22.0 Ordering Information I/O COUNT & OTHER NVM SIZE SRAM SIZE FAMILY/SERIES PSD BRAND NAME PSD = Standard Low Power Device 8 = Flash PSD for 8-bit MCUs 0 = 0Kb 1 = 16Kb 2 = 32Kb 3 = 64Kb 1 = 256Kb 2 = 512Kb 3 = 1Mb 4 = 2Mb 5 = 4Mb REVISION "Blank" = no rev. - A = Rev. A - B = Rev. B - C = Rev. C SPEED - 70 = 70ns - 90 = 90ns - 12 = 120ns - 15 = 150ns - 20 = 200ns PACKAGE TYPE J = PLCC U = TQFP M = PQFP B81 = BGA TEMP RANGE "Blank" = 0°C to +70°C (Commercial) I = –40°C to +85°C (Industrial) 2ND NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 3 = No 2nd Array V cc VOLTAGE "blank" = 5 Volt V = 3.0 VoltF = 27 I/O G = 52 I/O Flash PSD Part Number Construction 41 = Flash PSD for 16-bit MUCs (with simple PLD) 9 = Flash PSD for 8-bit MUCs (with simple PLD) 42 = Flash PSD for 16-bit MUCs (with CPLD) I I I I I I I I I I I I I I I I I I CHARACTER # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PART NUMBER PS D 4 2 13 F2 A 15 J ––

REVISION HISTORY

Table 1. Document Revision History

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