PSD411A1

PSD4XX STMICROELECTRONICS | Alldatasheet

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Technical content

This is information on a product still in production but not recommended for new designs. Figure 1. Packages

i PSD4XX Family PSD4XX/ZPSD4XX Field-Programmable Microcontroller Peripherals Table of Contents

Field-Programmable Microcontroller Peripherals Table of Contents (cont.)

1.0 Introduction Programmable Peripheral PSD4XX Family Field-Programmable Microcontroller Peripherals The PSD4XX family is a microcontroller peripheral that integrates high-performance and user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The PSD4XX products also provide a powerful microcontroller interface that eliminates the need for external “glue logic”. The no “glue logic” concept provides a user-programmable interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that is easy to use. The part’s integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will automatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are designed to consume minimum power using Zero-power CMOS technology that uses only 10 µA (typical) standby current. Unused product terms are automatically disabled, also reducing power, regardless of the Turbo bit setting. The main function of the DPLD is to perform address decoding for the internal I/O ports, EPROM, and SRAM. The address decoding can be based on up to 24 bits of address inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports separate program and data spaces (for 8031 compatible MCUs). The General-purpose PLD (GPLD) can be used to implement various logic functions defined by the user, such as:

• State machines
• Loadable counters and shift registers
• Inter-processor mailbox
• External control logic (chip selects, output enables, etc.). The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O pins.

1.0 Introduction (cont.) The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be individually configured to provide many functions, including the following:

• MCU I/O
• GPLD I/O
• Latched address output (for MCUs with multiplexed data bus)
• Data bus (for MCUs with non-multiplexed data bus). The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the ZPLDs, enabling the user to generate signals for external devices. The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four equal-sized blocks. Each block can occupy a different address location, allowing for versatile address mapping. The access time of the EPROM includes the address latching and DPLD decoding. The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a power failure. Therefore, you can place data in the SRAM that you want to keep after the power is switched off. Power switchover to the battery automatically occurs when V CC drops below Vstby. A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for microcontrollers with limited address space. The Page Register outputs are connected to both ZPLDs and thus can also be used for external paging schemes. The Power Management Unit (PMU) of the PSD4XX enables the user to control the power consumption on selected functional blocks, based on system requirements. For microcontrollers that do not generate a chip select input for the PSD, the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or Sleep Mode, based on the inactivity of ALE (or AS). Implementing your design has never been easier than with PSDsoft—ST ’s software development suite. Using PSDsoft, you can do the following:
• Configure your PSD4XX to work with virtually any microcontroller
• Specify what you want implemented in the programmable logic using a design file
• Simulate your design
• Download your design to the part using a programmer. 2.0 Key Features J Single-chip programmable peripheral for microcontroller-based applications J 256K to 1 Mbit of UV EPROM with the following features:
• Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16
• Divided into four equally-sized mappable blocks for optimized address mapping
• As fast as 70 ns access time, which includes address decoding
• Built-in Zero-power technology J 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as quick as 70 ns, including address decoding. The contents of the SRAM can be battery-backed by connecting a battery to the Vstby pin. The SRAM also has built-in Zero-power technology. J 40 I/O pins (divided into five 8-bit ports) that can be individually configured for:
• Standard MCU I/O
• PLD/macrocell I/O
• Latched address output
• High-order address inputs
• Special function I/O
• Open-drain output

2.0 Key Features J Two Zero-power Programmable Logic Devices (ZPLDs): the Decode PLD (DPLD) and the General-purpose PLD (GPLD) can be used for:

• Up to 59 Input and 126 output product terms
• 24 Macrocells and I/O
• Decode up to 16 MB of address
• State machines and state logic
• Generate external signals (chip selects, bus interface, etc.) J Microcontroller logic that eliminates the need for external “glue logic” has the following features:
• Ability to interface to multiplexed and non-multiplexed buses
• Built-in address latches for multiplexed address/data bus
• ALE and Reset polarity are programmable
• Multiple configurations are possible for interface to many different microcontrollers J Page logic is connected to the ZPLDs and expands the MCU address space to up to 16 times J Programmable power management allows:
• SRAM, EPROM, and ZPLDs to enter standby mode automatically
• Disabling of the clock input to the ZPLDs
• ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo bit setting J A security bit prevents reading the PSD4XX configuration and the ZPLD contents. Setting this bit will prevent the device from being copied on a device programmer. J Built-in security enables the user to block read accesses from a device programmer J Package choices include 68-pin PLCC, 68-pin CLDCC, and 80-pin TQFP J Programmable polarity Reset output (includes hysteresis), based on Reset input J Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC. 3.0 Notation Throughout this data sheet, references are made to the PSD4XX. In most cases, these references also cover the ZPSD4XX and ZPSD4XXV products. Exceptions will be noted. The main difference between the ZPSD4XX and the PSD4XX is the standby current (Isb). The ZPSD4XX devices have been rated for a lower standby current. Also, there is no low-voltage version of the PSD4XX. There is only the low-voltage version of the ZPSD4XX, which has a V suffix. Portable and battery powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this need, ST has developed a new Zero Power technology. PSD4XX products virtually eliminate the DC component of power consumption reducing it to standby levels. Eliminating the DC component is the basis for the words “Zero Power”. PSD4XX products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit functions while drawing minimal current. 4.0 Zero-Power Background

PROG. BUS INTRF ADIO PORT PROG. PORT PROG. PORT PORT C PROG. PORT PORT D CONTROL RD, WR AD0 – AD15 PC0 – PC7 PD0 – PD7 CLKIN CLKIN PAGE REG. ZPLD INPUT BUS GLOBAL CONFIG. SECURITY PORT A POWER MANAGER UNIT VSTDBY PA0 – PA7 PROG. PORT PORT B PB0 – PB7 PROG. PORT PORT E PE0 – PE7 ADDRESS/DATA/CONTROL BUS PORT A MACROCELLS PORT B MACROCELLS PORT E MACROCELLS (NOTE 2) 27PT (NOTE 1) (NOTE 1) 80PT 11PT CLKIN 256K–1M BIT EPROM

16 K BITS

MACROCELL FEEDBACK OR PORT INPUT CSIOP GENERAL PLD (GPLD) 24 MACROCELLS DECODE PLD (DPLD) NOTES: 1. ZPLD INPUT BUS – A1 = 36 + CLOCK = 37 INPUTS – A2 = 58 + CLOCK = 59 INPUTS 2. PORT E MACROCELLS AVAILABLE ON A2 VERSIONS ONLY. Figure 1. PSD4XX Block Diagram

Figure 3. PSDsoft Development Tools Shown in Figure 3 (below) is the software design flow for a PSD4XX device. should be set (such as the security bit). a result, the MCU firmware is merged with the logic and configuration definition of the PSD. PLD fusemap, and MCU firmware information. stimulus file since all of the signals and node names are taken from the design file.

are listed in Table 1. See the ordering information section at the end of this document. Table 1. PSD4XX Product Matrix NOTE: PMU = Power Management Unit.

Pin Name Pin Function Type Function Descriptions ADIO0 – ADIO15 Address/data bus I/O 1. Address/data bus, multiplexed bus mode 2. Address bus, non-multiplexed bus mode RD Multiple Names I Multiple functions 1. Read 1. Read signal 2. E 2. E signal (Clock) 3. DS 3. Data strobe signal 4. LDS 4. Low byte data strobe WR Multiple Names I Multiple functions 1. WR 1. Write signal 2. R/W 2. Read-write signal 3. WRL 3. Low byte write signal CSI Chip Select Input I Active low, select PSD4XX standby mode if high. RESET Reset Input I Reset I/O ports, ZPLD/macrocells, and Configuration Registers. Active low. CLKIN Input clock I Clock input to ZPLD macrocells, ZPLD Array and APD counter. Connect to ground if Clock Input not used. PA0 – PA7 I/O Port A I/O Multiple functions 1. I/O port 2. ZPLD/macrocell I/O port 3. Latched address outputs (PA0 – PA7) fi (A0 – A7) 4. High address inputs (A16 – A23) PB0 – PB7 I/O Port B I/O Multiple functions 1. I/O port 2. ZPLD/macrocell I/O port 3. Latched address outputs (PB0–PB7) fi (A0–A7) or (A8–A15) PC0 – PC7 I/O Port C I/O Multiple functions CMOS 1. I/O port or 2. ZPLD input port OD 3. Latched address outputs (PC0 – PC7) fi (A0–A7) 4. Data Port (D0 – D7, non-multiplexed bus) PD0 – PD7 I/O Port D I/O Multiple functions CMOS 1. I/O port or 2. ZPLD input port* OD 3. Latched address outputs (PD0–PD7) fi (A0–A7) or (A8–A15) 4. Data Port (D8–D15, non-multiplexed bus) 8.0 Table 2. PSD4XX Pin Descriptions The following table describes the pin names and pin functions of the PSD4XX. Pins that have multiple names and/or functions are defined by user configuration. *Available only in PSD4XXA2 and ZPSD4XXA2 Series.

Pin Name Pin Function Type Function Descriptions PE0 Port PE, pin 0 I/O Multiple functions 1. BHE 1. High byte enable, 16 bit data 2. PSEN 2. Read program memory, 8031 signal 3. WRH 3. Write high data byte 4. UDS 4. Upper Data Strobe 5. SIZ0 5. Byte enable, 68300 signal 6. PE0 6. I/O pin 7. PE0 7. ZPLD I/O pin 8. PE0 8. Latched Address Out – A0 PE1 Port PE, pin 1 I/O Multiple functions 1. ALE 1. Address strobe 2. PE1 2. I/O pin 3. PE1 3. ZPLD I/O pin 4. PE1 4. Latched Address Out – A1 PE2 Port PE, pin 2 Multiple functions 1. PE2 I/O 1. I/O pin 2. PE2 2. ZPLD I/O pin 3. PE2 3. Latched Address Out – A2 PE3 Port PE, pin 3 Multiple functions 1. PE3 I/O 1. I/O pin 2. PE3 2. ZPLD I/O pin 3. PE3 3. Latched Address Out – A3 PE4 Port PE, pin 4 Multiple functions 1. PE4 I/O 1. I/O pin 2. PE4 2. ZPLD I/O pin 3. PE4 3. Latched Address Out – A4 PE5 Port PE, pin 5 Multiple functions 1. PE5 I/O 1. I/O pin 2. PE5 2. ZPLD I/O pin 3. PE5 3. Latched Address Out – A5 PE6 Port PE, pin 6 Multiple functions 1. PE6 I/O 1. I/O pin 2. PE6 2. ZPLD I/O pin 3. PE6 3. Latched Address Out – A6 PE7 Port PE, pin 7 Multiple functions 1. APD CLK 1. Automatic Power Down Clock Input 2. PE7 I/O 2. I/O pin 3. PE7 3. ZPLD I/O pin 4. PE7 4. Latched Address Out – A7 Vstdby Vstdby I SRAM power pin for standby operation (battery backup) VCC VCC IV CC power pin GND GND I Ground pin 8.0 Table 2. PSD4XX Pin Descriptions (Cont.) *Available only in PSD4XXA2 and ZPSD4XXA2 Series.

9.0 The PSD4XX Architecture PSD4XX consists of five major functional blocks: J ZPLD Blocks J Bus Interface J I/O Ports J Memory Block J Power Management Unit The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. The chip configurations are specified by the user in the PSDsoft Development Software. Other configurations are specified by setting up the appropriate bits in the configuration registers during run time.

9.1 The ZPLD Block

The PSD4XX series devices provide two ZPLD configurations. The ZPLD in the PSD4XXA1 devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113 product terms. The PSD4XXA2 has a full function ZPLD with 24 registered macrocells and up to 126 product terms.

9.1.1 The PSD4XXA1 ZPLD Block

J 8 registered and 8 combinatorial macrocells J Combinatorial/registered outputs J Maximum 113 product terms J Programmable output polarity J User configured register clear/preset J User configured register clock input J 37 Inputs J Accessible via 16 I/O pins J Power Saving Mode J UV-Erasable General Description The ZPLD block has 2 embedded PLD devices: J DPLD The Address Decoding PLD, generating select signals to internal I/O or memory blocks. J GPLD The General Purpose PLD provides 8 registered and combinatorial programmable macrocells for general or complex logic implementation; dedicated to user application. Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same input bus. The true or complement of the 37 input signals are fed to the programmable AND-ARRAY. Names and sources of the input signals are shown in Table 3. The PB signals, depending on user configuration, can either be macrocell feedbacks or inputs from Port B.

Figure 4. ZPLD Block Diagram

8 I/O

80 PT PB0 – PB7

Table 3. ZPLD Input Signals9.0

9.1.1.1 The DPLD

ports based on address inputs A[7:0]. user in the ABEL file (PSDabel). are needed, the user can bring in the lines through Port A to the DPLD.

9.1.1.2 The GPLD

The structure of the General Purpose PLD consists of a programmable AND ARRAY and 2 sets of I/O Macrocells. The ARRAY has 37 input signals, same as the DPLD. From these inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells connected to Port B are named PB Macrocells. The PB macrocells are registered macrocells with D-type flip-flops, where PA consists of combinatorial macrocells.

9.1.1.3 TPA Macrocell Structure

Figure 5 shows the PA Macrocell block, which consists of 8 identical combinatorial macrocells. Each macrocell output can be connected to its own I/O pin on Port A. There is one user programmable global product term that is output from the GPLD’s AND ARRAY which is shared by all the macrocells in Port A: J PA.OE Enable or tri-state Port A output pins The circuit of a PA Macrocell is shown in Figure 6. There are 4 product terms from the GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as: J GPLD Input Use Port A pin as dedicated input J GPLD Output Use Port A pin as dedicated output 9.0 The PSD4XX Architecture (cont.)

Figure 5. DPLD Logic Array

4 EPROM

Figure 6. PA Macrocell Block Diagram

Figure 7. PA Macrocell

9.1.1.4 Port B Macrocell Structure

Figure 7 shows the PB Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable. The circuit of a PB Macrocell is shown in Figure 8. There are 10 product terms from the GPLDs AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as: J Registered Output Select output from D flip flop. J Combinatorial Output Select output from OR gate. J GPLD Input Use Port B pin as dedicated input. J GPLD Output Use Port B pin as dedicated output. J GPLD I/O Use Port B pin as bidirectional pin. J Macrocell Feedback Register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. In case of "Buried Feedback", where the output of the macrocell is not connected to a Port B pin, Port B can be configured to perform other user defined I/O functions. Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. The signals are defined as follow: J PRESET Active only if defined by a product term (PBi.PR) J CLEAR Two selectable inputs: Reset input and/or user defined product term (PBi.RE) J CLK Two selectable inputs – CLKIN input or user defined product term (PBi.CLK). The macrocell is operated in Synchronous Mode if the clock input is CLKIN, and is in Asynchronous Mode if the clock is a product-term clock defined by the user. Figure 9 shows the input/output path of a PB macrocell to the Port pin with which it is associated. If the Port pin is specified as a PB output pin in the PSDsoft, the MUX in the I/O Port Cell selects the PB Macrocell as an output of the Port pin. The output enable signal to the buffer in the I/O cell can be controlled by a product term from the AND Array. If the Port pin is specified as a ZPLD input pin, the MUX in the PB Macrocell selects the Port input signal to be one of the 61 signals in the ZPLD Input Bus. 9.0 The PSD4XX Architecture (cont.)

9.0 The PSD4XX Architecture (cont.)

9.1.1.5 The ZPLD Power Management

The ZPLD implements a Zero Power Mode, which provides considerable power savings for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the Power Management Mode Register 0 (PMMR0) has to be turned off. If none of the inputs to the ZPLD are switching for a time period of 90ns, the ZPLD puts itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume normal operation as soon as one or more of the inputs change state. Two other features of the ZPLD provide additional power savings: 1. Clock Disable: Users can disable the clock input to the ZPLD and/or macrocells,thereby reducing AC power consumption. 2. Product Term Disable: Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically for further power savings. The ZPLD power configuration is described in the Power Management Unit section.

Figure 8. PB Macrocell Block Diagram

Figure 9. PB Macrocell

Figure 10. PB Macrocell Input/Output Port

(cont.)

9.1.2 The PSD4XXA2 ZPLD Block

J Combinatorial/registered outputs J Maximum 126 product terms J Programmable output polarity J User configured register clear/preset J User configured register clock input J 59 Inputs J Accessible via 24 I/O pins J Power Saving Mode J UV-Erasable General Description The ZPLD block has 2 embedded PLD devices: J DPLD The Address Decoding PLD, generating select signals to internal I/O or memory blocks. J GPLD The General Purpose PLD provides 24 programmable macrocells for general or complex logic implementation; dedicated to user application. Figure 11 shows the architecture of the ZPLD. The PLD devices all share the same input bus. The true or complement of the 59 input signals are fed to the programmable AND-ARRAY. Names and source of the input signals are shown in Table 4. The PA, PB, PE signals, depending on user configuration, can either be macrocell feedbacks or inputs from Port A, B or E.

11 PT PE0 – PE7

Figure 11. PSD4XXA2 ZPLD Block Diagram

Table 4. ZPLD Input SignalsThe PSD4XX

9.1.2.1 The DPLD

ports based on address inputs A[7:0]. are a total of 59 inputs and 8 outputs. Each output consists of a single product term. by the user in the ABEL file (PSDabel). are needed, the user can bring in the lines through Port A to the DPLD.

Figure 12. DPLD Logic Array

(cont.)

9.1.2.2 The GPLD

The structure of the General Purpose PLD consists of a programmable AND ARRAY and 3 sets of I/O Macrocells. The ARRAY has 59 input signals, same as the DPLD. From these inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells connected to Port A are named PA Macrocells. The 3 sets of macrocells, PA, PB and PE, are similar in structure and function. Figure 13 shows the output/input path of a GPLD macrocell to the Port pin with which it is associated. If the Port pin is specified as a GPLD output pin in PSDsoft, the MUX in the I/O Port Cell selects the GPLD macrocell as an output of the Port pin. The output enable signal to the buffer in the I/O cell can be controlled by a product term from the AND ARRAY. If the Port pin is specified as a ZPLD input pin, the MUX in the GPLD macrocell selects the Port input signal to be one of the 61 signals in the ZPLD Input Bus.

9.1.2.3 Port A Macrocell Structure

Figure 14 shows the PA Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port A. There are 3 user programmable global product terms output from the GPLD’s AND ARRAY which are shared by all the macrocells in Port A: J PA.OE Enable or tri-state Port A output pins J PA.PR Preset D flip flop in the macrocells J PA.RE Reset/Clear D flip flop in the macrocells Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable. The circuit of a PA Macrocell is shown in Figure 15. There are 6 product terms from the GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as: J Registered Output Select output from D flip flop J Combinatorial Output Select output from OR gate J GPLD Input Use Port A pin as dedicated input J GPLD Output Use Port A pin as dedicated output J GPLD I/O Use Port A pin as bidirectional pin J Macrocell Feedback Register feedback for state machine implementations or expander feedback from the combinatorial output, to expand the number of product terms available to another macrocell. In case of "Buried Feedback", where the output of the macrocell is not connected to a Port A pin, Port A can be configured to perform other user defined I/O functions. The two global product terms assigned for asynchronous clear (PA.RE) and preset (PA.PR) are mainly for proper PA Macrocell initialization. The macrocell flip-flop can also be cleared during reset by MACRO-RST, if such an option is chosen. The clock source is always the input clock CLKIN.

Figure 13. GPLD Macrocell Input/Output Port

Figure 14. PA Macrocell Block Diagram

Figure 15. PSD4XXA2 PA Macrocell

(cont.)

9.1.2.4 Port B Macrocell Structure

Figure 16 shows the PB Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable. The circuit of a PB Macrocell is shown in Figure 17. There are 10 product terms from the GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as: J Registered Output Select output from D flip flop. J Combinatorial Output Select output from OR gate. J GPLD Input Use Port B pin as dedicated input. J GPLD Output Use Port B pin as dedicated output. J GPLD I/O Use Port B pin as bidirectional pin. J Macrocell Feedback Register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. In case of "Buried Feedback", where the output of the macrocell is not connected to a Port B pin, Port B can be configured to perform other user defined I/O functions. Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. The signals are defined as follow: J PRESET Active only if defined by a product term (PBx.PR) J CLEAR Two selectable inputs: Reset input or user defined product term (PBx .RE) J CLK Two selectable inputs – CLKIN input or user defined product term (PBx.CLK). The macrocell is operated in Synchronous Mode if the clock input is CLKIN, and is in Asynchronous Mode if the clock is a product-term clock defined by the user.

Figure 16. PSD4XXA2 PB Macrocell Block Diagram

Figure 17. PSD4XXA2 PB MacrocellThe PSD4XX

9.1.2.5 Port E Macrocell Structure

Figure 18 shows the PE Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port E. There are 3 user programmable global product terms output from the GPLD’s AND ARRAY which are shared by all the macrocells in Port E: J PE.OE Enable or tri-state Port PE output pins J PE.PR Preset D flip flop in the macrocells J PE.RE Reset/Clear D flip flop in the macrocells Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable. The circuit of a PE Macrocell is shown in Figure 19. There is only one product term from the GPLD’s AND ARRAY as input to the macrocell. Users can select the polarity of the output and configure the macrocell to operate as: J Registered Output Select output from D flip flop J Combinatorial Output Select output from OR gate J GPLD Input Use Port E pin as dedicated input J GPLD Output Use Port E pin as dedicated output J GPLD I/O Use Port E pin as bidirectional pin J Macrocell Feedback Register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. In case of "Buried Feedback", where the output of the macrocell is not connected to Port E pin, Port E can be configured to perform other user defined I/O functions. If pins PE0 and PE1 are used as bus control signal inputs (ALE, PSEN/BHE), the corresponding macrocells' feedbacks are disabled. The bus control signals are connected to the ZPLD Input Bus. The two global product terms assigned for asynchronous clear (PE.RE) and preset (PE.PR) are for proper PE Macrocell initialization. The macrocell flip-flop can also be cleared during reset by MACRO-RST as an option. The clock source is always the input clock CLKIN. The PSD4XX Architecture (cont.)

9.1.2.6 The ZPLD Power Management

The ZPLD implements a Zero Power Mode, which provides considerable power savings for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the Power Management Mode Register 0 (PMMR0) has to be turned off. If none of the inputs to the ZPLD are switching for a time period of 70ns, the ZPLD puts itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume normal operation as soon as one or more of the inputs change state. Two other features of the ZPLD provide additional power savings: 1. Clock Disable: Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC power consumption. 2. Product Term Disable: Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically for further power savings. The ZPLD power configuration is described in the Power Management Unit section. The PSD4XX Architecture (cont.)

Figure 18. PE Macrocell Block DiagramThe PSD4XX

Figure 19. PE Macrocell

Table 5. Typical Microcontroller Bus Types

9.2 Bus Interface

Interface is able to interface.

9.2.1 Bus Interface Configuration

microcontrollers are shown in following sections.

Table 6. Alternate Pin Functions

9.2.2 PSD4XX Interface To a Multiplexed Bus

Figure 21. The ADIO Port is in tri-state mode if none of the PSD4XX internal devices are

9.2.3 PSD4XX Interface To Non-Multiplexed Bus

accessed by the microcontroller.

Figure 20. Multiplexed Bus, 8 or 16-Bit Data Bus

Figure 21. ADIO Port, 16-Bit Multiplexed Bus Interface

Figure 22. Non-Multiplexed, 8 or 16-Bit Data

Table 7. 8-Bit Data Bus Table 8. 16-Bit Data Bus With BHE Table 9. 16-Bit Data Bus With WRH and WRL Table 10. 16-Bit Data Bus With SIZ0, A0 Table 11. 16-Bit Data Bus With UDS, LDS

9.2.4 Data Byte Enable

locations with A0 equal to “1”.

9.2.5 Optional Features

The PSD4XX provides two optional features to add flexibility to the Bus Interface: 1. Address In Port A can be configured as high order address (A16-A23) inputs to the ZPLD for EPROM or other decoding. Inputs are latched by ALE/AS if Multiplexed Bus is selected. Other Ports can be configured as address input ports for the ZPLD. These inputs should not be used for EPROM decoding and are not latched internally. 2. Address Out For multiplexed bus only. Latched address lines A0-A15 are available on Port A, B, C or D. Details on the optional features are described in the I/O Port section.

9.2.6 Bus Interface Examples

The next four figures show the PSD4XX interfacing with some popular microcontrollers. The examples show only the basic bus connections; some of the pin names on the PSD4XX parts change to reflect the actual pin functions. Figure 23 shows the interface to the 80C31. The 80C31 has a 16 bit address bus and an 8-bit data bus. The lower address byte is multiplexed with the data bus. The RD and WR signals are used for accessing the data memory (SRAM) and the PSEN signal is for reading program memory (EPROM). The ALE signal is active high and is used to latch the address internally. Port C provides latched address outputs A[7:0]. Ports A, B, D, and E (PE2-PE7) can be configured to perform other functions. The RSTOUT reset to the 80C31 is generated by the ZPLD from the RESET input. This configuration eliminates any reset race condition between the 80C31 and the PSD4XX. Figure 24 shows the 68HC11 interface, which is similar to the 80C31 except the PSD4XX generates internal RD and WR from the 68HC11’s E and R/W signals. In Figure 25, the Intel 80C196 microcontroller is interfaced to the PSD4XX. The 80C196 has a multiplexed 16-bit address and data bus. The BHE signal is used for data byte selection. Ports C and D are used as output ports for latched address A[15:0]. Pins PE6 and PE7 can be programmed as ZPLD outputs to provide the READY and BUSWIDTH control signals to the 80C196. Figure 26 shows Motorola’s MC68331 interfacing to the PSD4XX. The MC68331 has a 16-bit data bus and a 24-bit address bus. D15 – D8 from the MC68331 are connected to Port D, and D7 – D0 are connected to Port C. PSD4XX Family PSD4XX Family The PSD4XX Architecture (cont.)

Figure 23. Interfacing PSD4XX With 80C31

Figure 24. Interfacing PSD4XX With 68HC11

Figure 25. Interfacing PSD4XX With 80C196

Figure 26. Interfacing PSD4XX With Motorola 68331

9.3 I/O Ports

There are 5 programmable 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These ports all have multiple operating modes, depending on the configuration. Some of the basic functions are providing input/output for the ZPLD, or can be used for standard I/O. Each port pin is individually configurable, thus enabling a single 8-bit port to perform multiple functions. The I/O ports occupy 256 bytes of memory space as defined by “CSIOP”. Refer to the System Configuration section for I/O register address offset. To set up the port configuration the user is required to: 1. Define I/O Port Chip Select (CSIOP) in the ABEL file. 2. Initialize certain port configuration registers in the user’s program and/or 3. Specify the configuration in the PSD4XX PSDsoft Software. 4. Unused input pins should be tied to V CC or GND. The following is a description of the operating modes of the I/O ports. The functions of the port registers are described in later sections.

9.3.1 Standard MCU I/O

The Standard MCU I/O Mode provides additional I/O capability to the microcontroller. In this mode, the ports can perform standard I/O functions such as sensing or controlling various external I/O devices. Operation options of this mode are as follows: J Configuration 1. Declare pins or signals which are used as I/O in the ABEL file. 2. Set the bit or bits in the Control Register to "1". As Output Port – Write output data to Data Out Register – Set Direction Register to output mode 4.As Input Port – Set Direction Register to input mode – Read input from Data In Register The port remains an output or input port as long as the Direction Register is not changed.

9.3.2 PLD I/O

The PLD I/O mode enables the port to be configured as an input to the ZPLD, or as an output from the GPLD macrocell. The output can be tri-stated with a control signal defined by a product term from the ZPLD. This mode is configured by the user in the PSD4XX PSDsoft Software, and is enabled upon power up. For a detailed description, see the section on the ZPLD. J Configuration 1. Declare pins or signals in the ABEL file (PSDsoft). 2. Write logic equations in the ABEL file. 3. PSD Compiler maps the PLD functions to the PSD. The PSD4XX Architecture (cont.)

9.3.3 Address Out

For microcontrollers with a multiplexed address/data bus, the I/O ports in Address-Out mode are able to provide latched address outputs (A0 – A15) to external devices. This mode of operation requires the user to: J Configuration 1. Declare the pins used as address line outputs in the ABEL file (PSDsoft). 2. Write “0” to the corresponding bit in the Control Register associated with each I/O port. 3. Set the Direction Register to Output Mode.

9.3.4 Address In

There are two Address In modes: 1. For Port A - as other address line (A2-A7 and A16-A23) inputs to the DPLD. Additional address inputs included in the EPROM decoding must come from Port A. The address inputs are latched internally by ALE/AS if Multiplexed Bus is specified in PSDsoft. 2. For Ports C and D – as address inputs to the ZPLD for general decoding, should not be used in EPROM decoding. J Configuration 1. Declare pins or signals used as Address In in the ABEL file (PSDsoft). 3. Include latched address in logic equations.

9.3.5 Data Port

In this mode, the port is acting as a data bus port for a microcontroller which has a non-multiplexed address/data bus. The Data Port is connected to the data bus of the microcontroller and the ADIO port is connected to the address bus. J Configuration Select the non-multiplexed bus option in PSD configuration (PSDsoft).

9.3.6 Alternate Function In

This mode is per-pin configurable and enables the user to define pin PE7 of Port E as Automatic Power Down (APD) CLK input. J Configuration 1. Select input functions in PSD configuration. 2. PSD Compiler assigns pins for the selected options. The PSD4XX Architecture (cont.)

*PSD4XXA2 and ZPSD4XXA2 Only.

9.3.7 Peripheral I/O

I/O is in a DMA based design.

1. Declare the pins used as pheripheral I/O in the ABEL file.
2. Write logic equations for PSEL0 and PSEL1.
3. Write a “1” to the PIO bit in the VM Register to activate the Peripheral I/O operation.

See the section on Peripheral I/O for a detailed description.

9.3.8 Open Drain Outputs

Register changes the pin to open drain output. Table 12. Operating Modes of the I/O Ports

Table 13. Port Configuration Registers (PCR) Table 14. Port Data Registers (PDR)

9.3.9 Port Registers

and the registers and the ports to which they belong. Registers can be accessed by the microcontroller during normal read/write bus cycles. The I/O address offset of the registers are listed in the System Configuration section.

9.3.9.1 Control Register

This register is used in both Standard MCU I/O Mode and Address Out modes. For setting a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register. Writing a “0” to the register is required for the Address Out mode. The register has a default value of “0” after reset.

9.3.9.2 Direction Register

This register is used to control the direction of data flow in the I/O Ports. Writing a “1” to the corresponding bit in the register configures the port to be an output port, and a “0” forces the port to be an input port. The I/O configuration of the port pins can be determined by reading the Direction Register. After reset, the pins are in input mode.

9.3.9.3 Open Drain

This register determines whether the output pin driver of Ports C or D is a CMOS driver or an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects an Open Drain driver.

9.3.9.4 PLD – I/O Register

This is a read only status register. Reading a "1" indicates the corresponding pin is configured as a PLD pin. A "0" indicates the pin is an I/O pin.

9.3.9.5 Data In Register

This register is used in the Standard MCU I/O Mode configuration to read the input pins.

9.3.9.6 Data Out Register

This register holds the output data in the Standard MCU I/O Mode. The contents of the register can also be read.

9.3.9.7 Macrocell Out Register

This register enables the user to read the outputs of the GPLD macrocell (PA, PB, and PE macrocells).

9.3.9.8 I/O Register Address Offset

The I/O Register can be accessed by the microcontroller during normal read/write bus cycles. The address of a register is defined as: CSIOP + register address offset The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte space. The register address offset lies within this 256 byte space. Tables 16 and 16a are the address offset of the registers. The PSD4XX Architecture (cont.)

Table 16. Register Address Offset

9.3.10 Port A – Functionality and Structure

Port A is the most flexible of all the I/O ports. It can be configured to perform one or more of the following functions: J Standard MCU I/O Mode J PLD I/O J Address Out – latched address lines A[0-7] are assigned to pins PA[0-7]. J Address In – input port for other address lines, inputs can be latched by ALE. J Peripheral I/O Figure 27 shows the structure of a Port A pin. If the pin is configured as an output port, the multiplexer selects one of its three inputs as output. If the pin is configured as an input, the input connects to : 1. Data In Register as input in Standard MCU I/O Mode or 2. PA Macrocell as PLD input or 3. PA Macrocell through a latch latched by ALE, as Address In input.

9.3.11 Port B – Functionality and Structure

Port B is similar to Port A in structure. It can be configured to perform one or more of the following functions: J Standard MCU I/O Mode J PLD I/O J Address Out – address lines A[0-7] for 8-bit multiplexed bus or address lines A[8-15] for 16-bit multiplexed bus are assigned to pins PB[0-7]. Figure 28 shows the structure of a Port B pin. If the pin is configured as an output port, the multiplexer selects one of its three inputs as output. If the pin is configured as input, the input connects to : J Data In Register as input in Standard MCU I/O Mode or J PB Macrocell as PLD input The PSD4XX Architecture (cont.)

Figure 27. Port A Pin Structure

Figure 28. Port B Pin Structure

9.3.12 Port C and Port D – Functionality and Structure

Ports C and D are identical in function and structure and each can be configured to perform one or more of the following operating modes: J Standard MCU I/O Mode J PLD Input – direct input to ZPLD (PSD4XXA2 and ZPSD4XXA2 Only) J Address Out – latched address outputs – Port C: A[0-7] are assigned to pins PC[0-7] – Port D: A[0-7] for 8-bit multiplexed bus or A[8-15] for 16-bit multiplexed bus are assigned to pins PD0-7] J Data Port – Port C: D[0-7] for 8-bit non-multiplexed bus – Port D: D[8-15] for 16-bit non-multiplexed bus J Open Drain – select CMOS or Open Drain driver Figures 29 and 30 show the structure of a Port C or D pin. If the pin is configured as output port, the multiplexer selects one of the two inputs as output. If the pin is configured as input, the input connects to : J Data In Register as input in the Standard MCU I/O Mode or J ZPLD input (PSD4XXA2 and ZPSD4XXA2 Only)

9.3.13 Port E – Functionality and Structure

Port E can be configured to perform one or more of the following functions: J Standard MCU I/O Mode J PLD I/O (PSD4XXA2 and ZPSD4XXA2 Only) J Address Out – latched address lines A[0-7] are assigned to pins PE[0-7] J Alternate Function In – in this mode, the inputs to Port E pins are: – PE0 BHE or PSEN or WRH or UDS or SIZ0 – PE1 – ALE – PE7 APD CLK :clock input for Automatic Power Down Counter Figure 31 shows the structure of a Port E pin. The Control Logic block selects one of four sources through the multiplexer for pin output. If the pin is configured as input, the input goes to: J Data In Register as input in Standard MCU I/O Mode or J PE Macrocell as PLD input (PSD4XXA2 and ZPSD4XXA2 Only) or J Alternate Function In PSD4XX Family PSD4XX Family The PSD4XX Architecture (cont.)

Figure 29. Port C Pin Structure *Data Bus D [0 –7] is not connected to GPLD–Input. **GPLD–Input is available on A2 versions only.

Figure 30. Port D Pin Structure *Data Bus D [8–15] is not connected to GPLD–Input. **GPLD–Input is available on A2 versions only.

Figure 31. Port E Pin Structure *GPLD–Input is available on A2 versions only.

9.4 Memory Block

The PSD4XX provides EPROM memory for code storage and SRAM memory for scratch pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and are defined by the user in the PSDsoft Software. Figure 32 shows the organization of the Memory Block. The PSD4XX family uses Zero-power memory techniques that place memory into Standby Mode between MCU accesses. The memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to standby. This is done automatically and the designer has to do nothing special to benefit from this feature. Both the EPROM and SRAM have this feature.

9.4.1 EPROM

The PSD4XX provides three EPROM densities: 256Kbit, 512Kbit, or 1Mbit. The EPROM is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals (ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as 16K x 16, 32K x 16 or 64K x 16.

9.4.2 SRAM

The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled by chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode. This back-up mode is invoked when the V CC voltage drops under the Vstdby voltage by approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and cannot be lower than 2.7 volts.

9.4.3 Memory Select Map

The EPROM and SRAM chip select equations are defined in the ABEL file in terms of address and other DPLD inputs. The memory space for the EPROM chip select (ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB, or 32KB) it is selecting. The following rules govern how the internal PSD4XX memory selects/space are defined: J The EPROM blocks address space cannot overlap J SRAM, internal I/O and Peripheral I/O space cannot overlap J SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with priority given to SRAM or I/O. The portion of EPROM which is overlapped cannot be accessed. The Peripheral I/O space refers to memory space occupied by peripherals when Port A is configured in the Peripheral I/O Mode. The PSD4XX Architecture (cont.)

9.4.4 Memory Select Map For 8031 Application

code and data storage. The memory block's address space cannot overlap. show the memory configuration in the two modes. overlap EPROM space and has priority when PSEN is used. *= Reserved for future use, bits set to zero. Table 17. VM Register

Figure 32. Memory Block Diagram (128KB EPROM)

Figure 34. Port A In Peripheral I/O Mode

9.4.5 Peripheral I/O

decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode. determined by the RD/WR signals. microcontroller does not support DMA operations, such as tri-stating the address/data bus. receiving acknowledgement from the microcontroller.

Figure 35. PSD4XX Peripheral I/O Configuration

9.5 Power Management Unit

The PSD4XX provides many power saving options. By configuring the PMMRs (Power Management Mode Registers), the user can reduce power consumption. Table 18 shows the bit configuration of the PMMR0 and PMMR1. The microcontroller is able to control the power consumption by changing the PMMR bits at run time.

9.5.1 Standby Mode

There are two Standby Modes in the PSD4XX: J Power Down Mode J Sleep Mode

9.5.1.1 Power Down Mode

In this mode, the internal devices are shut down except for the I/O ports and the ZPLD. There are three ways the PSD4XX can enter into the Power Down Mode: by controlling the CSI input, by activating the Automatic Power Down (APD) Logic and the ZPLD, or when none of the inputs are changing and the Turbo bit is off. J The CSI The CSI input pin is an active low signal. When low, the signal selects and enables the PSD4XX. The PSD4XX enters into Power Down Mode immediately when the signal turns high. This signal can be controlled by the microcontrollers, external logic or it can be grounded. The CSI input turns off the internal bus buffers in Standby Mode. The address and control signals from the microcontroller are blocked from entering the ZPLD as inputs. J The APD Logic The APD unit enables the user to enter a power down mode independent of controlling the CSI input. This feature eliminates the need for external logic (decoders and latches) to power down the PSD. The APD unit concept is based on tracking the activity on the ALE pin. If the APD unit is enabled and ALE is not active, the 4-bit APD counter starts counting and will overflow after 15 clocks, generating a PD (Power Down) signal powering down the PSD. If sleep mode is enabled, then PD signal will also activate the sleep mode. Immediately after ALE starts pulsing the PSD will get out of the power down or sleep mode. The operation of APD is controlled by the PMMR (see Figure 36a). PMMR1 bit 0 selects the source of the APD counter clock. After reset the APD counter clock is connected to PE7 (APD CLK) on the PSD. In order to guarantee that the APD will not overflow there should be less than 15 APD clocks between two ALE pulses. If CLKIN frequency is adequate, then it can be connected to the APD and PE7 is used for other functions. The next step is to select the ALE power down polarity. Usually, MCUs entering power down will freeze their ALE at logic high or low. By programming bit 1 of PMMR0 the power down polarity can be defined for the APD. If the APD detects that the ALE is in the power down polarity for 15 APD counter clocks then the PSD will enter a power down mode. To enable the APD operation, bit 2 in the PMMR0 should be set high.

9.5.1.2 Sleep Mode

The Sleep Mode is activated if the SLEEP EN bit, the APD EN bit, and the ALE Polarity bit in the PMMR are set, and the APD Counter has overflowed after 15 clocks (see Figure 36). In Sleep Mode the PSD4XX consumes less power than the Power Down Mode. In this mode, the ZPLD still monitors the inputs and responds to them. As soon as the ALE starts pulsing, the PSD4XX exits the Sleep Mode. The PSD access time from Sleep Mode is specified by t LVDV1 . The ZPLD response time to an input transition is specified by tLVDV2 . The PSD4XX Architecture (cont.)

Figure 36. Power Management Unit

15 APD CLOCK

• SET ENABLE APD IN PMMR0 BIT 2
• SET PMMR0 BIT 0
• SET ENABLE APD IN PMMR0 BIT 2
• SET PMMR0 BIT 0 DISABLE CLOCKS ZPLD ACLK, ZPLD RCLK, TMR ZPLD DISABLE CLOCKS ZPLD ACLK, ZPLD RCLK, TMR ZPLD PSD IN POWER DOWN MODE PSD IN SLEEP MODE The PSD4XX Architecture (cont.)

0 X X Not Counting

1 X Pulsing Not Counting

111 Counting (Activates Standby

100 Counting (Activates Standby

Table 18. Power Management Mode Registers (PMMR0, PMMR1) Table 19. APD Counter Operation Bit 0* = Should be set to High (1) to operate the APD. Bit 10 = ALE Power Down (PD) Polarity Low. 1 = ALE Power Down (PD) Polarity High. Bit 20 = Automatic Power Down (APD) Disable. 1 = Automatic Power Down (APD) Enable. Bit 30 = EPROM/SRAM CMiser is OFF. 1 = EPROM/SRAM CMiser is ON. Bit 40 = ZPLD Turbo is ON. ZPLD is always ON. 1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing. Bit 50 = ZPLD Clock Input into the Array from the CLKIN pin input is connected. Every Clock change will Power Up the ZPLD when Turbo bit is OFF. 1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected. Bit 1 0 = Sleep Mode Disabled. Bit 2–70 = Reserved for future use, should be set to zero.

9.5.2 Other Power Saving Options

The PSD4XX provides additional power saving options. These options, except the SRAM Standby Mode, can be enabled/disabled by setting up the corresponding bit in the PMMR. J EPROM The EPROM power consumption in the PSD is controlled by bit 3 in the PMMR0 – EPROM CMiser. Upon reset the CMiser bit is OFF. This will cause the EPROM to be ON at all times as long as CSI is enabled (low). The reason this mode is provided is to reduce the access time of the EPROM by 10 ns relative to the low power condition when CMiser is ON. If CSI is disabled (high) the EPROM will be deselected and will enter standby mode (OFF) overriding the state of the CMiser. If CMiser is set (ON) then the EPROM will enter the standby mode when not selected. This condition can take place when CSI is high or when CSI is low and the EPROM is not accessed. For example, if the MCU is accessing the SRAM, the EPROM will be deselected and will be in low power mode. An additional advantage of the CMiser is achieved when the PSD is configured in the by 8 mode (8 bit data bus). In this case an additional power savings is achieved in the EPROM (and also in the SRAM) by turning off 1/2 of the array even when the EPROM is accessed (the array is divided internally into odd and even arrays). The power consumption for the different EPROM modes is given in the DC Characteristics table under I CC (DC) EPROM Adder. J SRAM Standby Mode The SRAM has a dedicated supply voltage VSTBY that can be used to connect a battery. When V CC becomes lower than VSTBY –0.6 then the PSD will automatically connect the VSTBY as a power source to the SRAM. The SRAM Standby Current (ISTBY ) is typically 0.5 µA. SRAM data retention voltage VDF is 2 V minimum. J Zero Power ZPLD ZPLD power/speed is controlled by the ZPLD_Turbo bit (bit 4) in the PMMR0. After reset the ZPLD is in Turbo mode and runs at full power and speed. By setting the bit to “1”, the Turbo mode is disabled and the ZPLD is consuming Zero Power current if the inputs are not switching for an extended time of 70 ns. The propagation delay time will be increased by 10ns after the Turbo bit is set to “1” (turned off) if the inputs change at a frequency of less than 15 MHz. The PSD4XX Architecture (cont.)

Table 20. I/O Pin Status During Power Down And Sleep Mode The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK). disabled if bits 5 – 7 PMMR0 are set and the APD has overflowed.

1. In Sleep Mode any input to the ZPLD will have a propagation delay of tLVDV2 .
2. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the

transition will have a propagation delay time of tLVDV3 .

Table 21. Register Address Offset devices relative to the CSIOP base address.

The following table is the address map offset of the I/O port registers. Table 22. I/O Register Address Offset

Data In This Register is used to read the inputs on the port pins. Control A “0” sets the corresponding port pin in Address Out Mode. A “1” sets the pin in MCU I/O Mode. Data Out Holds the output data in the MCU I/O Mode. This register is used to control the data flow in the I/O ports. Direction A “0” sets the corresponding pin as an input pin. A “1” sets the pin as an output pin. Open Drain A “0” sets the corresponding pin driver as a CMOS driver. A “1” sets the pin driver as an Open Drain Driver. Macrocell Out This register holds the outputs of the GPLD macrocells. Page Register A 4-bit register that supports paging.

1. Configures the PSD4XX SRAM to be accessed by “PSEN ” as

VM program space (8031 design).

1. Enables the Peripheral I/O Mode of Port A.

PMMR1 Mode and other power saving configurations. Table 23. Register Function

Table 24. Registers Reset Values Table 25. I/O Pin Status During Reset and Standby Mode

12.1 Reset Input

12.2 ZPLD and Memory During Reset

reset, but the data is not guaranteed.

12.3 Register Values During and After Reset

Table 24 summarizes the status of the volatile register values during and after reset. The default values of the volatile registers are “0” after reset.

12.4 ZPLD Macrocell Initialization

J The MACRO-RST (Reset) input, enabled and defined in PSDabel.

Symbol Parameter Condition Min Max Unit TSTG Storage Temperature CLDCC – 65 + 150 °C PLDCC – 65 + 125 °C Commercial 0 + 70 °COperating TemperatureIndustrial – 40 + 85 °C Voltage on any Pin With Respect to GND – 0.6 + 7 V V PP Programming Supply Voltage With Respect to GND – 0.6 + 14 V VCC Supply Voltage With Respect to GND – 0.6 + 7 V ESD Protection >2000 V 13.0 Specifications NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Type Temperature V CC VCC Tolerance Speed Grades Available Commercial 0° C to +70°C + 5 V ± 10% X X + 3 V ± 10% X X Industrial –40° C to +85°C + 5 V ± 10% X + 3 V ± 10% X Symbol Parameter Condition Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5.0 5.5 V VCC Supply Voltage ZPSD4XXV Versions 2.7 3.0 5.5 VOnly, All Speeds

13.2 Operating Range

13.3 Recommended Operating Conditions

13.1 Absolute Maximum Ratings

(cont.)

13.4 AC/DC Parameters

The following tables describe the AD/DC parameters of the PSD4XX family: J AC Timing Specification

• ZPLD Timing – Combinatorial Delays – Synchronous Clock Mode – Asynchronous Clock Mode
• Microcontroller Timing – Read Timing – Write Timing – Peripheral Mode Timing – Power Down and Reset Timing Following are some issues concerning the parameters presented: J In the DC specification the Supply Current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD4XX is in each mode. Also the supply power is considerably different if the ZPLD_TURBO bit is "OFF" and EPROM_CMISER is "ON". J The AC power component gives the ZPLD, EPROM, and SRAM mA/MHz specification. Figure 38 shows the ZPLD mA/MHz as a function of the number of Product Terms (PT) used. J In the ZPLD timing parameters add the required delay when ZPLD_TURBO is "OFF". J In the MCU timing specification add the required time delay when EPROM_CMISER is "ON". Figure 38a. Typical ICC /Frequency Consumption (PSD4XXA1 and ZPSD4XXA1 Versions) 100 01 0 1 5 5 20 25 PT100% PT25% COMPOSITE FREQUENCY AT PLD INPUTS (MHz) ICC – (mA) TURBO ON TURBO ONTURBO OFF TURBO OFF VCC = 5 V

Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % EPROM Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Sleep = 90% Number of product terms used (from fitter report) = 29 PT % of total product terms = 29/118 = 24.6% Turbo = off CMiser = on 8-bit bus mode Calculation (typical numbers used) ICC total = Isleep x %sleep + %normal x (ICC (ac) + ICC (dc)) = Isleep x %sleep + %normal x (%EPROM x 0.8 mA/MHz x Freq ALE + %SRAM x 1.4 mA/MHz x Freq ALE + %PLD x 2.5 mA/MHz x Freq PLD + #PT x 400 µA/PT) = 10 µA x 0.90 + 0.1 x (0.8 x 0.8 mA/MHz x 4 MHz = 0.9 µA + 0.1 x 34 = 0.9 µA + 3.4 mA = 3.4 mA Notes:Standby current consumption is handled similarly to Sleep Mode shown above. Calculation assumes I OUT = 0 mA. 13.5 Example of ZPSD4XX Typical Power Calculation at VCC = 5.0 VSpecifications (cont.)

Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VIH High Level Input Voltage 4.5 V < V CC < 5.5 V 2 V CC + 0.5 V VIL Low Level Input Voltage 4.5 V < V CC < 5.5 V –0.5 0.8 V VIH1 Reset High Level Input Voltage (Note 1) 0.8 V CC VCC + 0.5 V VIL1 Reset Low Level Input Voltage (Note 1) –0.5 0.2 V CC –0.1 V VHYS Reset Pin Hysteresis 0.3 V VOL Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V IOL = 8 mA, VCC = 4.5 V 0.15 0.45 V VOH Output High Voltage IOH = –20 µA, VCC = 4.5 V 4.4 4.49 V IOH = –2 mA, VCC = 4.5 V 2.4 3.9 V VSBY SRAM Standby Voltage 2.7 V CC V ISBY SRAM Standby Current V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTDBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB1 Standby Supply Power Down Mode CSI >V CC –0.3 V (Note 2) 50 100 µA (PSD4XX) Current Sleep Mode CSI >V CC –0.3 V (Note 3) 30 40 µA ISB2 Standby Supply Power Down Mode CSI >V CC –0.3 V (Note 2) 25 50 µA (ZPSD4XX) Current Sleep Mode CSI >V CC –0.3 V (Note 3) 10 20 µA ILI Input Leakage Current V SS < VIN < VCC –1 ±0.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ± 5 10 µA ZPLD_TURBO = OFF, See I SB1 f = 0 MHz (Note 4) and I SB2 ICC (DC) Operating ZPLD Adder ZPLD_TURBO = ON, (Note 4a) Supply Current f = 0 MHz 400 700 µA/PT EPROM Adder f = 0 MHz 0 mA SRAM Adder f = 0 MHz 0 mA ZPLD AC Adder See Fig. 38 4 mA/MHz CMiser = ON and EPROM AC Adder (8-bit bus mode) 0.8 2 mA/MHz All other cases 1.8 4 mA/MHzICC (AC) CMiser = ON and(Note 4a) (8-bit bus mode) 1.4 2.7 mA/MHz SRAM AC Adder CMiser = ON and 2 4 mA/MHz(16-bit bus mode) CMiser = OFF 3.8 7.5 mA/MHz

13.6 DC Characteristics (5 V ± 10% Versions)

1. CSI is high or internal Power Down mode is active. 3. Sleep mode bit is set and internal Power Down is active. 4. See ZPLD I CC /Frequency Power Consumption graph for details. 4a. IOUT = 0 mA.

-70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit I/O Input or Feedback totPD Combinatorial Output Port B, E 25 30 34 Add 10 ns tRPD Registered Input to (Note 1) 27 32 36 Add 10 nsCombinatorial Output tEA Input to Output Enable Any Input 25 28 32 Add 10 ns tER Input to Output Disable Any Input 25 28 32 Add 10 ns tARP Register Clear or Preset Any Input 27 30 34 Add 10 nsDelay tARPW Register Clear or Preset Any Input 20 25 29 nsPulse Width tARD Array Delay 16 18 22 ns Combinatorial Delays (5 V ± 10% Versions) NOTE: 1. Port A and latched address from ADIO (A0, A1, A8 – A15). If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. The -90 speed is available only on Industrial Temperature Range product.

13.7 AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions)

-70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tS + tCO ) 30.30 27.03 23.81 MHz Maximum Frequency fMAX Internal Feedback (fCNT ) 1/(tS +tCO –10) 43.48 37.04 31.25 MHz Maximum Frequency Pipelined Data 1/(tCH + tCL ) 50.00 41.67 33.33 MHz tS Input Setup Time Any Input 15 17 20 Add 10 ns tH Input Hold Time Any Input 0 0 0 0 ns tCH Clock High Time Clock Input 10 12 15 0 ns tCL Clock Low Time Clock Input 10 12 15 0 ns tCO Clock to Output Delay Clock Input 18 20 22 0 ns tARD Array Delay for Product Term Expansion Any Macrocell 16 18 22 0 ns tMIN Minimum Clock Period tCH + tCL 20 24 29 0 ns Synchronous Clock Mode (5 V ± 10%) If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. The -90 speed is available only on Industrial Temperature Range product.

-70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tSA + tCOA ) 26.32 25.00 20.41 MHz Maximum Frequency fMAXA Internal Feedback 1/(tSA +tCO A–10) 35.71 33.33 25.64 MHz (fCNTA ) (Note 1) Maximum Frequency Pipelined Data 1/(tCH + tCL ) 41.67 41.67 33.33 MHz tSA Input Setup Time Any Input 8 8 12 Add 10 ns tHA Input Hold Time Any Input 8 8 12 0 ns tCHA Clock High Time Any Input 12 12 15 0 ns tCLA Clock Low Time Any Input 12 12 15 0 ns tCOA Clock to Output Any Input 30 32 37 Add 10 nsDelay to Port B tARD Array Delay for Product Term Any Macrocell 16 18 22 0 ns Expansion t MINA Minimum Clock Period 1/fCNT 28 30 43 0 ns Asynchronous Clock Mode (5 V ± 10% , Note 1) AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions) NOTE: 1. Only Port B has asynchronous outputs. Clock into Macrocell Flip Flop is generated by a product term. If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. The -90 speed is available only on Industrial Temperature Range product.

Explanation of AC Symbols for Non ZPLD Timing. Example: tAVLX Time from Address Valid to ALE Invalid. A – Address L – Logic Level Low or ALE T – R/W C – Power Down N – Reset t – Time D – Input Data P – Port Signal V – Valid E –E Q – Output Data X – No Longer a Valid Logic Level H – Logic Level High R – WR, UDS, LDS, DS, IORD, PSEN Z – Float I – Interrupt S – Chip Select -70 -90* -15 EPROM_CMiser Symbol Parameter Conditions Min Max Min Max Min Max ON Unit tLVLX ALE or AS Pulse Width 18 20 28 0 ns tAVLX Address Setup Time (Note 3) 5 6 10 0 ns tLXAX Address Hold Time (Note 3) 7 8 11 0 ns tAVQV Address Valid to Data Valid (Note 3) 70 90 150 Add 10 ns tSLQV CS Valid to Data Valid 80 100 150 Add 10 ns RD to Data Valid 8/16-Bit Bus (Note 1) 20 32 40 0 ns tRLQV RD to Data Valid 8-Bit Bus, 8031 Separate (Note 2) 32 38 45 0 ns Mode t RHQX RD Data Hold Time (Note 1) 0 0 0 0 ns tRLRH RD Pulse Width (Note 1) 30 32 38 0 ns tRHQZ RD to Data High-Z (Note 1) 22 25 33 0 ns tEHEL E Pulse Width 30 32 38 0 ns tTHEH R/W Setup Time to Enable 81 0 1 8 0n s tELTL R/W Hold Time After Enable 000 0 n s In 16-Bit Data Bus 20 30 38 0 nstAVPV Address Input Valid to Mode (Note 9) Address Output Delay In 8-Bit Data Bus 22 32 48 0 nsMode (Note 9) Read Timing (5 V ± 10% Versions) NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals. 2. RD and PSEN have the same timing for 8031 mode. 3. Any input used to select an internal PSD4XX function. 4. In multiplexed mode latched address generated from ADIO delay to address output on any Port. *The -90 speed is available only on Industrial Temperature Range product.

13.8 Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions)

-70 -90* -15 EPROM_CMiser Symbol Parameter Conditions Min Max Min Max Min Max ON Unit tLVLX ALE or AS Pulse Width 18 20 28 ns tAVLX Address Setup Time (Note 1) 5 6 10 ns tLXAX Address Hold Time (Note 1) 7 8 11 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 18 20 30 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 22 25 35 ns tDVWH WR Data Setup Time (Note 3) 12 15 22 ns tWHDX WR Data Hold Time (Note 3) 5 5 5 ns tWLWH WR Pulse Width (Note 3) 18 20 28 ns tWHAX Trailing Edge of WR to Address Invalid (Note 3) 0 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid (Note 3) 25 30 38 ns In 16-Bit Data Bus 20 30 38 ns Address Input Valid toMode (Note 2) tAVPV Address Output Delay In 8-Bit Data Bus 22 32 48 nsMode (Note 2) Write Timing (5 V ± 10%) Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions) NOTES: 1. Any input used to select an internal PSD4XX function. 2. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals. *The -90 speed is available only on Industrial Temperature Range product.

-70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit tAVQV (PA) Address Valid to Data Valid (Note 3) 45 55 62 Add 10 ns tSLQV (PA) CS Valid to Data Valid 55 55 62 Add 10 ns RD to Data Valid (Notes 1 and 4) 22 26 45 0 nstRLQV (PA) RD to Data Valid

8031 Mode 32 38 45 0 ns

tDVQV (PA) Data In to Data Out Valid 22 22 26 0 ns tQXRH (PA) RD Data Hold Time (Note 1) 0 0 0 0 ns tRLRH (PA) RD Pulse Width (Note 1) 25 30 38 0 ns tRHQZ (PA) RD to Data High-Z (Note 1) 20 25 33 0 ns Port A Peripheral Data Mode Read Timing (5 V ± 10%) -70 -90 -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF Unit tWLQV (PA) WR to Data Propagation Delay (Note 2) 25 27 35 0 ns tDVQV (PA) Data to Port A Data Propagation Delay (Note 5) 22 22 26 0 ns tWHQZ (PA) WR Invalid to Port A Tri-state (Note 2) 20 25 33 ns Port A Peripheral Data Mode Write Timing (5 V ± 10%) NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals. 2. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals. 3. Any input used to select Port A Data Peripheral Mode. 4. Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A. If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. **The -90 speed is available only on Industrial Temperature Range product. Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions)

Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions) -70 -90* -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF Unit tLVDV ALE Access Time from Power Down 100 120 150 Add 10 ns tLVDV1 ALE or CSI Access Time from Sleep 120 150 200 0 ns tLVDV2 ZPLD Propagation Delay in Sleep Mode 600 600 600 0 ns tLVDV3 ZPLD Recovery Time after Sleep Mode 250 250 250 0 ns tCHCL APD Clock High Time Using PE7 10 12 15 0 ns tCLCH APD Clock Low Time Using PE7 10 12 15 0 ns fMAX APD Maximum Frequency Using PE7 35.00 30.00 22.00 0 MHz t1 RESET Active Low Time 150 200 300 0 ns RESET High to Operational Device 150 200 300 0 ns Power Down and Reset Timing (5 V ± 10%) *The -90 speed is available only on Industrial Temperature Range product.

Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 2.7 3 5.5 V VIH High Level Input Voltage 2.7 V < V CC < 5.5 V .7 V CC VCC +.5 V VIL Low Level Input Voltage 2.7 V < V CC < 5.5 V –0.5 .3 V CC V VIH1 Reset High Level Input Voltage (Note 1) .8 V CC VCC +.5 V VIL1 Reset Low Level Input Voltage (Note 1) –.5 .2 V CC –.1 V VHYS Reset Pin Hysteresis 0.3 V VOL Output Low Voltage IOL = 20 µA, VCC = 2.7 V 0.01 0.1 V IOL = 4 mA, VCC = 2.7 V 0.15 0.45 V VOH Output High Voltage IOH = –20 µA, VCC = 2.7 V 2.9 2.99 V IOH = –1 mA, VCC = 2.7 V 2.4 2.6 V VSBY SRAM Standby Voltage 2.7 V CC V ISBY SRAM Standby Current V CC = 0 V 0.5 1 µA IIDLE Idle Current (VSTBY Pin) V CC > VSBY –0.1 0.1 µA VDF SRAM Data Retention Voltage Only on V STBY 2V ISB Standby Supply Power Down Mode CSI >V CC –.3 V (Note 2) 5 15 µA Current Sleep Mode CSI >V CC –.3 V (Note 3) 1 5 µA ILI Input Leakage Current V SS < VIN < VCC –1 ±.1 1 µA ILO Output Leakage Current 0.45 < V IN < VCC –10 ± 5 10 µA ZPLD_TURBO = OFF, See ISB µA ICC (DC) Operating f = 0 MHz (Note 4) (Note 5) Supply Current ZPLD Only ZPLD_TURBO = ON, f = 0 MHz 200 400 µA/PT ZPLD AC Base (Note 4) See 2.0 mA/MHzFig 38c CMiser = ON EPROM AC Adder (8-Bit Bus Mode) 0.4 1.0 mA/MHz I CC (AC) All Other Cases 0.9 1.7 mA/MHz (Note 5) CMiser = ON and 0.7 1.3 mA/MHz8-Bit Bus Mode SRAM AC Adder CMiser = ON and 1 2 mA/MHz16-Bit Bus MoDe CMiser = OFF 1.9 3.8 mA/MHz

13.9 DC Characteristics (ZPSD4XXV Versions)

(3.0 V ± 10% Versions) 2. CSI deselected or internal PD is active. 3. Sleep mode bit is set and internal PD is active. 4. See ZPLD ICC/Frequency Power Consumption graph for details. 5. I OUT = 0 mA.

-20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF * Unit I/O Input or Feedback totPD Combinatorial Output Port B, E 55 80 Add 20 ns tRPD Registered Input to (Note 1) 55 85 Add 20 nsCombinatorial Output tEA Input to Output Enable Any Input 50 80 Add 20 ns tER Input to Output Disable Any Input 50 80 Add 20 ns tARP Register Clear or Preset Delay Any Input 55 80 Add 20 ns tARPW Register Clear or Preset Any Input 30 60 nsPulse Width tARD Array Delay 33 35 ns Combinatorial Delays (3.0 V ± 10%)

13.10 AC/DC Parameters – ZPLD Timing Parameters (ZPSD4XXV Versions)

(3.0 V ± 10%) NOTE: 1. Port A and latched address from ADIO (A0, A1, A8 – A15). -20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tS + tCO ) 28.57 11.11 MHz Maximum Frequency fMAX Internal Feedback (fCNT ) 1/(tS +tCO –10) 17.24 12.50 MHz Maximum Frequency Pipelined Data 1/(tCH + tCL ) 31.25 18.52 MHz tS Input Setup Time Any Input 45 60 Add 20 ns tH Input Hold Time Any Input 0 0 0 ns tCH Clock High Time Clock Input 16 27 0 ns tCL Clock Low Time Clock Input 16 27 0 ns tCO Clock to Output Delay Clock Input 30 33 0 ns tARD Array Delay for Product Term Expansion Any Macrocell 24 35 0 ns tMIN Minimum Clock Period t CH + tCL 30 30 0 ns Synchronous Clock Mode (3.0 V ± 10%) *NOTE: If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.

-20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tSA + tCOA ) 14.49 11.11 MHz Maximum Frequency 1/(t SA +tCO A –10) 16.95 12.50 MHzfMAXA Internal Feedback (fCNTA ) (Note 1) Maximum Frequency Pipelined Data 1/(tCH + tCL ) 31.25 18.52 MHz tSA Input Setup Time Any Input 13 30 Add 20 ns tHA Input Hold Time Any Input 13 30 0 ns tCHA Clock High Time Any Input 25 27 0 ns tCLA Clock Low Time Any Input 16 27 0 ns tCOA Clock to Output Delay Any Input to Port B 56 60 Add 20 ns tARD Array Delay for Product Term Expansion Any Macrocell 33 35 0 ns tMINA Minimum Clock Period 1/f CNT 59 80 0 ns Asynchronous Clock Mode (3.0 V ± 10%, Note 1) AC/DC Parameters – ZPLD Timing Parameters (ZPSD4XXV Versions) (3.0 V ± 10%) NOTE: 1. Only Port B has asynchronous outputs. Clock into macrocell Flip Flop is generated by a product term. *If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.

-20 -25 EPROM_CMiser Symbol Parameter Conditions Min Max Min Max ON Unit tLVLX ALE or AS Pulse Width 30 30 0 ns tAVLX Address Setup Time (Note 3) 12 15 0 ns tLXAX Address Hold Time (Note 3) 12 17 0 ns tAVQV Address Valid to Data Valid (Note 3) 200 250 Add 20 ns tSLQV CS Valid to Data Valid 200 275 Add 20 ns RD to Data Valid 8/16-Bit Bus (Note 1) 50 80 0 ns tRLQV RD to Data Valid 8-Bit Bus,

8031 Separate Mode (Note 2) 57 90 0 ns

tRHQX RD Data Hold Time (Note 1) 0 0 0 ns tRLRH RD Pulse Width (Note 1) 40 70 0 ns tRHQZ RD to Data High-Z (Note 1) 45 45 0 ns tEHEL E Pulse Width 40 70 0 ns tTHEH R/W Setup Time to Enable 20 15 0 ns tELTL R/W Hold Time After Enable 0 0 0 ns In 16-Bit Data Bus Address Input Valid to Mode (Note 4) 40 60 0 ns tAVPV Address Output Delay In 8-Bit Data Bus 50 60 0 nsMode (Note 4) Read Timing (3.0 V ± 10%) Explanation of AC Symbols for Non ZPLD Timing. Example: tAVLX Time from Address Valid to ALE Invalid. A – Address L – Logic Level Low or ALE T – R/W C – Power Down N – Reset t – Time D – Input Data P – Port Signal V – Valid E –E Q – Output Data X – No Longer a Valid Logic Level H – Logic Level High R – WR, UDS, LDS, DS, IORD, PSEN Z – Float I – Interrupt S – Chip Select

13.11 Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions)

(3.0 V ± 10%) NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals. 2. RD and PSEN have the same timing for 8031 mode. 3. Any input used to select an internal PSD4XX function. 4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

-20 -25 EPROM_CMiser Symbol Parameter Conditions Min Max Min Max ON Unit tLVLX ALE or AS Pulse Width 30 30 ns tAVLX Address Setup Time (Note 1) 12 15 ns tLXAX Address Hold Time (Note 1) 12 17 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 35 50 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 40 60 ns tDVWH WR Data Setup Time (Note 3) 25 35 ns tWHDX WR Data Hold Time (Note 3) 5 10 ns tWLWH WR Pulse Width (Note 3) 30 30 ns tWHAX Trailing Edge of WR to Address Invalid (Note 3) 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid (Note 3) 50 60 ns In 16-Bit Data Bus 40 60 ns Address Input Valid to Mode (Note 2) tAVPV Address Output Delay In 8-Bit Data Bus 50 60 nsMode (Note 2) Write Timing (3.0 V ± 10%) Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions) (3.0 V ± 10%) NOTES: 1. Any input used to select an internal PSD4XX function. 2. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.

-20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF Unit tAVQV (PA) Address Valid to Data Valid (Note 3) 95 120 Add 20 ns tSLQV (PA) CS Valid to Data Valid 100 120 Add 20 ns tRLQV (PA) RD to Data Valid (Notes 1 and 4) 50 90 0 ns tDVQV (PA) Data In to Data Out Valid 35 50 0 ns tQXRH (PA) RD Data Hold Time (Note 1) 0 0 0 ns tRLRH (PA) RD Pulse Width (Note 1) 40 70 0 ns tRHQZ (PA) RD to Data High-Z (Note 1) 35 60 0 ns -20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF Unit tWLQV (PA) WR to Data Propagation Delay (Note 2) 60 60 0 ns tDVQV (PA) Data to Port A Data Propagation Delay (Note 5) 40 50 0 ns tWHQZ (PA) WR Invalid to Port A Tri-state (Note 2) 35 60 0 ns Port A Peripheral Data Mode Read Timing (3.0 V ± 10%) Port A Peripheral Data Mode Write Timing (3.0 V ± 10%) Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions) (3.0 V ± 10%) NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals. 2. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals. 3. Any input used to select Port A Data Peripheral Mode. 4. Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A.

-20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF Unit tLVDV ALE Access Time from Power Down 170 250 Add 20 ns tLVDV1 ALE or CSI Access Time from Sleep 200 250 0 ns tLVDV2 ZPLD Propagation Delay in Sleep Mode 600 900 0 ns tLVDV3 ZPLD Recovery Time after Sleep Mode 250 400 0 ns tCHCL APD Clock High Time Using PE7 16 27 0 ns tCLCH APD Clock Low Time Using PE7 16 27 0 ns fMAX APD Maximum Frequency Using PE7 20.00 18.52 0 MHz t1 RESET Active Low Time 300 400 0 ns t2 RESET High to Operational Device 300 400 0 ns Power Down and Reset Timing (3.0 V ± 10%) Microcontroller Interface – AC/DC Parameters (3.0 V ± 10%)

Figure 39. Read Timing

14.0 Timing Diagrams

Figure 40. Write Timing

Figure 43. Combinatorial Timing – ZPLD

Pin No. PLDCC/CLDCC Pin No. PLDCC/CLDCC Package Package

1 GND 35 GND

2 ADIO_7 36 PE2

3 ADIO_6 37 PE1

4 ADIO_5 38 PE0

5 ADIO_4 39 CSI

6 ADIO_3 40 RESET

7 ADIO_2 41 RD

8 ADIO_1 42 CLKIN

9 ADIO_0 43 PB7

10 PC7 44 PB6

11 PC6 45 PB5

12 PC5 46 PB4

13 PC4 47 PB3

14 PC3 48 PB2

15 PC2 49 PB1

16 PC1 50 PB0

17 PC0 51 GND

18 VCC 52 VCC

19 GND 53 PD7

20 PA7 54 PD6

21 PA6 55 PD5

22 PA5 56 PD4

23 PA4 57 PD3

24 PA3 58 PD2

25 PA2 59 PD1

26 PA1 60 PD0

27 PA0 61 ADIO_15

28 Vstdby 62 ADIO_14

29 WR 63 ADIO_13

30 PE7 64 ADIO_12

31 PE6 65 ADIO_11

32 PE5 66 ADIO_10

33 PE4 67 ADIO_9

34 PE3 68 ADIO_8

18.0 PSD4XX Pin Assignments

Pin No. TQFP Pin No. TQFP Package Package

1 PC7 41 PB7

2 PC6 42 PB6

3 PC5 43 PB5

4 PC4 44 PB4

5 PC3 45 PB3

6 PC2 46 PB2

7 PC1 47 PB1

8 PC0 48 PB0

10 V CC 59 GND

11 GND 51 V CC

12 GND 52 V CC

13 PA7 53 PD7

14 PA6 54 PD6

15 PA5 55 PD5

16 PA4 56 PD4

17 PA3 57 PD3

18 PA2 58 PD2

19 PA1 59 PD1

20 PA0 60 PD0

21 NC 61 NC

22 NC 62 ADIO_15

23 Vstdby 63 ADIO_14

24 WR 64 ADIO_13

25 PE7 65 ADIO_12

26 PE6 66 ADIO_11

27 PE5 67 ADIO_10

28 PE4 68 ADIO_9

29 PE3 69 ADIO_8

30 GND 70 GND

31 GND 71 GND

32 PE2 72 ADIO_7

33 PE1 73 ADIO_6

34 PE0 74 ADIO_5

35 CSI 75 ADIO_4

36 RESET 76 ADIO_3

37 RD 77 ADIO_2

38 CLKIN 78 ADIO_1

39 NC 79 ADIO_0

40 NC 80 NC

60 PD0

59 PD1

58 PD2

57 PD3

56 PD4

55 PD5

54 PD6

53 PD7

51 VCC

50 GND

49 GND

48 PB0

47 PB1

46 PB2

45 PB3

44 PB4

43 PB5

42 PB6

41 PB7

V CC VCC GND GND PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 N/C ADIO–0 ADIO–1 ADIO–2 ADIO–3 ADIO–4 ADIO–5 ADIO–6 ADIO–7 GND GND ADIO–8 ADIO–9 ADIO–10 ADIO–11 ADIO–12 ADIO–13 ADIO–14 ADIO–15 N/C N/C N/C VSTDBY WR PE7 PE6 PE5 PE4 PE3 GND GND PE2 PE1 PE0 CSI RESET RD CLKIN N/C N/C Figure 54. Drawing U2 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) (TOP VIEW)

Family: Plastic Leaded Chip Carrier Millimeters Inches Symbol Min Max Notes Min Max Notes A 4.19 4.57 0.165 0.180 A1 2.41 3.00 0.095 0.118 A2 3.71 3.91 0.146 0.154 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.196 0.262 0.0077 0.0083 D 25.02 25.27 0.985 0.995 D1 24.13 24.23 0.950 0.954 D2 22.61 23.62 0.890 0.930 D3 20.32 Reference 0.800 Reference E 25.02 25.27 0.985 0.995 E1 24.13 24.23 0.950 0.954 E2 22.61 23.62 0.890 0.930 E3 20.32 Reference 0.800 Reference e1 1.27 Reference 0.050 Reference N6 8 6 8 030195R6 Drawing J5 – 68-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) A1 A2 E1 E A D 68123 e1B C

Family: Ceramic Leaded Chip Carrier – CERQUAD Millimeters Inches Symbol Min Max Notes Min Max Notes A 3.94 4.57 0.155 0.180 A1 2.29 2.92 0.090 0.115 A2 3.05 3.68 0.120 0.145 B 0.43 0.53 0.017 0.021 B1 0.66 0.81 0.026 0.032 C 0.15 0.25 0.006 0.010 D 25.02 25.27 0.985 0.995 D1 23.93 24.28 0.942 0.956 D2 22.35 23.88 0.880 0.940 D3 20.32 Reference 0.800 Reference E 25.02 25.27 0.985 0.995 E1 23.93 24.28 0.942 0.956 E2 22.35 23.88 0.880 0.940 E3 20.32 Reference 0.800 Reference e1 1.27 Reference 0.050 Reference N6 8 6 8 030195R6 Drawing L5 – 68-Pin Pocketed Ceramic Leaded Chip Carrier (CLDCC) – CERQUAD (Package Type L) B A1 A E1 E C 123 D To reduce lead damage, lead tips reside in pockets on the bottom of the package. View A View A

Drawing U2 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) D E3 E1 E Index Mark Standoff: 0.05 mm Min. Load Coplanarity: 0.102 mm Max. L C Be 1 A2 AA1 α Family: Plastic Thin Quad Flatpack (TQFP) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0° 8° 0° 8° A – 1.60 – 0.063 A1 0.54 0.74 0.021 0.029 A2 1.15 1.55 0.045 0.061 B 0.30 Reference 0.012 Reference C 0.09 0.20 0.004 0.008 D 15.75 16.25 0.620 0.640 D1 13.90 14.10 0.547 0.555 D3 12.35 Reference 0.486 Reference E 15.75 16.25 0.620 0.640 E1 13.90 14.10 0.547 0.555 E3 12.35 Reference 0.486 Reference e1 0.65 Reference 0.026 Reference L 0.35 0.75 0.014 0.030 N8 0 8 0 030195R1

Part # MCU PLDs/Decoders I/O Memory Other PSD ZPSD ZPSDV Data Path Inputs Ports EPROM SRAM Four 16-Bit Timer/Counters Interface Product Terms (w/BB) WatchDog (16-Bit) Input MicroÛ Cells Inter. Contr. Output MicroÛ Cells Periph. Mode Outputs Security Page APDReg. PSD411A1 ZPSD411A1 ZPSD411A1V 8 PLUS1 37 113 8 16 X 40 256Kb 16Kb X X X PSD401A1 ZPSD401A1 ZPSD401A1V 16/8 PLUS1 37 113 8 16 X 40 256Kb 16Kb X X X ZPSD412A0 8 PLUS1 37 113 8 16 X 40 512Kb 16Kb X X X PSD412A1 ZPSD412A1 ZPSD412A1V 8 PLUS1 37 113 8 16 X 40 512Kb 16Kb X X X PSD402A1 ZPSD402A1 ZPSD402A1V 16/8 PLUS1 37 113 8 16 X 40 512Kb 16Kb X X X PSD413A1 ZPSD413A1 ZPSD413A1V 8 PLUS1 37 113 8 16 X 40 1024Kb 16Kb X X X PSD403A1 ZPSD403A1 ZPSD403A1V 16/8 PLUS1 37 113 8 16 X 40 1024Kb 16Kb X X X PSD411A2 ZPSD411A2 ZPSD411A2V 8 PLUS1 59 126 24 24 X 40 256Kb 16Kb X X X PSD401A2 ZPSD401A2 ZPSD401A2V 16/8 PLUS1 59 126 24 24 X 40 256Kb 16Kb X X X PSD412A2 ZPSD412A2 ZPSD412A2V 8 PLUS1 59 126 24 24 X 40 512Kb 16Kb X X X PSD402A2 ZPSD402A2 ZPSD402A2V 16/8 PLUS1 59 126 24 24 X 40 512Kb 16Kb X X X PSD413A2 ZPSD413A2 ZPSD413A2V 8 PLUS1 59 126 24 24 X 40 1024Kb 16Kb X X X PSD403A2 ZPSD403A2 ZPSD403A2V 16/8 PLUS1 59 126 24 24 X 40 1024Kb 16Kb X X X20.1 PSD4XX Family – Selector Guide 20.0 PSD4XX Product Ordering Information

(cont.) Temperature (Blank = Commercial, I = Industrial, M = Military) Package Type Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) Revision (Blank = No Revision) Supply Voltage (Blank = 5V, V = 3 Volt) Base Part Number - see Selector Guide PSD (ST Programmable System Device) Fam. Power Down Feature (Blank = Standard, Z = Zero Power Feature) Z PSD -A -20 J I 413A2 V

20.2 Part Number Construction

Part Number (ns) Package Type Range PSD401A1-C-70J 70 68 Pin PLDCC Comm’l PSD401A1-C-70L 70 68 Pin CLDCC Comm’l PSD401A1-C-70U 70 68 Pin TQFP Comm’l PSD401A1-C-90JI 90 68 Pin PLDCC Industrial PSD401A1-C-90UI 90 68 Pin TQFP Industrial PSD401A1-C-12J 120 68 Pin PLDCC Comm’l PSD401A1-C-15J 150 68 Pin PLDCC Comm’l PSD401A1-C-15L 150 68 Pin CLDCC Comm’l PSD401A1-C-15U 150 68 Pin TQFP Comm’l PSD401A2-C-70J 70 68 Pin PLDCC Comm’l PSD401A2-C-70L 70 68 Pin CLDCC Comm’l PSD401A2-C-70U 70 68 Pin TQFP Comm’l PSD401A2-C-90JI 90 68 Pin PLDCC Industrial PSD401A2-C-90UI 90 68 Pin TQFP Industrial PSD401A2-C-15J 150 68 Pin PLDCC Comm’l PSD401A2-C-15L 150 68 Pin CLDCC Comm’l PSD401A2-C-15U 150 68 Pin TQFP Comm’l

20.3 Ordering Information

Part Number (ns) Package Type Range PSD402A1-C-70J 70 68 Pin PLDCC Comm’l PSD402A1-C-70L 70 68 Pin CLDCC Comm’l PSD402A1-C-70U 70 68 Pin TQFP Comm’l PSD402A1-C-90JI 90 68 Pin PLDCC Industrial PSD402A1-C-90UI 90 68 Pin TQFP Industrial PSD402A1-C-15J 150 68 Pin PLDCC Comm’l PSD402A1-C-15L 150 68 Pin CLDCC Comm’l PSD402A1-C-15U 150 68 Pin TQFP Comm’l PSD402A2-C-70J 70 68 Pin PLDCC Comm’l PSD402A2-C-70L 70 68 Pin CLDCC Comm’l PSD402A2-C-70U 70 68 Pin TQFP Comm’l PSD402A2-C-90JI 90 68 Pin PLDCC Industrial PSD402A2-C-90UI 90 68 Pin TQFP Industrial PSD402A2-C-15J 150 68 Pin PLDCC Comm’l PSD402A2-C-15L 150 68 Pin CLDCC Comm’l PSD402A2-C-15U 150 68 Pin TQFP Comm’l PSD403A1-C-70J 70 68 Pin PLDCC Comm’l PSD403A1-C-70L 70 68 Pin CLDCC Comm’l PSD403A1-C-70U 70 68 Pin TQFP Comm’l PSD403A1-C-90JI 90 68 Pin PLDCC Industrial PSD403A1-C-90UI 90 68 Pin TQFP Industrial PSD403A1-C-15J 150 68 Pin PLDCC Comm’l PSD403A1-C-15L 150 68 Pin CLDCC Comm’l PSD403A1-C-15U 150 68 Pin TQFP Comm’l PSD403A2-C-70J 70 68 Pin PLDCC Comm’l PSD403A2-C-70L 70 68 Pin CLDCC Comm’l PSD403A2-C-70U 70 68 Pin TQFP Comm’l PSD403A2-C-90JI 90 68 Pin PLDCC Industrial PSD403A2-C-90UI 90 68 Pin TQFP Industrial PSD403A2-C-15J 150 68 Pin PLDCC Comm’l PSD403A2-C-15L 150 68 Pin CLDCC Comm’l PSD403A2-C-15U 150 68 Pin TQFP Comm’l PSD411A1-C-70J 70 68 Pin PLDCC Comm’l PSD411A1-C-70L 70 68 Pin CLDCC Comm’l PSD411A1-C-70U 70 68 Pin TQFP Comm’l PSD411A1-C-90JI 90 68 Pin PLDCC Industrial PSD411A1-C-90UI 90 68 Pin TQFP Industrial PSD411A1-C-15J 150 68 Pin PLDCC Comm’l PSD411A1-C-15L 150 68 Pin CLDCC Comm’l PSD411A1-C-15U 150 68 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range PSD411A2-C-70J 70 68 Pin PLDCC Comm’l PSD411A2-C-70L 70 68 Pin CLDCC Comm’l PSD411A2-C-70U 70 68 Pin TQFP Comm’l PSD411A2-C-90JI 90 68 Pin PLDCC Industrial PSD411A2-C-90UI 90 68 Pin TQFP Industrial PSD411A2-C-15J 150 68 Pin PLDCC Comm’l PSD411A2-C-15L 150 68 Pin CLDCC Comm’l PSD411A2-C-15U 150 68 Pin TQFP Comm’l PSD412A1-C-70J 70 68 Pin PLDCC Comm’l PSD412A1-C-70L 70 68 Pin CLDCC Comm’l PSD412A1-C-70U 70 68 Pin TQFP Comm’l PSD412A1-C-90JI 90 68 Pin PLDCC Industrial PSD412A1-C-90UI 90 68 Pin TQFP Industrial PSD412A1-C-15J 150 68 Pin PLDCC Comm’l PSD412A1-C-15L 150 68 Pin CLDCC Comm’l PSD412A1-C-15U 150 68 Pin TQFP Comm’l PSD412A2-C-70J 70 68 Pin PLDCC Comm’l PSD412A2-C-70L 70 68 Pin CLDCC Comm’l PSD412A2-C-70U 70 68 Pin TQFP Comm’l PSD412A2-C-90JI 90 68 Pin PLDCC Industrial PSD412A2-C-90UI 90 68 Pin TQFP Industrial PSD412A2-C-15J 150 68 Pin PLDCC Comm’l PSD412A2-C-15L 150 68 Pin CLDCC Comm’l PSD412A2-C-15U 150 68 Pin TQFP Comm’l PSD413A1-C-70J 70 68 Pin PLDCC Comm’l PSD413A1-C-70L 70 68 Pin CLDCC Comm’l PSD413A1-C-70U 70 68 Pin TQFP Comm’l PSD413A1-C-90JI 90 68 Pin PLDCC Industrial PSD413A1-C-90UI 90 68 Pin TQFP Industrial PSD413A1-C-15J 150 68 Pin PLDCC Comm’l PSD413A1-C-15L 150 68 Pin CLDCC Comm’l PSD413A1-C-15U 150 68 Pin TQFP Comm’l PSD413A2-C-70J 70 68 Pin PLDCC Comm’l PSD413A2-C-70L 70 68 Pin CLDCC Comm’l PSD413A2-C-70U 70 68 Pin TQFP Comm’l PSD413A2-C-90JI 90 68 Pin PLDCC Industrial PSD413A2-C-90UI 90 68 Pin TQFP Industrial PSD413A2-C-15J 150 68 Pin PLDCC Comm’l PSD413A2-C-15L 150 68 Pin CLDCC Comm’l PSD413A2-C-15U 150 68 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range ZPSD401A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD401A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD401A1-C-70U 70 80 Pin TQFP Comm’l ZPSD401A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD401A1-C-90UI 90 80 Pin TQFP Industrial ZPSD401A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD401A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD401A1-C-15U 150 80 Pin TQFP Comm’l ZPSD401A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD401A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD401A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD401A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD401A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD401A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD401A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD401A1V-C-25U 250 80 Pin TQFP Comm’l ZPSD401A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD401A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD401A2-C-70U 70 80 Pin TQFP Comm’l ZPSD401A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD401A2-C-90UI 90 80 Pin TQFP Industrial ZPSD401A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD401A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD401A2-C-15U 150 80 Pin TQFP Comm’l ZPSD401A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD401A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD401A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD401A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD401A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD401A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD401A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD401A2V-C-25U 250 80 Pin TQFP Comm’l ZPSD402A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD402A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD402A1-C-70U 70 80 Pin TQFP Comm’l ZPSD402A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD402A1-C-90UI 90 80 Pin TQFP Industrial ZPSD402A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD402A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD402A1-C-15U 150 80 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range ZPSD402A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD402A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD402A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD402A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD402A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD402A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD402A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD402A1V-C-25U 250 80 Pin TQFP Comm’l ZPSD402A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD402A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD402A2-C-70U 70 80 Pin TQFP Comm’l ZPSD402A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD402A2-C-90UI 90 80 Pin TQFP Industrial ZPSD402A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD402A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD402A2-C-15U 150 80 Pin TQFP Comm’l ZPSD402A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD402A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD402A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD402A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD402A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD402A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD402A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD402A2V-C-25U 250 80 Pin TQFP Comm’l ZPSD403A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD403A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD403A1-C-70U 70 80 Pin TQFP Comm’l ZPSD403A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD403A1-C-90UI 90 80 Pin TQFP Industrial ZPSD403A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD403A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD403A1-C-15U 150 80 Pin TQFP Comm’l ZPSD403A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD403A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD403A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD403A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD403A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD403A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD403A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD403A1V-C-25U 250 80 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range ZPSD403A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD403A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD403A2-C-70U 70 80 Pin TQFP Comm’l ZPSD403A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD403A2-C-90LI 90 68 Pin CLDCC Industrial ZPSD403A2-C-90UI 90 80 Pin TQFP Industrial ZPSD403A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD403A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD403A2-C-15U 150 80 Pin TQFP Comm’l ZPSD403A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD403A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD403A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD403A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD403A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD403A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD403A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD403A2V-C-25U 250 80 Pin TQFP Comm’l ZPSD411A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD411A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD411A1-C-70U 70 80 Pin TQFP Comm’l ZPSD411A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD411A1-C-90UI 90 80 Pin TQFP Industrial ZPSD411A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD411A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD411A1-C-15U 150 80 Pin TQFP Comm’l ZPSD411A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD411A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD411A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD411A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD411A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD411A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD411A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD411A1V-C-25U 250 80 Pin TQFP Comm’l ZPSD411A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD411A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD411A2-C-70U 70 80 Pin TQFP Comm’l ZPSD411A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD411A2-C-90UI 90 80 Pin TQFP Industrial ZPSD411A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD411A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD411A2-C-15U 150 80 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range ZPSD411A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD411A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD411A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD411A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD411A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD411A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD411A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD411A2V-C-25U 250 80 Pin TQFP Comm’l ZPSD412A0-C-70J 70 68 Pin PLDCC Comm’l ZPSD412A0-C-70L 70 68 Pin CLDCC Comm’l ZPSD412A0-C-70U 70 80 Pin TQFP Comm’l ZPSD412A0-C-90JI 90 68 Pin PLDCC Industrial ZPSD412A0-C-90UI 90 80 Pin TQFP Industrial ZPSD412A0-C-15J 150 68 Pin PLDCC Comm’l ZPSD412A0-C-15L 150 68 Pin CLDCC Comm’l ZPSD412A0-C-15U 150 80 Pin TQFP Comm’l ZPSD412A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD412A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD412A1-C-70U 70 80 Pin TQFP Comm’l ZPSD412A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD412A1-C-90UI 90 80 Pin TQFP Industrial ZPSD412A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD412A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD412A1-C-15U 150 80 Pin TQFP Comm’l ZPSD412A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD412A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD412A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD412A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD412A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD412A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD412A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD412A1V-C-25U 250 80 Pin TQFP Comm’l ZPSD412A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD412A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD412A2-C-70U 70 80 Pin TQFP Comm’l ZPSD412A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD412A2-C-90UI 90 80 Pin TQFP Industrial ZPSD412A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD412A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD412A2-C-15U 150 80 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

Part Number (ns) Package Type Range ZPSD412A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD412A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD412A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD412A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD412A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD412A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD412A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD412A2V-C-25U 250 80 Pin TQFP Comm’l ZPSD413A1-C-70J 70 68 Pin PLDCC Comm’l ZPSD413A1-C-70L 70 68 Pin CLDCC Comm’l ZPSD413A1-C-70U 70 80 Pin TQFP Comm’l ZPSD413A1-C-90JI 90 68 Pin PLDCC Industrial ZPSD413A1-C-90UI 90 80 Pin TQFP Industrial ZPSD413A1-C-15J 150 68 Pin PLDCC Comm’l ZPSD413A1-C-15L 150 68 Pin CLDCC Comm’l ZPSD413A1-C-15U 150 80 Pin TQFP Comm’l ZPSD413A1V-C-20J 200 68 Pin PLDCC Comm’l ZPSD413A1V-C-20JI 200 68 Pin PLDCC Industrial ZPSD413A1V-C-20L 200 68 Pin CLDCC Comm’l ZPSD413A1V-C-20U 200 80 Pin TQFP Comm’l ZPSD413A1V-C-20UI 200 80 Pin TQFP Industrial ZPSD413A1V-C-25J 250 68 Pin PLDCC Comm’l ZPSD413A1V-C-25L 250 68 Pin CLDCC Comm’l ZPSD413A1V-C-25U 250 80 Pin TQFP Comm’l ZPSD413A2-C-70J 70 68 Pin PLDCC Comm’l ZPSD413A2-C-70L 70 68 Pin CLDCC Comm’l ZPSD413A2-C-70U 70 80 Pin TQFP Comm’l ZPSD413A2-C-90JI 90 68 Pin PLDCC Industrial ZPSD413A2-C-90UI 90 80 Pin TQFP Industrial ZPSD413A2-C-15J 150 68 Pin PLDCC Comm’l ZPSD413A2-C-15L 150 68 Pin CLDCC Comm’l ZPSD413A2-C-15U 150 80 Pin TQFP Comm’l ZPSD413A2V-C-20J 200 68 Pin PLDCC Comm’l ZPSD413A2V-C-20JI 200 68 Pin PLDCC Industrial ZPSD413A2V-C-20L 200 68 Pin CLDCC Comm’l ZPSD413A2V-C-20U 200 80 Pin TQFP Comm’l ZPSD413A2V-C-20UI 200 80 Pin TQFP Industrial ZPSD413A2V-C-25J 250 68 Pin PLDCC Comm’l ZPSD413A2V-C-25L 250 68 Pin CLDCC Comm’l ZPSD413A2V-C-25U 250 80 Pin TQFP Comm’l Ordering InformationPSD4XX Product Ordering Information (cont.)

PSD4XX, ZPSD4XX

REVISION HISTORY

Table 1. Document Revision History Eliminated various speed grades, Updated Specifications.

PSD4XX, ZPSD4XX Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.