PSD211R

PSD211R STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Figure 1. Packages

i PSD211R Family PSD211R ZPSD211R ZPSD211RV Low Cost Microcontroller Peripherals Table of Contents

PSD211R ZPSD211R ZPSD211RV Low Cost Microcontroller Peripherals Table of Contents (cont.)

1.0 Introduction Programmable Peripheral PSD211R Field-Programmable Microcontroller Peripheral The low cost PSD211R family integrates high-performance and user-configurable blocks of EPROM and programmable logic into one part. The PSD211R products also provide a powerful microcontroller interface that eliminates the need for external “glue logic”. The part’s integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. The major functional blocks of the PSD211R include:

• Two programmable logic arrays
• 256 Kb of EPROM
• Input latches
• Programmable I/O ports
• Programmable security The PSD211R family architecture (Figure 1) can efficiently interface with, and enhance, almost any 8-bit multiplexed microcontroller system. This solution provides microcontrollers the following:
• Chip-select logic, control logic, and latched address signals that are otherwise implemented discretely
• Port expansion (reconstructs lost microcontroller I/O)
• An EPROM (with security)
• Compatible with 8031-type architectures that use separate Program and Data Space. Updated March 1, 1999. See page 47.

2.0 Notation 1.0 Introduction (Cont.) The PSD211R I/O ports can be used for:

• Standard I/O ports
• Programmable chip select outputs
• Address inputs
• Demultiplexed address outputs. Implementing your design has never been easier than with PSDsoft—WSI’s software development suite. Using PSDsoft, you can do the following:
• Configure your PSD211R to work with virtually any 8-bit microcontroller
• Specify what you want implemented in the programmable logic using a high-level Hardware Description Language (HDL)
• Simulate your design
• Download your design to the part using a programmer. Throughout this data sheet, references are made to the PSD211R. In most cases, these references also cover the ZPSD211R and ZPSD211RV products. Exceptions will be noted. Also, references to the ZPSD211R will also cover the low-voltage ZPSD211RV. (Again, exceptions will be noted.) Use the following table to determine what references cover which product versions: Reference PSD211R ZPSD211R ZPSD211RV PSD211R or PSD X X X PSD211R only X Non-ZPSD X ZPSD versions only X X Non-V versions X X V versions only or 3 V part only or ZPSD211RV only X

PROG. PORT EXP. PORT C PC0–PC2 ES0 ES1 ES2 ES3 ES4 ES5 ES6 ES7 PROG. CONTROL SIGNALS A19/CSI RESET WR/R/W RD/E ALE/AS PSEN PAD A RESET WR ALE/AS RD PAD B A11–A15 PROG. PORT EXP. PORT B PB0–PB7 PROG. PORT EXP. PORT A PA0–PA7 A19/CSI RESET ALE/AS A19/CSI A8–A10 WR RD ALE/AS L A T C H L A T C H A8–A15 AD0–AD7 D0–D7 13 P.T. 27 P.T. LOGIC IN EPROM 256Kb A16–A18 CS8–CS10 CS0–CS7 A0–A7 CSIOPORT PROG. CHIP CONFIGURATION Figure 1. PSD211R Family Architecture

3.0 Key Features J Low cost programmable microcontroller peripheral J 256Kb of UV EPROM with the following features:

• Configurable as 32 K x 8
• Divided into eight equally-sized mappable blocks for optimized address mapping
• As fast as 70 ns access time, which includes address decoding J 19 I/O pins that can be individually configured for :
• Microcontroller I/O port expansion
• Programmable Address decoder (PAD) I/O
• Latched address output J Two Programmable Arrays (PAD A and PAD B) replace your discrete PLD or decoder and have the following features:
• Up to 13 Inputs and 24 outputs
• 36 Product terms (9 for PAD A and 27 for PAD B)
• Ability to decode up to 1 MB of address J Microcontroller logic that eliminates the need for external “glue logic” has the following features:
• Ability to interface to multiplexed buses
• Built-in address latches for multiplexed address/data bus
• ALE and Reset polarity are programmable (Reset polarity not programmable on V-versions)
• Multiple configurations are possible for interface to many different microcontrollers J Programmable power management with standby current as low as 1µA (V versions only)
• CMiser bit—programmable option to reduce AC power consumption in memory
• Turbo Bit (ZPSD only)—programmable bit to reduce AC and DC power consumption in the PADs J Built-in security locks the device and PAD decoding configuration J Wide Operating Voltage Range
• V-versions: 2.7 to 5.5 volts
• Others: 4.5 to 5.5 volts J Available in a variety of packaging (44-pin PLDCC, CLDCC, and PQFP) J Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.

4.0 PSD211R Family Feature Summary Use the following table to determine which PSD product will fit your needs. Refer back to this page whenever there is confusion as to which part has what features. J Motorola family:68HC11, 68HC05C0 J Intel family: 80C31, 80C51, 80C188, 80C198 J Philips family: 80C31 and 80C51 based MCUs J Zilog: Z8 Typical # PLD EPROM Turbo Standby Part Inputs Size Voltage Bit Current PSD211R 13 256 Kb 5 V 50 µA ZPSD211R 13 256 Kb 5 V X 10 µA ZPSD211RV 13 256 Kb 3 V/5 V X 1 µA Table 1. PSD211R Product Summary

• Cellular phone
• Digital PBX
• Digital speech
• FAX
• Digital Signal Processing (DSP) J Portable Industrial Equipment:
• Industrial Control
• Measurement meters
• Data recorders
• Security and access control J Medical Instrumentation:
• Hearing aids
• Monitoring equipment
• Diagnostic tools 6.0

Applications

NOTE: The low power version of the ZPSD211R (the ZPSD211RV) can only accept an active-low level Reset input. Portable and battery-powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this trend, WSI, Inc. developed a new lower power PSD part, denoted ZPSD211R. The Z stands for Zero-power because ZPSD products virtually eliminate the DC component of power consumption, reducing it to standby levels. Virtual elimination of the DC component is the basis for the words “Zero-power” in the ZPSD name. ZPSD products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit components, while drawing less power. 7.0 ZPSD Background

7.1 Integrated Power Management

and is only a few microamperes. contains the first architecture to apply Zero-power techniques to memory and logic blocks. Figure 2 compares ZPSD zero power operation to the operation of a discrete solution. short time. The ZPSD then latches the outputs of the PAD and EPROM to the new values. components, the system will consume operating power during the entire bus cycle. Figure 2. ZPSD Power Operation vs. Discrete Implementation

This pin is for 8031 or compatible MCUs that use PSEN to separate program space from data space. In this case, PSEN is used for reads from the EPROM. PSEN I Notes: 1) If your MCU does not output a PSEN signal, pull up this pin to V CC . 2) In programming mode, this pin is pulsed between VPP and 0 V. The following control signals can be connected to this port, based on WR/V PP your MCU (and the way you configure the PSD in PSDsoft): or I 1. WR—active-low write pulse. R/W/VPP 2. R/W—active-high read/active-low write input. Note: in programming mode, this pin must be tied to V PP . The following control signals can be connected to this port, based on RD/E I your MCU (and the way you configure the PSD in PSDsoft): 1. RD—active-low read input. 2. E—E clock input. The following control signals can be connected to this port: 1. CSI-Active-low chip select input. If your MCU supports a chip select output, and you want the PSD to save power when not A19/CSI I selected, use this pin as a chip select input. 2. If you don’t wish to use the CSI feature, you may use this pin as an additional input (logic or address) to the PAD. A19 can be latched with ALE/AS, or be a transparent logic input. PSD211R/ZPSD211R: This pin is user-programmable and can be configured to reset on a high- or low-level input. Reset must be applied for at least 100 ns. Reset I ZPSD211RV: This pin is not configurable, and the chip will only reset on an active-low level input. Reset must be applied for at least 500 ns, and no operations may take place for an additional 500 ns minimum. (See Figure 8.) ALE/AS I Connect ALE or AS to this pin. The polarity of this pin is configurable. The trailing edge of ALE/AS latches all multiplexed address inputs. PA0 PA1 PA2 These pins make up Port A. These port pins are configurable, and PA3 I/O can have the following functions: (see Figure 5) PA4 1. MCU I/O—in this mode, the direction of the pin is defined by its PA5 direction bit, which resides in the direction register. PA6 2. Latched address output. PA7 Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power. Table 2. PSD211R Pin Descriptions

Table 1. PSD211R Pin Descriptions (cont.) PSD211R Family Name Type Description These pins make up Port C. These port pins are configurable, and can have the following functions (see Figure 7): 1. PAD input—when configured as an input, a bit individually PC0 becomes an address or a logic input, depending on your PSDsoft PC1 I/O design file. When declared as an address, the bits are latched PC2 with ALE/AS. 2. PAD output—when configured as an output (i.e. there is an equation written for it in your PSDsoft design file), there is one product term available to it. AD0 AD1 AD2 These pins are the multiplexed, low-order address/data byte AD3 I/O (AD0-AD7). As inputs, address information is latched by the ALE/AS AD4 signal and used internally by the PSD. The pins also serve as MCU AD5 data bus inputs or outputs, depending on the MCU control signals AD6 (RD, WR, etc.). AD7 A10 A11 I/O These pins are the high-order address inputs (A8-A15).A12 A13 A14 A15 GND P Ground Pin V CC P Supply voltage input. Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power.

following figure. Ports A through C can be configured according to Table 3, below. Figure 3. Connecting a PSD211R to an 8-Bit Multiplexed-Bus MCU Table 3. Bus and Port Configuration Options NOTE: 1. Connect A16-A18 to Port C if your MCU outputs more than 16 bits of address. the internal EPROM blocks and I/O ports. decoding to select external devices or as a random logic replacement. a list of PAD A and PAD B functions.

become non-active. See Tables 7A and 7B.

1. RESET deselects all PAD output signals. See Tables 8A and 8B.
2. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively.

Port C. Port C can be configured as either input or output.

8 EPROM BLOCK

Figure 4. PAD DescriptionProgrammable

A16–A18 These are general purpose inputs from Port C. See Figure 4, Note 3. A11–A15 These are address inputs. RD/E This is the read pulse or enable strobe input. WR or R/W This is the write pulse or R/W select signal. ALE/AS This is the ALE or AS input to the chip. term equations. See Tables 8A and 8B. a function of up to four product terms of the PAD inputs. a function of up to two product terms of the PAD inputs. Note 3. Each of them is a function of one product term of the PAD inputs. Table 4. PSD211R PAD A and PAD B FunctionsProgrammable

The PSD211R has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications.

10.1 CSIOPORT Registers

the registers located in the CSIOPORT space. Table 5. CSIOPORT Registers for 8-Bit Data Busses

10.2 Port A (PA0-PA7)

through the DFF or an external source driving the pin.

PA0 of Port A may only pass A0, PA1 only A1, and so on. NOTE: 1. Default value is the value after reset. Figure 5. Port A Pin Structure

Figure 6. Port B Pin Structure

10.3 Port B (PB0-PB7)

through the DFF or an external source driving the pin. is not limited to chip selects only; they can be used for generic combinatorial logic as well. signals is comprised of two product terms. NOTE: 1. Default value is the value after reset.

10.4 Port C (PC0-PC2)

• Whether they are address or logic inputs
• Whether the input is transparent or latched by the trailing edge of ALE/AS. Notes: 1) If the inputs are addresses, they are routed to PAD A and B, and can be used in any or all PAD equations. 2) If the inputs are logic, they are routed to PAD B and can be used for Boolean equations that are implemented in any or all of the CS0-CS10 PAD B outputs. 3) If Port C pins are configured as inputs, they can not be individually configured as address or logic and latched or transparent. They must be configured as a group to be address or logic and latched or transparent. Alternately, PC0-PC2 can become CS8-CS10 outputs, respectively, providing the user with more external chip-select PAD outputs. Each of the signals (CS8-CS10) is comprised of one product term.

Figure 7. Port C (PC0-PC2) Pin Structure NOTES: 1. Port C pins can be individually configured as inputs or outputs, but not both.

1. PSDsoft sets this configuration prior to run-time based on your PSDsoft design file.

11.0 PSD Memory The following sections explain the EPROM memory block and how to program and erase the PSD211R.

11.1 EPROM

For all PSD211R devices, the EPROM is built using Zero-power technology. This means that the EPROM powers up only when the address changes. It consumes power for the necessary time to latch data on its outputs. After this, it powers down and remains in standby mode until the next address change. This happens automatically, and the designer has to do nothing special. The 32K x 8 EPROM is divided into eight equal-sized banks. Each bank can be placed in any address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs ES0-ES7, respectively. There is one product term for each bank select (ESi).

11.2 Programming and Erasure

Programming the device can be done using the following methods:

• WSI’s main programmer—PSDpro—which is accessible through a parallel port.
• WSI’s programmer used specifically with the PSD211R—PEP300.
• WSI’s discontinued programmer—Magic Pro.
• A 3rd party programmer, such as Data I/O. Information for programming the device is available directly from WSI. Please contact your local sales representative. Also, check our web site (waferscale.com) for information related to 3rd party programmers. Upon delivery from WSI, or after each erasure (using windowed part), the PSD211R device has all bits in the PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO state (logic 0). To clear all locations of their programmed contents (assuming you have a windowed version), expose the windowed device to an Ultra-Violet (UV) light source. A dosage of

30 W second/cm

2 is required for PSD211R devices, and 40 W second/cm2 for low-voltage (V suffix) devices. This dosage can be obtained with exposure to a wavelength of 2537 Å and intensity of 12000 µW/cm 2 for 40 to 45 minutes for the PSD211R and 55 to 60 minutes for the low-voltage (V suffix) devices. The device should be approximately 1 inch (2.54 cm) from the source, and all filters should be removed from the UV light source prior to erasure. The PSD211R devices will erase with light sources having wavelengths shorter than 4000 Å. However, the erasure times will be much longer than when using the recommended 2537 Å wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an environment, the package window should be covered with an opaque substance. 12.0 Control Signals Consult your MCU data sheet to determine which control signals your MCU generates, and how they operate. This section is intended to show which control signals should be connected to what pins on the PSD211R. You will then use PSDsoft to configure the PSD211R, based on the combination of control signals that your MCU outputs, for example RD, WR, and PSEN. The PSD211R is compatible with the following control signals:

• ALE or AS (polarity is programmable)
• WR or R/W
• RD/E
• PSEN
• A19/CSI
• RESET (polarity is programmable except on low voltage versions with the V suffix).

12.0 Control Signals (Cont.)

12.1 ALE or AS

Connect the ALE or AS signal from your MCU to this pin where applicable, and program the polarity using PSDsoft. The trailing edge (when the signal goes inactive) of ALE or AS latches the address on the appropriate address pins.

12.2 WR or R/W

Your MCU should output a stand-alone write signal (WR) or a multiplexed read/write signal (R/W). In either case, the signal should be connected to this pin.

12.3 RD/E

Your MCU should output either RD or E (clock). In either case, connect the appropriate signal to this pin. Note: if you have an MCU that outputs DS, it will not be compatible with the PSD211R, and you must use a PSD3XX family device.

12.4 PSEN

J If your MCU does not output PSEN (or some program select enable equivalent signal), tie this pin to Vcc (through a series resistor), and skip to the next signal. J If you use an 8-bit 8031 compatible MCU that outputs a separate signal when accessing program space, such as PSEN, connect it to this pin. You would then use PSDsoft to configure the EPROM in the PSD211R to respond to PSEN only or PSEN and RD. If you have an 8031 compatible MCU, refer to the “Program/Data Space and the 8031” section for further information.

12.5 A19/CSI

This pin is configured using PSDsoft to be either a chip select for the entire PSD device or an additional PAD input. If your MCU can generate a chip-select signal, and you wish to save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic input. J When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD in normal operation. However, when a high is detected on the pin, the PSD enters Power-down Mode. See Tables 7A and 7B for information on signal states during Power-down Mode. See section 16 for details about the reduction of power consumption. J When configured as A19, the pin can be used as an additional input to the PADs. It can be used for address or logic. It can also be ALE/AS dependent or a transparent input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always enabled. Port Configuration Mode(s) State AD0–AD15 All Input (Hi-Z) Port Pins PA0–PA7 MCU I/O Unchanged Latched Address Out Logic 1 MCU I/O Unchanged Port Pins PB0–PB7 Chip Select Outputs, CS0–CS7, CMOS Logic 1 Chip Select Outputs, CS0–CS7, Open Drain Hi-Z Port Pins PC0–PC2 Address or Logic Inputs, A16-A18 Input (Hi-Z) Chip Select Outputs, CS8–CS10, CMOS only Logic 1 Table 7A. Signal States During Power-down Mode

12.0 Control Signals (Cont.) Internal Signal State Component Internal Signal During Power-Down PAD A and PAD B CS0–CS10 Logic 1 (inactive) CSIOPORT, ES0–ES7 Logic 0 (inactive) All registers in CSIOPORT address N/A space, including: Direction Data All unchanged PMR (turbo bit, ZPSD only) Table 7B. Internal States During Power-down NOTE: N/A = Not Applicable

12.6 Reset Input

This is an asynchronous input to initialize the PSD device. Refer to tables 8A and 8B for information on device status during and after reset. The standard-voltage PSD211R and ZPSD211R (non-V) devices require a reset input. In this case, the reset input must be asserted for at least 100 nsec. The PSD will be functional immediately after reset is de-asserted. For these standard-voltage devices, the polarity of the reset input signal is programmable using PSDsoft (active-high or active-low), to match the functionality of your MCU reset. Note: It is not recommended to drive the reset input of the MCU and the reset input of the PSD with a simple RC circuit between power on ground. The input threshold of the MCU and the PSD devices may differ, causing the devices to enter and exit reset at different times because of slow ramping of the signal. This may result in the PSD not being opera- tional when accessed by the MCU. It is recommended to drive both devices actively. A supervisory device or a gate with hysteresis is recommended. For low-voltage ZPSD211RV devices only, the reset input must be asserted for at least 500 nsec. The ZPSD211RV will not be functional for an additional 500 nsec after reset is de-asserted (see Figure 8). These low voltage ZPSD211RV devices require an active-low polarity signal for reset. Unlike the PSD211R, the polarity of the reset input is not programmable for the ZPSD211RV. If your MCU operates with an active high reset, you must invert this signal before driving the ZPSD211RV reset input. You must design your system to ensure that the PSD comes out of reset and the PSD is active before the MCU makes its first access to PSD memory. Depending on the characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset may be needed.

500 nsec after reset before signal is valid. Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.

14.0 System In Figure 11, the PSD211R is configured to interface with Intel’s 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 80C31 uses signals RD to read from data memory and PSEN to read from code memory. It uses WR to write into the data memory. It also uses active high reset and ALE signals. Only the necessary connections are shown. Figure 11. Interface With Intel’s 80C31 NOTE: RESET to the PSD211R must be the output of a RESET chip or buffer. PSD211R (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.

In Figure 12, the PSD211R is configured to interface with Motorola’s 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes. It uses the term AS (address strobe) for the address latch pulse. RESET is an active low signal. Only the necessary connections are shown. Figure 12. Interface With Motorola’s 68HC11 (cont.)

15.0 Security Mode Security Mode in the PSD211R locks the contents of PAD A, PAD B, and all the configuration bits. The EPROM and I/O contents can be accessed only through the PAD. The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only be erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents of the PSD211R can not be uploaded (copied) on a device programmer. 16.0 Power Management PSDs from all 211R families use zero-power memory techniques that place memory into Standby Mode between MCU accesses. The memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to Standby. This is done automatically and the designer has to do nothing special to benefit from this feature. In addition to the benefits of Zero-power memory technology, there are ways to gain additional savings. The following factors determine how much current the entire PSD device uses:

• Use of CSI (Chip Select Input)
• Setting of the CMiser bit
• Setting of the Turbo Bit (ZPSD only)
• The number of product terms used in the PAD
• The composite frequency of the input signals to the PAD
• The loading on I/O pins. The total current consumption for the PSD is calculated by summing the currents from memory, PAD logic, and I/O pins, based on your design parameters and the power management options used.

16.1 CSI Input

Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire PSD to enter Power-down Mode, independent of any transition on the MCU bus (address and control) or other PSD inputs. During this time, the PSD device draws only standby current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal operation. See Tables 7A and 7B for information on signal states during Power-down Mode. The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.

16.2 CMiser bit

In addition to power savings resulting from the Zero-power technology used in the memory, the CMiser feature saves even more power under certain conditions. Savings are significant when the PSD is configured for an 8-bit data path because the CMiser feature turns off half of the array when memory is being accessed (the memory is divided internally into odd and even arrays). See the DC characteristics table for current usage related to the CMiser bit. You should keep the following in mind when using this bit:

• Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time.
• Memory access times are extended by 10 nsec for standard voltage (non-V) devices, and 20 nsec for low voltage (V) devices.

1. Power Management (cont.)

16.3 Turbo Bit (ZPSD only)

The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1=OFF 1=OFF 1=OFF 1=OFF 1=OFF 1=OFF 1=OFF 1=OFF Power Management Register (PMR) *Future Configuration bits are reserved and should be set to one when writing to this register. The default value at reset of all bits in the PMR is logic 0, which means the Turbo feature is enabled. The PAD logic (PAD A and PAD B) of the PSD will operate at full speed and full power. When the Turbo bit is set to logic 1, the Turbo feature is disabled. When disabled, the PAD logic will draw only standby current (micro-amps) while no PAD inputs change. Whenever there is a transition on any PAD input (including MCU address and control signals), the PAD logic will power up and will generate new outputs, latch those outputs, then go back to Standby Mode. Keep in mind that the signal propagation delay through the PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in non-turbo mode. Use of the Turbo bit does not affect the operation or power consumption of memory. Tremendous power savings are possible by setting the Turbo bit and going into non-turbo mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also reduces the AC power consumption of PAD logic when the composite frequency of all PAD inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V devices. Use figures 13 and 14 to calculate AC and DC current usage in the PAD with the Turbo bit on and off. You will need to know the number of product terms that are used in your design and you will have to calculate the composite frequency of all signals entering the PAD logic.

16.4 Number of Product Terms in the PAD Logic

The number of product terms used in your design relates directly to how much current the PADs will draw. Therefore, minimizing this number will be in your best interest if power is a concern for you. Basically, the amount of product terms your design will use is based on the following (see Figure 4):

• Each of the EPROM block selects, ES0-ES7 uses one product term (for a total of 8).
• The CSIOPORT select uses one product term.
• Port B, pins PB0-PB3 are allocated four product terms each if used as outputs.
• Port B, pins PB4-PB7 are allocated two product terms each if used as outputs.
• Port C, pins PC0-PC2 are allocated one product term each if used as outputs. Given the above product term allocation, keep the following three points in mind when calculating the total number of product terms your design will require: 1) The EPROM block selects and CSIOPORT select will use a product term whether you use these blocks or not. This means you start out with 9 product terms, and go up from there. 2) For Port B, if you use a pin as an output and your logic equation requires only one product term, you still have to include all the available product terms for that pin for power consumption, even though only one product term is specified. For example, if the output equation for pin PB0 uses just one product term, you will have to count PB0 as contributing four product terms to the overall count. With this in mind, you should use Port C for the outputs that only require one product term and PB4-7 for outputs that require two product terms. Use pins PB0-3 if you need outputs requiring more than two product terms or you have run out of outputs. 3) The following PSD functions do not consume product terms: MCU I/O mode, Latched Address Output, and PAD inputs (logic or address).

16.5 Composite Frequency of the Input Signals to the PAD Logic

Figure 14. From the figures, notice that the DC component (f = 0 MHz) of PAD current is input signals may count as just one transition when estimating the composite frequency. consume less power only if the composite frequency of all PAD inputs is less than 40 MHz. down (inputs are spaced less than 25 nsec) and no power savings can be achieved. Figure 14 is for low-voltage devices in which the “knee” frequency is 20 MHz. 1) Determine your highest frequency input for either PAD A or PAD B. number of distinct transitions. Since this is a complicated process, the following example should help.

3 Inputs: Int, Sel, Rdy

6 MCU I/O Outputs

3 Chip-Select Outputs

16.0 Power Management (cont.) All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into consideration when calculating the composite frequency. Before we make the calculation, let’s establish the following conditions:

• The input with the highest frequency is ALE, which is 2 MHz. So our base period is 500 nsec for this example.
• Only the address information from the multiplexed signals AD0-AD7 reach the PAD logic because of the internal address latch. Signal transitions from data on AD0-AD7 do not reach the PADs.
• The three inputs (Int, Sel, or Rdy) change state very infrequently relative to the 80C31 bus signals. Now, lets assume the following is a snapshot in time of all the input signals during a typical 80C31 bus cycle. We’ll use a code fetch as an example since that happens most often. ONE TYPICAL 80C31 BUS CYCLE (2 MHz, 500 nsec) ALE PSEN AD0-AD7 A8-A15 INT SEL RDY FOUR DISTINCT TRANSITIONS < 25 nsec ADDR DATA The calculation of the composite frequency is as follows:
• There are four distinct transitions (first four dotted lines) within the base period of 500 nsec. These first four transitions all count toward the final composite frequency.
• The transition at (1) in the diagram does not count as a distinct transition because it is within 25 nsec of a neighboring transition (use 50 nsec for a ZPSD211RV device).
• Transition (2) above does not add to the composite frequency because only the internally latched address signals reach the PADs, the data signal transitions do not.
• The transition at (3) just happens to appear in this snapshot, but its frequency is so low that it is not a significant contributor to the overall composite frequency, and will not be used.
• Divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec. 1/125 nsec = 8 MHz.
• Use 8 MHz as the composite frequency of PAD inputs when calculating current consumption. (See the next section for a sample current calculation.)

16.6 Loading on I/O pins

A final consideration when calculating the current usage for the entire PSD device is the loading on I/O pins. All specifications for PSD current consumption in this document assume zero current flowing through PSD I/O pins (including ADIO). I/O current is dictated by the individual design implementation, and must be calculated by the designer. Be aware that I/O current is a function of loading on the pins and the frequency at which the signals toggle.

17.0 Calculating Power Conditions Part Used = ZPSD211R (V CC = 5.0 V) MCU ALE Clock Frequency = 2.0 MHz Composite ZPLD input Frequency = 8.0 MHz (see example in above section) % EPROM Access = 80% % I/O access = 20% % Time CSI is high (standby mode) = 90% % Time CSI is low (normal operation mode) = 10% # Product terms used (see previous section) = 10 Turbo bit = OFF (Turbo Mode disabled) CMiser bit = ON MCU Bus Configuration = 8-bit multiplexed bus mode Calculation (Based on Typical AC and DC Currents) ICC total = Istandby x % time CSI is high + [ICC (AC) + ICC (DC)]x % time CSI is low. = Istandby x % time CSI is high + [%EPROM Access x 0.8 mA/MHz x Freq. ALE + ZPLD AC current (Figure 13: 10 PTs, 8 MHz, Non-Turbo)] x % time CSI is low. = 637 µA, based on the system operating in standby 90% of the time Once you have read the “Power Management” section, you should be able to calculate power. The following is a sample power calculation: NOTES: 1. Calculation is based on the assumption that Iout = 0 mA (no I/O pin loading). 2. ICC (DC) is zero for all ZPSD devices operating in non-turbo mode. 3. 10 product terms: 8 for EPROM, 1 for CSIOPORT, 1 for CS8 4. The 5% I/O access in the conditions section is when the MCU accesses CSIOPORT space. 5. Standby Mode can also be achieved without using the CSI pin. The ZPSD device will automatically go into Standby while no inputs are changing on any pin, and Turbo Mode is disabled.

36 PT Turbo

36 PT Non-Turbo

10 PT Turbo

10 PT Non-Turbo

Figure 13. Typical ICC vs. Frequency for the PAD (VCC = 5 V) Figure 14. Typical ICC vs. Frequency for the PAD (VCC = 3 V)

Symbol Parameter Condition Min Max Unit TSTG Storage Temperature CERDIP – 65 + 150 °C PLASTIC – 65 + 125 °C Voltage on any Pin With Respect to GND – 0.6 + 7 V VPP Programming Supply Voltage With Respect to GND – 0.6 + 14 V VCC Supply Voltage With Respect to GND – 0.6 + 7 V ESD Protection >2000 V Range Temperature V CC VCC Tolerance Commercial 0° C to +70°C + 3 V 1, + 5 V ± 10% Industrial –40° C to +85°C + 3 V 1, + 5 V ± 10% Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage PSD Versions, All Speeds 4.5 5 5.5 V VCC Supply Voltage ZPSD V Versions Only, 2.7 3.0 5.5 VAll Speeds 18.0 Specifications

18.3 Recommended Operating Conditions

NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

18.1 Absolute Maximum Ratings1

NOTE: 1. 3 V available on ZPSD211RV only.

18.2 Operating Range

Symbol Parameter Conditions Typical 2 Max Unit C IN Capacitance (for input pins only) VIN = 0 V 4 6 pF C OUT Capacitance (for input/output pins) VOUT = 0 V 8 12 pF C VPP Capacitance (for WR/VPP or R/W/VPP )V PP = 0 V 18 25 pF NOTES: 1. This parameter is only sampled and is not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages.

18.4 Pin Capacitance1

NOTES: 1. CMOS inputs: GND ± 0.3 V or VCC ± 0.3V. 2. TTL inputs: VIL≤ 0.8 V, VIH ‡ 2.0 V. 3. I OUT = 0 mA. 4. CSI/A19 is high and the part is in a power-down configuration mode. Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 4.5 5 5.5 V VIH High-Level Input Voltage 4.5 V < VCC > 5.5 V 2 V CC +. 1 V VIL Low-Level Input Voltage 4.5 V < VCC > 5.5 V – 0.5 0.8 V IOH = – 20 µA, VCC = 4.5 V 4.4 4.49 V VOH Output High Voltage IOH = – 2 mA, VCC = 4.5 V 2.4 3.9 V Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V VOL (See Figure 14) IOL = 8 mA, VCC = 4.5 V 0.15 0.45 V ZPSD211R 10 20 µA ISB Standby Supply Current (Notes 1,4)PSD211R Standby Supply Current 50 100 µA ILI Input Leakage Current V SS < VIN > VCC –1 ±.1 1 µA ILO Output Leakage Current .45 < VIN > VCC –10 ± 5 10 µA ZPLD Turbo Mode = Off, f = 0 MHz See I SB µA ZPSD211R ZPLD Turbo Mode = On, f = 0 MHz 0.5 1 mA/PT Operating Suppy CurrentEPROM, f = 0 MHz 0 0 µA ICC (DC) SRAM, f = 0 MHz 0 0 µA(Note 3) PLD, f = 0 MHz 0.5 1 mA/PT PSD211R EPROM, f = 0 MHz 0 0 µAOperating Supply Current SRAM, f = 0 MHz 0 0 µA ZPLD AC Base (See Figure 13) Fig. 13 1 mA/MHz ICC (AC) EPROM Access CMiser = On and 8-Bit Bus Mode 0.8 2.0 mA/MHz(Note 3) AC Adder CMiser = Off 1.8 4.0 mA/MHz

18.5 AC/DC Characteristics – PSD211R/ZPSD211R (All 5 V devices)

Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage All Speeds 2.7 3 5.5 V VIH High-Level Input Voltage 2.7 V < VCC > 5.5 V .7 V CC VCC +. 5 V VIL Low-Level Input Voltage 2.7 V < VCC > 5.5 V – 0.5 .3 V CC V IOH = – 20 µA, VCC = 2.7 V 2.6 2.69 V VOH Output High Voltage IOH = – 1 mA, VCC = 2.7 V 2.3 2.4 V IOL = 20 µA, VCC = 2.7 V 0.01 0.1 V VOL Output Low Voltage IOL = 4 mA, VCC = 2.7 V 0.15 0.45 V ISB Standby Supply Current V CC = 3.0 V 1 5 µA(Notes 1,4) ILI Input Leakage Current V IN = VCC or GND –1 ±.1 1 µA ILO Output Leakage Current V OUT = VCC or GND –1 .1 1 µA ZPLD Turbo Mode= Off, f = 0 MHz, VCC = 3.0 V See ISB µA ICC (DC) Operating Supply CurrentZPLD Turbo Mode= On, (Note 3) f = 0 MHz, VCC = 3.0 V 0.17 0.35 mA/PT EPROM, f = 0 MHz, VCC = 3.0 V 00µ A ZPLD AC Base See Figure 14 (V CC = 3.0 V) Fig. 14 0.5 mA/MHz CMiser = On and 8-Bit BusICC (AC) EPROM Access Mode (VCC = 3.0 V) 0.4 1 mA/MHz (Note 3) AC Adder CMiser = Off (VCC = 3.0 V) 0.9 1.7 mA/MHz

18.6 AC/DC DC Characteristics ZPSD211RV (3 V devices only)

NOTES: 1. CMOS inputs: GND ± 0.3 V or VCC ± 0.3V. 2. TTL inputs: VIL≤ 0.8 V, VIH ‡ 2.0 V. 3. IOUT = 0 mA. 4. CSI/A19 is high and the part is in a power-down configuration mode.

-70 -90 -15 CMiser Symbol Parameter On = Unit Min Max Min Max Min Max Add T1 ALE or AS Pulse Width 18 20 40 0 ns T2 Address Set-up Time 5 5 12 0 ns T3 Address Hold Time 7 8 10 0 ns T4 Leading Edge of Read to Data Active 0 0 0 0 ns T5 ALE Valid to Data Valid 80 100 160 10 ns T6 Address Valid to Data Valid 70 90 150 10 ns T7 CSI Active to Data Valid 80 100 160 10 ns T8 Leading Edge of Read to Data Valid 20 32 55 0 ns Leading Edge of Read to Data Valid in T8A 8031-Based Architecture Operating with PSEN 32 32 55 0 ns and RD in Separate Mode T9 Read Data Hold Time 0 0 0 0 ns T10 Trailing Edge of Read to Data High-Z 20 35 35 0 ns Trailing Edge of ALE or AS to Leading EdgeT11 of Write 000 0 n s T12 RD, E, PSEN Pulse Width 35 45 60 0 ns T12A WR Pulse Width 18 25 35 0 ns Trailing Edge of Write or Read to Leading EdgeT13 of ALE or AS 555 0 n s T14 Address Valid to Trailing Edge of Write 70 120 150 0 ns T15 CSI Active to Trailing Edge of Write 80 130 160 0 ns T16 Write Data Set-up Time 18 25 30 0 ns T17 Write Data Hold Time 5 5 10 0 ns T18 Port to Data Out Valid Propagation Delay 25 28 35 0 ns T19 Port Input Hold Time 0 0 0 0 ns T20 Trailing Edge of Write to Port Output Valid 30 35 50 0 ns T21 ADi 1 or Control to CSOi2 Valid 6 20 6 25 6 35 10 ns T22 ADi 1 or Control to CSOi2 Invalid 5 20 5 25 4 35 10 ns T23 Latched Address Outputs, Port A 22 22 28 0 ns T30 CSI Active to CSOi

2 Active 8 37 9 40 9 50 0 ns

T31 CSI Inactive to CSOi2 Inactive 8 37 9 40 9 50 0 ns T32 Direct PAD Input 3 as Hold Time 0 0 12 0 ns T33 R/W Active to E High 18 20 30 0 ns T34 E End to R/W 18 20 30 0 ns T35 AS Inactive to E high 0 0 0 0 ns T36 Address to Leading Edge of Write 18 20 25 0 ns

18.7 Timing Parameters – PSD211R/ZPSD211R (All 5 V devices)

NOTES: 1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or R/W, transparent PC0–PC2, ALE (or AS). 4. Control signals RD/E or WR or R/W.

-20 -25 CMiser Turbo Symbol Parameter On = Off = Unit Min Max Min Max Add Add T1 ALE or AS Pulse Width 50 60 0 0 ns T2 Address Set-up Time 15 20 0 0 ns T3 Address Hold Time 15 20 0 0 ns T4 Leading Edge of Read to Data Active 0 0 0 0 ns T5 ALE Valid to Data Valid 200 250 20 0 ns T6 Address Valid to Data Valid 200 250 20 0 ns T7 CSI Active to Data Valid 200 250 20 0 ns T8 Leading Edge of Read to Data Valid 50 60 0 0 ns Leading Edge of Read to Data Valid in T8A 8031-Based Architecture Operating with 70 80 0 0 ns PSEN and RD in Separate Mode T9 Read Data Hold Time 0 0 0 0 ns T10 Trailing Edge of Read to Data High-Z 50 55 0 0 ns Trailing Edge of ALE or AST11 to Leading Edge of Write 00 0 0 n s T12 RD, E, PSEN, or DS Pulse Width 75 85 0 0 ns T12A WR Pulse Width 45 55 0 0 ns Trailing Edge of Write or ReadT13 to Leading Edge of ALE or AS 55 0 0 n s T14 Address Valid to Trailing Edge of Write 200 250 0 0 ns T15 CSI Active to Trailing Edge of Write 200 250 0 0 ns T16 Write Data Set-up Time 40 50 0 0 ns T17 Write Data Hold Time 12 15 0 0 ns T18 Port to Data Out Valid Propagation Delay 50 60 0 0 ns T19 Port Input Hold Time 0 0 0 0 ns T20 Trailing Edge of Write to Port Output Valid 60 70 0 0 ns T21 ADi 1 or Control to CSOi2 Valid 5 55 5 60 0 20 ns T22 ADi 1 or Control to CSOi2 Invalid 4 55 4 60 0 20 ns T23 Latched Address Outputs, Port A 60 60 0 0 ns

18.8 Timing Parameters – ZPSD211RV (3 V devices only)

NOTES: 1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or R/W, transparent PC0–PC2, ALE (or AS). 4. Control signals RD/E or WR or R/W. -20 -25 CMiser Turbo Symbol Parameter On = Off = Unit Min Max Min Max Add Add Hold Time of Port A Valid During Write CSOiT29 Trailing Edge 33 0 0 n s T30 CSI Active to CSOi 2 Active 9 80 9 90 0 0 ns T31 CSI Inactive to CSOi 2 Inactive 9 80 9 90 0 0 ns T32 Direct PAD Input 3 as Hold Time 0 0 0 0 ns T33 R/W Active to E or DS Start 40 50 0 0 ns T34 E or DS End to R/W 40 50 0 0 ns T35 AS Inactive to E high 0 0 0 0 ns T36 Address to Leading Edge of Write 35 40 0 0 ns 18.8 Timing Parameters – ZPSD211RV (3 V devices only) (cont.)

18.9 Timing Diagrams for all PSD211R Parts

Figure 19. Timing using RD and WR signals See referenced notes on page 38.

Figure 20. Timing Using R/W and E signals See referenced notes on page 38.

Figure 21. Chip-select Output Timing

1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19,

RD/E, WR or R/W, transparent PC0–PC2, ALE in non-multiplexed modes.

1. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):

A0/AD0–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.

1. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through
2. CSOi product terms can include any of the PAD input signals shown in Figure 4, except for reset

Figure 22A. AC Testing Input/Output Waveform (5 V Versions ) Figure 23A. AC Testing Load Circuit (5 V Versions ) 3.0V TEST POINT 1.5V DEVICE UNDER TEST 2.01 V 195 Ω C L = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE)

0.9 VCC

TEST POINT 1.5V DEVICE UNDER TEST 2.0 V 400 Ω C L = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) Figure 22B. AC Testing Input/Output Waveform (3 V Versions ) Figure 23B. AC Testing Load Circuit (3 V Versions ) 18.10. AC Testing

Pin No. Pin No. 44-Pin 44-Pin PLDCC/CLDCC PQFP Pin Assignments (Package Type L/J) (Package Type M) PSEN 1 39 WR/V PP or R/W 2 40 RESET 3 41 PB7 4 42 PB6 5 43 PB5 6 44 PB4 7 1 PB3 8 2 PB2 9 3 PB1 10 4 PB0 11 5 GND 12 6 ALE or AS 13 7 PA7 14 8 PA6 15 9 PA5 16 10 PA4 17 11 PA3 18 12 PA2 19 13 PA1 20 14 PA0 21 15 RD/E 22 16 AD0/A0 23 17 AD1/A1 24 18 AD2/A2 25 19 AD3/A3 26 20 AD4/A4 27 21 AD5/A5 28 22 AD6/A6 29 23 AD7/A7 30 24 A8 31 25 A9 32 26 A10 33 27 GND 34 28 A11 35 29 A12 36 30 A13 37 31 A14 38 32 A15 39 33 PC0 40 34 PC1 41 35 PC2 42 36 A19/CSI 43 37 V CC 44 38 19.0 Pin Assignments

39 A15

38 A14

37 A13

36 A12

35 A11

34 GND

33 A10

30 AD7/A7

29 AD6/A6

6 PB5

5 PB6

4 PB7

3 RESET

2 WR/V or R/W

1 PSEN

43 A19/CSI

42 PC2

41 PC1

40 PC0

(TOP VIEW) 20.0 Package Information Figure 24. Drawing L4 –

44 Pin Ceramic

Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 –

44 Pin Plastic

Carrier (PLDCC) without Window (Package Type J) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 A15 A14 A13 A12 A11 GND A10 AD7/A7 AD6/A6 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 PB5 PB6 PB7 RESET WR/V PP or R/W PSEN V CC A19/CSI PC2 PC1 PC0 (TOP VIEW) Figure 25. Drawing M1 – (PQFP) (Package Type M)

Family: Plastic Leaded Chip Carrier Millimeters Inches Symbol Min Max Notes Min Max Notes A 4.19 4.57 0.165 0.180 A1 2.54 2.79 0.100 0.110 A2 3.76 3.96 0.148 0.156 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.246 0.262 0.0097 0.0103 D 17.40 17.65 0.685 0.695 D1 16.51 16.61 0.650 0.654 D2 14.99 16.00 0.590 0.630 D3 12.70 Reference 0.500 Reference E 17.40 17.65 0.685 0.695 E1 16.51 16.61 0.650 0.654 E2 14.99 16.00 0.590 0.630 E3 12.70 Reference 0.500 Reference e1 1.27 Reference 0.050 Reference N4 4 4 4 030195R6 Drawing J2 – 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) B A1 A2 E1 E A C D 44123

21.0 Package Drawings

Family: Ceramic Leaded Chip Carrier – CERQUAD Millimeters Inches Symbol Min Max Notes Min Max Notes A 3.94 4.57 0.155 0.180 A1 2.29 2.92 0.090 0.115 A2 3.05 3.68 0.120 0.145 B 0.43 0.53 0.017 0.021 B1 0.66 0.81 0.026 0.032 C 0.15 0.25 0.006 0.010 D 17.40 17.65 0.685 0.695 D1 16.31 16.66 0.642 0.656 D2 14.73 16.26 0.580 0.640 D3 12.70 Reference 0.500 Reference E 17.40 17.65 0.685 0.695 E1 16.31 16.66 0.642 0.656 E2 14.73 16.26 0.580 0.640 E3 12.70 Reference 0.500 Reference e1 1.27 Reference 0.050 Reference N4 4 4 4 030195R8 Drawing L4 – 44-Pin Pocketed Ceramic Leaded Chip Carrier (CLDCC) – CERQUAD (Package Type L) B A1 A E1 E C 123 D View A Commercial and Industrial packages include the lead pocket on the underside of the package but Military packages do not. View A

Drawing M1 – 44-Pin Plastic Quad Flatpack (PQFP) (Package Type M) B E1 E D L a A C Index Mark Standoff: 0.10 mm Min 0.25 mm Max Family: Plastic Quad Flatpack (PQFP) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0° 7° 0° 7° A – 2.35 – 0.092 A1 1.075 Reference 0.042 Reference A2 1.95 2.10 0.077 0.083 B 0.30 0.45 0.012 0.018 C 0.13 0.23 0.005 0.009 D 13.20 0.520 D1 10.00 0.394 D3 8.00 Reference 0.315 Reference E 13.20 0.520 E1 10.00 0.394 E3 8.00 Reference 0.315 Reference e1 0.80 Reference 0.031 Reference L 0.73 1.03 0.029 0.040 N4 4 4 4 030195R4

Part # MCU PLDs/Decoders I/O Memory Other PSD ZPSD ZPSD 8-Bit 16-Bit Interface Inputs Product PLD Page Ports Open EPROM SRAM Peripheral Security@ @ @ Data Data Terms Outputs Reg. Drain Mode5 V 5 V 2.7 V PSD211R ZPSD211R ZPSD211RV X STD-M 14 40 11 19 256Kb X

22.1 PSD211R Family – Selector Guide

22.0 PSD211R Ordering Information

Part Number (ns) Package Type Range PSD211R-B-70J 70 44 Pin PLDCC Comm’l PSD211R-B-70L 70 44 Pin CLDCC Comm’l PSD211R-B-70M 70 44 Pin PQFP Comm’l PSD211R-B-90J 90 44 Pin PLDCC Comm’l PSD211R-B-90JI 90 44 Pin PLDCC Industrial PSD211R-B-15J 150 44 Pin PLDCC Comm’l PSD211R-B-15L 150 44 Pin CLDCC Comm’l PSD211R-B-15M 150 44 Pin PQFP Comm’l ZPSD211R-B-70J 70 44 Pin PLDCC Comm’l ZPSD211R-B-70L 70 44 Pin CLDCC Comm’l ZPSD211R-B-70M 70 44 Pin PQFP Comm’l ZPSD211R-B-90JI 90 44 Pin PLDCC Industrial ZPSD211R-B-90MI 90 44 Pin PQFP Industrial ZPSD211R-B-15J 150 44 Pin PLDCC Comm’l ZPSD211R-B-15L 150 44 Pin CLDCC Comm’l ZPSD211R-B-15M 150 44 Pin PQFP Comm’l ZPSD211RV-B-20J 200 44 Pin PLDCC Comm’l ZPSD211RV-B-20JI 200 44 Pin PLDCC Industrial ZPSD211RV-B-20L 200 44 Pin CLDCC Comm’l ZPSD211RV-B-20M 200 44 Pin PQFP Comm’l ZPSD211RV-B-25J 250 44 Pin PLDCC Comm’l ZPSD211RV-B-25JI 250 44 Pin PLDCC Industrial 22.0 PSD211R Ordering Information (cont.)

22.3 Ordering Information

Temperature (Blank = Commercial, I = Industrial, M = Military) Package Type Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) Revision (Blank = No Revision) Supply Voltage (Blank = 5V, V = 3 Volt) Base Part Number - see Selector Guide PSD (WSI Programmable System Device) Fam. Power Down Feature (Blank = Standard, Z = Zero Power Feature) Z PSD -A -20 J I 413A2 V

22.2 Part Number Construction

PSD211R, ZPSD211R, ZPSD211RV

REVISION HISTORY

Table 1. Document Revision History

PSD211R, ZPSD211R, ZPSD211RV Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.