TPS7A05_V01 TI1 | Alldatasheet

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Output Current (mA) Ground Current (PA) 0 20 40 60 80 100 120 140 160 180 200 D043 TPS7A05 IN EN OUT GND C OUT C IN ON OFF Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A05 SBVS254C – FEBRUARY 2018– REVISED APRIL 2019 TPS7A051-µAUltralowIQ,200-mA,Low-DropoutRegulator inaSmall-SizePackage

1 Features

1• Ultralow IQ: 1 µA (typ), 3 µA (max) – IGND: 6 µA (typ) at 200 mA

  • Excellent transient response
  • Packages: – 1.0-mm × 1.0-mm X2SON (4) – 0.65-mm × 0.65-mm DSBGA (4) – SOT-23 (5) – SOT-23 (3) (preview)
  • Input voltage range: 1.4 V to 5.5 V
  • Output accuracy: 1% typical, 3% maximum
  • Available in fixed-output voltage: – 0.8 V to 3.3 V
  • Very low dropout: – 235 mV (max) at 200 mA (3.3 VOUT)
  • Active output discharge
  • Foldback current limit
  • Stable with a 0.47-µF or larger capacitor

2 Applications

  • Wearable electronics
  • Ultrabooks, tablets, E-readers
  • Always-on power supplies
  • Set-top boxes
  • Gaming controllers, remote controls, toys, drones
  • Wireless handsets and smart phones
  • Portable and battery-powered equipment

3 Description

The TPS7A05 is an ultra-small, low quiescent current low-dropout regulator (LDO) that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. The TPS7A05, with ultralow IQ (1 µA), consumes very-low quiescent current for extending battery life in battery-powered applications. The device can be operated from rechargeable Li-Ion batteries, Li- primary battery chemistries such as Li-SOCl2, Li- MnO2, as well as two- or three-cell alkaline batteries. The TPS7A05 is available with an active pulldown circuit to quickly discharge the output when disabled. The TPS7A05 is fully specified for TJ = –40°C to +125°C operation, and is available in standard X2SON (DQN), SOT-23 (DBV and DBZ), and DSBGA (YKA) packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS7A05 X2SON (4) 1.00 mm × 1.00 mm DSBGA (4) 0.65 mm × 0.65 mm SOT-23 (5) 2.90 mm × 1.60 mm SOT-23 (3)(2) 2.90 mm x 1.60 mm (1) For all available packages, see the package option addendum at the end of the data sheet. (2) Preview package. Typical Application Circuit Ground Current vs Output Current

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Table of Contents

11.3 Receiving Notification of Documentation Updates 27

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision B (August 2018) to Revision C Page Changes from Revision A (May 2018) to Revision B Page Changes from Original (February 2018) to Revision A Page

B A Not to scale EN GND IN OUT 1 2 A B Not to scale IN OUT EN GND 1GND 2OUT 3 IN Not to scale 1IN 2GND 3EN 4 NC

5 OUT

www.ti.com SBVS254C – FEBRUARY 2018– REVISED APRIL 2019 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

1-mm × 1-mm, 4-Pin X2SON Top View 5-Pin SOT-23 Top View 3-Pin SOT-23 Top View 4-Pin DSBGA, 0.35-mm Pitch Top View 4-Pin DSBGA, 0.35-mm Pitch Bottom View

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTIONNAME DQN DBV DBZ YKA IN 4 1 3 A1 Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input capacitor as close to input of the device as possible. EN 3 3 — B1 Input Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. VEN must not exceed VIN. GND 2 2 1 B2 — Ground pin. This pin must be connected to ground on the board. OUT 1 5 2 A2 Output Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. Follow the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the output capacitor as close to output of the device as possible. NC — 4 — — — No connect pin. This pin is not internally connected. Connect to ground or leave floating. Thermal pad Pad — — — — Connect the thermal pad to a large-area ground plane. This pad is not an electrical connection to the device ground.

www.ti.com SBVS254C – FEBRUARY 2018– REVISED APRIL 2019 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages with respect to GND. (3) VIN + 0.3 V or 3.6 V (whichever is smaller)

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage(2) IN –0.3 6.0 VEN –0.3 VIN + 0.3 OUT –0.3 VIN + 0.3 or 3.6(3) Current Maximum output current Internally limited A Temperature Operating junction temperature, TJ –40 125 Storage temperature, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Output current of 10 µA minimum required to meet output voltage accuracy specification.

6.3 Recommended Operating Conditions

VIN Input supply voltage 1.4 5.5 V VEN Enable supply voltage 0 VIN V VOUT Nominal output voltage range 0.8 3.3 V IOUT Output current(1) 0 200 mA CIN Input capacitor 1 µF COUT Output capacitor 0.47 1 22 µF TJ Operating junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS7A05 UNITDBZ (SOT-23) DBV (SOT-23) DQN (X2SON) YKA (DSBGA)

3 PINS 5 PINS 4 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 267.3 185.6 144.1 198.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 103.5 104.3 137.9 2.1 °C/W RθJB Junction-to-board thermal resistance 98.0 54.5 83.5 66.9 °C/W ΨJT Junction-to-top characterization parameter 9.2 31.0 5.3 0.9 °C/W YJB Junction-to-board characterization parameter 97.4 54.5 83.8 76.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 71.8 n/a °C/W

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated (1) IOUT ≥ 10 µA required to meet accuracy specifications. (2) VIN = 1.4 V for VOUT ≤ 0.9 V. (3) Load Regulation is normalized to the output voltage at IOUT = 1 mA. (4) Dropout is measured by ramping VIN down until VOUT = VOUT(nom) – 5%.

6.5 Electrical Characteristics

specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Nominal accuracy(1) VOUT ≥ 1.0 V, TJ = 25°C –1% 1% VOUT < 1.0 V, TJ = 25°C –10 10 mV Accuracy over temperature(1) VOUT ≥ 1.0 V, TJ = –40°C to +85°C –2% 2% VOUT ≥ 1.0 V –3% 3% VOUT < 1.0 V, TJ = –40°C to +85°C –20 20 mV VOUT < 1.0 V –30 30 VOUT = 1.825 V, TJ = +10℃ to +45℃, IOUT = 100 µA –0.9% 0.9% ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(2), TJ = –40°C to +85°C 5 16.5 mV VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(2) 18 mV ΔVOUT(ΔIOUT) Load regulation(3) 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V, TJ = –40°C to +85°C 20 43 mV 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V 55 mV IGND Ground current TJ = 25°C, IOUT = 1 µA 0.6 1 1.3 µAIOUT = 1 µA, TJ = –40°C to +85°C 2 IOUT = 1 µA 3 ISHDN Shutdown current VEN = 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C 100 300 nA ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V 210 450 700 mA ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V, TJ = 0°C to +85°C 250 450 700 mA ISC Short-circuit current limit VOUT = 0 V 65 150 mA VDO Dropout voltage(4) IOUT = 200 mA, TJ = –40°C to +85°C 0.8 V ≤ VOUT < 1.0 V 915 mV 1.0 V ≤ VOUT < 1.2 V 758 1.2 V ≤ VOUT < 1.5 V 609 1.5 V ≤ VOUT < 1.8 V 469 1.8 V ≤ VOUT < 2.5 V 341 2.5 V ≤ VOUT < 3.3 V 275 VOUT = 3.3 V 212 IOUT = 200 mA 0.8 V ≤ VOUT < 1.0 V 1004 1.0 V ≤ VOUT < 1.2 V 837 1.2 V ≤ VOUT < 1.5 V 679 1.5 V ≤ VOUT < 1.8 V 525 1.8 V ≤ VOUT < 2.5 V 382 2.5 V ≤ VOUT < 3.3 V 308 VOUT = 3.3 V 235 IOUT = 100 µA, TJ = +10℃ to +45℃ VOUT = 1.825 V 20 mV

www.ti.com SBVS254C – FEBRUARY 2018– REVISED APRIL 2019 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Power-supply rejection ratio f = 1 kHz, IOUT = 30 mA 40 dBf = 500 kHz, IOUT = 30 mA 30 f = 1 MHz, IOUT = 30 mA 40 VN Output voltage noise BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 30 mA 180 µVRMS VUVLO UVLO threshold VIN rising 1.21 1.3 1.37 V VUVLO(HYST) UVLO hysteresis VIN falling 40 mV VUVLO UVLO threshold VIN falling 1.17 1.33 V VEN(HI) EN pin logic high voltage 0.9 V VEN(LO) EN pin logic low voltage 0.4 V IEN EN pin current VEN = VIN = 5.5 V 10 nA RPULLDOWN Pulldown resistor VIN = 3.3 V, P version only 120 Ω Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 Reset, temperature decreasing 140 (1) See the Special Considerations When Ramping Down IN and Enable section for details on minimum ramp down rates to ensure specified start-up time.

6.6 Switching Characteristics

specified at TJ = –40 to +125°C, VIN = VOUT(nom) + VDO(max) + 0.5 V, IOUT = 10 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTR Start-up time(1) From EN assertion to VOUT = 95% × VOUT(nom) , VOUT = 1.8 V 1.5 2.8 ms

6.7 Typical Characteristics

Figure 1. IQ vs VIN and Temperature Figure 2. ISHDN vs VIN and Temperature Figure 3. ISHDN vs VIN and Temperature Figure 4. IGND vs IOUT up to 10 mA Figure 5. IGND vs IOUT up to 200 mA Figure 6. IOUT Transient 0 mA to 100 mA

1.2-V Bandgap Thermal Shutdown Error Amp Internal Controller OUT EN IN GND Active Discharge P-Version Only UVLO TPS7A05 SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS7A05 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance. These characteristics make the TPS7A05 ideal for most battery-powered applications. This low-dropout regulator (LDO) offers foldback current limit, shutdown, thermal protection, and optional active discharge.

7.2 Functional Block Diagram

/c116= 120□·□RL 120□+□RL

  • □COUT TPS7A05 www.ti.com SBVS254C – FEBRUARY 2018– REVISED APRIL 2019 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Excellent Transient Response

The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the device response time during transients. Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the control loop. The device response time across the output voltage range is constant because of the use of a buffered reference topology, which keeps the control loop in unity gain at any output voltage. These features give the device a wide loop bandwidth during transients that ensure excellent transient response while maintaining the device low IQ in steady-state conditions; see the Application and Implementation section for more details.

7.3.2 Active Discharge

Devices with this option have an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated when the device is disabled, in undervoltage lockout (UVLO), or in thermal shutdown. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant: (1) Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.

7.3.3 Low IQ in Dropout

In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs with adaptive biasing. The TPS7A05 detects when operating in dropout and disables the adaptive biasing, minimizing the IQ increase.

7.3.4 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit monitors the input voltage (VIN) to prevent the device from turning on before VIN rises above the lockout voltage. The UVLO circuit also disables the output of the device when VIN falls below the lockout voltage. If the device includes the optional active discharge, the output is connected to ground with a 120-Ω pulldown resistor when VIN is below the lockout voltage; see the Application and Implementation section for more details.

7.3.5 Enable

The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin disables all internal circuits. At the next turn-on, any voltage on the EN pin below the logic low voltage ensures a normal start-up waveform with start-up ramp rate control, provided there is enough time to discharge the output capacitance. If shutdown capability is not required, connect EN to IN. VEN must not exceed VIN.

7.3.6 Internal Foldback Current Limit

The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current; see Figure 29.

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Feature Description (continued) A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is ICL(typical); however, if VOUT is forced to 0 V the current limit is ISC (typical). In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ), thus limiting current to ICL(typical) and, when VOUT is approximately 0 V, current is limited to ISC (typical) to ensure normal start-up into a variety of loads. The foldback current limit is disengaged when IOUT < 1 mA (typical) to reduce IQ. As such, the current-limit loop takes longer to respond to a current-limit event when IOUT < 1 mA (typ). Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.

7.3.7 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (TJ) of the main pass-FET rises to Tsd(Shutdown) (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to Tsd(Reset) (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C reduces long- term reliability. A fast start-up when TJ > Tsd(Reset) (typical, outside of the specified operating range) causes the device thermal shutdown to assert at Tsd(Reset) and prevents the device from turning on until the junction temperature is reduced below Tsd(Shutdown).

7.4 Device Functional Modes

  • Normal operation: The device regulates to the nominal output voltage
  • Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
  • Shutdown: The output of the device is disabled and the discharge circuit is activated Table 1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

7.4.1 Normal Mode

7.4.2 Dropout Mode

7.4.3 Disable Mode

discharged to ground by an internal resistor.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

Y5V-rated capacitors is discouraged because of large variations in capacitance. capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

several inches from the input power source. within the range specified in the Recommended Operating Conditions table for stability.

8.1.3 Special Considerations When Ramping Down VIN and Enable

undesired startup behavior on the next power-on. normal soft-start startup. Figure 48 shows this response. Figure 48. Partial Startup, Shutdown, Normal Startup With VEN = VIN

before the output ramps up with a normal soft-start startup. Figure 49 shows this delay. Figure 49. Long Delay to Startup With VEN = VIN ramp down times for VIN and the EN pin.

8.1.4 Load Transient Response

are where the output voltage is in steady-state.

  • Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B)
  • Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C) During transitions from a heavy load to a light load, the:
  • Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F)
  • Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor.

Figure 50. Load Transient Waveform

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Application Information (continued)

8.1.5 Dropout Voltage

The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass transistor is in the linear region of operation, and the input-to-output resistance of the device is the drain-to-source resistance of the PMOS pass transistor. VDO scales with the output current and changes with temperature because the PMOS pass transistor functions like a resistor in dropout mode. For a graph of dropout voltage, see Figure 22. As with any linear regulator, PSRR and the transient response degrade as (VIN – VOUT) approaches dropout operation. See Figure 23 for dropout performance.

8.1.5.1 Behavior When Transitioning From Dropout Into Regulation

Some applications may have transients that place the device into dropout, especially as this device can be powered from a battery with high ESR. A typical application with these conditions is using a stack of two 1.55-V coin-cell batteries with an ESR of 30 Ω to create a 2.5-V rail and experiencing a load transient from 1 µA to 25 mA. This load transient causes the input supply to drop 750 mV, placing the device into dropout. The load transient saturates the output stage of the error amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load transient is limited because the error amplifier must first recover from saturation and then place the pass element back into active mode. During this time VOUT overshoots because the pass element is functioning as a resistor from VIN to VOUT. This device uses a loop pulldown circuit to help mitigate the overshoot. If operating under these conditions, applying a higher dc load or increasing the output capacitance reduces the overshoot because these solutions provide a path to dissipate the excess charge.

8.1.5.2 Behavior of Output Resulting From Line Transient When in Dropout

The output deviation resulting from a line transient can be significantly higher when the device is operating in dropout. As explained in the Dropout Voltage section, the response time of the error amplifier is limited when in dropout, so the output deviation is larger and can exceed twice the regulated output voltage. Care must be taken in applications where line transients are expected when the device is operating in dropout.

8.1.6 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. See Figure 46 for rising and falling thresholds. Figure 51 depicts the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:

  • Region A: The device does not start until the input reaches the UVLO rising threshold
  • Region B: Normal operation, regulating device
  • Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The output may fall out of regulation but the device is still enabled.
  • Region D: Normal operation, regulating device
  • Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows.
  • Region F: Normal operation followed by the input falling to the UVLO falling threshold
  • Region G: The device is disabled as the input voltage falls below the UVLO falling threshold to 0 V. The output falls as a result of the load and active discharge circuit.

Figure 51. Typical UVLO Operation

8.1.7 Power Dissipation (PD)

must be as free as possible of other heat-generating devices that cause added thermal stresses. across the various interfaces between the die junction and ambient air. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. the ambient air (TA). The equation is rearranged in Equation 5 for output current. resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.7.1 Estimating Junction Temperature

ΨJB) are used in accordance with Equation 6 and are given in the Thermal Information table.

  • PD is the power dissipated as explained in Equation 3
  • TT is the temperature at the center-top of the device package, and
  • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (6)

8.1.7.2 Recommended Area for Continuous Operation

  • Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level; see the Dropout Voltage section for more details.
  • The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification.
  • The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. – Equation 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT increases the output current must decrease.
  • The rated input voltage range governs both the minimum and maximum of VIN – VOUT.

Figure 52. Region Description for Continuous Operation

8.2 Typical Application

Figure 53. Operation From the Battery Input Supply

8.2.1 Design Requirements

Table 2 summarizes the design requirements for Figure 53. Table 2. Design Parameters

8.2.2 Design Considerations

consumed by the regulator shown in Figure 54 allows for long battery life.

8.2.3 Application Curve

Figure 54. IGND vs IOUT at 25°C

9 Power Supply Recommendations

recommended to be used to reduce the impedance of the input supply, especially during transients.

10 Layout

10.1 Layout Guidelines

  • Place input and output capacitors as close to the device as possible
  • Use copper planes for device connections to optimize thermal performance
  • Place thermal vias around the device to distribute heat
  • Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.

10.2 Layout Example

Figure 55. Layout Example for the YKA Package Figure 56. Layout Example for the DBV Package Figure 57. Layout Example for the DQN Package

device product folder on www.ti.com. (2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Spice Models

SPICE models for the TPS7A05 are available through the product folder under Tools & software.

11.1.2 Device Nomenclature

Table 3. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). P is optional; P indicates an active output discharge feature. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Documentation Support

11.2.1 Related Documentation

11.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

SBVS254C –FEBRUARY 2018– REVISED APRIL 2019 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 24-Jun-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PS7A0508PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0512PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0518PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0520PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0522PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0527PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0528PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0530PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PS7A0533PDBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 TPS7A0508PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1C6F TPS7A0508PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1C6F TPS7A0508PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 6G TPS7A0508PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 6G TPS7A0508PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 3 TPS7A0510PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IKF TPS7A0510PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IKF TPS7A0510PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C7 TPS7A0510PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C7

www.ti.com 24-Jun-2019 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7A0510PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 L TPS7A0512PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1ILF TPS7A0512PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1ILF TPS7A0512PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8 TPS7A0512PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8 TPS7A0512PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 M TPS7A0515PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IMF TPS7A0515PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IMF TPS7A0515PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C9 TPS7A0515PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C9 TPS7A0515PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 N TPS7A051825PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 P TPS7A0518PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1INF TPS7A0518PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1INF TPS7A0518PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CA TPS7A0518PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CA TPS7A0518PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 P TPS7A0522PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1P3F

www.ti.com 24-Jun-2019 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7A0522PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1P3F TPS7A0525PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IOF TPS7A0525PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IOF TPS7A0525PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CB TPS7A0525PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CB TPS7A0525PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 Q TPS7A05285PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IRF TPS7A05285PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IRF TPS7A05285PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CC TPS7A05285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CC TPS7A05285PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 R TPS7A0528PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DH TPS7A0528PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DH TPS7A0530PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1QWF TPS7A0530PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1QWF TPS7A0530PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DG TPS7A0530PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DG TPS7A0530PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 W

www.ti.com 24-Jun-2019 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7A0531PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1P4F TPS7A0531PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1P4F TPS7A0533PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IPF TPS7A0533PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1IPF TPS7A0533PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CD TPS7A0533PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CD TPS7A0533PYKAR ACTIVE DSBGA YKA 4 12000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 24-Jun-2019 Addendum-Page 5 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Apr-2019 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Apr-2019 Pack Materials-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A0508PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0508PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0508PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0508PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0508PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0510PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0510PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0510PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0510PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0510PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0512PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0512PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0512PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0512PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0512PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0515PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0515PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0515PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0515PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0515PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Apr-2019 Pack Materials-Page 3

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A051825PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0518PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0518PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0518PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0518PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0518PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0522PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0522PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0525PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0525PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0525PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0525PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0525PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A05285PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A05285PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A05285PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A05285PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A05285PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0528PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0528PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0530PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0530PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0530PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0530PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0530PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 TPS7A0531PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0531PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0533PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS7A0533PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS7A0533PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TPS7A0533PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TPS7A0533PYKAR DSBGA YKA 4 12000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Apr-2019 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE C TYP0.20 0.08 0.25 2.64 2.10

1.12 MAX

TYP0.10 0.01 3X 0.5 0.3 TYP0.6 0.2 1.9 0.95 TYP -80 A 3.04 2.80 B1.4 1.2 (0.95) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/C 04/2017 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG

www.ti.com PACKAGE OUTLINE C0.4 MAX 0.18 0.13

0.35 TYP

4X 0.25 0.15 0.35 TYP B E A D 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C 1 2

0.015 C A B

B A SCALE 14.000 D: Max = E: Max = 0.694 mm, Min = 0.694 mm, Min = 0.634 mm 0.634 mm

www.ti.com EXAMPLE BOARD LAYOUT 4X ( 0.2) (0.35) TYP (0.35) TYP ( 0.2) METAL 0.0325 MAX ( 0.2) SOLDER MASK OPENING

0.0325 MIN

DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X 1 2 A B NON-SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4X ( 0.21) (R0.05) TYP METAL TYP 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm - 0.1 mm THICK STENCIL SCALE:60X 1 2 A B

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9

1.45 MAX

0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/D 11/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/D 11/2018 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/D 11/2018 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes. 5. Shape of exposed side leads may differ. 6. Number and location of exposed tie bars may vary. www.ti.com B A SEATING PLANE C 0.08 PIN 1 INDEX AREA

0.1 C A B

0.05 C PIN 1 ID (OPTIONAL) NOTE 4 EXPOSED THERMAL PAD 2 3 1.05 0.95 1.05 0.95

0.4 MAX

2X 0.65 0.48+0.12 -0.1 3X 0.30 0.15 0.3 0.2 4X 0.28 0.15 0.05 0.00 (0.11) NOTE 5 NOTE 6 NOTE 6 (0.07) TYP (0.05) TYP

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: (continued) 7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented. www.ti.com SOLDER MASK DEFINED SOLDER MASK DETAIL

0.05 MIN

SCALE: 40X SYMM SYMM 4X (0.21) 4X (0.36) (0.65) (0.86) ( 0.48) SEE DETAIL 4X (0.18) (0.22) TYP EXPOSED METAL CLEARANCE (0.03) EXPOSED METAL

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1mm THICK STENCIL EXPOSED PAD 88% PRINTED SOLDER COVERAGE BY AREA SCALE: 60X SYMM SYMM SOLDER MASK EDGE 4X (0.21) 4X (0.4) (0.65) (0.9) ( 0.45) 4X (0.03) 4X (0.235) 4X (0.22)

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