PS7A0508PDBVT

TPS7A05 TI1 | Alldatasheet

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ADVANCE□INFORMATION TPS7A05 IN EN OUT GND C OUT C IN ON OFF Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS7A05 SBVS254 – FEBRUARY 2018 TPS7A051-µAIQ,200-mA,UltralowIQLow-DropoutRegulator ina1-mm×1-mmPackage

1 Features

1• Ultralow IQ: 1 µA (typ), 2 µA (max)

Excellent Transient Response
Packages: – 1.0-mm × 1.0-mm X2SON (4) – 0.70-mm × 0.70-mm DSBGA (4) – SOT-23 (5)
Input Voltage Range: 1.4 V to 5.5 V
Output Accuracy: 1% Typical, 1.5% Maximum
Available in Fixed-Output Voltage: – 0.8 V to 3.3 V
Very Low Dropout: – 204 mV (max) at 200 mA (3.3 VOUT)
Active Output Discharge
Foldback Current Limit
Stable With a 0.1-µF or Larger Capacitor

2 Applications

Wearable Electronics
Ultrabooks, Tablets, eReaders
Always-On Power Supplies
Set-Top Boxes
Gaming Controllers, Remote Controls, Toys, Drones
Wireless Handsets and Smart Phones
Portable and Battery-Powered Equipment

3 Description

The TPS7A05 device is an ultra-small, low quiescent current low-dropout regulator (LDO) that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. The TPS7A05, with ultralow IQ (1 µA), is designed specifically for battery-powered applications where very-low quiescent current is a critical parameter for extending battery life. The device can be operated from rechargeable Li-Ion batteries, Li-primary battery chemistries such as Li-SOCl2, Li-MnO2, as well as two- or three-cell alkaline batteries. The TPS7A05 is available with an active pulldown circuit to quickly discharge output loads when disabled. The TPS7A05 is fully specified for TJ = –40°C to +125°C operation, and is available in standard X2SON (DQN), SOT-23 (DBV), and DSBGA (YKA) packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS7A05 X2SON (4) 1.00 mm × 1.00 mm DSBGA (4) 0.70 mm × 0.70 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Circuit

11.2 Receiving Notification of Documentation Updates 17

12 Mechanical, Packaging, and Orderable

4 Revision History

February 2018 *

ADVANCE□INFORMATION 1 2 B A Not to scale EN GND IN OUT 1 2 A B Not to scale IN OUT EN GND 1IN 2GND 3EN 4 NC

5 OUT

5 Pin Configuration and Functions

1-mm × 1-mm X2SON-4 Top View 5-Pin SOT-23 Top View 4-Pin DSBGA, 0.35-mm pitch Top View 4-Pin DSBGA, 0.35-mm pitch Bottom View Pin Functions PIN I/O DESCRIPTIONNAME DQN DBV YKA IN 4 1 A1 Input Input pin. A 0.1-µF or greater effective capacitance is required from IN to ground and as close as possible to the device to minimize input impedance. For best transient response, use a 1-µF or larger ceramic capacitor from IN to ground. Place the input capacitor as close to input of the device as possible. EN 3 3 B1 Input Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. VEN must not exceed VIN. GND 2 2 B2 — Ground pin. This pin must be connected to ground and the thermal pad. OUT 1 5 A2 Output Regulated output pin. A 0.1-µF or greater effective capacitance is required from OUT to ground and as close as possible to the device for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT to ground. Place the output capacitor as close to output of the device as possible. NC — 4 — — No connect pin. This pin is not internally connected. Connect to ground or leave floating. Thermal pad Pad — — — Connect the thermal pad to a large-area ground plane.

ADVANCE□INFORMATION TPS7A05 SBVS254 – FEBRUARY 2018 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Maximum is VIN + 0.3 V or 3.6 V, whichever is smaller.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage IN –0.3 6.0 VEN –0.3 VIN + 0.3 OUT –0.3 3.6(2) Current OUT Internally limited A Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Fixed output options are available within this range in 50-mV increments. Texas Instruments offers samples of any available output voltage option upon customer request. For production of a specific voltage not normally released, minimum order quantities may apply; sample availability may also be limited. Contact your TI representative for additional information.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage 1.4 VOUT + VDO(max) + 0.1 5.5 V VEN Enable supply voltage 0 VIN V VOUT Nominal output voltage range(1) 0.8 3.3 mA IOUT Output current 0 200 mA CIN Input capacitance 0.1 1 µF COUT Output capacitance 0.5 1 22 µF TJ Operating junction temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS7A05 UNITDBV (SOT-23) DQN (X2SON) YKA (DSBGA)

5 PINS 4 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 185.6 144.1 198.0 °C/W RθJC(top) Junction-to-case(top) thermal resistance 104.3 137.9 2.1 °C/W RθJB Junction-to-board thermal resistance 54.5 83.5 66.9 °C/W ψJT Junction-to-top characterization parameter 31.0 5.3 0.9 °C/W ψJB Junction-to-board characterization parameter 54.5 83.8 67.0 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance n/a 71.8 n/a °C/W

ADVANCE□INFORMATION TPS7A05 www.ti.com SBVS254 – FEBRUARY 2018 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) VIN = 1.4 V for VOUT ≤ 0.9 V. (2) Load Regulation is normalized to the output voltage at IOUT = 1 mA. (3) Dropout is measured by ramping VIN down until VOUT = VOUT (nom) – 5%, with IOUT = 200 mA.

6.5 Electrical Characteristics

at VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); over recommended junction temperature range (TJ = –40°C to +125°C); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 1.4 5.5 V VOUT Nominal output voltage range 0.8 3.3 V Nominal accuracy TJ = 25°C –1 1 %VOUT Accuracy over temperature VOUT ≥ 1.0 V, TJ = –40°C to +85°C –1.5 1.5 %VOUT VOUT ≥ 1.0 V –3 3 VOUT < 1.0 V, TJ = –40°C to +85°C –15 15 mV VOUT < 1.0 V –30 30 ΔVOUT/ΔVIN Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(1), TJ = –40°C to +85°C 2.2 3 mV/V VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(1) 4 ΔVOUT/ΔIOUT Load regulation(2) 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V, TJ = –40°C to +85°C 20 38 mV 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V 50 IGND Ground current TJ = 25°C, IOUT = 1 µA 0.7 1 1.3 µAIOUT = 1 µA, TJ = –40°C to +85°C 2 IOUT = 1 µA 4 ISHDN Shutdown current VEN = 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C 100 300 nA ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.1 V 240 450 650 mA ISC Short-circuit current limit VOUT = 0 V 65 mA VDO Dropout voltage(3) 0.8 V ≤ VOUT < 1.0 V, TJ = –40°C to +85°C 1046 mV 1.0 V ≤ VOUT < 1.2 V, TJ = –40°C to +85°C 876 1.2 V ≤ VOUT < 1.5 V, TJ = –40°C to +85°C 670 1.5 V ≤ VOUT < 1.8 V, TJ = –40°C to +85°C 446 1.8 V ≤ VOUT < 2.5 V, TJ = –40°C to +85°C 336 2.5 V ≤ VOUT < 3.3 V, TJ = –40°C to +85°C 250 VOUT = 3.3 V, TJ = –40°C to +85°C 204 0.8 V ≤ VOUT < 1.0 V 1114 1.0 V ≤ VOUT < 1.2 V 953 1.2 V ≤ VOUT < 1.5 V 803 1.5 V ≤ VOUT < 1.8 V 535 1.8 V ≤ VOUT < 2.5 V 403 2.5 V ≤ VOUT < 3.3 V 299 VOUT = 3.3 V 245 PSRR Power-supply rejection ratio f = 1 kHz, IOUT = 30 mA 40 dBf = 500 kHz, IOUT = 30 mA 30 f = 1 MHz, IOUT = 30 mA 40 VN Output voltage noise BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 30 mA 180 µVRMS VUVLO UVLO threshold VIN rising 1.23 1.3 1.37 V VUVLO(HYST) UVLO hysteresis VIN falling 40 mV VEN(HI) EN pin logic high voltage 0.9 V VEN(LO) EN pin logic low voltage 0.4 V

ADVANCE□INFORMATION TPS7A05 SBVS254 – FEBRUARY 2018 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) at VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); over recommended junction temperature range (TJ = –40°C to +125°C); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IEN EN pin current VEN = VIN = 5.5 V 10 nA RPULL-DOWN Pulldown resistor VIN = 3.3 V 120 Ω Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 Reset, temperature decreasing 140

6.6 Switching Characteristics

at VIN = VOUT + VDO(max) + 0.5 V, IOUT = 30 mA, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTR Start-up time From EN assertion to VOUT = 95% × VOUT(nom) , VOUT = 1.8 V 1.5 ms

ADVANCE□INFORMATION Current Limit 1.2-V Bandgap Thermal Shutdown Error Amp Internal Controller OUT EN IN GND Active Discharge P-Version Only UVLO TPS7A05 www.ti.com SBVS254 – FEBRUARY 2018 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS7A05 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance. These characteristics make the TPS7A05 ideal for most battery-powered applications. This low-dropout regulator (LDO) offers optional active discharge, foldback current limit, shutdown, and thermal protection.

7.2 Functional Block Diagram

ADVANCE□INFORMATION /c116= 120□·□RL 120□+□RL

□COUT TPS7A05 SBVS254 – FEBRUARY 2018 www.ti.com Product Folder Links: TPS7A05 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Excellent Transient Response

The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the device response time to transients. Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the loop. The device response time across the output voltage range is constant because of the use of a buffered reference topology, which keeps the control loop in unity gain at any output voltage. These features give the device a wide loop bandwidth during transients that ensure excellent transient response while maintaining the device low IQ in steady-state conditions; see the Application and Implementation section for more details.

7.3.2 Active Discharge

The device has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated by an enable, undervoltage lockout (UVLO), or thermal shutdown. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant: (1) Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current for a short period of time.

7.3.3 Low IQ in Dropout

In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs with adaptive biasing. The TPS7A05 detects when operating in dropout conditions and disables the adaptive biasing, minimizing the IQ increase.

7.3.4 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit monitors the input voltage (VIN) to prevent the device from turning on before VIN rises above the lockout voltage. The UVLO circuit also disables the output of the device when VIN falls below the lockout voltage. If the device includes the optional active discharge, the output is connected to ground with a 120-Ω pulldown resistor when VIN is below the lockout voltage; see the Application and Implementation section for more details.

7.3.5 Enable

The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is greater than its rising voltage threshold (0.9 V, maximum), and the output of the device is turned off when the enable pin voltage is less than its falling voltage threshold (0.35 V, minimum). A voltage less than 0.35 V on the enable pin disables all internal circuits. At the next turn-on, this voltage ensures a normal start-up waveform with in-rush control, provided there is enough time to discharge the output capacitance. If shutdown capability is not required, connect EN to IN. VEN must not exceed VIN.

7.3.6 Internal Foldback Current Limit

The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current.

ADVANCE□INFORMATION TPS7A05 www.ti.com SBVS254 – FEBRUARY 2018 Product Folder Links: TPS7A05 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Feature Description (continued) A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is 450 mA (typical); however, if VOUT is forced to 0 V the current limit is 50 mA (typical). In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ), thus limiting current to 450 mA, and when VOUT is approximately 0 V, current is limited to 65 mA to ensure normal start-up into a variety of loads. The foldback current limit is disengaged when IOUT < 1 mA (typical) to reduce IQ. As such, the current-limit loop takes longer to respond to a current-limit event when IOUT < 1 mA (typ). Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.

7.3.7 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (TJ) of the main pass-FET rises to 160°C (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C reduces long- term reliability. A fast start-up when TJ > 140°C (typical, outside of the specified operating range) causes the device thermal shutdown to assert at TSD(rising) and prevents the device from turning on until the junction temperature is reduced below TSD(falling).

7.4 Device Functional Modes

Normal operation: The device regulates to the nominal output voltage
Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
Shutdown: The output of the device is disabled and the discharge circuit is activated Table 1 shows the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

7.4.1 Normal Mode

7.4.2 Dropout Mode

7.4.3 Disable Mode

discharged to ground by an internal resistor.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

Y5V-rated capacitors is discouraged because of large variations in capacitance. recommended herein account for a effective capacitance derating of approximately 50%.

8.1.2 Input and Output Capacitor Requirements (CIN and COUT)

greater of effective capacitance) at the input and output. The maximum recommended output capacitor is 22 µF.

8.1.3 Load Transient Response

broken down as described in this section. Regions A, E, and H are where the output voltage is in steady-state.

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B)
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C) During transitions from a heavy load to a light load, the:
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F)
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor.

Figure 1. Load Transient Waveform

8.1.4 Dropout Voltage

voltage is linearly proportional to the output current because the device is operating as a resistive switch. (VIN – VOUT) approaches dropout operation. Figure 2. Maximum Dropout Voltage vs Output Voltage

8.1.4.1 Behavior When Transitioning From Dropout Into Regulation

mA. This load transient causes the input supply to drop 750 mV, placing the device into dropout. from VIN to VOUT. This device uses a loop pulldown circuit to help mitigate the overshoot. overshoot because these solutions provide a path to dissipate the excess charge.

8.1.5 Undervoltage Lockout (UVLO) Operation

Region A: The device does not start until the input reaches the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The output may fall out of regulation but the device is still enabled.
Region D: Normal operation, regulating device

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold
Region G: The device is disabled as the input voltage falls below the UVLO falling threshold to 0 V. The output falls as a result of the load and active discharge circuit.

Figure 3. Typical UVLO Operation

8.1.6 Power Dissipation (PD)

must be as free as possible of other heat-generating devices that cause added thermal stresses. resistance across the various interfaces between the die junction and ambient air. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. the ambient air (TA). The equation is rearranged in Equation 5 for output current. resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.6.1 Estimating Junction Temperature

ΨJB) are given in the Thermal Information table and are used in accordance with Equation 6.

PD is the power dissipated as explained in Equation 3
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (6)

8.1.6.2 Recommended Area for Continuous Operation

Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level; see the Dropout Voltage section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. – Equation 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.

Figure 4. Region Description of Continuous Operation Regime

8.2 Typical Application

Figure 5. Capacitor-Free Operation From Battery Input Supply

8.2.1 Design Requirements

Table 2 summarizes the design requirements for Figure 5. Table 2. Design Parameters

8.2.2 Design Considerations

9 Power Supply Recommendations

recommended to be used to reduce the impedance of the input supply, especially during transients.

10 Layout

10.1 Layout Guidelines

Place input and output capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.

10.2 Layout Example

Figure 6. Layout Example for the YKA Package Figure 7. Layout Example for the DBV Package Figure 8. Layout Example for the DQN Package

device product folder on www.ti.com. (2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). the output when the device is disabled. YYY is the package designator. Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 9-Mar-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples P7A05285PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0508PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0510PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0512PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0515PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0518PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0525PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 PS7A0533PDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 9-Mar-2018 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP0.22 0.08 0.25 3.0 2.6 2X 0.95 1.9

1.45 MAX

TYP0.15 0.00 5X 0.5 0.3 TYP0.6 0.3 TYP8 1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/C 04/2017 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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Summary

1-uA IQ, 200-mA, Ultralow IQ Low-Dropout Regulator in a 1-mm x 1-mm Package

Description