TPS737 TI | Alldatasheet
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Technical content
TPS737 1-A Low-Dropout Regulator With Reverse Current Protection
1 Features
- Stable with 1-μF or larger ceramic output capacitor
- Input voltage range: 2.2 V to 5.5 V
- Ultra-low dropout voltage: 130 mV typical at 1 A
- Excellent load transient response—even with only 1-μF output capacitor
- NMOS topology delivers low reverse leakage current
- Initial accuracy: 1%
- Overall accuracy over line, load, and temperature:
- Less than 20 nA typical IQ in shutdown mode
- Thermal shutdown and current limit for fault protection
- Available in multiple output voltage versions: – Adjustable output: 1.20 V to 5.5 V – Custom outputs available using factory package-level programming
- M3-suffix devices are Advance Information only
2 Applications
- Point-of-load regulation for DSPs, FPGAs, ASICs, and microprocessors
- Post-regulation for switching supplies
- Portable and battery-powered equipment
3 Description
The TPS737 linear low-dropout (LDO) voltage regulator uses an NMOS pass transistor in a voltage- follower configuration. This topology is relatively insensitive to the output capacitor value and ESR, allowing for a wide variety of load configurations. Load transient response is excellent, even with a small 1-μF ceramic output capacitor. The NMOS topology also allows for very low dropout. The TPS737 uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Part numbers with the M3 suffix use an updated design on the latest TI process technology. Current consumption, when not enabled, is less than 20 nA and is designed for portable applications. This device is protected by thermal shutdown and foldback current limit. For applications that require higher output voltage accuracy, consider TI's TPS7A37 1% overall accuracy, 1-A low-dropout voltage regulator.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TPS737 DRB (VSON, 8) 3 mm × 3 mm DCQ (SOT-223, 6) 6.5 mm × 7.06 mm DRV (WSON, 6) 2 mm × 2 mm TPS737 (M3 suffix)(3) DRB (VSON, 8) 3 mm × 3 mm (1) For more information, see the Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Advance information (not Production Data). Specifications subject to change. TPS737xx GNDEN FB IN OUTVIN VOUT Optional
1.0 F/c109
Typical Application Circuit TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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4 Pin Configuration and Functions
TAB□IS□GND6 Figure 4-1. DCQ Package, 6-Pin SOT-223 (Top View) IN N/C N/C EN OUT N/C NR/FB GND Figure 4-2. DRB Package, 8-Pin VSON (Top View) IN N/C EN OUT NR/FB GND A. Power dissipation can limit operating range. Check the Thermal Information table. Figure 4-3. DRV Package(A), 6-Pin WSON (Top View) Table 4-1. Pin Functions PIN I/O DESCRIPTION NAME SOT-223 VSON WSON IN 1 8 6 I Unregulated input supply GND 3, 6 4, Pad 3, Pad — Ground EN 5 5 4 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See the Enable Pin and Shutdown section for more details. EN must not be left floating and can be connected to IN if not used. NR 4 3 2 — Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal band gap, reducing output noise to very low levels. FB 4 3 2 I Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 2 1 1 O Regulator output. A 1.0-μF or larger capacitor of any type is required for stability. NC — 2, 6, 7 5 — Not connected www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS737
5 Specifications
5.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage VIN –0.3 6 V VEN –0.3 6 VOUT –0.3 5.5 VNR, VFB –0.3 6 Peak output current IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation PDISS See Thermal Information Temperature Junction, TJ –55 150 Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22- C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage 2.2 5.5 V IOUT Output current 0 1 A TJ Operating junction temperature –40 125 °C TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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5.4 Thermal Information
THERMAL METRIC(1) TPS737(2) UNITDRB (VSON) DRB (VSON) M3(10) DCQ (SOT-223) DRV (WSON)(3)
8 PINS 8 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance(4) 49.5 47.7 53.1 67.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance(5) 58.9 68.9 35.2 87.6 °C/W RθJB Junction-to-board thermal resistance(6) 25.1 20.6 7.8 36.8 °C/W ψJT Junction-to-top characterization parameter(7) 1.7 3.4 2.9 1.8 °C/W ψJB Junction-to-board characterization parameter(8) 25.2 20.6 7.7 37.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance(9) 8.6 3.5 N/A 7.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application note. (2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: a. i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array. . iii. DRV: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array. Due to size limitation of thermal pad, 0.8-mm pitch array is used which is off the JEDEC standard. b. The top copper layer has a detailed copper trace pattern. The bottom copper layer is assumed to have a 20% thermal conductivity of copper, representing a 20% copper coverage. c. These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. (3) Power dissipation can limit operating range. (4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain RθJA using a procedure described in JESD51-2a (sections 6 and 7). (8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain RθJA using a procedure described in JESD51-2a (sections 6 and 7). (9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (10) M3-suffix devices are Advance Information only. www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS737
5.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 1 V(1), IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage(1) (2) 2.2 5.5 V VFB Internal reference (DCQ package) TJ = 25°C 1.198 1.204 1.21 V Internal reference (DRB and DRV packages) TJ = 25°C 1.192 1.204 1.216 VOUT Output voltage (TPS73701)(3) VFB 5.5 – VDO V Accuracy(1) (4) Nominal TJ = 25°C –1 1 5.36 V < VIN < 5.5 V, VOUT = 5.08 V, 10 mA < IOUT < 800 mA, –40°C < TJ < 85°C, TPS73701 (DCQ) –2 2 Over VIN, IOUT, and T VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 1 A, legacy silicon –3 ±0.5 3 VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 1A, new silicon, M3 suffix -1.5 ±0.5 1.5 ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.01 %/V ΔVOUT(ΔIOUT) Load regulation 1 mA ≤ IOUT ≤ 1 A 0.002 %/mA 10 mA ≤ IOUT ≤ 1 A 0.0005 VDO Dropout voltage(5) (VIN = VOUT(nom) – 0.1 V) IOUT = 1 A, legacy silicon 130 500 mV IOUT = 1 A, new silicon, M3 suffix 122 250 ZOUT(DO) Output impedance in dropout 2.2 V ≤ VIN ≤ VOUT + VDO 0.25 Ω ICL Output current limit VOUT = 0.9 × VOUT(nom) 1.05 1.6 2.2 A IOS Short-circuit current VOUT = 0 V, legacy silicon 450 mA VOUT = 0 V, new silicon, M3 suffix 510 IREV Reverse leakage current(6) (–IIN) VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT 0.1 μA IGND GND pin current IOUT = 10 mA 400 μAIOUT = 1 A, legacy silicon 1300 IOUT = 1 A, new silicon, M3 suffix 880 ISHDN Shutdown current (IGND) VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 20 nA IFB FB pin current (TPS73701) 0.1 0.6 μA PSRR Power-supply rejection ratio (ripple rejection) f = 100 Hz, IOUT = 1 A 58 dB f = 10 kHz, IOUT = 1 A 37 Vn Output noise voltage BW = 10 Hz to 100 kHz COUT = 10 μF 27 × VOUT μVRMS tSTR Start-up time VOUT = 3 V, RL = 30 Ω, COUT = 1 μF 600 μsVOUT = 3 V, RL = 30 Ω, COUT = 1 μF, M3 suffix 431 VEN(HI) EN pin high (enabled) 1.7 VIN V VEN(LO) EN pin low (shutdown) 0 0.5 V IEN(HI) EN pin current (enabled) VEN = 5.5 V 20 nA Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 Reset, temperature decreasing 140 TJ Operating junction temperature –40 125 °C (1) Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater. (2) For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and can result in an overvoltage condition on the output. To avoid this situation, disable the device before powering down VIN. (3) The TPS73701 is tested at VOUT = 1.2 V. (4) Tolerance of external resistors not included in this specification. (5) VDO is not measured for fixed output versions with VOUT(nom) < 2.3 V because minimum VIN = 2.2 V. (6) Fixed-voltage versions only; see the Application Information section for more information. TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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5.6 Typical Characteristics
for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted) 0.5 0.4 0.3 0.2 0.1 /c45 0.1 /c45 0.2 /c45 0.3 /c45 0.4 /c45 0.5 Change□in□V (%) OUT 0 100 200 300 400 500 600 700 800 900 1000 I (mA)OUT Referred□to□I =□10mAOUT /c45 40 C/c176 +125 C/c176 +25 C/c176 Figure 5-1. Load Regulation 0.20 0.15 0.10 0.05 /c45 0.05 /c45 0.10 /c45 0.15 /c45 0.20 Change□in□V (%) OUT V V/c45 (V)IN OUT +125 C/c176 +25 C/c176 /c45 /c176 40 C Referred□to□V =□V +□1.0V□at□I =□10mAIN OUT OUT Figure 5-2. Line Regulation 200 180 160 140 120 100 V (mV) DO 0 100 200 300 400 500 600 700 800 900 1000 I (mA)OUT +125/c176 C +25/c176 C V =□2.5VOUT /c45 40 C/c176 Figure 5-3. Dropout Voltage vs Output Current 200 180 160 140 120 100 V (mV) DO /c45 50 /c45 25 0 25 50 75 100 150 T emperature□( C)/c176 125 Figure 5-4. Dropout Voltage vs Temperature Percent□of□Units□(%) V Error (%)OUT I =□10mAOUT Figure 5-5. Output Voltage Histogram Percent□of□Units□(%) /c45100/c4590 /c4580 /c4570 /c4560 /c4550 /c4540 /c4530 /c4520 /c4510 0 10 20 30 40 50 60 70 80 90 100 Worst□Case□dV /dT□(ppm/ /c176 C)OUT I =□10mAOUT Figure 5-6. Output Voltage Drift Histogram www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS737
5.6 Typical Characteristics (continued)
for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted) 2500 2000 1500 1000 500 I ( /c109A) GND 0 200 400 600 800 1000 I (mA)OUT V =□5.0VIN V =□3.3VIN V =□2.2VIN Figure 5-7. Ground Pin Current vs Output Current 3000 2500 2000 1500 1000 500 I ( A) /c109 GND /c45 50 /c45 25 0 25 50 75 100 125 T emperature□(/c176 C) I =□1AOUT V =□5.0VIN V =□3.3VIN V =□2.2VIN Figure 5-8. Ground Pin Current vs Temperature 0.1 0.01 I ( /c109A) GND /c45 50 /c45 25 0 25 50 75 100 125 T emperature (/c176 C) V =□0.5VENABLE V =□V +□0.5VIN OUT Figure 5-9. Ground Pin Current in Shutdown vs Temperature Output Current (A) Output Voltage (V) ICL ISC 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.5 V = 3.3VOUT Figure 5-10. Current Limit vs VOUT (Foldback) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Current□Limit□(A) V (V)IN Figure 5-11. Current Limit vs VIN 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Current□Limit□(A) /c45 50 /c45 25 0 25 50 75 100 125 T emperature□(/c176 C) V =□1.2VOUT Figure 5-12. Current Limit vs Temperature TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted) 10k10 Ripple□Rejection□(dB) 100 1k 100k 1M 10M Frequency□(Hz) I =□1mAOUT C =□1 /c109FOUT I =□1mAOUT C =□AnyOUT I =□1mAOUT C =□10 /c109FOUT I =□100mAOUT C =□AnyOUT I =□100mAOUT C =□10 /c109FOUT I =□100mAO C =□1 /c109FO Figure 5-13. PSRR (Ripple Rejection) vs Frequency PSRR□(dB) V V/c45 (V)IN OUT Frequency□=□10kHz C =□10 F V =□2.5V I =□100mA /c109OUT OUT OUT Figure 5-14. PSRR (Ripple Rejection) vs (VIN – VOUT) 0.1 0.01 e V/ /c109 /c214( Hz) N 10 100 1k 10k 100k Frequency□(Hz) C =□1 F /c109OUT C =□10 F /c109OUT I =□150mAOUT Figure 5-15. Noise Spectral Density V (uVrms) N C (F)FF 10p 100p 1n 10n V = 2.5VOUT C = 0 F μOUT R = 39.2kΩ1 10Hz < Frequency < 100kHz Figure 5-16. TPS73701 RMS Noise Voltage vs CFB V N (uVrms) C (mF)OUT 0.1 1 10 VOUT = 5.0V VOUT = 3.3V VOUT = 1.5V CNR = 0.01 F μ 10Hz < Frequency < 100kHz Figure 5-17. RMS Noise Voltage vs COUT 140 120 100 V N (uVrms) CNR (F) 1p 10p 100p 1n 10n VOUT = 5.0V VOUT = 3.3V VOUT = 1.5V COUT = 0 F μ 10Hz < Frequency < 100kHz Figure 5-18. RMS Noise Voltage vs CNR www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS737
for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted) 10 s/div/c109 200mV/div VOUT IOUT C =□10nFNR C =□10 FOUT /c109 10mA Figure 5-19. TPS73733 Load Transient Response 10 s/div/c109 100mV/div VOUT VIN C =□10nFNR C =□10 FOUT /c109 4.3V 5.3V Figure 5-20. TPS73733 Line Transient Response 100 s/div/c109 1V/div 1V/div V OUT VEN R =□20 /c87L C =□10 F /c109OUT R =□20 /c87L C =□1 F /c109OUT Figure 5-21. TPS73701 Turnon Response 100 s/div/c109 1V/div 1V/div V OUT VEN R =□20 /c87L C =□10 F /c109OUT R =□20 /c87L C =□1 F /c109OUT Figure 5-22. TPS73701 Turnoff Response /c451 /c452 Volts 50ms/div VIN VOUT Figure 5-23. TPS73701, VOUT = 3.3-V Power Up and Power Down 0.1 0.01 I (nA)ENABLE /c45 50 /c45 25 0 25 50 75 100 125 T emperature (/c176 C) Figure 5-24. IEN vs Temperature TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF (unless otherwise noted) V (V ) N RMS C (F)FB 10p 100p 1n 10n V =□2.5VOUT C =□0 F /c109OUT R =□39.2k /c871 Figure 5-25. TPS73701 RMS Noise Voltage vs CFB 160 140 120 100 I (nA)FB /c45 50 /c45 25 0 25 50 75 100 125 T emperature□( C)/c176 Figure 5-26. TPS73701 IFB vs Temperature 10 s/div/c109 100mV/div VOUT IOUT 250mA 10mA C =□10 F /c109OUT C =□10nFFB R =□39.2k /c871 Figure 5-27. TPS73701 Load Transient, Adjustable Version 5 s/div/c109 100mV/div VOUT VIN 4.5V 3.5V C =□10 F /c109OUT V =□2.5VOUT C =□10nFFB Figure 5-28. TPS73701 Line Transient, Adjustable Version www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS737
6 Detailed Description
6.1 Overview
The TPS737 is a low-dropout (LDO) regulator that uses an n-type field effect (NMOS) pass transistor to achieve ultra-low dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features combined with an enable input make the TPS737 designed for portable applications. This regulator offers a wide selection of fixed-output voltage versions and an adjustable-output version. All versions have thermal and overcurrent protection, including foldback current limit.
6.2 Functional Block Diagrams
27kΩ 8kΩ Current Limit Thermal Protection Bandgap NR OUT EN GND IN R1 + R2 = 80kΩ 4MHz Charge Pump Figure 6-1. Fixed-Voltage Version TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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1.2 V 1.5 V 1.8 V 2.5 V 2.8 V 3.0 V 3.3 V Short 23.2 k/c87 28.0 k/c87 39.2 k/c87 44.2 k/c87 46.4 k/c87 52.3 k/c87 Open 95.3 k/c87 56.2 k/c87 36.5 k/c87 33.2 k/c87 30.9 k/c87 30.1 k/c87 NOTE: V OUT = (R1 + R2)/R2 /c1801.204; R1 || R2 /c64 19 k/c87 for best accuracy. Servo Error Amp Ref Current Limit Thermal Protection Bandgap OUT FB EN GND IN 80 k/c878 k/c87 27 k/c87 4-MHZ Charge Pump Standard 1% Resistor Values for Common Output Voltages Figure 6-2. Adjustable-Voltage Version
6.3 Feature Description
6.3.1 Output Noise
A precision band-gap reference is used to generate the internal reference voltage, V ref. This reference is the dominant noise source within the TPS737xx and generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: OUT1 2 N RMS RMS
2 REF
V(R R )V 32 V 32 V R V /c43/c61 /c109 /c180 /c61 /c109 /c180 (1) Because the value of VR is 1.2 V, this relationship reduces to: RMS N RMS OUT VV ( V ) 27 V (V ) V /c109/c230 /c246/c109 /c61 /c180 /c231 /c247 /c232 /c248 (2) for the case of no CNR. An internal 27-k Ω resistor in series with the noise-reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise-reduction capacitor, C NR, is connected from NR to ground. For C NR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship: /c109VRMS V (3) for CNR = 10 nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS737
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, C FB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance. Limit this capacitor to 0.1 µF. The TPS737 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass transistor above V OUT. The charge pump generates approximately 250 μV of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.
6.3.2 Internal Current Limit
The TPS737 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps protect the regulator from damage during output short-circuit conditions by reducing current limit when V OUT drops below 0.5 V. See Figure 5-10 in the Typical Characteristics section. From Figure 5-10, approximately –0.2 V of V OUT results in a current-limit of 0 mA. Therefore, if OUT is forced below –0.2 V before EN goes high, the device can possibly not start up. In applications that work with both a positive and negative voltage supply, the TPS737 must be enabled first.
6.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and compatible with standard TTL-CMOS levels. V EN below 0.5 V (maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated V OUT (see Figure 5-21). When shutdown capability is not required, EN can be connected to V IN. However, the pass transistor can possibly not be discharged using this configuration, and the pass transistor can be left on (enhanced) for a significant time after V IN is removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power up. In addition, for V IN ramp times slower than a few milliseconds, the output can overshoot upon power up. Current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section for more information.
6.3.4 Reverse Current
The NMOS pass transistor of the TPS737 provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass transistor is pulled low. To make sure that all charge is removed from the gate of the pass transistor, the EN pin must be driven low before the input voltage is removed. If the EN pin is not driven low, the pass transistor can be left on because of stored charge on the gate. After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Reverse current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin. There is additional current flowing into the OUT pin as a result of the 80-k Ω internal resistor divider to ground (see Figure 6-1 and Figure 6-2). For the TPS73701, reverse current can flow when VFB is more than 1.0 V above VIN.
6.4 Device Functional Modes
Driving the EN pin over 1.7 V turns on the regulator. Driving the EN pin below 0.5 V causes the regulator to enter shutdown mode. In shutdown, the current consumption of the device is reduced to 20 nA, typically. TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Application Information
The TPS737 low-dropout (LDO) regulator uses an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS737 designed for portable applications. This regulator offers a wide selection of fixed-output voltage versions and an adjustable-output version. All versions have thermal and overcurrent protection, including foldback current-limit.
7.2 Typical Application
Figure 7-1 shows the basic circuit connections for the fixed-voltage models. Figure 7-2 gives the connections for the adjustable output version (TPS73701). TPS737xx GNDEN IN OUTVIN VOUT ON OFF Figure 7-1. Typical Application Circuit for Fixed-Voltage Versions TPS73701 GNDEN FB IN OUTVIN VOUT VOUT = x□1.204(R1 + R2) R1 CFB Optional□input□capacitor. May□improve□source impedance,□noise,□or□PSRR. Output□capacitor must□be 1.0 F ./c179 /c109 Optional□capacitor reduces□output□noise and□improves transient□response. OFF ON Figure 7-2. Typical Application Circuit for Adjustable-Voltage Version
7.2.1 Design Requirements
R1 and R 2 can be calculated for any output voltage using the formula shown in Figure 7-2 . Sample resistor values for common output voltages are given in Figure 6-2. For best accuracy, make the parallel combination of R 1 and R 2 approximately equal to 19 k Ω. This 19 k Ω, in addition to the internal 8-k Ω resistor, presents the same impedance to the error amp as the 27-k Ω band-gap reference output. This impedance helps compensate for leakages into the error amplifier terminals.
7.2.2 Detailed Design Procedure
Provide an input supply with adequate headroom to account for dropout and output current to compensate for the GND pin current and to power the load. Further, select adequate input and output capacitors as discussed in the Input and Output Capacitor Requirements section. www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS737
7.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability if input impedance is very low, good analog design practice is to connect a 0.1- μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS737 requires a 1- μF output capacitor for stability. The device is designed to be stable for all available types and values of capacitors. In applications where multiple low-ESR capacitors are in parallel, ringing can occur when the product of C OUT and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this requirement.
7.2.2.2 Dropout Voltage
The TPS737 uses an NMOS pass transistor to achieve extremely low dropout. When (V IN – V OUT) is less than the dropout voltage (V DO), the NMOS pass transistor is in the linear region of operation and the input-to-output resistance is the RDS(on) of the NMOS pass transistor. For large step changes in load current, the TPS737 requires a larger voltage drop from V IN to V OUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the DC dropout. Values of (VIN – VOUT) above this line ensure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (V IN-to-VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (V IN – V OUT) close to DC dropout levels], the TPS737 can take a couple of hundred microseconds to return to the specified regulation accuracy.
7.2.2.3 Transient Response
The low open-loop output impedance provided by the NMOS pass transistor in a voltage-follower configuration allows operation without a 1-µF output capacitor. As with any regulator, the addition of additional capacitance from the OUT pin to ground reduces undershoot magnitude but increases undershoot duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin also improves the transient response. The TPS737 does not have an active pulldown when the output is overvoltage. This architecture allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This architecture also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor C OUT and the internal and external load resistance. The rate of decay is given by: (Fixed voltage version) OUT OUT LOAD VdV dT C 80k R/c61 /c180 /c87 /c80 (4) (Adjustable voltage version) OUT OUT 1 2 LOAD VdV dT C 80k (R R ) R/c61 /c180 /c87 /c43 /c80 /c80 (5) TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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7.2.3 Application Curves
Ripple□Rejection□(dB) 100 1k 100k 1M 10M Frequency□(Hz) I =□1mAOUT C =□1 /c109FOUT I =□1mAOUT C =□AnyOUT I =□1mAOUT C =□10 /c109FOUT I =□100mAOUT C =□AnyOUT I =□100mAOUT C =□10 /c109FOUT I =□100mAO C =□1 /c109FO Figure 7-3. PSRR (Ripple Rejection) vs Frequency 0.1 0.01 e V/ /c109 /c214( Hz) N 10 100 1k 10k 100k Frequency□(Hz) C =□1 F /c109OUT C =□10 F /c109OUT I =□150mAOUT Figure 7-4. Noise Spectral Density /c451 /c452 Volts 50ms/div VIN VOUT Figure 7-5. TPS73701, VOUT = 3.3-V Power-Up and Power-Down
7.3 Best Design Practices
Place at least one 1-μF ceramic capacitor as close as possible to the OUT pin of the regulator. Do not place the output capacitor more than 10-mm away from the regulator. Connect a 1- μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator for improved transient performance. Do not exceed the absolute maximum ratings.
7.4 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.2 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR help improve the output noise performance.
7.5 Layout
7.5.1 Layout Guidelines
To improve AC performance such as PSRR, output noise, and transient response, design the printed-circuit- board (PCB) with separate ground planes for V IN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device. www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS737
7.5.1.1 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and to provide reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 6: D IN OUT OUTP V V I u (6) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On both the VSON (DRB) and WSON (DRV) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of copper PCB area to make sure the device does not overheat. On the SOT-223 (DCQ) package, the primary conduction path for heat is through the tab to the PCB. That tab must be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 7: A JA D
125 C TR PT
q (7) Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heat sinking can be estimated using Figure 7-6. 160 140 120 100 /c113JA ( C/W)/c176 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area ( ) in2 DCQ DRV DRB RθJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard. Figure 7-6. RθJA vs Board Size Figure 7-6 shows the variation of R θJA as a function of ground plane copper area in the board. Figure 7-6 is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and is not intended to be used to estimate actual thermal performance in real application environments. Note When the device is mounted on an application PCB, use ΨJT and ΨJB, as explained in the Thermal Information table.
7.5.1.2 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from damage caused by overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 35°C above the maximum expected ambient condition of the application. This buffer produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS737 is designed to protect against overload conditions. This circuitry is not intended to replace proper heat sinking. Continuously running the TPS737 into thermal shutdown degrades device reliability.
7.5.1.3 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 8). For backward compatibility, an older θJC,Top parameter is listed as well. /c89 /c89JT J T JT D:□□□T =□T + P /c183 /c89 /c89JB J B JB D:□□□T =□T + P /c183 (8) where:
- PD is the power dissipation shown by Equation 6
- TT is the temperature at the center-top of the device package
- TB is the PCB temperature measured 1-mm away from the device package on the PCB surface (as Figure 7-8 shows) Note Both T T and T B can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring T T and T B, see the Using New Thermal Metrics application note , available for download at www.ti.com. As Figure 7-7 shows, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 8 is a good way to estimate T J by simply measuring T T or TB, regardless of the application board size. /c89 /c89 and ( C/W) JT JB /c176 0 2 4 6 8 10 Board Copper Area (in )2 51 3 7 9 DRV DCQ DRB /c89JT DRV DCQ DRB /c89JB Figure 7-7. ΨJT and ΨJB vs Board Size www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS737
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, see the Using New Thermal Metrics application note , available for download at www.ti.com. For further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on the TI website. Figure 7-8 shows the measuring points for DRB, DRV, and DCQ packages. (a) Example DRB (SON) Package Measurement (b) Example DRV (SON) Package Measurement 1mm T on top of IC T T on PCB surface B (c) Example DCQ (SOT-223) Package Measurement T on top of IC T T on PCB surface B 1mm 1mm X X TT TB See note (1) A. Power dissipation can limit operating range. Check the Thermal Information table. Figure 7-8. Measuring Points for TT and TB
7.5.2 Layout Example
Figure 7-9. Layout Example TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
8.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS737. The TPS73701DRVEVM-529 evaluation module (and related user's guide ) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore.
8.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS737 is available through the product folders under Tools & Software.
8.1.2 Device Nomenclature
Table 8-1. Ordering Information(1) PRODUCT VOUT (1) TPS737xxyyyz(M3) xx is the nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable (2)). yyy is the package designator. z is the package quantity. M3 is a suffix designator for devices that use the latest manufacturing flow (CSO: RFB). Device performance is denoted by new chip throughout the document and applies only to devices with the M3 suffix. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. (2) For fixed 1.20-V operation, tie FB to OUT.
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation see the following:
- Texas Instruments, Using New Thermal Metrics application note
- Texas Instruments, TPS73701DRVEVM-529 User's Guide user guide
- Texas Instruments, TMS320DM644x Power Reference Design application note
- Texas Instruments, TPS73x01DRBEVM-518 User's Guide user guide
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. www.ti.com TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS737
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision R (December 2019) to Revision S (November 2023) Page Changes from Revision Q (May 2015) to Revision R (December 2019) Page
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS737 SBVS067S – JANUARY 2006 – REVISED NOVEMBER 2023 www.ti.com
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www.ti.com 3-Nov-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PS73701DRBRM3 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 125 Samples TPS73701DCQ ACTIVE SOT-223 DCQ 6 78 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73701 Samples TPS73701DCQG4 ACTIVE SOT-223 DCQ 6 78 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73701 Samples TPS73701DCQR ACTIVE SOT-223 DCQ 6 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73701 Samples TPS73701DCQRG4 ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73701 Samples TPS73701DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BZN Samples TPS73701DRBRG4 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BZN Samples TPS73701DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BZN Samples TPS73701DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QTN Samples TPS73701DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QTN Samples TPS73718DCQ ACTIVE SOT-223 DCQ 6 78 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73718 Samples TPS73718DCQR ACTIVE SOT-223 DCQ 6 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73718 Samples TPS73718DCQRG4 ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73718 Samples TPS73718DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 RAL Samples TPS73718DRBT LIFEBUY SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 RAL TPS73725DCQ ACTIVE SOT-223 DCQ 6 78 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73725 Samples TPS73725DCQR ACTIVE SOT-223 DCQ 6 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73725 Samples TPS73730DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CVT Samples TPS73730DRBT LIFEBUY SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CVT TPS73733DCQ ACTIVE SOT-223 DCQ 6 78 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73733 Samples Addendum-Page 1
www.ti.com 3-Nov-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS73733DCQG4 ACTIVE SOT-223 DCQ 6 78 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73733 Samples TPS73733DCQR ACTIVE SOT-223 DCQ 6 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TPS73733 Samples TPS73733DCQRG4 ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS73733 Samples TPS73733DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SIJ Samples TPS73733DRVT LIFEBUY WSON DRV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SIJ TPS73734DCQ ACTIVE SOT-223 DCQ 6 78 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OCH Samples TPS73734DCQR ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OCH Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2
www.ti.com 3-Nov-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS737 :
- Automotive : TPS737-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 3-Nov-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 3-Nov-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73701DCQR SOT-223 DCQ 6 2500 356.0 356.0 35.0 TPS73701DCQRG4 SOT-223 DCQ 6 2500 346.0 346.0 29.0 TPS73701DRBR SON DRB 8 3000 552.0 346.0 36.0 TPS73701DRBT SON DRB 8 250 552.0 185.0 36.0 TPS73701DRVR WSON DRV 6 3000 213.0 191.0 35.0 TPS73718DCQRG4 SOT-223 DCQ 6 2500 346.0 346.0 29.0 TPS73718DRBR SON DRB 8 3000 356.0 356.0 35.0 TPS73718DRBT SON DRB 8 250 210.0 185.0 35.0 TPS73725DCQR SOT-223 DCQ 6 2500 356.0 356.0 35.0 TPS73730DRBR SON DRB 8 3000 356.0 356.0 35.0 TPS73730DRBT SON DRB 8 250 210.0 185.0 35.0 TPS73733DCQR SOT-223 DCQ 6 2500 356.0 356.0 35.0 TPS73733DCQRG4 SOT-223 DCQ 6 2500 346.0 346.0 41.0 TPS73733DRVR WSON DRV 6 3000 213.0 191.0 35.0 TPS73733DRVT WSON DRV 6 250 213.0 191.0 35.0 TPS73734DCQR SOT-223 DCQ 6 2500 346.0 346.0 41.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 3-Nov-2023 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS73701DCQ DCQ SOT-223 6 78 543 8.6 3606.8 2.67 TPS73701DCQG4 DCQ SOT-223 6 78 532.13 8.63 3.6 3.68 TPS73701DRBR DRB VSON 8 3000 381 4.83 2286 0 TPS73701DRBRG4 DRB VSON 8 3000 381 4.83 2286 0 TPS73701DRBT DRB VSON 8 250 381 4.83 2286 0 TPS73718DCQ DCQ SOT-223 6 78 543 8.6 3606.8 2.67 TPS73725DCQ DCQ SOT-223 6 78 532.13 8.63 3.6 3.68 TPS73733DCQ DCQ SOT-223 6 78 543 8.6 3606.8 2.67 TPS73733DCQG4 DCQ SOT-223 6 78 532.13 8.63 3.6 3.68 TPS73734DCQ DCQ SOT-223 6 78 532.13 8.63 3.6 3.68 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 8X 0.37 0.25 1.75 0.1 1.95 1.5 0.1 6X 0.65
1 MAX
8X 0.5 0.3 0.05 0.00 (0.65) A 3.1 2.9 B 3.1 2.9 (DIM A) TYP 4X (0.23) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
8X (0.31) (1.75) (2.8) 6X (0.65) (1.5) ( 0.2) VIA TYP (0.5) (0.625) 8X (0.6) (R0.05) TYP (0.825) (0.23) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.31) 8X (0.6) (1.34) (1.55) (2.8) 6X (0.65) (0.725) 4X (0.23) (2.674) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM
www.ti.com PACKAGE OUTLINE C 7.26 6.86 5.08 5X 0.51 0.41 1.27 TYP 3.05
2.951.8 MAX
0.10 0.02 0.32 0.24 0.25 GAGE PLANE A 6.6 6.4 NOTE 3 B3.6 3.4 NOTE 3 1.14 0.910 -8 TYP (1.6) SOT - 1.8 mm max heightDCQ0006A PLASTIC SMALL OUTLINE 4214845/C 11/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
0.1 C A B
0.08 SCALE 2.000
www.ti.com EXAMPLE BOARD LAYOUT 5X (2.05) 5X (0.65)
0.2 TYP
(6) (2.05) (3.2) 4X (1.27) (R0.05) TYP (1.35) (0.775) TYP SOT - 1.8 mm max heightDCQ0006A PLASTIC SMALL OUTLINE 4214845/C 11/2021 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM PKG METALSOLDER MASK OPENING EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (6) (1.27) TYP (R0.05) TYP 5X (2.05) 5X (0.65) (0.755) 4X (1.31) 4X (0.92) (0.56) TYP SOT - 1.8 mm max heightDCQ0006A PLASTIC SMALL OUTLINE 4214845/C 11/2021 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F
www.ti.com PACKAGE OUTLINE C 6X 0.35 0.25 1.6 0.1 6X 0.3 0.2 1.3 1 0.1 4X 0.65 0.8 0.7 0.05 0.00 B 2.1 1.9 A 2.1 1.9 (0.2) TYP WSON - 0.8 mm max heightDRV0006D PLASTIC SMALL OUTLINE - NO LEAD 4225563/A 12/2019 PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500
www.ti.com EXAMPLE BOARD LAYOUT (1) 4X (0.65) (1.95) 6X (0.3) 6X (0.45) (1.6) (R0.05) TYP ( 0.2) VIA TYP (1.1) WSON - 0.8 mm max heightDRV0006D PLASTIC SMALL OUTLINE - NO LEAD 4225563/A 12/2019 SYMM 3 4 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 6X (0.3) 6X (0.45) 4X (0.65) (0.7) (1) (1.95) (R0.05) TYP (0.45) WSON - 0.8 mm max heightDRV0006D PLASTIC SMALL OUTLINE - NO LEAD 4225563/A 12/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X SYMM 3 4 SYMM METAL
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