TPS65197 TI | Alldatasheet
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CS_1 CLKOUT2 CS_2 CLKOUT3 CS_3 CLKOUT4 CS_4 CLKOUT5 CLKOUT6 STVOUT RESETOUT STVIN RESETIN DISCH1 DISCH2 DischargeDIS_SENSE VGH VGL1 VGL2 GND SEL_CS V(GH) V(GL1) V(GL2) V(CLK1) V(CLK2) V(CLK3) V(CLK4) V(CLK5) V(CLK6) V(STV) V(RESET) V(CLKOUT1) V(CLKOUT2) V(CLKOUT3) V(CLKOUT4) V(CLKOUT5) V(CLKOUT6) V(STVOUT) V(RESETOUT) Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 TPS65197x:8-ChannelLevel-ShifterSupportingNo,2-Channeland3-Channel Charge-SharingwithPanelDischargetoVGHduringShut-Down
1 Features
1• 8-Channel Level-Shifter (STV, RESET, 6 × CLK)
- High Output-Voltage Level 16.5 V to 45 V (VGH)
- Low Output-Voltage Level Down to –20 V (VGL)
- Selectable Charge-Sharing – No Charge-Sharing – 2-Channel Charge-Sharing – 3-Channel Charge-Sharing
- 2-Channel Panel Discharge
- T-CON Failure Detection – TPS65197: Logic Resets by STV Pulse – TPS65197B: No Reset of the Logic
- Latched Shut-Down Detection (Clocks to VGH)
- Supports 100-kHz Clock Operating Frequency
- 28-Pin 4-mm × 4-mm QFN Package
2 Applications
- Gate-in-Panel (GIP) LCD – Notebook – Monitor – TV
3 Description
The TPS65197/B is an 8-channel level-shifter with discharge function intended for use in LCD display applications such as Notebooks, Monitors and TVs. The device converts the timing-controller (T-CON) logic-level signals to the high-level signals needed by the gate-in-panel (GIP) display. The clock outputs, CLKOUTx, support normal level shifting operation and 2-channel or 3-channel charge- sharing, which can be used to improve picture quality and power consumption. At power down, all outputs follow their input signals as long as possible; when the discharge function is used, the outputs are pulled high (VGH). The TPS65197 implements a logic reset to ignore wrong T-CON signals after the rising STV edge which forces all 6 output clocks to VGL1. The next CLKIN1 rising edge unlocks the logic and enables normal operation. The TPS65197B does not have the logic reset and always follows its input signals. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS65197 WQFN (28) 4.00 mm x 4.00 mm TPS65197B WQFN (28) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.
4 Simplified Schematic
TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TPS65197 TPS65197B Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Table of Contents
13 Mechanical, Packaging, and Orderable
5 Revision History
Changes from Revision C (May 2017) to Revision D Page Changes from Revision B (July 2015) to Revision C Page Changes from Revision A (June 2015) to Revision B Page Changes from Original (April 2012) to Revision A Page
- Added ESD Ratings table, Timing Requirements table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
CS_4 CLKIN6 CLKOUT5 CLKOUT6 STVOUT RESETOUT DISCH2 DISCH1 VGH GND VGL1 VGL2 SEL_CS DIS_SENSE RESETIN CLKIN5 CLKIN4 CLKIN3 CLKIN2 CLKIN1 STVIN CLKOUT1 CS_1 CLKOUT2 CS_2 CLKOUT3 CS_3 CLKOUT4 Exposed Thermal Pad TPS65197,TPS65197B www.ti.com SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 Product Folder Links: TPS65197 TPS65197B Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated
6 Pin Configuration and Functions
28-Pin WQFN With Thermal Pad Top View Pin Functions PIN I/O/P DESCRIPTION NAME NUMBER CLKIN1 20 I Clock 1 input CLKIN2 19 I Clock 2 input CLKIN3 18 I Clock 3 input CLKIN4 17 I Clock 4 input CLKIN5 16 I Clock 5 input CLKIN6 15 I Clock 6 input CLKOUT1 22 I/O Clock 1 output CLKOUT2 24 I/O Clock 2 output CLKOUT3 26 I/O Clock 3 output CLKOUT4 28 I/O Clock 4 output CLKOUT5 2 I/O Clock 5 output CLKOUT6 3 I/O Clock 6 output CS_1 23 I/O Clock 1 charge-sharing input CS_2 25 I/O Clock 2 charge-sharing input CS_3 27 I/O Clock 3 charge-sharing input CS_4 1 I/O Clock 4 charge-sharing input DISCH1 7 I/O Discharge 1 output. Internally connected to VGL1 and VGH DISCH2 6 I/O Discharge 2 output. Internally connected to VGL2 and VGH DIS_SENSE 13 I Discharge sense terminal GND 9 – Ground RESETIN 14 I RESET input RESETOUT 5 I/O RESET output
TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TPS65197 TPS65197B Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O/P DESCRIPTION NAME NUMBER SEL_CS 12 I Charge-sharing method-selection terminal. When left floating or pulled to GND, charge-sharing is disabled. STVIN 21 I STV input STVOUT 4 I/O STV output VGH 8 P Positive supply voltage. Place a buffer capacitor close to this terminal. VGL1 10 P Negative supply voltage for all outputs except discharge 2. Place a buffer capacitor close to this terminal. VGL2 11 P Negative supply voltage for discharge 2 Thermal pad – – The thermal pad is connected to VGL1. (1) With respect to the GND terminal
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Terminal voltage(1) SEL_CS, DIS_SENSE, CLKIN1, CLKIN2, CLKIN3, CLKIN4, CLKIN5, CLKIN6, STVIN, RESETIN –0.3 7 V VGH –0.3 50 VGL1, VGL2 –25 0.3 CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CS_1, CS_2, CS_3, CS_4, STVOUT, RESETOUT, DISCH1, DISCH2 –25 50 VGH – VGLx 62 VGL1 – VGL2 –20 0 Operating junction temperature, TJ –40 150 ºC Storage temperature, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±700
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(GH) Voltage range of positive supply 16.5 45 V V(GL_x) Voltage range of negative supply –20 –3 V(GH) – V(GL_x) Voltage difference between V(GH) and V(GL_x) 0 60 VGL1 – VGL2 Voltage difference between V(GL1) and V(GL2) (V(GL1) must be more negative than V(GL2)) –20 0 TA Operating free-air temperature –40 85 TJ Operating junction temperature –40 125
TPS65197,TPS65197B www.ti.com SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 Product Folder Links: TPS65197 TPS65197B Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
7.4 Thermal Information
THERMAL METRIC(1) TPS65197/B UNITRUY
28 PINS
RθJA Junction-to-ambient thermal resistance 34.5 °C/W RθJCtop Junction-to-case (top) thermal resistance 25.5 RθJB Junction-to-board thermal resistance 7.5 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 7.5 RθJCbot Junction-to-case (bottom) thermal resistance 2.5
7.5 Electrical Characteristics
V(GH) = 30 V, V(GL1) = –10 V, V(GL2) = –8 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(GH) Input voltage range V(GH) 16.5 45 VV(GL1) Input voltage range V(GL1) –20 –3 V(GL2) Input voltage range V(GL2) –20 –3 I(GH) Positive supply current CLKINx = STVIN = RESETIN = SEL_CS = 0 V, DIS_SENSE = 5 V 0.3 1 mAI(GL1) Negative supply current –0.5 –0.05 I(GL2) Negative supply current –0.5 –0.05 V(UVLO) Undervoltage lockout threshold V(GH) rising, TJ = –40ºC to 85ºC 13.5 15 16.5 V V(GH) falling, TJ = –40ºC to 85ºC 2 3.5 5 T(SD) Thermal shutdown temperature TJ rising 130 150 170 °C INPUT SIGNALS (CLKINx, STVIN, RESETIN, SEL_CS, DIS_SENSE) VIH High-level input voltage CLKINx, STVIN, RESETIN Input rising 1.65 V VIL Low-level input voltage CLKINx, STVIN, RESETIN Input falling 0.8 V(SEL_CS) Charge-sharing-disabled voltage 0.5 3-Channel Charge-Sharing voltage 1 2 2-Channel Charge-Sharing voltage 2.8 6.5 V(DIS_SENS Discharge detection threshold V(DIS_SENSE) falling, TJ = 0ºC to 85ºC 1.17 1.26 1.36 IIN Input current CLKINx, STVIN, RESETIN, DIS_SENSE CLKINx = STVIN = RESETIN = DIS_SENSE = 5 V 2 100 nA Input current SEL_CS SEL_CS = 5 V 50 100 µA R(SEL_CS) SEL_CS pin, internal pulldown resistance 50 100 150 kΩ LEVEL SHIFTERS (CLKOUT1 to CLKOUT6) rDS(on) High-side on-resistance, CLKOUTx I(OUT) = 10 mA, sourcing (high side) 11 25 ΩLow-side on-resistance, CLKOUTx I(OUT) = 10 mA, sinking (low side) 7 15 R(CS) Internal charge-sharing resistance I(CS) = 10 mA, TJ = –40ºC to 85ºC 30 60 100 LEVEL SHIFTERS (STVOUT, RESETOUT) rDS(on) High-side on-resistance STVOUT, RESETOUT I(OUT) = 10 mA, sourcing (high side) 30 60 Ω Low-side on-resistance STVOUT, RESETOUT I(OUT) = 10 mA, sinking (low side) 15 30
20% 80% Slew+ Slew- STVOUT RESETOUT CLKOUTx tdr tdf STVIN RESETIN CLKINx 50% 90% 10% 3.3 V GND VGH VGL1 CLKIN1 CLKOUT1 Tdf(CS) 90% Tdr(CS) 3.3 V GND 50% VGH VGL1 CLKIN4 50% 10% CLKOUT4 Tdr(CS) 90% Tdf(CS) 10% 3.3 V GND VGH VGL1 STVOUT RESETOUT CLKOUTx VGH VGL1 TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TPS65197 TPS65197B Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Electrical Characteristics (continued) V(GH) = 30 V, V(GL1) = –10 V, V(GL2) = –8 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DISCHARGE OUTPUTS (DISCH1, DISCH2) rDS(on) High-side on-resistance, DISCH1 I(OUT) = 10 mA, sourcing (high side) 14 60 Ω Low-side on-resistance DISCH1 I(OUT) = 10 mA, sinking (low side) 3 10 High-side on-resistance, DISCH2 I(OUT) = 10 mA, sourcing (high side) 14 60 Low-side on-resistance DISCH2 I(OUT) = 10 mA, sinking (low side) 10 20
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT LEVEL SHIFTERS (CLKOUT1 to CLKOUT6) Slew+ Slew rate, rising C(OUT) = 4.7 nF, V(OUT) = 20% to 80% 50 140 V/µs Slew– Slew rate, falling 50 150 tdr Propagation delay V(OUT) rising, C(OUT) = 150 pF 40 100 ns tdf V(OUT) falling, C(OUT) = 150 pF 50 100 tdr(CS) V(OUT) rising, C(OUT) = 150 pF, R(CS) = 50 Ω 50 150 tdf(CS) V(OUT) falling, C(OUT) = 150 pF, R(CS) = 50 Ω 70 150 LEVEL SHIFTERS (STVOUT, RESETOUT) Slew+ Slew rate, rising C(OUT) = 4.7 nF, V(OUT) = 20% to 80% 20 50 V/µs Slew– Slew rate, falling 30 60 tdr Propagation delay V(OUT) rising, C(OUT) = 150 pF 40 100 ns tdf V(OUT) falling, C(OUT) = 150 pF 50 100
7.7 Typical Characteristics
Figure 1. Propagation Delay, Charge Sharing Disabled Figure 2. Propagation Delay, Charge Sharing Enabled Figure 3. Slew Rate
CS_1 CS_2 CS_3 CS_4 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN5 CLKIN6 VGH VGL1 STVOUTSTVIN VGH VGL1 RESETOUTRESETIN VGL1 VGH SEL_CS Charge-Sharing logic GND VGL2 VREF VGH VGL1 VGH VGL2Logic all outputs = VGH when DIS_SENSE < VREF DIS_SENSE DISCH1 DISCH2 TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TPS65197 TPS65197B Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The TPS65197/B is a 8-channel level-shifter with optional discharge function during shut-down. It supports no charge-sharing as well as 2-channel and 3-channel charge-sharing. Two channels are used to generate the STV and RESET signal, the remaining 6 channels generate the clocks. The two discharge outputs (DISCH1 and DISCH2) are connected to VGL1 and VGL2 during operation, at shutdown both discharge outputs are connected to VGH.
8.2 Functional Block Diagram
DIS_SENSE DISCH1 DISCH2 typ. 1.2 V UVLO typ. 15 V UVLO typ. 3.5 V Outputs follow VGH Outputs follow VGL1 Outputs follow VGL1 VGL1 VGL2 Outputs follow VGH Outputs follow VGL1 , VGL2 TPS65197,TPS65197B www.ti.com SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 Product Folder Links: TPS65197 TPS65197B Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Sequencing
8.3.2 Power Up
At power up VGL1 and VGL2 must be present before VGH is rising. VGL1 must be always more negative or equal to VGL2, VGH should not rise faster than in 100 us. All clock output channels and DISCH1 follow VGL1, DISCH2 follows VGL2 until VGH rises above its rising UVLO threshold voltage of 15 V, then all clock output channels of the TPS65197B follow their input signals. The TPS65197 has a different startup behavior as CLKOUT1 to CLKOUT6 are forced to VGL1 until the 1st rising edge of CLKIN1 releases all clocks. The discharge-sense (DIS_SENSE) voltage must be higher than its maximum threshold voltage of 1.36 V before VGH reaches the rising UVLO threshold of 15 V, otherwise all outputs are forced to VGH and the state is latched. The selected Charge-Sharing method is latched when VGH reaches the rising UVLO according to the SEL_CS voltage, it is reset with the falling UVLO.
8.3.3 Power Down
When the discharge-sense (DIS_SENSE) voltage falls below its typical threshold voltage of 1.26 V, all clock output channels follow VGH until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock output channels and DISCH1 follow VGL1, DISCH2 follows VGL2. Once discharge-sense is triggered the state is latched, to reset and continue normal operation VGH has to fall below the falling UVLO threshold of 3.5 V. In case the discharge-sense (DIS_SENSE) voltage stays high during power down, all clock output channels follow their input signals until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock output channels follow VGL1. The discharge channels follow VGL1 and VGL2 all the time.
8.3.4 Disabling the Discharge Function
When the discharge function is not used, the DIS_SENSE pin must be pulled above its maximum threshold voltage of 1.36 V all the time (for example to 3.3 V).
TPS65197,TPS65197B SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TPS65197 TPS65197B Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Feature Description (continued)
8.3.5 Undervoltage Lockout
To avoid improper operation of the device at low input voltages, an undervoltage lockout function is implemented. When VGH is below the UVLO threshold each output channel is clamped to its respective negative supply, VGL1 or VGL2.
8.3.6 Thermal Shutdown
A thermal shutdown is implemented to prevent damage because of excessive heat or power dissipation. Once the junction temperature exceeds a typical value of 150 ºC, all outputs are set to high-impedance. This state is latched. VGH must fall below the falling UVLO (3.5 V) to reset the thermal shutdown.
8.4 Device Functional Modes
8.4.1 Output Clock Behavior
The STV and RESET channels always follow their inputs while the clocks 1 to 6 behave different for TPS65197 and TPS65197B. TPS65197: At startup the output signals CLKOUT1 to CLKOUT6 are forced low (VGL1) until the first rising edge of CLKOUT1 releases all clocks. Every rising edge of STVIN stops the Charge-Sharing and resets the output signals CLKOUT1 to CLKOUT6 (that is, forced low) until the next rising edge of CLKIN1 after which the clock outputs follow their inputs again. The rising edge of CLKIN1 should occur not sooner than 50 ns after the rising edge of STVIN. This logic ensures a proper reset and a clean start every frame. TPS65197B: The TPS65197B does not have the reset logic as TPS65197 and all outputs always follow their input signals (also at startup). If Charge-Sharing is activated every rising edge of STVIN stops the Charge-Sharing and the output signals CLKOUT1 to CLKOUT6 follow their input signals. The next Charge-Sharing event should not occur sooner than 50 ns after the rising edge of STVIN.
8.4.2 Charge-Sharing Methods TPS65197
Figure 4. TPS65197: Charge-Sharing Disabled (CS_SEL < 0.5 V) Charge-sharing of CLKOUT1 ↔ CLKOUT3 between CLKIN1↓ CLKIN3↑. Charge-sharing of CLKOUT3 ↔ CLKOUT5 between CLKIN3↓ CLKIN5↑. Charge-sharing of CLKOUT5 ↔ CLKOUT1 between CLKIN5↓ CLKIN1↑. Charge-sharing of CLKOUT2 ↔ CLKOUT4 between CLKIN2↓ CLKIN4↑. Charge-sharing of CLKOUT4 ↔ CLKOUT6 between CLKIN4↓ CLKIN6↑. Charge-sharing of CLKOUT6 ↔ CLKOUT2 between CLKIN6↓ CLKIN2↑. Figure 5. TPS65197: 3-Channel Charge-Sharing (CS_SEL = 1 V… 2 V)
Charge-sharing of CLKOUT1 ↔ CLKOUT4 between CLKIN1↓ CLKIN4↑ and CLKIN4↓ CLKIN1↑. Charge-Sharing of CLKOUT2 ↔ CLKOUT5 between CLKIN2↓ CLKIN5↑ and CLKIN5↓ CLKIN2↑. Charge-Sharing of CLKOUT3 ↔ CLKOUT6 between CLKIN3↓ CLKIN6↑ and CLKIN6↓ CLKIN3↑. Figure 6. TPS65197: 2-Channel Charge-Sharing (CS_SEL = 2.8 V… 6.5 V)
Outputs follow their Inputs.
8.4.3 Charge-Sharing Methods TPS65197B
Figure 7. TPS65197B: Charge-Sharing Disabled (CS_SEL < 0.5 V) Charge-sharing of CLKOUT1 ↔ CLKOUT3 between CLKIN1↓ CLKIN3↑. Charge-sharing of CLKOUT3 ↔ CLKOUT5 between CLKIN3↓ CLKIN5↑. Charge-sharing of CLKOUT5 ↔ CLKOUT1 between CLKIN5↓ CLKIN1↑. Charge-sharing of CLKOUT2 ↔ CLKOUT4 between CLKIN2↓ CLKIN4↑. Charge-sharing of CLKOUT4 ↔ CLKOUT6 between CLKIN4↓ CLKIN6↑. Charge-sharing of CLKOUT6 ↔ CLKOUT2 between CLKIN6↓ CLKIN2↑. Figure 8. TPS65197B: 3-Channel Charge-Sharing (CS_SEL = 1 V… 2 V)
Outputs follow their Inputs. Charge-sharing of CLKOUT1 ↔ CLKOUT4 between CLKIN1↓ CLKIN4↑ and CLKIN4↓ CLKIN1↑. Charge-Sharing of CLKOUT2 ↔ CLKOUT5 between CLKIN2↓ CLKIN5↑ and CLKIN5↓ CLKIN2↑. Charge-Sharing of CLKOUT3 ↔ CLKOUT6 between CLKIN3↓ CLKIN6↑ and CLKIN6↓ CLKIN3↑. Figure 9. TPS65197B: 2-Channel Charge-Sharing (CS_SEL = 2.8 V… 6.5 V)
50 V / 0603
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
channel and 3-channel charge-sharing.
9.2 Typical Application
Figure 10. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the input parameters shown in Table 1. Table 1. Design Parameters
16.5 V to 45 V
9.2.2 Detailed Design Procedure
capacitors which should be close to the device and have a good connection to ensure clean output signals.
9.2.3 Application Curves
Figure 11. Power Up, Power Down Figure 12. No Charge Sharing Input Signals
Figure 19. 3-Channel Charge Sharing Outputs Figure 20. 3-Channel Charge Sharing Outputs
10 Power Supply Recommendations
capacitor on VGH and VGL1 should be used to ensure clean output signals.
CS_4 CLKIN6 CLKOUT5 CLKOUT6 STVOUT RESETOUT DISCH2 DISCH1 VGH GND VGL1 VGL2 SEL_CS DIS_SENSE RESETIN CLKIN5 CLKIN4 CLKIN3 CLKIN2 CLKIN1 STVIN CLKOUT1 CS_1 CLKOUT2 CS_2 CLKOUT3 CS_3 CLKOUT4 VIA to VGL1 Plane TPS65197,TPS65197B www.ti.com SLVSBB0D –APRIL 2012–REVISED FEBRUARY 2018 Product Folder Links: TPS65197 TPS65197B Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
Proper PCB layout is essential for achieving the expected performance and a low device temperature. The following points should be considered.
- Place the supply decoupling capacitors as close as possible to device terminals VGH and VGL1.
- Use wide traces to route power from the bias IC to the device to avoid voltage drops. The device is able to sink and source high peak currents up to 1 A. If wide traces are not possible, place additional 1-µF capacitors of at least 0805 size close to the supply decoupling capacitors.
- The output channel traces should be kept as short as possible to reduce EMI emissions, and not too thin to minimize stray inductances producing voltage overshoots at the panel, because high peak currents up to 1 A can flow.
- The thermal pad must be connected by many vias to a large copper area on a VGL1 potential, to be used as a heat sink. Use a copper area of at least 10 cm2. The bigger the copper area, the cooler the device temperature. On a multilayer board, use the copper areas of as many layers as possible to maximize the heat sink.
- Output resistors for clock channels 1 to 6 can be used to reduce EMI emissions and device temperature if necessary. They generate heat and should therefore not be placed close to the device.
11.2 Layout Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
12.2 Related Links
resources, tools and software, and quick access to order now. Table 2. Related Links
12.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS65197BRUYR Active Production WQFN (RUY) | 28 3000 | LARGE T&R Yes NIPDAU | NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65197B TPS65197BRUYR.B Active Production WQFN (RUY) | 28 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65197B TPS65197BRUYT Active Production WQFN (RUY) | 28 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 65197B TPS65197BRUYT.B Active Production WQFN (RUY) | 28 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 65197B TPS65197RUYR Active Production WQFN (RUY) | 28 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65197A TPS65197RUYR.B Active Production WQFN (RUY) | 28 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65197A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65197BRUYR WQFN RUY 28 3000 346.0 346.0 33.0 TPS65197BRUYT WQFN RUY 28 250 182.0 182.0 20.0 TPS65197RUYR WQFN RUY 28 3000 346.0 346.0 33.0 Pack Materials-Page 2
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4219146/C 03/2021 www.ti.com WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK-NO LEAD RUY0028A A 0.08 C
0.1 C A B
0.05 C B SYMM SYMM PIN 1 INDEX AREA 4.1 3.9 4.1 3.9 0.8 0.7 0.05 0.00 SEATING PLANE C 28X 0.25 0.15 2.4 24X 0.4 SQ 2.6±0.1 2X 2.4 8 14 28X 0.5 0.3 2228
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4219146/C 03/2021 www.ti.com WQFN - 0.8 mm max heightRUY0028A PLASTIC QUAD FLATPACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL
0.05 MAX
0.05 MIN
2X (3.8) 2X (2.4) (2.4) (3.8) 28X (0.2) 24X (0.4) SQ (2.6) 2X (1.05) 2X (1.05) (R0.05) TYP 8 14 2228 28X (0.6) (Ø0.2) VIA TYP
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4219146/C 03/2021 www.ti.com WQFN - 0.8 mm max heightRUY0028A PLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED COVERAGE BY AREA SCALE: 15X SYMM SYMM 2X (3.8) (3.8) 28X (0.2) 24X (0.4) SQ (1.15) 2X (0.675) 2X (0.675) (R0.05) TYP 8 14 2228 28X (0.6) METAL TYP
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