PS560430YFQDBVRQ1

Texas Instruments

SIMPLE SWITCHER 4-V to 36-V, 600-mA synchronous step-down converter

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ADVANCE□INFORMATION CB SW L C BOOT FB VIN VIN up to 36 V C OUT EN C IN GND VOUT R FBT R FBB Copyright © 2017, Texas Instruments Incorporated IOUT (A) Efficiency (%) 0.001 0.01 0.1 1 100 D001 VIN=8V VIN=12V VIN=24V VIN=36V Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS560430-Q1 SLUSDF5 –JANUARY 2019 TPS560430-Q1SIMPLESWITCHER®4-Vto36-V,600-mAsynchronousstep-down converter

1 Features

1• Qualified for automotive applications

AEC-Q100 qualified with the following results: - Device temperature grade 1: –40°C to 125°C ambient operating temperature range - Device HBM ESD classification level 2 - Device CDM ESD classification level C5
Configured for rugged industrial applications – Input voltage range: 4 V to 36 V – 600-mA continuous output current – Minimum switching-on time: 60 ns – 98% maximum duty cycle – Support startup with pre-biased output – Short circuit protection with hiccup mode – ±1.5% tolerance voltage reference over temperature from –40°C to 125°C – Precision enable
Small solution size and ease of use – Integrated synchronous rectification – Internal compensation for ease of use – SOT-23-6 package
Various options in pin-to-pin compatible package – 2.1-MHz frequency – PFM and forced PWM (FPWM) options
Create a custom design using the TPS560430-Q1 with the WEBENCH® Power Designer

2 Applications

Infotainment and cluster
ADAS
Telematics control unit
General purpose wide VIN power supplies

3 Description

The TPS560430-Q1 is an easy to use synchronous step-down DC-DC converter capable of driving up to 600-mA load current. With a wide input range of 4 V to 36 V, the device is suitable for a wide range of applications from industrial to automotive for power conditioning from an unregulated source. The TPS560430-Q1 is 2.1-MHz operating frequency for small solution size. The TPS560430-Q1 also has FPWM (forced PWM) version to achieve constant frequency and small output voltage ripple over the full load range. Soft-start and compensation circuits are implemented internally which allows the device to be used with minimum external components. The device has built-in protection features, such as cycle-by-cycle current limit, hiccup mode short-circuit protection, and thermal shutdown in case of excessive power dissipation. The TPS560430-Q1 is available in SOT-23-6 package. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS560430-Q1 SOT-23-6 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Efficiency vs Output Current VOUT = 5 V, 2100 kHz, PFM

12.3 Receiving Notification of Documentation Updates 24

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2019 * Advance information release.

ADVANCE□INFORMATION GND 3 4 EN 6CB FB SW VIN TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Device Comparison Table

ORDERABLE PART NUMBER Frequency PFM or FPWM Output PS560430YQDBVRQ1 2.1 MHz PFM Adjustable PS560430YFQDBVRQ1 2.1 MHz FPWM Adjustable (1) A = Analog, P = Power, G = Ground.

6 Pin Configuration and Functions

TYPE (1) DESCRIPTION NAME NO CB 1 P Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF capacitor from this pin to the SW pin. EN 4 A Precision enable input to the convertor. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input allows adjustable UVLO by external resistor divider. FB 3 A Feedback input to the convertor. Connect a resistor divider to set the output voltage. Never short this terminal to ground during operation. GND 2 G Power ground terminals, connected to the source of low-side FET internally. Connect to system ground, ground side of CIN and COUT. Path to CIN must be as short as possible. SW 6 P Switching output of the convertor. Internally connected to source of the high-side FET and drain of the low-side FET. Connect to power inductor. VIN 5 P Supply input terminal to internal bias LDO and high-side FET. Connect to input supply and input bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and GND.

ADVANCE□INFORMATION TPS560430-Q1 SLUSDF5 –JANUARY 2019 www.ti.com Product Folder Links: TPS560430-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40 °C to 125 °C (unless otherwise noted) (1) PARAMETER MIN MAX UNIT Input Voltages VIN to GND –0.3 38 VEN to GND –0.3 VIN + 0.3 FB to GND –0.3 5.5 Output Voltages SW to GND –0.3 VIN + 0.3 VSW to GND less than 10 ns transient –3.5 38 CB to SW –0.3 5.5 TJ Junction temperature (2) –40 150 Tstg Storage temperature –65 150 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2500 V Charged-device model (CDM), per AEC Q100-011 ±750 (1) Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted) (1) PARAMETER MIN MAX UNIT Input Voltages VIN to GND 4 36 VEN 0 VIN FB 0 4.5 Output Voltage VOUT 1.0 95% of VIN V Output Current IOUT 0 600 mA Temperature Operating junction temperature range, TJ –40 +125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 (2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

7.4 Thermal Information

THERMAL METRIC (1) DBV (6 PINS) UNIT RθJA (2) Junction-to-ambient thermal resistance 173 °C/W RθJC_T Junction-to-case (TOP) thermal resistance 116 °C/W RθJC_B Junction-to-case (BOTTOM) thermal resistance 31 °C/W ψJT Junction-to-top characterization parameter 20 °C/W ψJB Junction-to-board characterization parameter 30 °C/W

ADVANCE□INFORMATION TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Ensured by design.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 4 V to 36 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VIN Operation input voltage 4 36 V VIN_UVLO Undervoltage lockout thresholds Rising threshold 3.55 3.75 4.00 VFalling threshold 3.25 3.45 3.65 Hysteresis 0.3 IQ Operating quiescent current (non- switching) PFM version, VEN = 3.3 V, VFB = 1.1V 80 120 µA ISHDN Shutdown current VEN = 0 V 3 10 µA ENABLE (EN PIN) VEN_H Enable rising threshold voltage 1.1 1.23 1.36 V VEN_L Enable falling threshold voltage 0.95 1.1 1.22 V VEN_HYS Enable hysteresis voltage 0.13 V IEN Leakage current at EN pin VEN = 3.3 V 10 200 nA VOLTAGE REFERENCE (FB PIN) VREF Reference voltage TJ = 25 °C 0.995 1.00 1.005 V TJ = –40 °C to 125 °C 0.985 1.00 1.015 V IFB Leakage current at FB pin VFB = 1.2 V 0.2 50 nA CURRENT LIMITS AND HICCUP IHS_LIMIT Peak inductor current limit 0.8 1.1 1.4 A ILS_LIMIT Valley inductor current limit 0.62 0.8 0.98 A ILS_ZC Zero cross current (PFM version) 20 mA ILS_NEG Negative current limit (FPWM version) -0.7 -0.5 -0.3 A VHICCUP Hiccup threshold of FB pin % of reference voltage 40% INTEGRATED MOSFETS RDS_ON_HS High-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V 450 mΩ RDS_ON_LS Low-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V 240 mΩ THERMAL SHUTDOWN (1) TSHDN Thermal shutdown threshold 170 °C THYS Hysteresis 12 °C

7.6 Timing Requirements

7.7 Switching Characteristics

7.8 Typical Characteristics

VIN = 12 V, fSW = 2.1MHz, TA = 25°C, unless otherwise specified. Figure 1. Efficiency vs Load Current Figure 2. Efficiency vs Load Current Figure 3. Load Regulation Figure 4. Line Regulation Figure 5. Dropout Figure 6. IQ vs Temperature

ADVANCE□INFORMATION EA REF EN SW CB Internal SS Oscillator Precision Enable LDO PFM Detector Slope Comp PWM CONTROL LOGIC UVLOTSD Freq Foldback Zero Cross HICCUP Detector VIN R C C C GND FB LSI Sense HSI Sense FB VCC Enable Ton_min/Toff_min Detector Copyright © 2017, Texas Instruments Incorporated TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TPS560430-Q1 regulator is an easy to use synchronous step-down DC-DC converter operating from 4-V to 36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution size. The family has multiple versions applicable to various applications, refer to Device Comparison Table for detailed information. The TPS560430-Q1 employs fixed-frequency peak-current mode control. The device enters PFM Mode at light load to achieve high efficiency for PFM version. And FPWM version is provided to achieve low output voltage ripple, tight output voltage regulation, and constant switching frequency at light load. The device is internally compensated, which reduces design time, and requires few external components. Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for a wide range of applications. Protection features include thermal shutdown, VIN under-voltage lockout, cycle-by- cycle current limit, and hiccup mode short-circuit protection. The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control

inversely proportional to the input voltage: D = VOUT / VIN. Figure 10. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.3.2 Adjustable Output Voltage

temperature variation of the resistor dividers affect the output voltage regulation. Figure 11. Output Voltage Setting

8.3.3 Enable

connect the EN to VIN. This allows self-start-up of the TPS560430-Q1 when VIN is within the operating range. recommended to apply EN voltage when VIN is 0 V. Figure 12. System UVLO by Enable Divider

8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback

ns in the TPS560430-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off. switching frequency foldback. which may extend the maximum duty cycle or lower the minimum duty cycle. regulation according to Equation 2. leads to a lower effective drop-out. With frequency foldback, VIN_MAX is raised, and VIN_MIN is lowered by decreased fSW. Figure 13. Frequency Foldback at TON_MIN Figure 14. Frequency Foldback at TOFF_MIN

ADVANCE□INFORMATION IN OUT OUT OUT_MAX LS SW IN V - V VI = I + × 2 × f × L V TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Feature Description (continued)

8.3.5 Bootstrap Voltage

The TPS560430-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the CB and SW pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the high-side MOSFET is off and the low-side switch conducts. The recommended value of the bootstrap capacitor is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is recommended for stable performance over temperature and voltage.

8.3.6 Over Current and Short Circuit Protection

The TPS560430-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating. High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold IHS_LIMIT which is constant. The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below the ILS_LIMIT. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. This is somewhat different to the more typical peak current limit, and results in Equation 6 for the maximum load current. (6) If the feedback voltage is lower than 40% of the VREF, the current of the LS switch triggers ILS_LIMIT for 256 consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the regulator shuts down and keeps off for a period of hiccup, THICCUP (135 ms typical), before the TPS560430-Q1 tries to start again. If over- current or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to the device. For FPWM version, the inductor current is allowed to go negative. Should this current exceed the LS negative current limit ILS_NEG, the LS switch is turned off and HS switch is turned on immediately. This is used to protect the LS switch from excessive negative current.

8.3.7 Soft Start

The integrated soft-start circuit prevents input inrush current impacting the TPS560430-Q1 and the input power supply. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The typical soft-start time is 1.8 ms. The TPS560430-Q1 also employs over-current protection blanking time TOCP_BLK (33 ms typical) at the beginning of power-up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the inrush current is large enough to trigger the current-limit protection, which may make the device entering into hiccup mode. The device tries to restart after the hiccup period, then hit current-limit and enter into hiccup mode again, so VOUT cannot ramp up to the setting voltage ever. By introducing OCP blanking feature, the hiccup protection function is disabled during TOCP_BLK, and TPS560430-Q1 charges the VOUT with its maximum limited current, which maximizes the output current capacity during this period. Kindly note that, the peak current limit (IHS_LIMIT) and valley current limit (ILS_LIMIT) protection function are still available during TOCP_BLK, so there is no concern of inductor current running away.

8.3.8 Thermal Shutdown

The TPS560430-Q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170°C. Both HS and LS FETs stop switching in thermal shutdown. Once the die temperature falls below 158°C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPS560430-Q1. When VEN is below 0.95 V, the device is in shutdown mode. The TPS560430-Q1 also employs VIN under voltage lock out protection (UVLO). If VIN voltage is below its UVLO threshold 3.25 V, the regulator is turned off.

8.4.2 Active Mode

The TPS560430-Q1 is in Active Mode when both VEN and VIN are above their respective operating threshold. The simplest way to enable the TPS560430-Q1 is to connect the EN pin to VIN pin. This allows self-startup when the input voltage is in the operating range: 4.0 V to 36 V. Please refer to Enable section for details on setting these operating levels. In Active Mode, depending on the load current, the TPS560430-Q1 will be in one of four modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple (for both PFM and FPWM versions). 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation (only for PFM version). 3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for PFM version). 4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for FPWM version).

8.4.3 CCM Mode

Continuous Conduction Mode (CCM) operation is employed in the TPS560430-Q1 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode and the maximum output current of 600 mA can be supplied by the TPS560430-Q1.

8.4.4 Light-Load Operation (PFM Version)

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the TPS560430-Q1 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM operation, the LS switch is turned off when the inductor current drops to ILS_ZC (20 mA typical) to improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load. At even lighter current load, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency operation. When either the minimum HS switch ON time tON_MIN or the minimum peak inductor current IPEAK_MIN (150mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode, switching frequency is decreased by the control loop to maintain output voltage regulation when load current reduces. Switching loss is further reduced in PFM operation due to less frequent switching actions.

8.4.5 Light-Load Operation (FPWM Version)

For FPWM version, TPS560430-Q1 is locked in PWM mode at full load range. This operation is maintained, even in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

accesses comprehensive databases of components. Please go to ti.com for more details.

9.2 Typical Application

fixed output voltage. Figure 15 shows a basic schematic. Figure 15. Application Circuit control loop. can be used to simplify the output filter component selection. Table 1. L and COUT Typical Values

9.2.1 Design Requirements

parameters listed in Table 2 as the input parameters. Table 2. Design Example Parameters

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS560430-Q1 device with the WEBENCH® Power Designer.

Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

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Run electrical simulations to see important waveforms and circuit performance
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ADVANCE□INFORMATION IN_MAX OUT OUT MIN OUT IND IN_MAX SW V - V VL = × I × K V × f OUT IN_MAX OUT L IN_MAX SW V × V - V ûL V × L × f OUT REF FBT FBB REF V - VR = × R V TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2.2 Output Voltage Set-Point

The output voltage of the TPS560430-Q1 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used to determine the output voltage of the converter: (7) Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1.0 V, the RFBT value can then be calculated using Equation 7. The formula yields to a value 88.4 kΩ, a standard value of 88.7 kΩ is selected.

9.2.2.3 Switching Frequency

The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in smaller solution size and lower component cost. However higher switching frequency brings more switching loss, which makes the solution less efficient and produce more heat. The switching frequency is also limited by the minimum on-time of the integrated power switch, the input voltage, the output voltage and the frequency shift limitation as mentioned in Minimum ON-Time, Minimum OFF-Time and Frequency Foldback section. For this example, a switching frequency of 2.1 MHz is selected.

9.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND should be 20% to 60%. During an instantaneous over current operation event, the RMS and peak inductor current can be high. The inductor current rating should be a bit higher than current limit. (8) (9) In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio. For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 8.6µH. Choose the nearest standard 8.2-µH ferrite inductor with a capability of 1-A RMS current and 1.5-A saturation current.

ADVANCE□INFORMATION OH OL OUT SW OUT_SHOOT 8 × I -I1C > × 2 f × û9 L IND OUT OUT_C SW OUT SW OUT ûL . × I û9 8× f × C 8× f × C OUT_ESR L IND OUTû9 ûL × ESR = K × I × ESR TPS560430-Q1 SLUSDF5 –JANUARY 2019 www.ti.com Product Folder Links: TPS560430-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

9.2.2.5 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability, output voltage overshoot and undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors: (10) The other is caused by the inductor current ripple charging and discharging the output capacitors: (11) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks. Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a large load step happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator’s control loop usually needs 8 or more clock cycles to regulate the inductor current equal to the new load level. The output capacitance must be large enough to supply the current difference for 8 clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum output capacitance needed for specified VOUT overshoot and undershoot. (12) where

KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
IOL = Low level output current during load transient
IOH = High level output current during load transient
VOUT_SHOOT = Target output voltage overshoot or undershoot For this design example, the target output ripple is 30 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30 mV, and chose KIND = 0.4. Equation 10 yields ESR no larger than 125 mΩ and Equation 11 yields COUT no smaller than 0.91 µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 4.3 µF by Equation 12. In summary, the most stringent criteria for the output capacitor is 4.3 µF. Consider of derating, one 10-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR is used.

ADVANCE□INFORMATION ENT ENB IN_FALLING ENH EN_HYS ENB R + RV = V - V × R IN_RISING ENT ENB ENH VR = -1 × RV § · ¨ ¸ ¨ ¸ © ¹ ENT ENB IN_RISING ENH ENB R + RV = V × R TPS560430-Q1 www.ti.com SLUSDF5 –JANUARY 2019 Product Folder Links: TPS560430-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2.6 Input Capacitor Selection

The TPS560430-Q1 device requires high frequency input decoupling capacitor(s). The typical recommended value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the current rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.

9.2.2.7 Bootstrap Capacitor

Every TPS560430-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

9.2.2.8 Under Voltage Lockout Set-Point

The system under voltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO level. (13) The EN rising threshold (VENH) for TPS560430-Q1 is set to be 1.23 V (typical). Choose the value of RENB to be 200 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can be calculated using Equation 14: (14) The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling UVLO threshold, equals 5.3 V, can be calculated by Equation 15, where EN hysteresis voltage, VEN_HYS, is 0.13 V (typical). (15)

9.2.3 Application Curves

Figure 16. Ripple at No Load Figure 17. Ripple at Full Load Figure 18. Start Up by VIN Figure 19. Start-Up by EN Figure 20. Load Transient Figure 21. Short Protection

Figure 22. Short Recovery

10 Power Supply Recommendations

The TPS560430-Q1 is designed to operate from an input voltage supply range between 4.0 V and 36 V. This input supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the TPS560430-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the TPS560430-Q1 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF or 22-µF electrolytic capacitor is a typical choice.

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. 1. The input bypass capacitor CIN must be placed as close as possible to the VIN and GND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the GND pin. 2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer. 3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible. 4. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 5. Provide adequate device heat-sinking. GND, VIN and SW pins provide the main heat dissipation path, make the GND, VIN and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125 °C.

11.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and GND pins is the key to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current conduction path to minimize parasitic resistance. The output capacitors should be placed close to the VOUT end of the inductor and closely grounded to GND pin.

11.1.2 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to the feedback resistor divider should be routed away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high value resistors are used to set the output voltage. It is recommended to route the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage feedback path from EMI noises.

11.2 Layout Example

Figure 23. Layout

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS560430-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

AN-1149 Layout Guidelines for Switching Power Supplies

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 19-Mar-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PS560430YFQDBVTQ1 ACTIVE SOT-23 DBV 6 250 TBD Call TI Call TI -40 to 125 PS560430YQDBVTQ1 ACTIVE SOT-23 DBV 6 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 19-Mar-2019 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF TPS560430-Q1 :

Catalog: TPS560430 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95

1.45 MAX

0.15

0.00 TYP

6X 0.50 0.25 0.6

0.3 TYP

0 TYP

1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/B 03/2018 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated

Product Information

PS560430YFQDBVRQ1 specifications and overview.

Summary

SIMPLE SWITCHER 4-V to 36-V, 600-mA synchronous step-down converter

Description

SIMPLE SWITCHER 4-V to 36-V, 600-mA synchronous step-down converter

Source title PS560430YFQDBVRQ1 Datasheet(PDF) - Texas Instruments

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