PS543B25TRASR

TPS543B25T_V01 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 43

Technical content

TPS543B25T 4-V to 18-V Input, 25-A, Synchronous, SWIFT™ Step-Down Converter With Internally Compensated, Advanced Current Mode Control in Thermally Enhanced Package

1 Features

• Fixed-frequency, internally compensated, advanced current mode (ACM) control
• Integrated 6.5-mΩ and 2-mΩ MOSFETs
• 4-V to 18-V input voltage range
• 0.5-V to 7-V output voltage range
• True differential remote sense amplifier (RSA)
• Three selectable PWM ramp options to optimize the control loop performance
• Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz
• Synchronizable to an external clock
• 0.5-V, ±0.5% voltage reference accuracy over full temperature range
• 1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times
• Monotonic start-up into prebiased outputs
• Selectable current limits to support 25-A and 20-A operation
• Enable with adjustable input undervoltage lockout
• Power-good output monitor
• Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection
• –40°C to 150°C operating junction temperature
• 2.5-mm × 4.5-mm, 17-pin WQFN-HR package with 0.5-mm pitch
• Lead-free (RoHS compliant), Lead-free (Pb-free) conversion
• Pin compatible with the 20 A-TPS543B22 , 16 A- TPS543A26 and 12 A-TPS543A22
• WEBENCH® and SIMPLIS models available

2 Applications

• Wireless and wired communications infrastructure equipment
• Optical and fiber networks
• Test and measurement
• Medical and healthcare

3 Description

The TPS543B25T is a high-efficiency 18-V, 25-A synchronous buck converter employing an internally compensated, fixed-frequency advanced current mode (ACM) control architecture, which while always operating under FCCM, generates output voltages from 0.5 V to 7 V. The device is capable of providing high efficiency while operating at a switching frequency up to 2.2 MHz, making the device optimal for designs requiring a small solution size. The fixed frequency controller can operate from 500 kHz to

2.2 MHz and can be synchronized to an external

clock using the SYNC pin. Additional features include a high accuracy voltage reference, two-wire remote sense, selectable soft-start times, monotonic start- up into prebiased outputs, selectable current limits, adjustable UVLO through the EN pin, and a full suite of fault protections. The TPS543B25T is available in a small 2.5-mm × 4.5-mm HotRod™ WQFN-FCRLF package.

Package Information

PART NUMBER PACKAGE (1) PACKAGE SIZE(2) TPS543B25T RAS (WQFN-FCRLF, 17) 2.50 mm × 4.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. RMSEL 2.2 μ F CIN 10 Ω CBOOT COUT RFBT RFBB PGND AGND VOUT0.1 μ F RFSEL AGND PGND PGND VIN VIN VDRV VCC SYNC/FSEL MSEL BOOT SW FB GOSNS AGND PGND L TPS543B25T Simplified Application Output Current (A) Efficiency (%) 0 5 10 15 20 25 100 Vin = 12V 150nH 0.39m  V OUT = 1.0 V, 1 MHz V OUT = 1.2 V, 1 MHz V OUT = 1.5 V, 1 MHz V OUT = 1.8 V, 1 MHz V OUT = 3.3 V, 1 MHz Typical Application Efficiency ADVANCE INFORMATION TPS543B25T SLVSH68 – JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2023 * Initial release TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

5 Pin Configuration and Functions

Figure 5-1. 17-Pin WQFN-FCRLF RYS Package (Bottom View) 6 7 121314 Not to scale BOOT PGND SW VIN EN PG SYNC/FSELAGND VCC VDRV VIN PGND FB GOSNS MSEL PGND PGND Figure 5-2. 17-Pin WQFN-FCRLF RYS Package (Top View) Table 5-1. Pin Functions Pin Type(1) Description Name No. AGND 1 — Ground return for internal analog circuits VCC 2 I Supply for analog control circuitry. Connect a 10-Ω resistor from VDRV to this pin and bypass with a 0.1-μF capacitor to AGND. VDRV 3 O Internal 5-V regulator output and internal connection to drivers. Bypass these pins with a 2.2-μF capacitor to PGND. See Section 7.3.2. VIN 4, 9 I Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 1-μF capacitor from each VIN to PGND close to the IC is required. PGND 5, 8, 16, 17 — Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET. SW 6 O Switch node of the converter. Connect this pin to the output inductor. BOOT 7 I Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to SW. EN 10 I Enable pin. Float or tie high to enable, or enable and disable with an external signal, or adjust the input undervoltage lockout with a resistor divider. See Section 7.3.3. PG 11 O Open-drain power-good indicator. See Section 7.3.10. SYNC/FSEL 12 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the MSEL 13 I A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude. See Section 7.3.9. GOSNS 14 I Ground sense return and input to the differential remote sense amplifier FB 15 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set the output voltage. See Section 7.3.6. (1) I = input, O = output www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS543B25T

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20 ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20 ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage VCC, VDRV –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG 5 mA TJ Operating junction temperature –40 150 °C Tstg –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to PGND.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 25 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1) UNITRAS (QFN, JEDEC) RAS (QFN, TI EVM)

17 PINS 17 PINS

RθJA Junction-to-ambient thermal resistance 33.9 18.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.2 Not applicable (2) °C/W RθJB Junction-to-board thermal resistance 5.5 Not applicable (2) °C/W TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

6.4 Thermal Information (continued)

THERMAL METRIC(1) UNITRAS (QFN, JEDEC) RAS (QFN, TI EVM) ψJT Junction-to-top characterization parameter 0.7 1.3 °C/W ψJB Junction-to-board characterization parameter 5.5 6.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 Not applicable °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Not applicable to an EVM layout.

6.5 Electrical Characteristics

TJ = –40°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 20 32 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.8 4.00 4.2 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO VVDRV Internal linear regulator output voltage VVIN = 12 V, IVDRV = 25 mA 4.5 V Internal linear regulator dropout voltage VVIN – VVDRV, VVIN = 3.8 V, IVDRV = 25 mA 390 mV Internal linear regulator short-circuit current limit VVIN = 12 V 150 mA VCCUVLO(R) VCC UVLO rising threshold 3.4 V VCCUVLO(H) VCC UVLO hysteresis 0.4 V ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.75 µA EN pin sourcing current VEN = 1.3 V 11.6 µA EN HIGH to start of switching delay (1) EN from 0V to 3V rising 1 ms REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 150°C 497.5 500 502.5 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 3 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V FSYNC(range) Frequency synchronization range to not adversly affect loop stability. (1) FCLK – 20% FCLK + 20% www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS543B25T

6.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SOFT-START tSS1 Soft-start time 0 to 100% VOUT RMSEL = 2.1 kΩ 1 ms tSS2 Soft-start time 0 to 100% VOUT RMSEL = 2.49 kΩ 2 ms tSS3 Soft-start time 0 to 100% VOUT RMSEL = 2.94 kΩ 4 ms tSS4 Soft-start time 0 to 100% VOUT RMSEL = 3.57 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VVDRV = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 28 ns TOFF(min) Minimum OFF pulse width (1) 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit RMSEL = 2.1 kΩ 32.4 36 39.6 A IHS(OC2) RMSEL = 22.1 kΩ 26.1 29 31.9 A ILS(OC1) Low-side valley current limit RMSEL = 2.1 kΩ 24.75 27.5 30.25 A ILS(OC2) RMSEL = 22.1 kΩ 19.8 22 24.2 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120% VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80% VREF POWER GOOD Power-good threshold VFB rising (Good) 88% 91% 94% VREF Power-good threshold VFB rising (OV Fault) 112% 115% 118% VREF Power-good threshold VFB falling (Good) 103.5% 106.5% 109.5% VREF Power-good threshold VFB falling (UV Fault) 79% 82% 85% VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.6 V Min VIN for valid PG output EN = 0V, PGOOD pulled up to 5V 1 V PG delay going from low to high 201 us PG delay going from high to low 11 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 175 °C TJ(HYS) Thermal shutdown hysteresis (1) 12 °C (1) Specified by design TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

6.6 Typical Characteristics

Junction Temperature ( o C) R DSON(HS) (mOhm) -50 -25 0 25 50 75 100 125 150 V(BOOT- SW) = 4.5 V Figure 6-1. High-Side FET RdsON Junction Temperature ( o C) R DSON(LS) (mOhm) -50 -25 0 25 50 75 100 125 150 V(VDRV) = 4.5 V Figure 6-2. Low-Side FET RdsON Junction Temperature ( o Overcurrent Limit (A) -50 -25 0 25 50 75 100 125 150 High Limit Low Limit Figure 6-3. Overcurrent Limit Junction Temperature ( o C) Negative Overcurrent Limit (A) -50 -25 0 25 50 75 100 125 150 Figure 6-4. Negative Overcurrent Limit Junction Temperature ( o C) Enable(V) -50 -25 0 25 50 75 100 125 150 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 EN voltage to Switch Rising Falling Figure 6-5. Enable Voltage Junction Temperature ( o C) Voltage Reference (V) -50 -25 0 25 50 75 100 125 150 0.475 0.4875 0.5 0.5125 0.525 Figure 6-6. VREF www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS543B25T

6.6 Typical Characteristics (continued)

Junction Temperature ( o C) VIN UVLO (V) -60 -40 -20 0 20 40 60 80 100 120 140 160 3.75 3.875 4.125 4.25 Rising Figure 6-7. VIN UVLO Junction Temperature ( o C) VCC UVLO (V) -50 -25 0 25 50 75 100 125 150 2.25 2.5 2.75 3.25 3.5 3.75 Rising Falling Figure 6-8. VCC UVLO Figure 6-9. PG Threshold Figure 6-10. PG Leakage Current Junction Temperature ( o C) Enable Pin Current ( A) -50 -25 0 25 50 75 100 125 150 0.5 1.5 2.5 3.5 4.5 VIN = 4V VIN = 12V VIN = 18V Figure 6-11. Enable Pin Current at Different VIN Junction Temperature ( o C) Soft Start Time (ms) -50 -25 0 25 50 75 100 125 150 1 ms 2 ms 4 ms 8 ms Figure 6-12. Soft Start TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

Junction Temperature ( o C) Supply Current (mA) -50 -25 0 25 50 75 100 125 150 0.5 1.5 2.5 3.5 4.5 VIN = 12 V EN = 1.3 V FB = 550 mV Figure 6-13. Non-Switching Supply Current Junction Temperature ( o C) Shutdown Current (  A) -50 -25 0 25 50 75 100 125 150 VIN = 12V EN = 0V Figure 6-14. Shutdown Supply Current 8/31/2022 Junction Temperature ( o C) VDRV Voltage (V) -50 -25 0 25 50 75 100 125 150 2.5 3.5 4.5 VIN = 4 V VIN = 12 V VIN = 18 V Figure 6-15. VDRV vs Temperature Junction Temperature ( o C) Switching Frequency (kHz) -50 -25 0 25 50 75 100 125 150 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 500 kHz 750 kHz 1000 kHz 1500 kHz 2200 kHz Figure 6-16. Switching Frequency vs Temperature www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS543B25T

7 Detailed Description

7.1 Overview

The TPS543B25T is a 25-A, high-performance, synchronous buck converter with two integrated N-channel MOSFETs. The TPS543B25T has a maximum operating junction temperature of 150°C, making the device designed for high-ambient temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The device features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin. Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPS543B25T has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see Section 7.3.7.2 for details). The TPS543B25T is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise.

7.2 Functional Block Diagram

ILIMOC_FLT OC_FLT Thermal Shutdown UVLO VIN_UVLOUVLOVCC_UVLO VIN_UVLO VCC_UVLO EN_UVLO EN_UVLO UVLOBOOT SW GOSNS Remote Sense VCC AGND

7.3 Feature Description

7.3.1 VIN Pins and VIN UVLO

The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for V IN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal V IN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

A second means to enable the device is provided by interfacing to the EN pin. See Section 7.3.3 for more details.

7.3.2 Internal Linear Regulator and Bypassing

The VDRV pin is connected internally to the output of the internal (4.5 V nominal) linear regulator (LDO) and to the MOSFET drivers. Bypass VDRV to PGND with a ceramic capacitor. TI recommends a value of 2.2 μF to 10 μF. The VCC pin is the source for the internal control circuitry. Connect a 10- Ω resistor from VDRV to VCC and bypass VCC to AGND with a ceramic capacitor (0.1 μF recommended). UV To analog, digital circuits To bootstrap, drivers AGND PGND 2.2 μF 0.1 μF UV Linear Regulator (LDO) VCC VDRV VIN Figure 7-1. Device Bypassing Not intended to drive VCC with any source other than VDRV. Not intended to connect VDRV to any external source or load.

7.3.3 Enable and Adjustable UVLO

The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Make sure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in Figure 7-2. The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 1 and Equation 2. When using the adjustable UVLO function, TI recommends 500 mV or greater hysteresis. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS543B25T

Figure 7-2. Adjustable UVLO Using EN ENFALLING START STOP ENRISING ENT ENFALLING p h ENRISING VV V VR VI 1 I V § · u ¨ ¸ © ¹ § · u ¨ ¸ © ¹ (1) ENT ENFALLING ENB STOP ENFALLING ENT p h R V R V V R I I u u (2)

7.3.3.1 Internal Sequence of Events During Startup

The enable feature of the TPS543B25T provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPS543B25T reads the pin strap configuration as determined by the state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPS543B25T initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

EN Lower THRESHOLD 0.8 V Enable LDO Soft Start EN Upper Threshold 1.2 V Read Pin Strap, assumes LDOOK Power ON Delay Initialize control circuits Figure 7-3. Internal Start-Up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical).

7.3.4 Switching Frequency Selection

The switching frequency of the device is selected by connecting a resistor (R FSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in Table 7-1. It is required to use a 1% tolerance resistor or better. Table 7-1. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200

7.3.5 Switching Frequency Synchronization to an External Clock

The TPS543B25T can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS543B25T

7.3.5.1 Internal PWM Oscillator Frequency

When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to Section 7.3.5.3. The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Table 7-2. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. Table 7-3 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Table 7-3. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884

7.3.5.2 Loss of Synchronization

If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

Figure 7-4. Clock Synchronization Transition

7.3.5.3 Interfacing the SYNC/FSEL Pin

If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the R FSEL value. Figure 7-5 shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the R FSEL value. Power the buffer from the VDRV output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the R FSEL value. When powering the buffer from the VDRV pin, the external load on the VDRV pin must be less than 2 mA. RFSEL VDRV SYNC/FSEL VCC GND Figure 7-5. Interfacing the SYNC/FSEL Pin with a Buffer

7.3.6 Remote Sense Amplifier and Adjusting the Output Voltage

Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (V OUT) to the FB pin as shown in Figure 7-6. Use 1% tolerance or better divider resistors. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS543B25T

Figure 7-6. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 k Ω, use Equation 3 to calculate the top resistor in the divider. OUT FBT FBB REF VR R 1 V § · u ¨ ¸ © ¹ (3)

7.3.7 Loop Compensation Guidelines

The TPS543B25T employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying V IN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections.

7.3.7.1 Output Filter Inductor Tradeoffs

The selection of the output inductor is one of the most important choices to make in designing a converter. The following is a short list of considerations to make when determining the value of the inductance used. Other considerations are found in the Section 8. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = VIN − VOUT ∆ I × VOUT VIN × 1 fSW (4)

• A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response.
• The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold.
• The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses.

7.3.7.2 Ramp Capacitor Selection

The TPS543B25T uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see Section 7.3.9). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in Figure 8-1. Many applications perform best with a CRAMP value of 4 pF, however, its up to the user to measure the loop gain and phase to determine the optimum CRAMP value for their specific application. 1. First, calculate the RAMP time constant using Equation 5 and Table 7-4. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

τCRAMP = CRAMP × 10 6 Lookup1 − Lookup2 × VOUT VIN (5) Table 7-4. RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 2. Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. VCRAMP = VIN × tON + 100 ns τCRAMP (6)

• A larger CRAMP capacitance results in highest loop gain.
• A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. Figure 7-7 and Figure 7-8 show how the loop changes with each ramp setting for the schematic in Section 8. Frequency (Hz) Gain (dB) 1000 2000 5000 10000 100000 1000000 -40 -30 -20 -10 Vin = 12 V, Vout = 1.0 V Iout = 25 A 1000 kHz Ramp = 1pF Ramp = 2pF Ramp = 4pF Figure 7-7. Loop Gain vs Ramp Settings Frequency (Hz) Phase ( o 1000 2000 5000 10000 100000 1000000 -180 -135 -90 -45 135 180 225 Vin = 12 V, Vout = 1.0 V Iout = 25 A 1000 kHz Ramp = 1pF Ramp = 2pF Ramp = 4pF Figure 7-8. Loop Phase vs Ramp Settings

7.3.7.3 Output Capacitor Selection

• Ensure the ESR zero frequency of the capacitors used is at least 5× the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. fESR_ZERO = 1 2π × R ESR × C (7)
• The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability.
• The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease.
• The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS543B25T

VRIPPLE = ∆ I × RESR + 1 2π × f SW × C (8)

7.3.7.4 Design Method for Good Transient Response

The following method to design converter compensation optimizes the load transient response. 1. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. ZOUT_REQUIRED = delta_V OUT delta_I OUT (9) 2. Select a value for output inductance. L = VIN − VOUT ∆ I × VOUT VIN × 1 fSW (10) 3. Calculate the required converter output impedance to meet the transient response goal. ZOUT_CONVERTER = 0.00135 + L τ CRAMP 34 × VOUT VREF (11) Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. 4. Calculate the minimum output capacitance required to meet the impedance requirements. COUT_MIN = 1 2π × Z OUT_CONVERTER × f CO_DESIRED (12) where

• fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. 5. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z CAPACITOR = R ESR_CAPACITOR + 1 2π × C CAPACITOR × F CO (13) NCAPACITORS = ZCAPACITOR ZOUT_CONVERTER (14) 6. Using one of the tools on TI.com, simulate with the values for the design.

7.3.8 Soft Start and Prebiased Output Start-Up

During start-up, the device softly increases the reference voltage from zero to its final value, thereby reducing converter inrush current. There are four options for the soft-start time, which is the time it takes for the reference to ramp to 0.5 V:

• 1 ms
• 2 ms
• 4 ms
• 8 ms The soft-start time is selected with a resistor to AGND on the MSEL pin. See Section 7.3.9. If a prebiased output condition exists prior to start-up, the device prevents current from being discharged from the output. During monotonic prebiased start-up, the low-side MOSFET is not allowed to sink current until the SS pin voltage is higher than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if the BOOT-SW voltage is below its UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

to turn on to charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another layer of protection for the device after the high-side MOSFET begins to switch.

7.3.9 MSEL Pin

The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, R MSEL, from MSEL to AGND. Table 7-5 lists the resistor values for the available options. Use a 1% tolerance resistor or Table 7-5. MSEL Pin Selection RMODE (kΩ) Current Limits CRAMP (pF) Soft-Start Time (ms)

1.78 High 1 1

2.21 High 1 2

2.74 High 1 4

3.32 High 1 8

4.02 High 2 1

4.87 High 2 2

5.9 High 2 4

7.32 High 2 8

9.09 High 4 1

11.3 High 4 2

14.3 High 4 4

18.2 High 4 8

22.1 Low 1 1

26.7 Low 1 2

33.2 Low 1 4

40.2 Low 1 8

49.9 Low 2 1

60.4 Low 2 2

76.8 Low 2 4

102 Low 2 8

137 Low 4 1

174 Low 4 2

243 Low 4 4

412 Low 4 8

7.3.10 Power Good (PG)

The TPS543B25T PG pin is an open-drain output requiring an external pullup resistor to output a high signal. After the FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a 256-µs deglitch time, the PG pin is de-asserted and the pin floats. TI recommends a pullup resistor between the values of 10 k Ω and 100 k Ω to a voltage source that is 5.5 V or less. PG is in a defined state after the VIN input voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or greater than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PG pin is pulled low. PG is immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters thermal shutdown.

7.3.11 Output Overload Protection

The TPS543B25T protects against output overload (that is, overcurrent) events by cycle-by-cycle current limiting both the high-side MOSFET and low-side MOSFET. In an extended overcurrent condition, the device enters hiccup mode. Different protections are active during positive inductor current and negative inductor current conditions. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS543B25T

7.3.11.1 Positive Inductor Current Protection

Current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls below the low-side MOSFET overcurrent threshold, effectively limiting the peak current in the case of a short-circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup mode. The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received from the controller, the device skips processing that PWM pulse. The device does not turn the high-side MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate counters for the high-side and low-side overcurrent events. If the off time is too short, the low-side overcurrent can not trip. The low-side overcurrent, however, begins tripping after the high-side peak overcurrent limit is crossed, as exceeding the peak current limit shortens the on time and lengthens the off time. Both the high-side and low-side positive overcurrent thresholds are programmable using the MSEL pin. Two sets of thresholds are available ("High" and "Low"), which are summarized in Table 7-6. The values for these thresholds are obtained using open-loop measurements with a DC current to accurately specify the values. In real applications, the inductor current ramps and the ramp rate is a function of the voltage across the inductor (VIN – VOUT) as well as the inductance value. The ramp rate combined with delays in the current sense circuitry then results in slightly different values than specified. The current at which the high-side overcurrent limit takes effect can be slightly higher than specified, and the current at which the low-side overcurrent limit takes effect can be slightly lower than specified. Table 7-6. Overcurrent Thresholds MSEL Current Limit Setting High-Side Overcurrent Typical Value (A) Low-Side Overcurrent Typical Value (A) High 36 27.5 Low 29 22

7.3.11.2 Negative Inductor Current Protection

Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is immediately turned off. The next high-side MOSFET turn-on is determined by the clock and PWM comparator. The negative overcurrent threshold minimum value is 7 A. Similar to the positive inductor current protections, the actual value of the inductor current when the current sense comparators trip is a function of the current ramp rate. As a result, the current at which the negative inductor current limit takes effect can be slightly more negative than specified.

7.3.12 Output Overvoltage and Undervoltage Protection

The TPS543B25T incorporates both output overvoltage and undervoltage protection. If an overvoltage is detected, the device tries to discharge the output voltage to a safe level before attempting to restart. When the overvoltage threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent threshold is reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero. Then, the low-side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. The process repeats until the output voltage falls back into the PG window. After this happens, the device restarts and goes through a soft start cycle. The device does not wait the hiccup time before restarting. When an undervoltage condition is detected, the device enters hiccup where it waits seven soft-start cycles before restarting. Undervoltage protection is enabled after soft start is complete. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

7.3.13 Overtemperature Protection

When the die temperature exceeds 165°C, the device turns off. After the die temperature cools below the hysteresis level, typically by 12°C, the device restarts. While waiting for the temperature to fall below the hysteresis level, the device does not switch or attempt to hiccup to restart. After the temperature falls below the hysteresis level, the device restarts without going through hiccup.

7.3.14 Output Voltage Discharge

When the TPS543B25T is enabled, but the high-side FET and low-side FET are disabled due to a fault condition, the output voltage discharge mode is enabled, turning on the discharge FET from SW to PGND to discharge the output voltage. The discharge FET is turned off when the converter is ready to resume switching, either after the fault clears or after the wait time before hiccup is over. The output voltage discharge mode is activated by any of the following fault events:

• High-side or low-side positive overcurrent
• Thermal shutdown
• Output voltage undervoltage
• VIN UVLO

7.4 Device Functional Modes

7.4.1 Forced Continuous-Conduction Mode

The TPS543B25T operates in forced continuous-conduction mode (FCCM) throughout normal operation.

7.4.2 Discontinuous Conduction Mode During Soft Start

At the beginning of soft start, the converter operates in discontinuous conduction mode (DCM) for the first 16 PWM cycles. During this time, a zero-cross detect comparator is used to turn off the low-side MOSFET when the current reaches zero amps, preventing the discharge of any prebiased conditions on the output. After the 16 cycles of DCM, the converter enters FCCM mode for the remainder of start-up and into regulation. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS543B25T

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPS543B25T is a synchronous buck converter designed for 4-V to 18-V input and 25-A load. This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.

8.2 Typical Applications

8.2.1 1.0-V Output, 1-MHz Application SW Output: 1.0 V at 25 AVIN10µFCI41uFCHF2 0.1uFEN CBTFB FSEL Net-TiePGND MODE PGNDNet-Tie 10kRPGD CFFPGNDAGNDRMODERFSEL RFBTRFBBPGND EN AGND 100uFCO4100µFCO3100uFCO2100uFCO1 AGND 10uF1uFCI3CHF122uFCI5 22uFCI6PGND AGND0.1uFCBP2.2uFCBIAS 10.0RBODE10.0RFLTVCC VO_SNSBODE-RENBRENT CI7 0CI8 RBT Net-Tie + CBULK LOVIN VOUT2 V C C V I N 4 VIN 9 P G N D 5 - 8

7 B O O T

1 0 E N F B 1 5 G O S N S 1 4 M S E L 1 3 P G 1 1 S W 6 1 2 S Y N C / F S E L V D R V 3 A G N D 1 P G N D 1 6 P G N D 1 7 U 1 100uFCO5100uFCO6 Figure 8-1. 12-V Input, 1.0-V Output, 1-MHz Schematic

8.2.1.1 Design Requirements

For this design example, use the parameters shown in Table 8-1. Table 8-1. Design Parameters Parameter Example Value Input voltage range (VIN) 4.5 to 18 V, 12-V nominal Output voltage (VOUT) 1.0 V Output current rating (IOUT) 25A Switching frequency (fSW) 1000 kHz Steady state output ripple voltage 10 mV Output current load step 12.5 A Transient response ± 50 mV (± 5%) TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Switching Frequency

The first step is to decide on a switching frequency. The TPS543B25T can operate at five different frequencies from 500 kHz to 2.2 MHz. f SW is set by the resistor value from the FSEL pin to ground. Typically, the highest switching frequency possible is desired because it produces the smallest solution size. A high switching frequency allows for smaller inductors and output capacitors compared to a power supply that switches at a lower frequency. The main tradeoff made with selecting a higher switching frequency is extra switching power loss, which hurts the efficiency of the regulator. The maximum switching frequency for a given application can be limited by the minimum on time of the regulator and the maximum f SW can be estimated with Equation 15. Using the maximum minimum on time of 40 ns and 18.0-V maximum input voltage for this application, the maximum switching frequency is 1389 kHz. The selected switching frequency must also consider the tolerance of the switching frequency. A switching frequency of 1000 kHz was selected for a good balance of solution size and efficiency. To set the frequency to 1000 kHz the selected FSEL resistor is 11.8 kΩ per Table 7-1. OUT SW IN V1f max tonmin V max u (15) Figure 8-2 shows the maximum recommended input voltage versus output voltage for each FSEL frequency. This graph uses the maximum minimum on time of 40 ns and includes 10% tolerance on the switching frequency. Output Voltage (V) Maximum Input Voltage (V) fsw = 500 kHz fsw = 750 kHz fsw = 1000 kHz fsw = 1500 kHz fsw = 2200 kHz Figure 8-2. Maximum Input Voltage vs Output Voltage

8.2.1.2.2 Output Inductor Selection

To calculate the value of the output inductor, use Equation 16 . K IND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. Choosing small inductor ripple currents can degrade the transient response performance. The inductor ripple, KIND, is normally from 0.1 to 0.4 for the majority of applications giving a peak to peak ripple current range of 2 A to 8 A. The target IRIPPLE must be 1 A or larger. For this design example, KIND = 0.2 is used and the inductor value is calculated to be 0.183 µH. An inductor with an inductance of 0.150 µH is selected. It is important that the RMS (root mean square) current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 18 and Equation 19. For this design, the RMS inductor current is 25.96A, and the peak inductor current is 28.498 A. The chosen inductor is a SLR1050A-151KEC. The inductor has a saturation current rating of 51 A, an RMS current rating of 56.7 A, and a typical DC series resistance of 0.39 mΩ. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS543B25T

The peak current through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated in Equation 19. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify the current ratings of the inductor based on the switch current limit rather than the steady-state peak inductor current. L1 = VIN − VOUT Io × K IND × VOUT VIN × 1 fSW (16) Iripple = VINMAX − VOUT L1 × VOUT VINMAX × f SW (17) ILrms = IO 2 + 1 12 × VINMAX − VOUT L1 × VOUT VINMAX × f SW (18) vertical spacer ILpeak = I OUT + Iripple 2 (19)

8.2.1.2.3 Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these criteria. The desired response to a large change in the load current is the first criteria and is typically the most stringent. A regulator does not respond immediately to a large, fast increase or decrease in load current. The output capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop must sense the change in the output voltage then adjust the peak switch current in response to the change in load. The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop bandwidth is near fSW / 10. Equation 20 estimates the minimum output capacitance necessary. For this example, the transient load response is specified as a 5% change in V OUT for a load step of 12.5 A. Therefore, ΔIOUT is 12.5 A and ΔVOUT is 50 mV. Using this target gives a minimum capacitance of 398 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response. OUT OUT SWOUT I 1C fV 2 10 '! u ' Su (20) where

• ΔIOUT is the change in output current.
• ΔVOUT is the allowable change in the output voltage. In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down after a load step down can be the limiting factor. Equation 21 estimates the minimum output capacitance necessary to limit the change in the output voltage after a load step down. Using the 0.150-µH inductance selected gives a minimum capacitance of 234 µF. OUT OUT OUT OUT OUT L I C 2 V V u ' ! u ' u (21) TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the target maximum steady state output voltage ripple is 10 mV. Under this requirement, Equation 22 yields 88 µF. 1 1Co > Voripp le8 sw Irip ple /c180 /c180 /c166 (22) where

• ΔIOUT is the change in output current.
• ΔVOUT is the allowable change in the output voltage.
• fSW is the regulators switching frequency.
• VORIPPLE is the maximum allowable steady state output voltage ripple.
• IRIPPLE is the inductor ripple current. Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on the MODE pin. Equation 23 estimates the minimum capacitance needed for loop stability. Equation 23 sets the minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum value. See Figure 8-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 1-V output, the minimum ratio is 35 and with this ratio, Equation 23 gives a minimum capacitance of 207 µF. OUT SW OUT Ratio 1C 2 f L (23) Equation 24 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and this shows the ESR must be less than 6 m Ω. In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple. Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data sheet specifies the RMS value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor must support. For this application, Equation 25 yields 1.2 A and ceramic capacitors typically have a ripple current rating much higher than this. Vo rippleResr < Iripple (24) vertical spacer /c180 /c45 /c180 /c180 /c180 /c166 Vout (Vinm ax Vout)Icorm s =

12 Vinm ax L1 sw

(25) Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website. For this application example, six 100-µF, 10-V, X5R, 1210 ceramic capacitors each with 3 m Ω of ESR are used. With the six parallel capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer's website is 570 µF. There is about -5% DC bias derating at 1 V. This design was able to use less than the calculated minimum because the loop crossover frequency was above the f SW / 10 estimate as shown in Figure 8-8. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS543B25T

8.2.1.2.4 Input Capacitor

Input decoupling ceramic capacitors type X5R, X7R, or similar from VIN to PGND that are placed as close as possible to the IC are required. A total of at least 66 µF of capacitance is required and some applications can require a bulk capacitance. TI recommends at least 1 µF of bypass capacitance as close as possible to each VIN pin to minimize the input voltage ripple. A 1-µF capacitor must be placed as close as possible to both VIN pins 4 and 9 on the same side of the board of the device to provide high frequency bypass to reduce the high frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum RMS input current. The RMS input current can be calculated using Equation 26. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. Two 22-µF, 1210, X7R, 25-V, two 10-µF, 0805, X7S, 25-V, and two 1- μF, 0402 or 0603, X7R 25-V capacitors in parallel has been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 25 µF at the nominal input voltage of 12 V. Additional 100-µF ceramic capacitance and 220-µF aluminum electrolytic are also used to bypass long leads when connected a lab bench top power supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 26. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the nominal design example values of I OUT(MAX) = 25 A , C IN = 25 μF, and f SW = 1000 kHz, the input voltage ripple with the 12-V nominal input is 76.4 mV and the RMS input ripple current with the 4.5-V minimum input is 10.39 A. ICINRMS = I OUT × VINMIN − VOUT VINMIN × VOUT VINMIN (26) vertical spacer ∆ VIN = IOUTMAX × 1 − VOUT VIN × VOUT VIN CIN × fsw (27)

8.2.1.2.5 Adjustable Undervoltage Lockout

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R ENT and R ENB. The UVLO has two thresholds: one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. For the example design, the supply is set to turn on and start switching after the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts switching, it continues to do so until the input voltage falls below 3.95 V (UVLO stop or disable). In this example, these start and stop voltages set by the EN resistor divider were selected to have more hysteresis than the internally fixed VIN UVLO. Equation 1 and Equation 2 can be used to calculate the values for the upper and lower resistor values. For these equations to work, V START must be 1.1 × V STOP due to the voltage hysteresis of the EN pin. For the voltages specified, the standard resistor value used for RENT is 16.9 kΩ and for RENB is 6.04 kΩ. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

8.2.1.2.6 Output Voltage Resistors Selection

The output voltage is set with a resistor divider created by R FBT and R FBB from the output node to the FB pin. Use 1% tolerance or better resistors. For this example design, 4.99 k Ω was selected for R FBB. Using Equation 28, RFBT is calculated as 4.99 kΩ. This is a standard 1% resistor. OUT FBT FBB REF VR R 1 V § · u ¨ ¸ © ¹ (28) If the PCB layout does not use the recommended AGND to PGND connection in Section 8.4.1, noise on the feedback pin can degrade the output voltage regulation at maximum load. Using a smaller R FBB of 1.00 k Ω minimizes the impact of this noise.

8.2.1.2.7 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. The capacitor must be rated for at least 10-V to minimize DC bias derating. A resistor be added in series with the BOOT capacitor to slow down the turn on of the high-side MOSFET and reduce overshoot rising edge overshoot on the SW pin. This comes with the tradeoff of more power loss and lower efficiency.

8.2.1.2.8 VDRV and VCC Capacitor Selection

A 2.2-µF ceramic capacitor must be connected between the VDRV pin and PGND for proper operation. The capacitor must be rated for at least 10 V to minimize DC bias derating. The VDRV pin is the output of an internal linear regulator and the supply to the gate drivers. The VCC pin is the supply for the analog control circuits and must have a 0.1-µF and 10-V rated or better ceramic capacitor connected from VCC to AGND. A 10- Ω 0402 resistor must be connected between the VDRV to VCC pins.

8.2.1.2.9 PGOOD Pullup Resistor

A 10-kΩ resistor is used to pull up the power-good signal when FB conditions are met. The pullup voltage source must be less than the 6-V absolute maximum of the PGOOD pin.

8.2.1.2.10 Current Limit Selection

The MODE pin is used to select between two current limit settings. Select the current limit setting whose minimum is greater than at least 1.1 times the maximum steady state peak current. This is to provide margin for component tolerance and load transients. For this design, the minimum current limit must be greater than 7.45 A so the high current limit setting is selected.

8.2.1.2.11 Soft-Start Time Selection

The MODE pin is used to select between four different soft-start times, which is useful if a load has specific timing requirements for the output voltage of the regulator. A longer soft-start time is also useful if the output capacitance is very large and requires large amounts of current to quickly charge the output capacitors to the output voltage level. The large currents necessary to charge the capacitor can reach the current limit or cause the input voltage rail to sag due excessive current draw from the input power supply. Limiting the output voltage slew rate solves both of these problems. The example design has the soft-start time set to 1.0 ms. With this soft-start time, the current required to charge the output capacitors to the nominal output voltage is only 0.14 A. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS543B25T

8.2.1.2.12 Ramp Selection and Control Loop Stability

The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends on V OUT, f SW, L OUT, and C OUT. To get started, calculate LC double pole frequency using Equation 29. Then calculate the ratio between f SW and f LC. Based on this ratio and the output voltage, select the recommended ramp setting using Figure 8-3 . With a 1-V output, TI recommends the 1-pF ramp for ratios between approximately 35 and 58, TI recommends the 2-pF ramp for ratios between approximately 58 and 86, and TI recommends the 4-pF ramp for ratios greater than approximately 86. In general, use the largest ramp capacitor the design can support. Increasing the ramp capacitor improves transient response but can reduce stability margin or increase on-time jitter. For this design, f LC is 17.5 kHz and the ratio is 57 which is on the border of the 1-pF and 2-pF ramp settings. Through bench evaluation, it was found the design had sufficient stability margin with the 2-pF ramp so this setting was selected for the best transient response. The recommended ramp settings given by Figure 8-3 include margin to account for potential component tolerances and variations across operating conditions so it is possible to use a higher ramp setting as shown in this example. LC OUT OUT

2 L C

(29) fSW/fLC Output Voltage (V) 20 30 40 50 60 70 80 90 100 0.5 1.5 2.5 3.5 4.5 5.5 4 pF 2 pF 1 pF Figure 8-3. Recommended Ramp Settings Use a feedforward capacitor (C FF) in parallel with the upper feedback resistor (R FBT) to add a zero into the control loop to provide phase boost. Include a placeholder for this capacitor as the zero it provides can be required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the zero. The pole and zero frequency are not independent so as a result, after the zero location is chosen, the pole is fixed as well. The zero is placed at 1 / 4 the f SW by calculating the value of C FF with Equation 30. The calculated value is 128 pF — round this down to the closest standard value of 120 pF. Using bench measurements of the AC response, the feedforward capacitor for this example design was increased to 180 pF to improve the transient response. FF SW FBT 1C fR 2 Su u (30) TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

Using a larger feedforward capacitors to further improve the transient response but take care to ensure there is a minimum of –9-dB gain margin in all operating conditions is possible. The feedforward capacitor injects noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node. Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 100- Ω resistor in series with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer together degrading the phase boost the feedforward capacitor provides. When using higher ESR output capacitors, such as polymer or tantalum, their ESR zero (f ESR) must be accounted for. The ESR zero can be calculated using Equation 31 . If the ESR zero frequency is less than the estimated bandwidth of 1/10th the fSW, it can affect the gain margin and phase margin. A series R-C from the FB pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this design so the effect of the ESR zero is ignored. ESR OUT ESR 1f 2 C R uSu u (31)

8.2.1.2.13 MODE Pin

The MODE resistor is set to 4.87 k Ω to select the high current limit setting, 2.0-ms soft-start, and the 2-pF ramp. See Table 7-5 for the full list of the MODE pin settings. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS543B25T

8.2.1.3 Application Curves

Output Current (A) Efficiency (%) 0 5 10 15 20 25 100 Vin = 12VVout = 1V V IN = 5.0 V, 1 MHz V IN = 8.0 V, 1 MHz V IN = 12.0 V, 1 MHz V IN = 14.0 V, 1 MHz Figure 8-4. Efficiency Curves Figure 8-5. Load Regulation Input Voltage (V) Output Voltage (V) 4 6 8 10 12 14 16 18 0.98 0.983 0.986 0.989 0.992 0.995 0.998 1.001 1.004 1.007 1.01 1.013 1.016 1.019 IOUT = 0 A, 1 MHz IOUT = 12.5 A, 1 MHz IOUT = 25 A, 1 MHz Figure 8-6. Line Regulation Frequency (Hz) Gain (dB) Phase (Degrees) 1000 2000 5000 10000 100000 1000000 -40 -200 -30 -150 -20 -100 -10 -50 0 0 10 50 20 100 30 150 40 200 50 250 60 300 70 350 80 400 Vin = 12 V, Vout = 1.0 V Iout = 25 A 1000 kHz 2pF Gain Phase Figure 8-7. Bode Plot ILOAD (25A/div) VOUT (20mV/div) 1V dc o set VIN=12V IOUT = 0A to 25A 200 s/div SW (10V/div) Figure 8-8. Load Transient EN (2V/div) VOUT (500mV/div) VDRV (5V/div) VIN (10V/div) VIN=12V IOUT = 0A 400s/div Figure 8-9. EN Start-Up – Measuring BP5 TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

ILOAD (10A/div) VOUT (10mV/div) 1V dc o set VIN=12V IOUT = 0A 2 s/div SW (10V/div) Figure 8-16. Output Ripple – No Load ILOAD (10A/div) VOUT (10mV/div) 1V dc o set VIN=12V IOUT = 25A 2 s/div SW (10V/div) Figure 8-17. Output Ripple – Full Load ILOAD (20A/div) VIN (20mV/div) ac coupled VIN=12V IOUT = 0A 1 s/div SW (10V/div) Figure 8-18. Input Ripple – No Load ILOAD (20A/div) VIN (200mV/div) ac coupled VIN=12V IOUT = 25A 1 s/div SW (10V/div) Figure 8-19. Input Ripple – Full Load IL (20A/div) VOUT (1V/div) VIN=12V 200 s/div SW (10V/div) Figure 8-20. Overcurrent Protection – Overload IL (20A/div) VOUT (1V/div) VIN=12V 400 s/div SW (10V/div) Figure 8-21. Overcurrent Protection – Short TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

IL (20A/div) VOUT (1V/div) VIN=12V 4 ms/div SW (10V/div) Figure 8-22. Overcurrent Protection – Hiccup and Recover

8.3 Power Supply Recommendations

The TPS543B25T is designed to operate from an input voltage supply range between 4 V and 18 V. This supply voltage must be well regulated. Proper bypassing of the input supply is critical for proper electrical performance, as is the PCB layout and the grounding scheme. A minimum of 10- μF (after derating) ceramic capacitance, type X5R or better, must be placed near the device. TI recommends splitting the ceramic input capacitance equally between the VIN and PGND pins on each side of the device resulting in at least 5 µF of ceramic capacitance on each side of the device.

8.4 Layout

8.4.1 Layout Guidelines

Layout is a critical portion of good power supply design. See Figure 8-23 for a PCB layout example. Key guidelines to follow for the layout are:

• Make VIN, PGND, and SW traces as wide as possible to reduce trace impedance and improve heat dissipation. Use vias and traces on others layers to reduce VIN and PGND trace impedance.
• Use multiple vias near the PGND pins and use the layer directly below the device to connect them together, which helps to minimize noise and can help heat dissipation.
• Use vias near both VIN pins and provide a low impedance connection between them through an internal layer.
• Place a 1-μF/25-V/X6R or better dielectric ceramic capacitors from each VIN to PGND pins and place them as close as possible to the device on the same side of the PCB. Place the remaining ceramic input capacitance next to these high frequency bypass capacitors. The remaining input capacitance can be placed on the other side of the board but use as many vias as possible to minimize impedance between the capacitors and the pins of the IC.
• Place the inductor as close as possible to the device to minimize the length of the SW node routing.
• Place the BOOT-SW capacitor as close as possible to the BOOT and SW pins. Use a 0.1-μF/16-V/X6R or better dielectric ceramic capacitor for the BOOT capacitor.
• Place the 2.2-μF/10-V/X6R or better dielectric ceramic capacitor as close as possible to the VDRV and PGND pins.
• Connect 10-Ω resistor from VDRV to VCC and a 0.1-μF/10-V/X6R or better dielectric ceramic capacitor from VCC to AGND.
• Place the bottom resistor in the FB divider as close as possible to the FB and GOSNS pins of the IC. Also keep the upper feedback resistor and the feedforward capacitor near the IC. Connect the FB divider to the output voltage at the desired point of regulation.
• Use vias on the AGND islands on top layer to connect to AGND layer island on an internal layer. Connect the internal AGND island to PGND at one point.
• Return the FSEL and MODE resistors to a quiet AGND island. www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS543B25T

8.4.2 Layout Example

0402 PGND

Figure 8-23. Example PCB Layout TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

34 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

8.4.3 Thermal Performance

Test Conditions: fSW = 1 MHz, Vin = 12 V, Vout = 1 V, Iout = 25A, Inductor = 150nH (0.39 m Ω typ), Ambient temperature = 25°C Figure 8-24. Thermal Image at 25°C Ambient www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS543B25T

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

SWIFT™, HotRod™, and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

10.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS543B25TRASR WQFN- FCRLF www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPS543B25T

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS543B25TRASR WQFN-FCRLF RAS 17 5000 346 346 33 TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

38 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

www.ti.com PACKAGE OUTLINE 2.6 2.4 4.6 4.4 0.7 0.6 0.01 0.00 2X 2 .000 PKG0 2X 1.5 2X 1 2X 0.5 0.5 1.5 1 .000PKG00.5 0.5 2X 1 28X 0.3 0.2 0.5 0.5 117X 0.475 0.275 1.25 1.05 0.775 0.575 0.825 0.625 1.05 0.85 2X 1.2 1.0 0.2875 1.2375 (0.13) TYP (0.3) TYP (0.125) TYP (0.418) 2X (0.163) (3.504) 4229424/A 02/2023 WQFN-FCRLF - 0.7 mm max heightRAS0017A PLASTIC QUAD FLATPACK - NO LEAD 0.08C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

0.1 CAB

0.05 C PIN 1 INDEX AREA EXPOSED SILICON SEATING PLANE PIN 1 ID (45 X 0.27) 6 7 SEE ALTERNATE PIN SHAPE DETAIL ALTERNATE PIN SHAPE SCALE 4.000 AB C www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPS543B25T

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG0 .000 PKG0 (2.25) (0.725) (0.675) 2X ()0.288 2X ()1.238 (0.3) 2X (0.95)

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND ()2 2X ()1.5 2X ()1 2X ()0.5 2X ()0.5 2X ()1 2X ()1.5 2X ()2 (1.25) (0.75) 13X (0.25) 15X (0.25) 7X (0.575) 3X (0.575) 3X (0.575) ()1.163 ()1.163 ()2.163 (1.15) ( 0.2) TYP VIA 2X ()0.332X ()0.93 4X ()0.7 4X ()1.3 ()1 ()0.5 ()0.5 (0.575) 15X (0.325) ()2 (R0.05) TYP 3X (R0.12) WQFN-FCRLF - 0.7 mm max heightRAS0017A PLASTIC QUAD FLATPACK - NO LEAD 4229424/A 02/2023 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literatur e number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE SCALE: 20X SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP EXPOSED METAL METAL EDGE SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED TPS543B25T SLVSH68 – JUNE 2023 www.ti.com ADVANCE INFORMATION

40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS543B25T

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG0 .000 PKG0 ()0.288 ()1.238 ( 0.9) (0.66) (0.62) 2X (1.08) 2X ()2 2X ()1.5 2X ()1 2X ()0.5 2X ()0.5 2X ()1 2X ()1.5 2X ()2 ()2.163 ()2.163 4X (0.5) 4X (0.5) 10X (0.575) 6X (0.25) 22X (0.25) 2X (0.25) (R0.05) TYP 4X (R0.12) ()0.188()0.188 WQFN-FCRLF - 0.7 mm max heightRAS0017A PLASTIC QUAD FLATPACK - NO LEAD 4229424/A 02/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X PRINTED SOLDER COVERAGE BY AREA PADS 1, 7 & 12: 83% PAD 5 & 8: 91% PAD 6: 73% PAD 16: 85% PAD 17: 86% SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP EXPOSED METAL TYP EXPOSED METAL TYP www.ti.com TPS543B25T SLVSH68 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPS543B25T

www.ti.com 23-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PS543B25TRASR ACTIVE WQFN-FCRLF RAS 17 5000 TBD Call TI Call TI -40 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated