PROASIC3E ACTEL | Alldatasheet
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v1.4 1 I/O Structures in IGLOOe and ProASIC3E Devices Introduction Low-power flash devices feature a flexible I/O structure, supporting a range of mixed voltages (1.2 V, ProASIC3E families support Pro I/Os. Users designing I/O solutions are faced with a number of implementation decisions and configuration choices that can directly impact the efficiency and effectiveness of their final design. The flexible I/O structure, supporting a wide variety of voltages and I/O standards, enables users to meet the growing challenges of their ma ny diverse applications. The Actel Libero ® Integrated Design Environment (IDE) provides an easy way to implement I/O that will result in robust I/O design. This document first describes th e two different I/O types in terms of the standards and features they support. It then explains the individual features and how to implement them in Actel's Libero IDE. Figure 1 • I/O Block Logical Representation Input Register E = Enable PinA Y PAD 1 2 OCE ICE ICE Input Register Input Register CLR/PRE CLR/PRE CLR/PRE CLR/PRE CLR/PRE Pull-Up/-Down Resistor Control Signal Drive Strength and Slew Rate Control Output Register Output Register To FPGA Core From FPGA Core Output Enable Register OCE I/O / CLR or I/O / PRE / OCE I/O / Q0 I/O / Q1 I/O / ICLK I/O / D0 I/O / D1 / ICE I/O / OCLK I/O / OE Scan Scan Scan
I/O Structures in IGLOOe and ProASIC3E Devices 2v 1 . 4 Low-Power Flash Device I/O Support The low-power flash FPGAs listed in Table 1 support I/Os and the fu nctions described in this document. IGLOO Terminology In documentation, the terms IGLOO series and IGLO O devices refer to all of the IGLOO devices as listed in Table 1. Where the information applies to only on e product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series a nd ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between th e IGLOO and ProASIC3 devices, refer to the Industry’s Lowest Power FPGAs Portfolio. Table 1 Flash-Based FPGAs Series Family * Description IGLOO IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards ProASIC3 ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information.
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 3 Pro I/Os—IGLOOe, ProASIC3EL, and ProASIC3E Table 2 shows the voltages and compat ible I/O standards for Pro I/Os. I/Os provide programmable slew rates, drive strengths, and weak pull-up and pull-down circuits. All I/O standards, except 3.3 V "5 V Input Tolerance" section on page 20 for possible implementation s of 5 V tolerance. Single- ended input buffers support both the Schmitt trigger and programmable delay options on a per– I/O basis. All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" sect ion in the datasheet for more information. During power-up, before reaching activation levels, the I/O inpu t and output buffers are disabled while the weak pull-up is enabled. Activation levels are described in the datasheet. Table 2 Supported I/O Standards A3PE600 A3PE1500 A3PE3000/ A3PE3000L AGLE600 AGLE1500 AGLE3000 Single-Ended LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V, 3.3 V PCI/PCI-X ✓✓✓ Differential LVPECL, LVDS, B-LVDS, M-LVDS ✓✓✓ Voltage-Referenced GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II ✓✓✓
I/O Structures in IGLOOe and ProASIC3E Devices 4v 1 . 4 I/O Banks and I/O Standards Compatibility I/Os are grouped into I/O voltage banks. Each I/O voltage bank has dedicated I/O supply and ground voltages (VMV/GNDQ for input buffers and VCCI/GND for output buffers). Because of these de dicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 3 on page 5 shows the required voltage compatibility values for each of these voltages. There are eight I/O banks (two per side). Every I/O bank is divided into minibanks. Any user I/O in a V REF minibank (a minibank is the region of scope of a V REF pin) can be configured as a V REF pin (Figure 2). Only one V REF pin is needed to control the entire VREF minibank. The location and scope of the VREF minibanks can be determined by the I/O name. For details, see th e user I/O naming conventions for "IGLOOe and ProASIC3E" on page 33. Table 5 on page 5 shows the I/O standards supported by IGLOOe and ProASIC3E devices, and the corresponding voltage levels. I/O standards are compatible if they comply with the following: Their V CCI and VMV values are identical. Both of the standards need a V REF, and their VREF values are identical. All inputs and disabled outputs are voltage tolerant up to 3.3 V. For more information about I/O an d global assignments to I/O ba nks in a device, refer to the specific pin table for the device in the packag ing section of the datasheet, and see the user I/O naming conventions for "IGLOOe and ProASIC3E" on page 33. Figure 2 Typical IGLOOe and ProASIC3E I/O Bank Detail Showing VREF Minibanks Bank 3 Bank 2 Any I/O in a VREF minibank can be used to provide the reference voltage to the common V REF signal for the VREF minibank. Common VREF signal for all I/Os in VREF minibanks Up to five VREF minibanks within an I/O bankF VREF signal scope is between 8 and 18 I/Os. I/O Pad VCCI VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCC GND JTAG CCC/PLL “C” CCC/PLL “B” CCC/PLL “D”
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 5 Table 3 VCCI Voltages and Compatible IGLOOe and ProASIC3E Standards VCCI and VMV (typical) Compatible Standards LVDS, B-LVDS, and M-LVDS 1.8 V LVCMOS 1.8 1.5 V LVCMOS 1.5, HSTL (Class I and II) Table 4 VREF Voltages and Compatible IGLOOe and ProASIC3E Standards VREF (typical) Compatible Standards
1.5 V SSTL3 (Class I and II)
1.25 V SSTL2 (Class I and II)
1.0 V GTL+ 2.5, GTL+ 3.3 0.8 V GTL 2.5, GTL 3.3
0.75 V HSTL (Class I and II)
Table 5 Legal IGLOOe and ProASIC3E I/O Usage Matrix within the Same Bank I/O Bank Voltage (typical) Minibank Voltage (typical) LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V
3.3 V PCI/PCI-X
GTL+ (3.3 V) GTL+ (2.5 V) GTL (3.3 V) GTL (2.5 V) HSTL Class I and II (1.5 V) SSTL2 Class I and II (2.5 V) SSTL3 Class I and II (3.3 V) LVDS, B-LVDS, and M-LVDS, DDR (2.5 V ± 5%) LVPECL (3.3 V)
3.3 V –
0.80 V 1.00 V 1.50 V
2.5 V –
0.80 V 1.00 V 1.25 V
1.8 V –
1.5 V –
0.75 V Note: White box: Allowable I/O standard combination Gray box: Illegal I/O standard combination
I/O Structures in IGLOOe and ProASIC3E Devices 6v 1 . 4 Features Supported on Every I/O Table 6 lists all features supported by transmitter/r eceiver for single-ended and differential I/Os. Table 7 on page 7 lists the performance of each I/O technology. Table 6 IGLOOe and ProASIC3E I/O Features Feature Description All I/O High performance ( Table 7 on page 7) Electrostatic disc harge protection I/O register combining option Single-Ended and Voltage-Referenced Transmitter Features Hot-swap in every mode except PCI or 5 V–input–tolerant (these modes use clamp diodes and do not allow hot-swap) Activation of hot-insertion (disabling the clamp diode) is selectable by I/Os. Output slew rate: 2 slew rates Weak pull-up and pull-down resistors Output drive: 5 drive strengths Programmable output loading Skew between output buffer enable/disable time: 2 ns delay on rising edge and 0 ns delay on falling edge (see "Selectable Skew between Output Buffer Enable and Disable Times" section on page 24 for more information) LVTTL/LVCMOS 3.3 V outputs co mpatible with 5 V TTL inputs Single-Ended Receiver Features 5 V–input–tolerant receiver (Table 13 on page 19) Schmitt trigger option Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns with '111' setti ng, 0.85-ns intermediate delay increments (at 25°C, 1.5 V) Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. Voltage-Referenced Differential Receiver
Features
Programmable delay: 0 ns if bypa ssed, 0.46 ns with '000' setting, 4.66 ns with '111' setting, 0.6- ns intermediate delay increments (at 25°C, 1.5 V) Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. CMOS-Style LVDS, B-LVDS, M-LVDS, or LVPECL Transmitter Two I/Os and external resistors are used to provide a CMOS-style LVDS, DDR LVDS, B-LVDS, and M-LVDS/LVPECL transmitter solution. Activation of hot-insertion (disabling the clamp diode) is selectable by I/Os. High slew rate Weak pull-up and pull-down resistors Programmable output loading LVDS, DDR LVDS, B-LVDS, and M-LVDS/LVPECL Differential Receiver Programmable delay: 0 ns if bypa ssed, 0.46 ns with '000' setting, 4.66 ns with '111' setting, 0.6- ns intermediate delay increments (at 25°C, 1.5 V)
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 7 Table 7 Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength and high slew selected) Specification Maximum Performance ProASIC3E IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage IGLOOe V2, 1.2 V DC Core Supply Voltage LVTTL/LVCMOS 3.3 V 200 MHz 180 MHz TBD LVCMOS 2.5 V 250 MHz 230 MHz TBD LVCMOS 1.8 V 200 MHz 180 MHz TBD LVCMOS 1.5 V 130 MHz 120 MHz TBD PCI 200 MHz 180 MHz TBD PCI-X 200 MHz 180 MHz TBD HSTL-I 300 MHz 275 MHz TBD HSTL-II 300 MHz 275 MHz TBD SSTL2-I 300 MHz 275 MHz TBD SSTL2-II 300 MHz 275 MHz TBD SSTL3-I 300 MHz 275 MHz TBD SSTL3-II 300 MHz 275 MHz TBD GTL+ 3.3 V 300 MHz 275 MHz TBD GTL+ 2.5 V 300 MHz 275 MHz TBD GTL 3.3 V 300 MHz 275 MHz TBD GTL 2.5 V 300 MHz 275 MHz TBD LVDS 350 MHz 300 MHz TBD M-LVDS 200 MHz 180 MHz TBD B LVDS 200 MHz 180 MHz TBD LVPECL 350 MHz 300 MHz TBD
I/O Structures in IGLOOe and ProASIC3E Devices 8v 1 . 4 I/O Architecture I/O Tile The I/O tile provides a flexible, programmable s tructure for implementing a large number of I/O standards. In addition, the regi sters available in the I/O tile can be used to support high- performance register inputs and outputs, with register enab le if desired ( Figure 3). The registers can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure (see DDR for Actel’s Low-Power Flash Devices for more information). As depicted in Figure 3, all I/O registers share one CLR port. The output register and output enable register share one CLK port. Figure 3 I/O Block Logical Representation Input Register E = Enable PinA Y PAD 1 2 OCE ICE ICE Input Register Input Register CLR/PRE CLR/PRE CLR/PRE CLR/PRE CLR/PRE Pull-Up/-Down Resistor Control Signal Drive Strength and Slew Rate Control Output Register Output Register To FPGA Core From FPGA Core Output Enable Register OCE I/O / CLR or I/O / PRE / OCE I/O / Q0 I/O / Q1 I/O / ICLK I/O / D0 I/O / D1 / ICE I/O / OCLK I/O / OE
I/O Structures in IGLOOe and ProASIC3E Devices 10 v1.4 I/O Registers Each I/O module contains several input, output, and enable registers. Refer to Figure 5 for a simplified representation of the I/O block. The number of input re gisters is selected by a set of switches (not shown in Figure 3 on page 8 ) between registers to implement single-ended or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CL R/PRE signal is employed by a ll I/O registers when I/O register combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain rules. Notes: 1. All NMOS transistors connected to th e I/O pad serve as ESD protection. 2. See Table 2 on page 3 for available I/O standards. Figure 5 Simplified I/O Buffer Circuitry Programmable Input Delay Control Input Buffer Standard2 and Schmitt Trigger Control Input Signal to Core Logic Input Buffer OE (from core logic) Output Signal (from core logic) Output Buffer Logic and Enable Skew Circuit Drive Strength and Output Slew Rate Control Clamp Diode ESD Protection1 Weak Pull- Down Control (from core) Clamp Diode ESD Protection1 VCCI I/O PAD Weak Pull-Up Control (from core) Hot-Swap, 5 V Tolerance, and Clamp Diode Control Output Buffer VCCIVCCI
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 11 I/O Standards Single-Ended Standards These I/O standards use a push-pull CMOS output stage with a voltage referenced to system ground to designate logical states. The input buffer conf iguration, output drive, and I/O supply voltage (VCCI) vary among the I/O standards (Figure 6). The advantage of these standards is that a comm on ground can be used for multiple I/Os. This simplifies board layout and reduces system cost. Their low-edge-rate ( dv/dt) data transmission causes less electromagnetic interference (EMI) on th e board. However, they are not suitable for high-frequency (>200 MHz) switching due to noise impact and higher power consumption. LVTTL (Low-Voltage TTL) This is a general-purpose standard (EIA/JESD8-B) for 3.3 V applications. It uses an LVTTL input buffer and a push-pull output buffer. The LVTTL output buffer can have up to six different programmable drive strengths. The default drive strength is 12 mA. V CCI is 3.3 V. Refer to "I/O Programmable Features" on page 15 for details. LVCMOS (Low-Voltage CMOS) The low-power flash devices provide four different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 1.8 V, and LVCMOS 1.5 V. LVCMOS 3.3 V is an extension of the LVCMOS standard (JESD8-B– compliant) used for general-purpose 3.3 V applications. LVCMOS 2.5 V is an extension of the LVCMOS standard (JESD8-5–compliant) used for general-purpose 2.5 V applications. LVCMOS 2.5 V for the 30 k gate devices has a clamp diode to V CCI, but for all other devices there is no clamp diode. There is yet another standard supported by IGLOO and ProASIC3 devices (except A3P030): LVCMOS 2.5/5.0 V. This standard is simila r to LVCMOS 2.5 V, with the exception that it can support up to 3.3 V on the input side (2.5 V output drive). LVCMOS 1.8 V is an extension of the LVCMOS standard (JESD8-7–comp liant) used for general- purpose 1.8 V applications. LVCMOS 1.5 V is an extension of the LVCMOS standard (JESD8-11– compliant) used for general-purpose 1.5 V applications. use a 3.3 V–tolerant CMOS input buffer and a push-pull output buffer. Like LVTTL, the output buffer has up to seven different programmable drive strengths (2, 4, 6, 8, 12, 16, and 24 mA). Refer to "I/O Programmable Features" on page 15 for details.
3.3 V PCI (Peripheral Component Interface)
This standard specifies support for both 33 MHz and 66 MHz PC I bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an exte rnal resistor, this I/O standard can be 5 V–compliant for low-power flash devices. It does not have programmable drive strength. Figure 6 Single-Ended I/O Standard Topology OUT GND IN GND Device 1 Device 2 VCCI VCCI
I/O Structures in IGLOOe and ProASIC3E Devices 12 v1.4
3.3 V PCI-X (Peripheral Component Interface Extended)
An enhanced version of the PCI specification, 3. 3 V PCI-X can support higher average bandwidths; it increases the speed that data can move with in a computer from 66 MHz to 133 MHz. It is backward-compatible, which means devices can op erate at conventional PCI frequencies (33 MHz and 66 MHz). PCI-X is more fault-tolerant than PC I. It also does not have programmable drive strength. Voltage-Referenced Standards I/Os using these standards are referenced to an external reference voltage (VREF) and are supported on E devices only. HSTL Class I and II (High-Speed Transceiver Logic) These are general-purpose, high-s peed 1.5 V bus standards (EIA/J ESD 8-6) for signaling between integrated circuits. The signaling range is 0 V to 1.5 V, a nd signals can be either single-ended or differential. HSTL requires a differential amplif ier input buffer and a push -pull output buffer. The reference voltage (VREF) is 0.75 V. These standards are used in the memory bus interface with data switching capability of up to 400 MHz. The other advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, of which low-power flash devices support Class I and II. These classes are defined by standard EIA/JESD 8-6 from the Electronic Industries Alliance (EIA): Class I – Unterminated or symmetrically parallel-terminated Class II – Series-terminated Class III – Asymmetrically parallel-terminated Class IV – Asymmetrically double-parallel-terminated SSTL2 Class I and II (Stub Series Terminated Logic 2.5 V) These are general-purpose 2.5 V me mory bus standards (JESD 8-9) for driving transmission lines, designed specifically for driving the DDR SD RAM modules used in computer memory. SSTL2 requires a differential amplifier input buffer and a push-pull outp ut buffer. The reference voltage (VREF) is 1.25 V. SSTL3 Class I and II (Stub Series Terminated Logic 3.3 V) These are general-purpose 3.3 V me mory bus standards (JESD 8-8) for driving transmission lines. SSTL3 requires a differential am plifier input buffer and a push-p ull output buffer. The reference voltage (VREF) is 1.5 V. Figure 7 SSTL and HSTL Topology OUT GND IN GNDVREF VREF VCCI VCCI Device 1 Device 2
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 13 GTL 2.5 V (Gunning Transceiver Logic 2.5 V) This is a low-power standard (JESD 8-3) for electrical sign als used in CMOS circuits that allows for low electromagnetic interference at high transfer speeds. It has a voltage swing between 0.4 V and 1.2 V and typically operates at speeds of between 20 and 40 MHz. VCCI must be connected to 2.5 V. The reference voltage (VREF) is 0.8 V. GTL 3.3 V (Gunning Transceiver Logic 3.3 V) This is the same as GTL 2.5 V above, except VCCI must be connected to 3.3 V. GTL+ (Gunning Transceiver Logic Plus) This is an enhanced version of GTL that has defined slew rates and higher voltage levels. It requires a differential amplifier input buffer and an open -drain output buffer. Even though the output is open-drain, VCCI must be connected to either 2.5 V or 3.3 V. The reference voltage (VREF) is 1 V. Differential Standards These standards require two I/Os per signal (called a “signal pair”). Logic values are determined by the potential difference between the lines, not wi th respect to ground. Th is is why differential drivers and receivers have much better noise immunity than single-ended standards. The differential interface standards offer higher performance and lower power consumption than their single-ended counterparts. Two I/O pins are used for each data transfer channel. Both differential standards require resistor termination. LVPECL (Low-Voltage Positive Emitter Coupled Logic) LVPECL requires that one data bit be carried thro ugh two signal lines; th erefore, two pins are needed per input or output. It also requires external resisto r termination. Th e voltage swing between the two signal lines is approximately 850 mV. When the power supply is +3.3 V, it is commonly referred to as Low-Voltage PECL (LVPEC L). Refer to the device datasheet for the full implementation of the LVPECL transmitter and receiver. LVDS (Low-Voltage Differential Signal) LVDS is a moderate-speed differ ential signaling syste m, in which the transmitter generates two different voltages that are compared at the receiver. LVDS uses a differential driver connected to a terminated receiver through a constant-impedance transmission line. It requires that one data bit be carried through two sign al lines; therefore, the user will n eed two pins per input or output. It also requires external resistor termination. The vo ltage swing between the two signal lines is approximately 350 mV. VCCI is 2.5 V. Low-power flash devices contain dedicated circuitry supporting a high-speed LVDS standard that has its own user specification. Refer to the device datasheet for the full implementation of the LVDS transmitter and receiver. Figure 8 Differential Topology VCCI DEVICE 1 GND VREF OUTn OUTp INn INp VCCI DEVICE 2 GND VREF
I/O Structures in IGLOOe and ProASIC3E Devices 14 v1.4 B-LVDS/M-LVDS Bus LVDS (B-LVDS) refers to bus interface circ uits based on LVDS technology. Multipoint LVDS (M-LVDS) specifications extend the LVDS sta ndard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The driver requires series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. These configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate termi nations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 9. The input and output buffer delays are available in the LVDS sections in the datasheet. Example: For a bus consisting of 20 equi distant loads, the te rminations given in EQ 1 provide the required differential voltage, in worst case industrial operating conditions, at the farthest receiver: RS =6 0 Ω, RT = 70 Ω, given ZO = 50 Ω (2") and Zstub = 50 Ω (~1.5"). EQ 1 Figure 9 A B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDSR RS RS Receiver Zstub T RS RS Transceiver R RS RS Receiver T Transceiver D RS RS Driver EN EN EN EN EN Zstub Zstub Zstub Zstub Zstub Zstub Zstub Z0 Z0 Z0Z0 RS RS Zstub Zstub
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 15 I/O Features Low-power flash devices support multiple I/O features that make board design easier. For example, an I/O feature like Schmitt Trigger in the ProASIC3E input buffer saves the board space that would be used by an external Schmitt trigger for a sl ow or noisy input signal. These features are also programmable for each I/O, which in turn gives flexibility in interfacin g with other components. The following is a detailed description of all available features in low-power flash devices. I/O Programmable Features Low-power flash devices offer many flexible I/O features to support a wide variety of board designs. Some of the features are prog rammable, with a range for selection. Table 8 lists programmable I/O features and their ranges. Hot-Swap Support A pull-up clamp diode must not be present in the I /O circuitry if the hot-swap feature is used. The
3.3 V PCI standard requires a pull-up clamp diode on the I/O, so it cannot be selected if hot-swap
capability is required. The A3P030 device does no t support 3.3 V PCI, so it is the only device in the ProASIC3 family that supports the hot-swap feat ure. All devices in the ProASIC3E family are hot- swappable. All standards except LVCMOS 2.5/5.0 V and 3.3 V PCI/PCI-X suppor t the hot-swap feature. The hot-swap feature appears as a read-only check box in the I/ O Attribute Editor that shows whether an I/O is hot-swappable or not. Refer to Power-Up/-Down Behavior of Low-Power Flash Devices for details on hot-swapping. Hot-swapping (also called hot-plugging) is the operation of hot insertion or hot removal of a card in a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 9 on page 16 to Table 12 on page 17. The I/Os also need to be configured in hot- insertion mode if hot-plugging compliance is required. The AGL030 and A3P030 devices have an I/O structure that allows the support of Level 3 and Le vel 4 hot-swap with only two levels of staging. Table 8 Programmable I/O Features (user control via I/O Attribute Editor) Feature Description Range Slew Control Output slew rate HIGH, LOW Output Drive (mA) Output drive s trength 2, 4, 6, 8, 12, 16, 24 Skew Control Output tristate enable delay option ON, OFF Resistor Pull Resistor pull circuit Up, Down, None Input Delay Input delay OFF , 0–7 Schmitt Trigger Schmitt trigger for input only ON, OFF Note: Limitations of these features with respect to different devices are discussed in later sections.
I/O Structures in IGLOOe and ProASIC3E Devices 16 v1.4 Table 9 Hot-Swap Level 1 Description Cold-swap Power Applied to Device No Bus State – Card Ground Connection – Device Circuitry Connected to Bus Pins – Example Application System and card with Actel FPGA chip are powered down, and the card is plugged into the system. Then the power supplies are turned on for the system but not for the FPGA on the card. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices: Compliant Other IGLOO/ProASIC3 devices: Compliant if bus switch used to isolate FPGA I/Os from rest of system IGLOOe/ProASIC3E devices: Compliant I/Os can, but do not have to be set to hot-insertion mode. Table 10 Hot-Swap Level 2 Description Hot-swap while reset Power Applied to Device Yes Bus State Held in reset state Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins – Example Application In the PCI hot-plug specification, reset control circuitry isolates the ca rd busses until the card supplies are at their nominal operating levels and stable. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant I/Os can but do not have to be set to hot-insertion mode. Other IGLOO/ProASIC3 devices: Compliant
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 17 Table 11 Hot-Swap Level 3 Description Hot-swap while bus idle Power Applied to Device Yes Bus State Held idle (no ongoing I/O processes during insertion/removal) Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-fre e during power-up or power-down Example Application Board bus shared with card bus is "frozen," and there is no toggling activity on the bus. It is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A – Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B – Three levels of staging (first: GND; second: supplies; third: all other pins) Table 12 Hot-Swap Level 4 Description Hot-swap on an active bus Power Applied to Device Yes Bus State Bus may have active I/O processes ongoing, but device being inserted or removed must be idle. Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-fre e during power-up or power-down Example Application There is activity on th e system bus, and it is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A – Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B – Three levels of staging (first: GND; second: supplies; third: all other pins)
I/O Structures in IGLOOe and ProASIC3E Devices 18 v1.4 IGLOOe and ProASIC3E For devices requir ing Level 3 and/or Level 4 compliance, the board drivers connected to the I/Os must have 10 k Ω (or lower) output drive resist ance at hot insertion, and 1 k Ω (or lower) output drive resistance at hot removal. This resistance is the transmitter resistance sending a signal toward the I/O, and no additional resistance is needed on the board. If that cannot be assured, three levels of staging can be used to achi eve Level 3 and/or Level 4 compli ance. Cards with two levels of staging should have the following sequence: Grounds Powers, I/Os, and other pins Cold-Sparing Support Cold-sparing refers to the ability of a device to leav e system data undisturb ed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Cold-sparing is supported on ProASIC3E devices only when the user provides resistors from each power supply to ground. The resistor value is calculated based on the decoupling capacitance on a given power supply. The RC constant should be greater than 3 µs. To remove resistor current during operation, it is suggested that the resistor be disconnected (e.g., with an NMOS switch) from the power supply after the supply has reached its final value. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for details on cold-sparing. Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. Th is means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. The 30 k gate devices fully support cold-sparing, since the I/O clamp diode is always off (see Table 13 on page 19). If the 30 k gate device is used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. This can be done with a discharge resistor or a switched resistor. This is necessary because the 30 k gate devices do not have built-in I/O clamp diodes. For other IGLOOe and ProASIC3E devices, since th e I/O clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each I/O pin to 0 V. If th e resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitance is in parallel with th e resistor). The RC time constant should ensure full discharge of supplies before cold-sparing func tionality is required. The resistor is necessary to ensure that the power pins are discharged to ground every time there is an interruption of power to the device. IGLOOe and ProASIC3E devices support cold-sparing for all I/O configurations. Standards, such as PCI, that require I/O clamp diodes can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 V. When targeting low-power applications, I/O cold-sparing may add additional current if a pin is configured with either a pull-up or pull-down resistor and driven in the opposite direction. A small static current is induced on each I/O pin when the pin is driven to a voltage opposite to the weak pull resistor. The current is eq ual to the voltage drop across the input pin divided by the pull resistor. Refer to the "Detailed I/O DC Characterist ics" section of the appr opriate family datasheet for the specific pull resistor value for the corresponding I/O standard. For example, assuming an LVTTL 3.3 V input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven LOW. For LVTTL 3.3 V, the pull-up resistor is ~45 kΩ, and the resulting current is equal to 3.3 V / 45 kΩ = 73 µA for the I/O pin. This is true also when a weak pull-down is chosen and the input pin is driven HIGH. This current can be avoided by driving the input LOW when a weak pull-down resistor is used and driving it HIGH when a weak pull-up resistor is used.
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 19 This current draw can occur in the following cases: In Active and Static modes: – Input buffers with pull-up, driven LOW – Input buffers with pull-down, driven HIGH – Bidirectional buffers with pull-up, driven LOW – Bidirectional buffers with pull-down, driven HIGH – Output buffers with pull-up, driven LOW – Output buffers with pull-down, driven HIGH – Tristate buffers with pull-up, driven LOW – Tristate buffers with pull-down, driven HIGH In Flash*Freeze mode: – Input buffers with pull-up, driven LOW – Input buffers with pull-down, driven HIGH – Bidirectional buffers with pull-up, driven LOW – Bidirectional buffers with pull-down, driven HIGH Electrostatic Discharge Protection Low-power flash devices are tested per JEDEC Standard JESD22-A114-B. These devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. All IGLOO and ProASIC3 devices are tested to the following models: the Human Body Model (HBM) with a tolerance of 2,000 V, the Machine Model ( MM) with a tolerance of 250 V, and the Charged Device Model (CDM) with a tolerance of 200 V. Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND and its N side connected to the pad. During operation, these diod es are normally biased in the off state, except when transient voltage is significantly above VCCI or below GND levels. In 30 k gate devices, the first diode is always off. In other devices, the clamp diode is always on and cannot be switched off. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 13 for more information about the I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected. Table 13 I/O Hot-Swap and 5 V Input Tolerance Capabilities in IGLOOe and ProASIC3E Devices I/O Assignment Clamp Diode Hot Insertion
5 V Input
3.3 V LVTTL/LVCMOS No Yes Yes 1 Enabled/Disabled
3.3 V PCI, 3.3 V PCI-X Yes No Yes 1 Enabled/Disabled LVCMOS 2.5 V 2 No Yes No Enabled/Disabled LVCMOS 2.5 V / 5.0 V 2 Yes No Yes 3 Enabled/Disabled LVCMOS 1.8 V No Yes No Enabled/Disabled LVCMOS 1.5 V No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled Differential, LVDS/B-LVDS/M-LVDS/LVPECL No Yes No Enabled/Disabled Notes: 1. Can be implemented with an external IDT bus sw itch, resistor divider, or Zener with resistor. 2. In the SmartGen Core Reference Guide , select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard. 3. Can be implemented with an external resistor and an internal clamp diode.
I/O Structures in IGLOOe and ProASIC3E Devices 20 v1.4
5 V Input and Output Tolerance
IGLOO and ProASIC3 devices are both 5 V-input– and 5 V–output–tolerant if certain I/O standards are selected. Table 6 on page 6 shows the I/O standards that support 5 V input tolerance. Only 3.3 V LVTTL/LVCMOS standards support 5 V output tolerance. Refer to the appropriate family datasheet for detailed description and configuration information. This feature is not shown in the I/O Attribute Editor.
5 V Input Tolerance
I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS 2.5 V / 5.0 V configurations are used (see Table 13 on page 19 ). There are four recommended solutions for achieving 5 V receiver tolerance (see Figure 10 on page 21 to Figure 13 on page 23 for details of board and macro setups ). All the solutions meet a commo n requirement of limiting the voltage at the input to 3.6 V or less. In fact, th e I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures. Solution 1 The board-level design mu st ensure that the reflected waveform at the pad does not exceed the limits provided in the recommended operating conditions in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. This solution requires two board resistors, as demonstrated in Figure 10 on page 21. Here are some examples of possible resi stor values (based on a simplified si mulation model with no line effects and 10 Ω transmitter output resista nce, where Rtx_out_high = [V CCI –V OH]/I OH and Rtx_out_low = VOL /I OL). Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 Ω Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low-medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 Ω Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA t RISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be assured for an y combination of transmitter supply (5 V ± 0.5 V), transmitter output resistance, and board resistor tolerances. Temporary overshoots are allowe d according to the overshoot and undersh oot table in the datasheet.
I/O Structures in IGLOOe and ProASIC3E Devices 22 v1.4 Solution 3 The board-level design mu st ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the vo ltage must be limited by the bus switch, as shown in Figure 12. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Figure 12 Solution 3 Solution 3 Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os. I/O Input 3.3 V 5.5 V 5.5 V Bus Switch IDTQS32X23
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 23 Solution 4 The board-level design mu st ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. Figure 13 Solution 4 Solution 4 2.5 V5.5 V 2.5 V Requires one board resistor. Available for LVCMOS 2.5 V / 5.0 V. I/O Input Rext On-Chip Clamp Diode Table 14 Comparison Table for 5 V–Compliant Receiver Solutions Solution Board Components Speed Current Limitations
1 Two resistors Low to High 1 Limited by transmitter's drive strength
2 Resistor and Zener 3.3 V Medium Limit ed by transmitter's drive strength
3 Bus switch High N/A
4 Minimum resistor value 2,3,4,5
R = 47 Ω at TJ = 70°C R = 150 Ω at TJ = 85°C R = 420 Ω at TJ = 100°C Medium Maximum diode current at 100% du ty cycle, signal constantly at 1 52.7 mA at TJ = 70°C / 10-year lifetime 16.5 mA at TJ = 85°C / 10-year lifetime 5.9 mA at TJ = 100°C / 10-year lifetime For duty cycles other than 100%, the currents can be increased by a factor of 1 / (duty cycle). Example: 20% duty cycle at 70°C Maximum current = (1 / 0.2) × 52.7 mA = 5 × 52.7 mA = 263.5 mA Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long-term reliability. 3. At 70°C, customers could still use 420 Ω on every I/O. 4. At 85°C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150Ω ) and the current is higher. Also, the designer can still use 420 Ω and use the solution on every I/O. 5. At 100°C, the 5 V solution on every I/O is permitted, since 420 Ω are used to limit the current to 5.9 mA.
I/O Structures in IGLOOe and ProASIC3E Devices 24 v1.4
5 V Output Tolerance
IGLOO and ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO ex ternal I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O. When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTL the VIL =0 . 8V a n d VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level 1 and level 0 will be recognized correctly by 5 V TTL receivers. Schmitt Trigger A Schmitt trigger is a buffer used to convert a sl ow or noisy input signal into a clean one before passing it to the FPGA. Using Schmitt trigger buff ers guarantees a fast, noise-free input signal to the FPGA. ProASIC3E devices have Schmitt triggers built into their I/O circuitry. The Schmitt trigger is available for the LVTTL, LVCMOS, and 3.3 V PCI I/O standards. This feature can be implemented by using a Physical Design Constraints (PDC) command (Table 6 on page 6) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. Selectable Skew between Output Buffer Enable and Disable Times Low-power flash devices have a configurable skew block in the output buffer circuitry that can be enabled to delay output buffer assertion without affecting deassertion time. Since this skew block is only available for the OE signal, the feature can be used in tristate and bidirectional buffers. A typical 1.2 ns delay is added to the OE signal to prevent potential bus co ntention. Refer to the appropriate family datasheet for detailed timing diagrams and descriptions. The Skew feature is available for all I/O standards. This feature can be implemented by using a PDC command ( Table 6 on page 6 ) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. The configurable skew block is us ed to delay output buffer asse rtion (enable) without affecting deassertion (disable) time. Figure 14 Block Diagram of Output Enable Path ENABLE (OUT) Skew Circuit Output Enable (from FPGA core) I/O Output Buffers ENABLE (IN) MUX Skew Select
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 27 I/O Register Combining Every I/O has several embedded registers in the I/O tile that are close to the I/O pads. Rather than using the internal register from the core, the user has the option of using these registers for faster clock-to-out timing, and external hold and setup. When combining these registers at the I/O buffer, some architectural rules must be met. Provided th ese rules are met, the user can enable register combining globally during Compile (as shown in the "Compiling the Design" section in the I/O Software Control in Low-Power Flash Devices section of the handbook). This feature is supported by all I/O standards. Rules for Registered I/O Function: 1. The fanout between an I/O pin (D, Y, or E) and a register must be equal to one for combining to be considered on that pin. 2. All registers (Input, Ou tput, and Output Enable) connected to an I/O must share the same clear or preset function: – If one of the registers has a CLR pin, all th e other registers that are candidates for combining in the I/O must have a CLR pin. – If one of the registers has a PRE pin, all th e other registers that are candidates for combining in the I/O must have a PRE pin. – If one of the registers has neither a CLR nor a PRE pin, all the other registers that are candidates for combining must have neither a CLR nor a PRE pin. – If the clear or preset pins are present, they must have the same polarity. – If the clear or preset pins are present, th ey must be driven by the same signal (net). 3. Registers connected to an I/O on the Output and Output Enable pins must have the same clock and enable function: – Both the Output and Output En able registers must have an E pin (clock enable), or none at all. – If the E pins are present, they must have th e same polarity. The CLK pins must also have the same polarity. In some cases, the user may want registers to be combined with the input of a bibuf while maintaining the output as-is. This can be achieved by using PDC commands as follows: set_preserve <signal name> ----register will not combine Weak Pull-Up and Weak Pull-Down Resistors When the I/O is pulled up, it is connected to the V CCI of its corresponding I/O bank. When it is pulled down, it is connected to GND. Refer to the datasheet for more information. For low-power applications, configuration of the pull-up or pull-down of the I/O can be used to set the I/O to a known state while the devi ce is in Flash*Freeze mode. Refer to Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information. The Flash*Freeze (FF) pin cannot be configured with a weak pull -down or pull-up I/O attribute, as the signal needs to be driven at all times. Output Slew Rate Control The slew rate is the amount of time an input signal takes to get from logic LOW to logic HIGH or vice versa. It is commonly defined as the propagation delay between 10% and 90% of the signal's voltage swing. Slew rate control is available for the output buffers of low-power flash devices. The output buffer has a programmable slew rate for both HIGH-to-LOW and LOW-to -HIGH transitions. Slew rate control is available for LVTTL, LVCMOS, and PCI-X I/O standards. The other I/O standards have a preset slew value.
I/O Structures in IGLOOe and ProASIC3E Devices 28 v1.4 The slew rate can be implemented by using a PDC command ( Table 6 on page 6), setting it "High" or "Low" in the I/O Attribute Editor in Designer, or instantiating a special I/O macro. The default slew rate value is "High." IGLOOe and ProASIC3E devices support output slew rate control: high and low. Actel recommends the high slew rate option to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Output Drive The output buffers of IGLOOe and ProASIC3E devices can provide multiple drive strengths to meet signal integrity requirements. The LVTTL and LVCMOS (except 1.2 V LVCMOS) standards have selectable drive strengths. Other standards have a preset value. Drive strength should also be selected according to the design requirements and noise immunity of the system. The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, standards have a high output slew rate by default. For other IGLOOe and ProASIC3E devices, refer to Table 15 for more informati on about the slew rate and drive strength specification. There will be a difference in ti ming between the Standard Plus I/O banks and the Advanced I/O banks. Refer to the I/O timing tables in the datasheet for the standards supported by each device. Table 15 IGLOOe and ProASIC3E I/O Standards—Output Drive and Slew Rate I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Slew LVTTL/LVCMOS 3.3 V LVCMOS 2.5/5.0 V ✓✓ ✓ ✓✓✓✓ High Low LVCMOS 1.8 V ✓✓ ✓ ✓✓✓ –H i g h L o w
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 29 Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout Each I/O voltage bank has a separate ground and power plane for input and output circuits (VMV/GNDQ for inpu t buffers and V CCI/GND for output buff ers). This isolation is necessary to minimize simultaneous switchin g noise from the input and output (SSI and SSO). The switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. Since voltage bounce originates on the package inductance, the VMV and V CCI supplies have separate package pin assignmen ts. For the same reason, GND and GNDQ also have separate pin assignments. The VMV and VCCI pins must be shorted to each other on the board. Also, the GND and GNDQ pins must be shorted to each other on the board. Th is will prevent unwanted current draw from the power supply. SSOs can cause signal integrity problems on adjacent signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bo nd wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals adjace nt to those busses. Additionally, SSOs can produce ground bounce noise and V CCI dip noise. These two noise types are caused by rapidly changing currents through GND and VCCI package pin inductances during switching activities (EQ 2 and EQ 3). Ground bounce noise voltage = L(GND) × di/dt EQ 2 VCCI dip noise voltage = L(VCCI) × di/dt EQ 3 Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The shielding should be done both on the board and inside the package unless otherwise described. In-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to the SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to be adequately shielded from mutu al coupling and inductive noise that can be generated by the SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package. PCBs perform an important function in feeding sta ble supply voltages to the IC and, at the same time, maintaining signal integrity between devices. Key issues that need to be considered are as follows: Power and ground plane design and decoupling network design Transmission line reflections and terminations For extensive data per package on th e SSO and PCB issues, refer to the ProASIC3/E SSO and Pin Placement and Guidelines chapter of the handbook.
I/O Structures in IGLOOe and ProASIC3E Devices 30 v1.4 I/O Software Support In Actel's Libero IDE software, default settings have been defi ned for the various I/O standards supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 16 lists the valid I/O attributes that can be manipulated by the user for each I/O standard. Single-ended I/O standards in low-power flash devices support up to five different drive strengths. Table 17 on page 31 lists the default values for the above sele ctable I/O attributes as well as those that are preset for each I/O standard. Refer to Table 16 for SLEW and OUT_DRIVE settings. Table 18 on page 32 lists the voltages for the supported I/O standards. Table 16 IGLOOe and ProASIC3E I/O Attributes vs. I/O Standard Applications I/O Standard SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) HOT_SWAPPABLE SSTL2 Class I and II ✓✓ ✓ ✓ ✓✓ SSTL3 Class I and II ✓✓ ✓ ✓ ✓✓ LVDS, B-LVDS, M-LVDS ✓✓ ✓ ✓ ✓ LVPECL ✓✓✓ ✓
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 31 Table 17 IGLOOe and ProASIC3E I/O Default Attributes I/O Standard SLEW (output only) OUT_DRIVE (output only) SKEW (tribuf and bibuf only) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) LVTTL/LVCMOS 3.3 V See Table 15 on page 28 See Table 15 on page 28 Off None 35 pF – Off 0 Off LVCMOS 2.5 V Off None 35 pF – Off 0 Off LVCMOS 2.5/5.0 V Off None 35 pF – Off 0 Off LVCMOS 1.8 V Off None 35 pF – Off 0 Off LVCMOS 1.5 V Off None 35 pF – Off 0 Off PCI (3.3 V) Off None 10 pF – Off 0 Off PCI-X (3.3 V) Off None 10 pF – Off 0 Off GTL+ (3.3 V) Off None 10 pF – Off 0 Off GTL+ (2.5 V) Off None 10 pF – Off 0 Off GTL (3.3 V) Off None 10 pF – Off 0 Off GTL (2.5 V) Off None 10 pF – Off 0 Off HSTL Class I Off None 20 pF – Off 0 Off HSTL Class II Off None 20 pF – Off 0 Off SSTL2 Class I and II Off None 30 pF – Off 0 Off SSTL3 Class I and II Off None 30 pF – Off 0 Off LVDS, B-LVDS, M-LVDS Off None 0 pF – Off 0 Off LVPECL Off None 0 pF – Off 0 Off
I/O Structures in IGLOOe and ProASIC3E Devices 32 v1.4 Table 18 Supported IGLOOe, ProASIC3L, and ProASIC3E I/O Standards and Corresponding VREF and VTT Voltages I/O Standard Input/Output Supply Voltage (VMVTYP/VCCI_TYP) Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_TYP) LVTTL/ L VCMOS 3.3 V 3.30 V – – LVCMOS 2.5 V 2.50 V – – LVCMOS 2.5/5.0 V Input 2.50 V – – LVCMOS 1.8 V 1.80 V – – LVCMOS 1.5 V 1.50 V – – PCI 3.3 V 3.30 V – – PCI-X 3.3 V 3.30 V – – GTL+ 3.3 V 3.30 V 1.00 V 1.50 V GTL+ 2.5 V 2.50 V 1.00 V 1.50 V GTL 3.3 V 3.30 V 0.80 V 1.20 V GTL 2.5 V 2.50 V 0.80 V 1.20 V HSTL Class I 1.50 V 0.75 V 0.75 V HSTL Class II 1.50 V 0.75 V 0.75 V SSTL3 Class I 3.30 V 1.50 V 1.50 V SSTL3 Class II 3.30 V 1.50 V 1.50 V SSTL2 Class I 2.50 V 1.25 V 1.25 V SSTL2 Class II 2.50 V 1.25 V 1.25 V LVDS, DDR LVDS, B-LVDS, M-LVDS 2.50 V – – LVPECL 3.30 V – –
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 33 IGLOOe and ProASIC3E Due to the comprehensive and flexible nature of IGLOOe and ProASIC3E device user I/Os, a naming scheme is used to show the details of each I/O (Figure 20 on page 34). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature = FF/Gmn/IOuxwByVz Gmn is only used for I/Os that also have CCC access—i.e., global pins. FF = Indicates the I/O dedicated for the Flash*Fr eeze mode activation pin in IGLOOe only G= G l o b a l m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (south east corner), E (southwe st corner), and F (west middle) n = Global input MUX and pin number of the associat ed Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or C2. Refer to Global Resources in Acte l Low-Power Flash Devices for information about the three input pins per clock source MUX at CCC location m. u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction x = P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os that support single-ended and voltage-referenced I/O standards only w = D (Differential Pair), P (Pair), or S (Single-Ende d). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded ou t. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizo ntal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number (0–7). The bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction. V = V REF z = V REF minibank number (0–4). A given voltage-referenced signal spans 16 pins (typically) in an I/O bank. Voltage banks may have multiple VREF minibanks.
I/O Structures in IGLOOe and ProASIC3E Devices 34 v1.4 Board-Level Considerations Low-power flash devices have robust I/O featur es that can help in reducing board-level components. The devices offer si ngle-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. Although, in many cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. This section covers important board-level considerations to facilitate optimum device performance. Termination Proper termination of all signal s is essential for good signal quality. Nonterminated signals, especially clock signals, can cause malfunctioning of the device. For general termination gu idelines, refer to the Board-Level Considerations application note for Actel FPGAs. Also refer to Pin Descriptions for termination requirements for specific pins. Low-power flash I/Os are equipped with on-chip pull-up/-down resistors. The user can enable these resistors by instantiating them either in the top level of the design (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for the available I/O macros wi th pull-up/-down) or in the I/O Attribute Editor in Designer if generic input or output buffers are instantiated in the top level. Unused I/O pins are configured as inputs with pull-up resistors. As mentioned earlier, low-power flash devices ha ve multiple programmable drive strengths, and the user can eliminate unwanted overshoot and undershoot by adjusting the drive strengths. Figure 20 User I/O Naming Conventions of IGLOOe and ProASIC3E Devices – Top View GNDQ VMV7 VMV6 GNDQ VMV0 GNDQ GND GND GNDQ VMV1VMV4 TMS TDI TCK GNDQ GND GND GNDQ VMV5 VCC VCC VCOMPLF VCCPLF VCOMPLE VCCPLE VCOMPLA VCCPLA GND VCCIB7 VCCIB6 GND VCC VCC VCCIB0 VCC VCCIB1 VCC VCCIB4 VCCIB5 VCC GNDQ VMV2 GND TRST TDO VMV3 GNDQ VCOMPLB VCOMPLC VCCPLB VCCPLC VJTAG VCC VCC VCOMPLD VPUMP VCCPLD VCCIB2 GND VCC VCCIB3 CCC/PLL “D” Bank 5 Bank 4 JTAG Bank 3 Bank 2 JTAG Bank 6 Bank 7 AGLE600/A3PE600 A3PE1500 AGLE3000A3PE3000 Bank 0 Bank 1 CCC/PLL “C” CCC/PLL “B” CCC/PLL “E” CCC/PLL “F” CCC/PLL “A”
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 35 Power-Up Behavior Low-power flash devices are power-up/-down friendly; i.e., no particular sequencing is required for power-up and power-down. This eliminates extra board componen ts for power-up sequencing, such as a power-up sequencer. During power-up, all I/Os are tristated, irrespective of I/O macro type (input buffers, output buffers, I/O buffers with weak pull-ups or weak pull-downs, etc.). Once I/Os become activated, they are set to the user-selected I/O macros. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for details. Drive Strength Low-power flash devices have up to seven prog rammable output drive strengths. The user can select the drive strength of a particular output in the I/O Attribute Editor or can instantiate a specialized I/O macro, such as OUTBUF_S_12 (slew = low, out_drive = 12 mA). The maximum available drive strength is 24 mA pe r I/O. Though no I/O should be forced to source or sink more than 24 mA indefinitely, I/Os may handle a higher amount of current (refer to the device IBIS model for maximum so urce/sink current) during signal transition (AC current). Every device package has its own power dissipation lim it; hence, power calculation must be performed accurately to determine how much current can be tolerated per I/O within that limit. I/O Interfacing Low-power flash devices are 5 V–input– and 5 V–output–tolerant without adding any extra circuitry. Along with other low-voltage I/O macros, this 5 V tolera nce makes these devices suitable for many types of board component interfacing. Table 19 shows some high-level interfacing examples using low-power flash devices. Table 19 High-Level Interface Examples Interface Clock I/O Type Frequency Type Signals In Signals Out Data I/O GM Src Sync 125 MHz LVTTL 8 8 125 Mbps TBI Src Sync 125 MHz LVTTL 10 10 125 Mbps XSBI Src Sync 644 MHz LVDS 16 16 644 Mbps XGMI Src Sync DDR 156 MHz HSTL1 32 32 312 Mbps FlexBus 3 Sys Sync 104 MHz LVTTL ≤ 32 ≤ 32 ≤ 104 Pos-PHY3/SPI-3 Sys Syn c 104 LVTTL 8,16,32 8,16,32 ≤ 104 Mbps FlexBus 4/SPI-4.1 Src Sync 200 MHz HSTL1 16,64 16,64 200 Mbps Pos-PHY4/SPI-4.2 Src Sync DDR ≥ 311 MHz LVDS 16 16 ≥ 622 Mbps SFI-4.1 Src Sync 622 MHz LVDS 16 16 622 Mbps CSIX L1 Sys Sync ≤ 250 MHz HSTL1 32,64,96,128 32,64,96,128 ≤ 250 Mbps Hyper Transport Sys Sync DDR ≤ 800 MHz LVDS 2,4,8,16 2,4,8,16 ≤ 1.6 Gbps Rapid I/O Parallel Sys Sync DDR 250 MHz – 1 GHz LVDS 8,16 8,16 ≤ 2 Gbps Star Fabric CDR LVDS 4 4 622 Mbps Note: Sys Sync = System Synchronous Clocking, Src Sync = Source Synchronous Clocking, and CDR = Clock and Data Recovery.
I/O Structures in IGLOOe and ProASIC3E Devices 36 v1.4 Conclusion IGLOOe and ProASIC3E support for multiple I/O standards minimizes board-level components and makes possible a wide variety of applications. Th e Actel Designer software, integrated with Actel Libero IDE, presents a clear visual display of I/O assignments, allowing users to verify I/O and board- level design requirements before programming the device. The IGLOOe and ProASIC3E device I/O features and functionalities en sure board designers can produce low-cost and low-power FPGA applications fulfilling the complexities of contemporary design needs. Related Documents Handbook Documents Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf DDR for Actel’s Low-Power Flash Devices http://www.actel.com/documents/LPD_DDR_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Power-Up/-Down Behavior of Low-Power Flash Devices http://www.actel.com/documents/LPD_PowerUp_HBs.pdf ProASIC3/E SSO and Pin Placement and Guidelines http://www.actel.com/documents/PA3_E_SSO_HBs.pdf User’s Guides Actel Libero IDE User’s Guide http://www.actel.com/documents/libero_ug.pdf IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen Core Reference Guide http://www.actel.com/documents/genguide_ug.pdf
I/O Structures in IGLOOe and Pro ASIC3E Devices v1.4 37 Part Number and Revision Date This document contains content extracted from th e Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content we re made only to be co nsistent with existing datasheet information. Part Number 51700094-024-3 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.4) Page v1.3 (October 2008) The terminology in the "Low-Power Flash Device I/O Support" section was revised. v1.2 (June 2008) The "Low-Power Flash Device I/O Support" section was revised to include new families and make the information more concise. v1.1 (March 2008) The following changes were made to the family descriptions in T a b l e1·F l a s h - Based FPGAs: ProASIC3L was updated to include 1.5 V. The number of PLLs for ProASIC3 E was changed from five to six. v1.0 (January 2008) This document was previously part of I/O Structures in IGLOO and ProASIC3 Devices. To provide information specific to IGLOOe, ProASIC3E, and ProASIC3EL, the content was separated and made into a new document. For information on other low-power flas h family I/O structures, refer to the following documents: I/O Structures in IGLOO and ProASIC3 Devices contains information specific to IGLOO, ProASIC3, and ProASIC3L I/O features. I/O Structures in IGLOO PLUS Devices contains information specific to IGLOO PLUS I/O features. N/A