PRN299 CALMIRCO | Alldatasheet
Document overview
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Technical content
Features
Stable resistor network Reduces power dissipation on the clock lines Ideal for high-speed clock termination Reduces board space by 70% vs. 1206 discretes and component count by more than 50% PAC VGA200 is a trademark of California Micro Devices Corp. Application Note High speed microprocessors line Intels Pentium/P6, Apple PowerPC, SPARC and other CISC and RISC based systems need well-controlled and precise clock signals to maintain a synchronous systems. The fast edge rated clock signals will exhibit transmission line effects on the clock lines resulting in undershoots and overshoots. The integrated PECL termination is designed to suppress the undershoots and overshoots on the clock lines. The PECL RC terminator dissipates very low power compared to the resistor termination network. Why thin.film R networks? The PECL termination is an integrated R network fabricated on a silicon substrate using advanced thin film technology. This will have a fixed time constant and will not create additional skew on the clock lines. It has a low parasitic inductance compared to discrete and conventional thick film R terminators and provide effective termination at high frequencies.
Applications
PECL clock termination When placing an order please specify desired shipping: Tubes or Tape & Reel. TS RADNA NOITAMROFNIGNIREDROTRAPD egakcaPr ebmuNtraPgniredrO sniPe lytSg nikraMtraP 33 2-TOS9 92NRP MARGAIDCITAMEHCSSEULAVDRADNATS R 1 (ΩΩΩΩΩ)± %1 R 2 (ΩΩΩΩΩ)± %1 R 3 (ΩΩΩΩΩ)± %1 050 54 .64
'2000 California Micro Devices Corp. All rights reserved. 3/00215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com PRN299 SGNITARMUMIXAMETULOSBA retemaraPg nitaRt inU V 1CC V, 2CC V, 3CC V& 4CC egatlovylppus0 .6+,5.0-DNGV tnerrucdrawrof1DedoiD0 01A u :stupnitaegatlovCD V 3_OEDIV,2_OEDIV,1_OEDIVV ,5.0-DNG 1CC 5.0+V 3_MRET,2_MRET,1_MRET0 .6+,0.6-V 2NI_CDD,1NI_CDDV ,5.0-DNG 2CC 5.0+ 2TUO_CDD,1TUO_CDDV ,5.0-DNG 3CC 5.0+V 2NI_CNYS,1NI_CNYSV ,5.0-DNG 4CC 5.0+V :erutarepmeT egarotS0 51+ot04- oC tneibmAgnitarepO0 7+ot0 oC noitapissidrewopegakcaP0 .1W Note 1: These parameter applies only to the HSYNC and VSYNC channels. Note 2: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V CC1, VCC3 and V CC4 must be bypassed to GND via a low impedance ground plane with a 0.2uF , low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015). Note 3: This parameter is guaranteed by design and characterization. SCITSIRETCARAHCGNITAREPOLACIRTCELE )esiwrehtodeificepssselnusnoitidnocgnitareporevo( lobmySr etemaraPs noitidnoCN IMP YTX AMT INU I 1CC V 1CC tnerrucylppusV 1CC tastupniOEDIV;V5=V 1CC DNGro0 1A u I 3,2CC V 2CC V, 3CC tnerrucylppusV 2CC V= 3CC V5=0 1A u I 4CC V 4CC tnerrucylppusV 4CC VroDNGtastupniCNYS;V5= 4CC ;0 1A u VtanipPU_RWP ;4CC dedaolnustuptuoCNYS V 4CC PU_RWP;V0.3tastupniCNYS;V5=0 02A u Vtanip 4CC dedaolnustuptuoCNYS; V 4CC CNYS;DNGtatupniPU_RWP;V5=0 1A u dedaolnustuptuo V SAIB V SAIB egatlovtiucricnepoV morfnwardtnerruclanretxeoN SAIB nipV 4CC 8.0-V RT ecnatsisernoitanimretOEDIV 52.175 75 7.87 Ω RT gnihctamecnatsiser 12 % V HI egatlovtupnihgiHcigoL 1 V 4CC V0.5=0 .2V V LI egatlovtupniwoLcigoL 1 V 4CC V0.5=8 .0V V HO egatlovtuptuohgiHcigoL 1 I HO V,Am4-= 4CC V0.5=4 .4V V LO egatlovtuptuowoLcigoL 1 I LO V,Am4= 4CC V0.5=4 .0V Rb R, p eulavrotsiseRV ,PU_RWP 3CC V0.5=5 .01 2 M Ω Rc V 2CC rotsisernwod-llupV 2CC V0.3=5 .05 .13 M Ω IN tnerructupnI stupniOEDIVV 1CC V;V5= NI V= 1CC DNGro1 ± µA stupniCNYSV,CNYSHV 4CC V;V5= NI V= 4CC DNGro1 ± µA I FFO level,tnerrucegakaeletatsFFOV ( 2CC V- NI_CDD )< V;V4.0 CDD _ TUO V= 2CC 01 µA TEFNgnitfihsV ( 2CC V- TUO_CDD )< V;V4.0 CDD _ NI V= 2CC 01 µA V NO levelssorcapordegatloVV 2CC V;V5.2= S I,DNG= SD Am3=5 1.0V NOdenrutnehwTEFNgnitfihs CNI ecnaticapactupnI 3 3_OEDIV,2_OEDIV,1_OEDIVV 1CC V;V0.5= NI zHM1taderusaem;V5.2=0 .4F p V 1CC V;V5.2= NI zHM1taderusaem;V52.1=5 .4 t HLP yalednoitagaporpH-LsrevirdCNYSC L V;Fp05= CC ttupnI;V5= r tdna f < sn58 2 1s n t LHP yalednoitagaporpL-HsrevirdCNYSC L V;Fp05= CC ttupnI;V5= r tdna f < sn58 2 1s n tr t, f semitllaf&esirtuptuosrevirdCNYSC L V;Fp05= CC ttupnI;V5= r tdna f < sn57 s n V DSE egatlovdnatshtiwDSE 3,2 V 1CC V= 3CC V= 4CC V5=8 ±V k
' 2000 California Micro Devices Corp. All rights reserved. 3/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com CALIFORNIA MICRO DEVICES PRN299 Typical Connection Diagram A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is required while the PAC VGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the VCC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PAC VGA200 is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose. For the same reason, V CC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected to the ground of the video DAC IC. TS RADNA NOITAMROFNIGNIREDROTRAPD egakcaPr ebmuNtraPgniredrO sniPe lytSg nikraMtraP 42P OSQQ 002AGVCAP When placing an order please specify desired shipping: Tubes or Tape & Reel.