REF4132-Q1_V01 TI1 | Alldatasheet
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Technical content
+5 V +5 V -5 V -2.5 V +2.5 V EN VIN VREF GND N/C 10 N 10 N Load Current (mA) Dropout Voltage (V) 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 0.4 5 100 +25°C -40°C +125°C D001 Product Folder Order Now T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. REF4132-Q1 SNAS795A –FEBRUARY 2020–REVISED JULY 2020 REF4132-Q1Low-Drift,Low-Power,Small-FootprintSeriesVoltageReference
1 Features
1• Qualified for automotive applications
- AEC-Q100 qualified with the following results: – Device temperature grade 1: –40ºC to +125ºC ambient operating temperature range – Device HBM ESD classification level 2
- Voltage options: 2.5V, 3V, 3.3V, 4.096V, 5V
- Initial accuracy: ±0.05% (maximum)
- Temperature coefficient : A grade: 12 ppm/°C (maximum) B grade: 30 ppm/°C (maximum)
- Operating temperature range: −40°C to +125°C
- Output current: ±10 mA
- Low quiescent current: 100 μA (maximum)
- Output 1/f noise (0.1 Hz to 10 Hz): 15 µVPP/V
- Excellent long-term stability 30 ppm/1000 hrs
- Small footprint 5-pin SOT-23 package
2 Applications
- ADAS front camera
- ADAS surround view system ECU
- Traction inverter
- Automotive DC/DC converter
- HEV/EV On-board (OBC) & wireless charger
3 Description
The REF4132-Q1 device is a low temperature drift (12 ppm/°C), low-power, high-precision CMOS voltage reference, featuring ±0.05% initial accuracy, low operating current with power consumption less than 100μA. This device also offers very low output noise of 15 μVp-p /V, which enables its ability to maintain high signal integrity with high-resolution data converters in noise critical systems. Packaged in the same SOT-23-5 package, REF4132-Q1 offers enhanced specifications and pin-to-pin replacement for LM4128-Q1 and LM4132-Q1. Stability and system reliability are further improved by the low output-voltage hysteresis of the device and low long-term output voltage drift. Furthermore, the small size and low operating current of the devices (100 μA) can benefit portable and battery-powered applications. REF4132-Q1 is specified for the wide temperature range of −40°C to +125°C. Device Information(1) PART NAME PACKAGE BODY SIZE (NOM) REF4132-Q1 SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Dropout vs. Current Load Over Temperature
SNAS795A –FEBRUARY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: REF4132-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table of Contents
10.2 Typical Application: Basic Voltage Reference
13.2 Receiving Notification of Documentation Updates 18
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February 2020) to Revision A Page
www.ti.com SNAS795A –FEBRUARY 2020–REVISED JULY 2020 Product Folder Links: REF4132-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
5 Device Comparison Table
REF4132 - 2.5 2.5 V REF4132 - 3.0 3 V REF4132 - 3.3 3.3 V REF4132 - 4.0 4.096 V REF4132 - 5.0 5 V
6 Pin Configuration and Functions
NO. NAME
1 N/C – No connect pin, leave floating
2 GND Ground Ground
3 EN I/O Enable pin. Enables or disables the device.
4 VIN Power Input supply
5 VREF Output Reference output
SNAS795A –FEBRUARY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: REF4132-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified in the Electrical Characteristics Table is not implied.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN –0.3 6 V Enable voltage VEN –0.3 VIN + 0.3 V Output voltage VREF –0.3 5.5 V Output short circuit current ISC 20 mA Operating temperature range TA –55 150 °C Storage temperature range Tstg –65 170 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100- 002(1) ±2500 V Charged-device model (CDM), per AEC Q100- 011 ±1500 (1) Dropout voltage
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input Voltage VREF + VDO (1) 5.5 V VEN Enable Voltage 0 VIN V IL Output Current –10 10 mA TA Operating Temperature –40 25 125 ℃ (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) DEVICE UNITDBV
5 PINS
RθJA Junction-to-ambient thermal resistance 185 °C/W RθJC(top) Junction-to-case (top) thermal resistance 156 °C/W RθJB Junction-to-board thermal resistance 29.6 °C/W ΨJT Junction-to-top characterization parameter 33.8 °C/W ΨJB Junction-to-board characterization parameter 29.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
www.ti.com SNAS795A –FEBRUARY 2020–REVISED JULY 2020 Product Folder Links: REF4132-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) At higher ambient temperature the short circuit current capacity is limited due to junction temeprature max limit
7.5 Electrical Characteristics
At VIN = 5.5 V, VEN = VIN, CREF = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃ to 125℃; typical specifications at TA = 25℃ unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.05 0.05 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C REF4132 A grade 12 ppm/℃ –40°C ≤ TA ≤ 125°C REF4132 B grade 30 ppm/℃ LINE & LOAD REGULATION ΔVREF/ΔVIN Line Regulation VREF + VDO ≤ VIN ≤ 5.5 V 2 ppm/V VREF + VDO ≤ VIN ≤ 5.5 V 15 ppm/V VREF = 5 V, VREF + VDO ≤ VIN ≤ 5.5 V 55 ppm/V ΔVREF/ΔIL Load Regulation IL = 0 mA to 10mA, VIN = VREF + VDO 20 ppm/mA IL = 0 mA to 10mA, VIN = VREF + VDO 120 ppm/mA POWER SUPPLY VIN Input voltage VREF + VDO 5.5 V IQ Quiescent current Active mode 80 100 µA Shutdown mode, VEN = 0 V 2.5 5 µA VEN Enable pin Voltage Voltage reference in active mode (EN=1) 1.6 V Voltage reference in shutdown mode (EN=0) 0.5 V IEN Enable pin current VEN = 5.5 V 1 2 µA VDO Dropout voltage IL = 0 mA 50 mV IL = 0 mA 100 mV IL = 10 mA 500 mV ISC Short circuit current (1) VREF = 0 V 18 11.5 mA TURNON tON Turn-on time 0.1% settling, CL = 1 µF, 10% to 90% 2.5 ms NOISE en(p-p) Low frequency noise ƒ = 0.1 Hz to 10 Hz 15 ppmp-p en Wide band noise ƒ = 10 Hz to 10 kHz 24 µVrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 1000h at 35℃ 30 ppm VHYST Output voltage hysteresis TA= 25℃ to −40℃ to 125℃ to 25℃ 35 ppm CAPACITIVE LOAD CL Stable output capacitor range 0.1 10 µF
7.6 Typical Characteristics
Figure 1. Temperature Drift Figure 2. VIN vs IQ over Temperature Figure 3. Output Voltage Accuracy vs Temperature Figure 4. Quiescent Current vs Temperature Figure 5. Short Circuit Current Figure 6. Power-Supply Rejection Ratio vs Frequency
8 Parameter Measurement Information
8.1 Solder Heat Shift
soldering is a common cause of this error. board thickness is 1.65 mm and the area is 114 mm × 152 mm. Figure 21. Reflow Profile Figure 22. Solder Heat Shift Distribution, VREF (%)
8.2 Long-Term Stability
exhibited by the reference over time. Figure 23. Long Term Stability - 1000 hours (VREF)
8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF4132-Q1 soldered to a PCB, similar to a real-world application.
- VHYST = thermal hysteresis (in units of ppm)
- VNOM = the specified output voltage
- VPRE = output voltage measured at 25°C pre-temperature cycling
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to +125°C and returns to 25°C. (1)
Figure 24. Thermal Hysteresis Distribution (VREF)
8.4 Power Dissipation
- PD is the device power dissipation
- TJ is the device junction temperature
- TA is the ambient temperature
- RθJA is the package (junction-to-air) thermal resistance (2) Because of this relationship, acceptable load current in high temperature conditions may be less than the maximum current-sourcing capability of the device. In no case should the device be operated outside of its maximum power rating because doing so can result in premature failure or permanent damage to the device.
8.5 Noise Performance
setup is shown in Figure 25. Figure 25. 0.1-Hz to 10-Hz Noise (VREF)
9 Detailed Description
9.1 Overview
REF4132-Q1 showing basic band-gap topology.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Supply Voltage
current. Use a power supply with a fast rising edge and low output impedance to easily prevent this issue. The supply current vs supply voltage figure is shown in Figure 26. Figure 26. Supply Current vs Supply Voltage
9.3.2 Low Temperature Drift
9.3.3 Load Current
- TJ = junction temperature (°C),
- TA = ambient temperature (°C),
- PD = power dissipated (W), and
- RθJA = junction-to-ambient thermal resistance (°C/W) (4) The REF4132-Q1 maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
9.4.1 EN Pin
voltage. See the Thermal Information for logic high and logic low voltage levels.
9.4.2 Negative Reference Voltage
temperature coefficients of R1 and R2. Figure 27. REF4132-Q1 and OPA735 Create Positive and Negative Reference Voltages
validate and test their design implementation to confirm system functionality.
10.1 Application Information
systems. The table below shows the typical application of REF4132-Q1 and its companion ADC. Table 1. Typical Applications and Companion ADC
10.2 Typical Application: Basic Voltage Reference Connection
capacitors according to the guidelines in Layout Guidelines. Figure 28. Basic Reference Connection
10.2.1 Design Requirements
parameters listed in Table 2 as the input parameters. Table 2. Design Example Parameters
10.2.2 Detailed Design Procedure
10.2.2.1 Input and Output Capacitors
reduce high frequency supply noise. so increases the turnon time of the device. to reduce overall ESR on the output.
10.2.2.2 VIN Slew Rate Considerations
10.2.2.3 Shutdown/Enable Feature
pin, and the reference remains operational continuously.
10.2.3 Application Curves
Figure 29. Quiescent Current vs Temperature Figure 30. Quiescent Current Shutdown Mode
11 Power Supply Recommendations
ranging between 0.1 µF to 10 µF.
12 Layout
12.1 Layout Guidelines
- Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF of the REF4132-Q1.
- Decouple other active devices in the system per the device specifications.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Figure 31. Layout Example
SNAS795A –FEBRUARY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: REF4132-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
- INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt Monitors
- Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 30-Jun-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PREF4132A25DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132A30DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132A33DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132A40DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132B25DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132B30DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132B33DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PREF4132B40DBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 REF4132A25DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25MC REF4132A30DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25NC REF4132A33DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25OC REF4132A40DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25PC REF4132A50DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25QC REF4132B25DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25XC REF4132B30DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25RC REF4132B33DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25SC REF4132B40DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25TC REF4132B50DBVRQ1 PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 25VC
www.ti.com 30-Jun-2020 Addendum-Page 2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF REF4132-Q1 :
- Catalog: REF4132 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
0 TYP
1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/E 09/2019 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
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