REF35_V02 TI | Alldatasheet
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Technical content
REF35 Ultra Low-Power, High-Precision Voltage Reference
1 Features
- Ultra-low quiescent current: – 650 nA (typical)
- Initial accuracy: ±0.05% (maximum)
- Temperature coefficient: – 12 ppm/°C (maximum for −40°C to 105°C)
- Output 1/f noise (0.1 Hz to 10 Hz): 3.3 ppmP-P
- NR pin to reduce noise
- EN pin to reduce shutdown current consumption
- Long-term stability: 40 ppm at 1k hour
- Thermal hysteresis: 70 ppm
- Specified temperature range: −40°C to +105°C
- Operating temperature range: −55°C to +125°C
- Output current: +10 mA, −5 mA
- Input voltage: VREF + VDO to 6 V
- Output voltage options:
- Small footprint 6-pin SOT−23 package
- Smallest footprint 4-pin WCSP package
2 Applications
- Flow transmitter
- Blood glucose monitor
- Servo drive control module
- Power quality analyzer
- Fault indicator
- Oscilloscope
- Process analytics
- Optical Module
3 Description
The REF35 is a family of nanopower, low-drift, high- precision series reference devices. The REF35 family features ±0.05% initial accuracy with 650 nA typical power consumption. The temperature coefficient (12 ppm/°C) and long-term stability (40 ppm at 1000 hours) of the device can help improve system stability and reliability. The low power consumption combined with high precision specifications are suitable for wide variety of portable and low current applications. The REF35 supplies up to 10 mA current with 3.3 ppmp-p noise and 20 ppm/mA load regulation. With this feature set, REF35 creates a strong low-noise, high accuracy power supply for precision sensors and 12–16b data converters. The family is specified for operation from –40°C to 105°C and is functional over –55°C to 125°C. The wide temperature is suited for industrial applications. REF35 is available in wide output voltage variants starting from 1.024 V to 5.0 V. The device is offered in a space-saving, 6-pin SOT-23 and 4-pin WCSP package options. Contact your local TI sales representative for available voltage and package options.
Package Information
PART NUMBER PACKAGE (1) BODY SIZE (NOM) REF35xxx SOT-23 (6) 2.90 mm × 1.60 mm WCSP (4) (2) 1.05 mm × 0.84 mm (1) For all available voltage variants and packages, see the orderable addendum at the end of the data sheet. (2) Product preview. VIN EN 0.1 μF 1 μF GND GNDGND GND GND NR VREF Optional Input Output REF35 Connection Diagram Typical Application Use Cases R REF35 Current SENSE Amplifier Biasing CSA, INA, DFA etc REF35 R R R R V GND Sensor power supply Bridge, Thermocouple etc ADC / DAC REF35 REF VDD GND Data Converter power supply REF35 Use Case REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
11.2 Receiving Notification of Documentation Updates.. 27
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (December 2021) to Revision A (August 2022) Page REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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5 Device Comparison
SOT-23 (6) WCSP (4) (1) REF35102QDBVR REF35102YBHR 1.024 V REF35120QDBVR REF35120YBHR 1.2 V REF35125QDBVR REF35125YBHR 1.25 V REF35160QDBVR REF35160YBHR 1.6 V REF35180QDBVR REF35180YBHR 1.8 V REF35205QDBVR REF35205YBHR 2.048 V REF35250QDBVR REF35250YBHR 2.5 V REF35300QDBVR REF35300YBHR 3.0 V REF35330QDBVR REF35330YBHR 3.3 V REF35409QDBVR REF35409YBHR 4.096 V REF35500QDBVR REF35500YBHR 5.0 V (1) Product preview. Contact local TI support for samples.
6 Pin Configuration and Functions
Figure 6-1. DBV Package 6-Pin SOT-23 Top View Not to scale VREF VIN GND EN A1 A2 B1 B2 Preview only Figure 6-2. YBH Package 4-Pin WCSP Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NAME SOT-23 WCSP GND 1 B1 Ground Device ground connection GND 2 - Ground Device ground connection EN 3 B2 Input Enable connection. Enables or disables the device. VIN 4 A2 Power Input supply voltage connection NR 5 - Output Noise reduction pin. Connect a capacitor to reduce noise. VREF 6 A1 Output Reference voltage output www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: REF35
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage IN –0.3 6.5 V Enable voltage EN –0.3 IN + 0.3 (2) V Output voltage VREF –0.3 IN + 0.3 (2) V Output short circuit current ISC 20 mA Operating temperature range TA –55 125 °C Storage temperature range Tstg –65 170 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) IN + 0.3 V or 6.5 V, whichever is lower
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins (2) ±750 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT IN Input voltage (1) VOUT + VDO (2) 6 V EN Enable voltage 0 IN V IL Output current –5 10 mA TA Operating temperature –40 25 125 °C (1) For VREF = 1.024 V to 1.5 V, minimum VIN = 1.7 V (2) VDO = Dropout voltage
7.4 Thermal Information
THERMAL METRIC(1) REF35 UNITDBV (SOT-23)
6 PINS
RθJA Junction-to-ambient thermal resistance 164.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 102.5 °C/W RθJB Junction-to-board thermal resistance 59.6 °C/W ΨJT Junction-to-top characterization parameter 44.0 °C/W ΨJB Junction-to-board characterization parameter 59.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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7.5 Electrical Characteristics
At VIN = VREF + 0.5 V, VEN = VIN, CL = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃ to 125℃, typical specifications TA = 25℃; unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25℃ –0.05 0.05 % Output voltage temperature coefficient –40℃ ≤ TA ≤ 105℃ 12 ppm/℃ LINE AND LOAD REGULATION ΔVREF/ ΔVIN Line regulation VREF < 2.5 V; VIN = VREF + VDO to VINMAX;–40℃ ≤ TA ≤ 105℃ 40 160 ppm/V VREF ≥ 2.5 V; VIN = VREF + VDO to VINMAX;–40℃ ≤ TA ≤ 105℃ 40 120 ppm/V ΔVREF/ΔIL Load regulation IL = 0 mA to 10 mA, VIN = VREF + VDO Source 20 60 ppm/mA IL = 0 mA to 5 mA, VIN = VREF + VDO Sink 40 350 ppm/mA POWER SUPPLY VIN Input voltage (1) VREF + VDO 6 V IQ Quiescent current Active mode TA = 25℃ 0.65 0.9 µA Shutdown mode TA = 25℃ 0.1 VEN Enable pin voltage Active mode (EN = 1 or Float) 0.7 x VIN V Shutdown mode (EN = 0) 0.3 x VIN IEN Enable pin current VEN = VIN 0.05 0.1 uA VDO Dropout voltage IL = 5 mA 120 mV IL = 10 mA 250 ISC Short circuit current, Sourcing VREF = 0 V, TA = 25℃ 33 mA ISC Short circuit current, Sinking VREF = VIN V, TA = 25℃ 21 mA TURN-ON TIME tON Turn-on time (2) 0.1% settling, CL = 1 µF, VREF = 2.5 V 2 ms NOISE en Output voltage noise ƒ = 10 Hz to 1 kHz, CL = 1 µF 0.7 ppmrms enp-p Low-frequency noise ƒ = 0.1 Hz to 10 Hz, VREF ≥ 2.5 V 3.8 ppmp-p ƒ = 0.1 Hz to 10 Hz, VREF < 2.5 V 3.3 ppmp-p HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 1000h at 35°C 40 ppm Output voltage hysteresis 25°C, –40°C, 105°C, 25°C (cycle 1) 70 ppm Output voltage hysteresis 25°C, –40°C, 105°C, 25°C (cycle 2) 20 ppm Output voltage hysteresis 25°C, –40°C, 85°C, 25°C (cycle 1) 50 ppm Output voltage hysteresis 25°C, –40°C, 85°C, 25°C (cycle 2) 13 ppm STABLE CAPACITANCE RANGE Input capacitor range 0.1 µF www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: REF35
At VIN = VREF + 0.5 V, VEN = VIN, CL = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃ to 125℃, typical specifications TA = 25℃; unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT Output capacitor range (3) 0.1 10 µF (1) For VREF = 1.024 V to 1.5 V, minimum VIN = 1.7 V (2) Scales linearly with VREF. (3) ESR for the capacitor <= 400 mΩ REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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7.6 Typical Characteristics
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted) Temperature ( C) Drift (ppm) -40 0 40 80 120 -250 250 500 750 1000 VREF = 5V VREF = 2.5V VREF = 1.25V Figure 7-1. Output Voltage Drift vs Free-Air Temperature Temperature Coefficient (ppm/ C) Population (%) 0 1 2 3 4 5 6 7 8 9 10 11 − 40 C to 85 C − 40 C to 105 C Figure 7-2. Temperature Coefficient Distribution (VREF = 1.25 V) Temperature Coefficient (ppm/ C) Population (%) 0 1 2 3 4 5 6 7 8 9 10 11 − 40 C to 85 C − 40 C to 105 C Figure 7-3. Temperature Coefficient Distribution (VREF = 2.5 V) Temperature Coefficient (ppm/ C) Population (%) 0 1 2 3 4 5 6 7 8 9 10 11 − 40 C to 85 C − 40 C to 105 C Figure 7-4. Temperature Coefficient Distribution (VREF = 5.0 V) Initial Accuracy (%) Population (%) Figure 7-5. Initial Accuracy Distribution Noise Bin (ppmp-p) Population (%) CL = 10uF CL = 1uF Figure 7-6. 0.1 Hz to 10 Hz Noise Distribution (VREF = 1.25 V, CNR = Open, IL = 0 mA) www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: REF35
7.6 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted) Noise Bin (ppmp-p) Population (%) CL= 10uF CL = 1uF Figure 7-7. 0.1 Hz to 10 Hz Noise Distribution (VREF = 2.5 V, CNR = Open, IL = 0 mA) Noise Bin (ppmp-p) Population (%) CL = 10uF CL = 1uF Figure 7-8. 0.1 Hz to 10 Hz Noise Distribution (VREF = 5 V, CNR = Open, IL = 0 mA) Noise Bin (ppmp-p) Population (%) CNR = Open CNR = 1uF CNR = 10uF Figure 7-9. 0.1 Hz to 10 Hz Noise Distribution (VREF = 2.5 V, CL = 1 μF, IL = 0 mA) Noise Bin (ppmp-p) Population (%) IL = 0mA IL = 1mA IL = 10mA Figure 7-10. 0.1 Hz to 10 Hz Noise Distribution (VREF = 2.5 V, CL = 1 μF, CNR = Open) Frequency (Hz) Noise Density (nV/ Hz) 10 100 1000 10000 100000 150 300 450 600 750 C L = 0.1 F C L = 1 F C L = 10 F Figure 7-11. Noise Density vs Frequency (VREF = 1.25 V, IL = 0 mA) Frequency (Hz) Noise Density (nV/ Hz) 10 100 1000 10000 100000 200 400 600 800 1000 C L = 0.1 F C L = 1 F C L = 10 F Figure 7-12. Noise Density vs Frequency (VREF = 2.5 V, IL = 0 mA) REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted) Figure 7-13. Noise Density vs Frequency (VREF = 5 V, IL = 0 mA) Temperature ( C) Load Regulation Sourcing (ppm/mA) -40 0 40 80 120 -10 Figure 7-14. Load Regulation (Sourcing 10 mA) vs Free-Air Temperature Temperature ( C) Load Regulation Sinking (ppm/mA) -40 0 40 80 120 Figure 7-15. Load Regulation (Sinking 5 mA) vs Free-Air Temperature Time (1 ms/div) VREF (50 mV/div) IL = 1 mA IL = -1 mA Figure 7-16. Load Transient Response (VREF = 2.5 V, CL = 10 μF) Time (1 ms/div) VREF (400 mV/div) IL = 10 mA IL = -5 mA Figure 7-17. Load Transient Response (VREF = 2.5 V, CL = 10 μF) Time (1 ms/div) VREF (100 mV/div) IL = 1 mA IL = -1 mA Figure 7-18. Load Transient Response (VREF = 2.5 V, CL = 1 μF) www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: REF35
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted) Time (1ms/div) VREF (600 mV/div) IL = 10 mA IL = -5 mA Figure 7-19. Load Transient Response (VREF = 2.5 V, CL = 1 μF) Time (1ms/div) IL = 1mA IL = -1mA VREF (90mV/div) Figure 7-20. Load Transient Response (VREF = 1.25 V, CL = 1 μF) Time (1ms/div) VREF (650 mV/div) IL = 10 mA IL = -5 mA Figure 7-21. Load Transient Response (VREF = 1.25 V, CL = 1 μF) Temperature ( C) Line Regulation (ppm/V) -40 0 40 80 120 Figure 7-22. Line Regulation vs Free-Air Temperature Time (1ms/div) VIN (4.3V/div) IL = 0mA (160mV/div) IL = 1mA (160mV/div) Figure 7-23. Line Transient Response (VREF = 1.25 V, CL = 1 μF) Time (1ms/div) VIN (3V/div) IL = 0mA (100mV/div) IL = 1mA (100mV/div) Figure 7-24. Line Transient Response (VREF = 2.5 V, CL = 1 μF) REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted) Frequency (Hz) PSRR (dB) 10 100 1000 10000 100000 1000000 1E+7 120 C IN =0.1 F, C L =1 F Figure 7-25. Power Supply Rejection Ratio (VREF = 2.5 V, IL = 0 mA) Frequency (Hz) Output Impedance ( ) 10 100 1000 10000 100000 1000000 1E+7 0.05 100 1000 10000 C L = 0.1 F C L = 1 F C L = 10 F Figure 7-26. Output Impedance Temperature ( C) Quiescent current ( A) -40 0 40 80 120 0.5 1.5 2.5 Figure 7-27. Quiescent Current vs Free-Air Temperature Figure 7-28. Dropout Voltage vs Free-Air Temperature Solder Heat Shift % Population (%) Figure 7-29. Solder Heat Shift Distribution Time (hr) VREF Stability (ppm) 0 400 800 1200 1600 2000 -200 -160 -120 -80 -40 120 160 200 Figure 7-30. Long Term Stability - 2000 hours (VREF) www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: REF35
8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF35 have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a common cause of this error. To illustrate this effect, a total of 32 devices were soldered on one printed circuit board using lead-free solder paste and the paste manufacturer suggested reflow profile. Figure 8-1 shows the reflow profile. The printed circuit board is comprised of FR4 material. The board thickness is 1.66 mm and the area is 174 mm × 135 mm. 100 150 200 250 300 0 50 100 150 200 250 300 350 400 Temperature (C) Time (seconds) C01 Figure 8-1. Reflow Profile The reference output voltage is measured before and after the reflow process; Figure 8-2 shows the typical shift. Although all tested units exhibit very low shifts (< 0.03%), higher shifts are also possible depending on the size, thickness, and material of the printed circuit board (PCB). An important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device must be soldered in the last pass to minimize its exposure to thermal stress. Solder Heat Shift % Population (%) Figure 8-2. Solder Heat Shift Distribution, VREF (%) REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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8.2 Temperature Coefficient
The REF35 is designed and tested for a low output voltage temperature coefficient. The temperature coefficient is defined as the change in output voltage over temperature. The temperature coefficient is calculated using the box method in which a box is formed by the minimum/maximum values for the nominal output voltage over the operating temperature range. REF35 has a low maximum temperature coefficient of 12 ppm/°C from –40°C to +105°C. The box method specifies limits for the temperature error but does not specify the exact shape and slope of the device under test. Due to temperature curvature correction to achieve low-temperature drift, the temperature drift is expected to be non-linear. See TI's Analog Design Journal, Precision voltage references, for more information on the box method. Use Equation 1 for the box method. REF(MAX) REF(MIN) 6 REF(25 C) V V Drift 10V Temperature Rangeq § · u ¨ ¸ ¨ ¸ u© ¹ (1) Figure 8-3 shows a typical voltage versus temperature curves for various reference voltages. Figure 8-4 shows the distribution of temperature coefficients for REF35250 devices. Temperature ( C) Drift (ppm) -40 0 40 80 120 -250 250 500 750 1000 VREF = 5V VREF = 2.5V VREF = 1.25V Figure 8-3. Output Voltage Drift Vs Free-Air Temperature Temperature Coefficient (ppm/ C) Population (%) 0 1 2 3 4 5 6 7 8 9 10 11 − 40 C to 85 C − 40 C to 105 C Figure 8-4. Temperature Coefficient Distribution
8.3 Long-Term Stability
One of the key performance parameters of the REF35 references is long-term stability also known as long-term drift. The long-term stability value is tested in a setup that reflects standard PCB board manufacturing practices. The boards are made of standard FR4 material and the board does not have special cuts or grooves around the devices to relieve the mechanical stress of the PCB. The devices and boards in this test do not undergo high temperature burn in post-soldering prior to testing. These conditions reflect a real world use case scenario and common manufacturing techniques. During the long-term stability testing, precautions are taken to ensure that only the long-term stability drift is measured. The boards are maintained at 35°C in an oil bath. The oil bath ensures that the temperature is constant across the device over time compared to an air oven. The measurements are captured every 30 minutes with a calibrated 8.5 digit multimeter. The typical long-term stability characteristic is expressed as a deviation of the reference voltage output over time. Figure 8-5 shows that the typical drift value for the REF35 6-pin SOT-23 package is 40 ppm from 0 to 1000 hours and 55 ppm from 0 to 2000 hours. It is important to understand that long-term stability is not ensured by design and that the value is typical. The REF35 will experience the highest drift in the initial 1000 hr. Subsequent deviation is typically lower than first 1000 hr. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: REF35
Time (hr) VREF Stability (ppm) 0 400 800 1200 1600 2000 -200 -160 -120 -80 -40 120 160 200 Figure 8-5. Long Term Stability - 2000 hours (VREF)
8.4 Thermal Hysteresis
Thermal hysteresis is measured with the REF35 soldered to a PCB, similar to a real-world application. Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling the device through the specified temperature range, and returning to 25°C. The PCB was baked at 150°C for 30 minutes before thermal hysteresis was measured. Use Equation 2 to calculate the thermal hysteresis: 6PRE POST HYST NOM | V V |V 10 ppm V § · u ¨ ¸ © ¹ (2) where
- VHYST = thermal hysteresis (in units of ppm)
- VNOM = the specified output voltage
- VPRE = output voltage measured at 25°C pre-temperature cycling
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to +85°C or –40°C to +105°C and returns to 25°C. The graphs below show the typical thermal hysteresis distribution across various temperature ranges in two cycles. REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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Thermal Hysteresis - Cycle 1 (ppm) Population (%) 0 10 20 30 40 50 60 70 80 90 Figure 8-6. Thermal Hysteresis Distribution –40ºC to 85ºC, Cycle 1 Thermal Hysteresis - Cycle 2 (ppm) Population (%) 0 10 20 30 40 50 60 70 Figure 8-7. Thermal Hysteresis Distribution –40ºC to 85ºC, Cycle 2 Thermal Hysteresis - Cycle 1 (ppm) Population (%) 20 30 40 50 60 70 80 90 100 110 120 130 Figure 8-8. Thermal Hysteresis Distribution –40ºC to 105ºC, Cycle 1 Thermal Hysteresis - Cycle 2 (ppm) Population (%) 0 10 20 30 40 50 60 70 80 Figure 8-9. Thermal Hysteresis Distribution –40ºC to 105ºC, Cycle 2
8.5 Noise Performance
The reference pin output noise is categorized as low frequency and broadband noise. The following sections describe these categories in detail.
8.5.1 Low-Frequency (1/f) Noise
Flicker noise, also known as 1/f noise, is a low-frequency noise that affects the device output voltage which can affect precision measurements in ADCs. This noise increases proportionally with output voltage and operating temperature. Noise is measured by filtering the output from 0.1 Hz to 10 Hz. The 1/f noise is an extremely low value, therefore the frequency of interest must be amplified and band-pass filtered. This is done by using a high-pass filter to block the DC voltage. The resulting noise is then amplified by a gain of 1000. The bandpass filter is created by a series of high-pass and low-pass filter that adds additional gain to make it more visible on a oscilloscope as shown in Figure 8-10 . Figure 8-11 shows the effect of flicker noise over 10 second for REF35250. Flicker noise must be tested in a Faraday cage enclosure to block environmental noise. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: REF35
Fc = 0.07Hz Low Noise Preamplifier G = 1000 2nd Order High-pass Filter Fc = 0.1Hz G = 10 2nd Order Low-pass Filter Fc = 10Hz G = 10 2nd Order Low-pass Filter Fc = 10Hz G = 1 Oscilloscope Supply Buffer Figure 8-10. Low-Frequency (1/f) Noise Test Setup Time (1sec/div) 1 V/div GND Figure 8-11. 0.1 Hz to 10 Hz Voltage Noise Figure 8-12 shows the typical 1/f noise (0.1 Hz to 10 Hz) distribution across various load conditions. REF35 device also offers noise reduction functionality by adding an optional capacitor between NR (pin 5) and ground pins. Figure 8-13 shows the typical 1/f noise (0.1 Hz to 10 Hz) distribution across REF35 devices with various capacitance between NR pin and GND. REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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Noise Bin (ppmp-p) Population (%) IL = 0mA IL = 1mA IL = 10mA Figure 8-12. 0.1 Hz to 10 Hz Noise Distribution vs Load Conditions Noise Bin (ppmp-p) Population (%) CNR = Open CNR = 1uF CNR = 10uF Figure 8-13. 0.1 Hz to 10 Hz Noise Distribution vs NR Capacitance
8.5.2 Broadband Noise
Broadband noise is a noise that appears at higher frequency compared to 1/f noise. The broadband noise is measured by high-pass filtering the output of the reference device, followed by a gain stage and measuring the result on a spectrum analyzer as shown in Figure 8-14. REF35xxxCIN GND VIN EN NR VREF GND Optional CL High-pass Filter Fc = 10Hz G = 11 Amplifier G = 11 Supply Spectrum Analyzer Figure 8-14. Broadband Noise Test Setup For noise sensitive designs, a low-pass filter can be used to reduce broadband output noise. When designing a low-pass filter, take special care to ensure the output impedance of the filter does not degrade AC performance. This can occur in RC low-pass filters where a large series resistance can impact the load transients due to output current fluctuations. The REF35 device also offers noise reduction functionality by adding an optional capacitor between NR (pin 5) and ground pins. Figure 8-15 and Figure 8-16 show the noise spectrum for REF35250 and REF35500 devices respectively across various load capacitance. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: REF35
Frequency (Hz) Noise Density (nV/ Hz) 10 100 1000 10000 100000 200 400 600 800 1000 CL = 0.1 F CL = 1 F CL = 10 F Figure 8-15. Noise Spectrum 10 Hz to 100 kHz (VREF = 2.5 V) Figure 8-16. Noise Spectrum 10 Hz to 100 kHz (VREF = 5 V)
8.6 Power Dissipation
The REF35 voltage references are capable of source up to 10 mA and sink up to 5 mA of load current across the rated input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage and load current must be carefully monitored to ensure that the device does not exceeded its maximum power dissipation rating. The maximum power dissipation of the device can be calculated with Equation 3: J A D JAT T P R T u (3) where
- PD is the device power dissipation
- TJ is the device junction temperature
- TA is the ambient temperature
- RθJA is the package (junction-to-air) thermal resistance Because of this relationship, acceptable load current in high temperature conditions may be less than the maximum current-sourcing capability of the device. In no case should the device be operated outside of its maximum power rating because doing so can result in premature failure or permanent damage to the device. REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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9 Detailed Description
9.1 Overview
The REF35 is family of ultra-low current, low-noise, precision band-gap voltage references that are specifically designed for excellent initial voltage accuracy and drift. The Functional Block Diagram is a simplified block diagram of the REF35 showing basic band-gap topology.
9.2 Functional Block Diagram
R Buffer EN Control EN GND NR VREF Rp VIN Rp for Open Drain EN control
9.3 Feature Description
9.3.1 Supply Voltage
The REF35 family of references features an extremely low dropout voltage. For 10 mA loaded conditions, a maximum dropout voltage is 250 mV. Figure 7-28 shows a typical dropout voltage (V DO) versus load current. The device supports operation with input voltage range from V REF + VDO to 6 V. The typical quiescent current is 650 nA and maximum quiescent current over temperature is only 2.6 μA. The low dropout voltage coupled with ultra-low current enable the operation across multiple battery powered applications.
9.3.2 EN Pin
The REF35 family supports device enable and disable functionality through logic level control on EN pin. The EN pin of REF35 does not use an internal pull-up resistor. Instead, the pin uses new 'clean EN' technology. This allows the EN pin to be in a no connect condition at start-up, and no extra current is drawn from the supply when the EN pin is pulled low in shutdown mode. When EN pin is pulled high or left unconnected at start-up, the device is in active mode. When EN pin is driven by an open-drain output, a pull-up resistor to VIN is required. The device must be in active mode for normal operation. The EN pin must not be pulled higher than VIN supply voltage. The device can be placed in shutdown mode by pulling the EN pin low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the device drops to 100 nA at room temperature. When changing the device state from shutdown to active state, ensure the EN pin is not left floating. Also note that for applications where EN pin is no-connect, total parasitic capacitance on EN pin should be restricted within 30 pF. See the Electrical Characteristics table for logic high and logic low voltage levels.
9.3.3 NR Pin
The REF35 pin allows access to the band-gap through the NR pin. Placing a capacitor from the NR pin to GND creates a low-pass filter in combination with the internal resistance of 60 k Ω. Leakage of the capacitance directly impacts the accuracy and temperature drift. If NR functionality is used, choose a low leakage capacitor. A capacitance of 1 μF creates a low-pass filter with corner frequency around 2.7 Hz. Such a filter decreases the overall noise on the VREF pin. Higher capacitance results in a lower filter cut off frequency, further reducing output noise. Please note, using the capacitor on NR pin also increases start-up time. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: REF35
9.4 Device Functional Modes
9.4.1 Basic Connections
Figure 9-1 shows the typical connections for the REF35. TI recommends a supply bypass capacitor (C IN) ranging from 0.1 μF to 10 μF. A 0.1 μF to 10 μF output capacitor (CL) must be connected from REF to GND. The equivalent series resistance (ESR) value of CL must be lower than 400 mΩ to ensure output stability. VIN EN CIN CL GND GNDGND GND GND NR VREF Optional AVDD REF REF35 Figure 9-1. Basic Connections
9.4.2 Start-Up
Figure 9-2 shows the start-up behavior of REF35250 device with 1 μF load capacitance. REF35 device ensures the output voltage settles to the expected output voltage within specified accuracy without oscillations. The start-up time is dependent on the output voltage variant, output capacitance and NR pin capacitance. Higher capacitance leads to longer start-up time. Time (5 ms/div) V IN (1.5V/div) V REF (1.25V/div) Figure 9-2. REF35250 Start-Up Behavior, CL = 1 μF
9.4.3 Output Transient Behavior
The REF35 output buffer is capable of sourcing 10 mA load current as well as sink 5 mA of load current. The output stage is designed using class AB architecture with ultra-low quiescent current. This architecture avoids the dead zone around the no load condition. The output buffer uses a fast start-up implementation to achieve 2ms typical turn-on time at CL = 1 μF and no-load current condition. Figure 9-3 and Figure 9-4 show the output settling behavior for light load transient and high load transient respectively. REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
REF35 with low current consumption and class leading performance specifications is suitable reference for multiple applications. The device can also be used as a precision low noise power supply to sensor or data converter instead of traditional LDO or DC/DC based power supply. Basic applications includes positive/negative voltage reference and data acquisition systems. The table below shows the typical application of REF35 and its companion ADC/DAC. Table 10-1. Typical Applications and Companion ADC/DAC APPLICATIONS ADC/DAC PLC - DCS ADS7028, DAC8881, ADS1287, ADS7953 Rack Server ADS7028, ADS7128, ADS7138 Field Transmitters - Pressure, Flow ADS124S08 Optical Module, Optical Line Card ADS7068, ADS7138 Medical Blood Glucose Meter ADS1112 Power quality analyzer ADC3662 Thermal imaging ADC3541
10.2 Typical Applications
10.2.1 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF35 and OPA735 can be used to provide a dual-supply reference from a 5 V supply. Figure 10-1 shows the REF35250 used to provide a 2.5 V supply reference voltage. The low drift performance of the REF35250 complements the low offset voltage and zero drift of the OPA735 to provide an accurate solution for split-supply applications. Take care to match the temperature coefficients of R1 and R2. REF35250 10 k 10 k GND +5 V +5 V +2.5 V -5 V -2.5 V 1 2 OPA735 Figure 10-1. REF35 and OPA735 Create Positive and Negative Reference Voltages REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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10.2.2 Precision Power Supply and Reference
Figure 10-2 shows the basic configuration for the REF35 device as precision power supply to ADS7038 data converter which uses its power supply AVDD as reference. Connect bypass capacitors according to the guidelines in the Input and Output Capacitors section. ADS7038 GND REF35500 10 μF GND 1 μF AVDD GND +6 V Input
0 V to 5 V
0.1 μF 0.1 μF Figure 10-2. Basic Reference Connection
10.2.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 10-2 as the input parameters. Table 10-2. Design Example Parameters DESIGN PARAMETER VALUE Input voltage range VIN 0 V - 5 V Output resolution 12-bit REF35 input capacitor 1 µF REF35 output capacitor 10 µF
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Selection of Reference
The REF35500 reference is selected for this design. The REF35500 device operates of very low quiescent current while offering ±0.05% initial accuracy and very low noise. These parameters help improve system accuracy as compared to external LDO based power supply. The 5 V reference voltage supports the 0 V to 5 V input range specification.
10.2.2.2.2 Input and Output Capacitors
A 1 μF to 10 μF electrolytic or ceramic capacitor can be connected to the input to improve transient response in applications where the supply voltage may fluctuate. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: REF35
A ceramic capacitor of at least a 0.1 μF must be connected to the output to improve stability and help filter out high frequency noise. Add an additional 10 μF capacitor in parallel to improve transient performance in response to sudden changes in load current; however, keep in mind that doing so increases the start-up time of the device. Best performance and stability is attained with low-ESR, low-inductance ceramic chip-type output capacitors (X5R, X7R, or similar). If using an electrolytic capacitor on the output, place a 0.1 μF ceramic capacitor in parallel to reduce overall ESR on the output. Place the input and output capacitors as close as possible to the device.
10.2.2.2.3 Selection of ADC
ADS7038 12-bit 8 channel multiplexed ADC is chosen for this application. The ADC offers low current operation with averaging mode to increase the resolution to 16-bit with internal averaging modes while operating with slow sampling speed.
10.2.2.3 Application Curves
Table 10-3 and Figure 10-3 show the captured measurement results for various DC inputs. The ADC output is captured and analyzed for output accuracy error and code spread with REF35500 as power supply versus LDO as power supply. REF35 offers better accuracy and lower noise than the LDO device at lower quiescent current. This results in lower error in measurement as well as lower ADC output code variation across various OSR settings. Table 10-3. DC Input Performance Test Results INPUT V ADC OSR SETTING REF35500 LDO ERROR CODE SPREAD ERROR CODE SPREAD 1.0 V 0 0.01 mV 32 LSB 8.9 mV 48 LSB 8 0.3 mV 10 LSB 9.21 mV 16 LSB 128 0.38 mV 6 LSB 9.26 mV 6 LSB 2.5 V 0 0.69 mV 32 LSB 22.89 mV 64 LSB 8 1.44 mV 10 LSB 23.63 mV 18 LSB 128 1.17 mV 3 LSB 23.41 mV 5 LSB 4 V 0 2.27 mV 32 LSB 37.84 mV 48 LSB 8 3.01 mV 24 LSB 38.62 mV 24 LSB 128 2.46 mV 3 LSB 38.09 mV 17 LSB REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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Input voltage (V) Error (mV) 0 1 2 3 4 5 REF35-OSR0 REF35-OSR8 REF35-OSR128 LDO-OSR0 LDO-OSR8 LDO-OSR128 Figure 10-3. Error vs Input Voltage
10.3 Power Supply Recommendations
The REF35 family of references feature an extremely low-dropout voltage. These references can be operated with a supply of only 50 mV above the output voltage at no load. TI recommends a supply bypass capacitor ranging between 0.1 µF to 10 µF.
10.4 Layout
10.4.1 Layout Guidelines
Figure 10-4 shows an example of a PCB layout for a data acquisition system using the REF35. Some key considerations are:
- Connect low-ESR, 0.1 μF ceramic bypass capacitors at VIN, VREF of the REF35.
- Decouple other active devices in the system per the device specifications.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. Figure 10-5 shows the pin compatibility with TI REF30xx, REF31xx and REF33xx series references in the 3-pin SOT-23 package when using the REF35xxx family footprint. You must rotate the REF30xx, REF31xx and REF33xx reference devices by 180º before assembly. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: REF35
10.4.2 Layout Examples
C C Optional C Figure 10-4. Layout Example Not to scale REF35 REF30 REF31 REF33 VREF OUT (Pin 2) NR VIN IN (Pin 1) GND GND (Pin 3) GND EN C C Optional C Figure 10-5. Pin Compatibility With REF30xx, REF31xx and REF33xx REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 www.ti.com
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
- Texas Instruments, INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt Monitors data sheet
- Texas Instruments, Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design
- Texas Instruments, Precision voltage references Analog Design Journal
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com REF35 SNAS809A – DECEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF35
www.ti.com 13-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PREF35125QDBVR ACTIVE SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 125 Samples REF35120QDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2RVI Samples REF35125QDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2RUI Samples REF35300QDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2SLI Samples REF35500QDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2RWI Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
www.ti.com 13-Nov-2022 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF35120QDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0 REF35125QDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0 REF35300QDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0 REF35500QDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50 0.25 0.6
0.3 TYP
0 TYP
1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/C 06/2021 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
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