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Document overview
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Technical content
- General description The PR5331C3HN is a highly integrated transceiver module for contactless reader/writer communication at 13.56 MHz. A dedicated ROM code is implemented to handle different RF protocols by an integrated microcontroller. The system host controller communicates with the PR5331C3HN by using the USB or the HSU link. The protocol between the host controller and the PR5331C3HN, on top of this physical link is the CCID protocol.
1.1 RF protocols
PR5331C3HN supports the PCD mode for FeliCa (212 kbps and 424 kbps), ISO/IEC14443 Type A and B (from 106 kbps to 848 kbps), MIFARE (106 kbps), B' cards (106 kbps), picoPass tag (106 kbps) and Innovision Jewel cards (106 kbps) The Initiator passive mode (from 106 kbps to 424 kbps) can be supported through the PC/SC transparent mode.
1.2 Interfaces
The PR5331C3HN supports a USB 2.0 full speed interface (bus powered or host powered mode). Alternatively to the USB interface, a High Speed UART (from 9600b up to 1.2 Mb) can be used to connect the PR533 to a host. The PR5331C3HN has also a master I2C-bus interface that allows to connect one of the following peripherals:
- An external EEPROM: in this case the PR5331C3HN is configured as master and is able to communicate with external EEPROM (address A0h) which can store configuration data like PID, UID and RF parameters. When a USB host interface is used, these parameters are retrieved from the EEPROM at startup of the device
- A TDA8029 contact smart card reader
1.3 Standards compliancy
PR5331C3HN offers commands in order for applications to be compliant with “EMV Contactless Communication Protocol Specification V2.0.1”. PR5331C3HN supports RF protocols ISO/IEC 14443A and B such as compliancy with Smart eID standard can be achieved at application level. PR533 USB NFC integrated reader solution Rev. 3.6 — 27 October 2014 206436 Product short data sheet COMPANY PUBLIC
Rev. 3.6 — 27 October 2014 206436 2 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution Support of USB 2.0 full speed, interoperable with USB 3.0 hubs. The PR533C3HN in PCD mode is compliant with EMV contactless specification V2.0.1.
1.4 Supported operating systems
- Microsoft Windows 2000
- Microsoft Windows XP (32 and 64 bits)
- Microsoft Windows 2003 Server (32 and 64 bits)
- Microsoft Windows 2008 Server (32 and 64 bits)
- Microsoft Windows Vista (32 and 64 bits)
- Microsoft Windows 7 (32 and 64 bits) The PR533 is supported by the following OS through the PCSC-Lite driver:
- GNU/Linux using libusb 1.0.x and later
- Mac OS Leopard (1.5.6 and newer)
- Mac OS Snow Leopard (1.6.X)
- Solaris
- FreeBSD 2. Features and benefits USB 2.0 full speed host interface and CCID protocol support Integrated microcontroller implements high-level RF protocols Buffered output drivers to connect an antenna with minimum number of external components Integrated RF level detector Integrated data mode detector Supports ISO/IEC 14443A Reader/Writer mode up to 848 kbit/s Supports ISO/IEC 14443B Reader/Writer mode up to 848 kbit/s Supports contactless communication according to the FeliCa protocol at 212 kbit/s and 424 kbit/s Supports MIFARE encryption Typical operating distance in Read/Write mode for communication to ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending on antenna size and tuning I2C-bus master interface allows to connect an external I2C EEPROM for configuration data storage or to control a TDA8029 contact smart card reader Low-power modes Hard power-down mode Soft power-down mode Only one external oscillator required (27.12 MHz Crystal oscillator) Power modes USB bus power mode 2.5 V to 3.6 V power supply operating range in non-USB bus power mode
[1] V DDD, VDDA and VDD(TVDD) must always be at the same supply voltage. Table 1. Quick reference data
[2] Refer to Section 14.4 “ Licenses”. [3] MSL 2 (Moisture Sensitivity Level). firmware or which can be accessible for data transaction by a host baseband. Table 2. Ordering information
27 MHz OSC
48 MHz
Rev. 3.6 — 27 October 2014 206436 5 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution 6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for HVQFN 40 (SOT618-1) aaa-000044 PR533 P70_IRQ VMID RX RSTOUT_N AVDD DVSS TVSS2 DM TX2 DP TVDD PVDD TX1 DELATT TVSS1 P30 LOADMOD P31 DVSS P32_INT0 AVSS AUX1 AUX2 DVSS OSCIN OSCOUT TESTEN P35 VBUS DVDD RSTPD_N SVDD SIGIN SIGOUT P34 SDA P50_SCL P33_INT1 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 terminal 1 index area Transparent top view Table 3. PR533 pin description
Description
LOADMOD 2 O DVDD load modulation output provides digital signal for FeliCa and MIFARE card operating mode TVSS1 3 G transmitter ground: suppli es the output stage of TX1 TX1 4 O TVDD transmitter 1: transmits modulated 13.56 MHz energy carrier TVDD 5 P transmitter power supply: supplies the output stage of TX1 and TX2 TX2 6 O TVDD transmitter 2: delivers t he modulated 13.56 MHz energy carrier TVSS2 7 G transmitter ground: suppli es the output stage of TX2 AVDD 8 P analog power supply VMID 9 P AVDD internal reference voltage: This pin delivers the internal reference voltage. RX 10 I AVDD receiver input: Input pin for the re ception signal, which is the load modulated
13.56 MHz energy carrier from the antenna circuit
AUX1 12 O DVDD auxiliary output 1: This pin delivers analog and digital test signals AUX2 13 O DVDD auxiliary output 2: This pin delivers analog and digital test signals DVSS 14 G digital ground
Rev. 3.6 — 27 October 2014 206436 6 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution OSCIN 15 I AVDD crystal oscillator in put: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fclk = 27.12 MHz). OSCOUT 16 O AVDD crystal oscillator output: output of the inverting amplifier of the oscillator. I0 17 I DVDD interface mode lines: selects the used host interface; in test mode I0 is used as test signals.I1 18 I DVDD TESTEN 19 I DVDD test enable pin: when set to 1 enable the test mode. when set to 0 reset the TCB and disable the access to the test mode. P35 20 I/O DVDD general purpose I/O signal P70_IRQ 21 I/O PVDD interrupt request: output to signal an interrupt event to the host (Port 7 bit 0) RSTOUT_N 22 O PVDD output reset signal; when LOW it indicates that the circuit is in reset state. DVSS 23 G digital ground DM 24 I/O PVDD USB D data line in USB mode or TX in HSU mode; in test mode this signal is used as input and output test signal DP 25 I/O PVDD USB D+ data line in USB mode or RX in HSU mode; in test mode this signal is used as input and output test signal. PVDD 26 P I/O pad power supply DELATT 27 O PVDD optional output for an external 1.5 k resistor connection on D+. P30 28 I/O PVDD general purpose I/O signal. Can be configured to act either as RX line of the second serial interface UART or general purpose I/O. In test mode this signal is used as input and output test signal. P31 29 I/O PVDD general purpose I/O signal. Can be configured to act either as TX line of the second serial interface UART or general purpose I/O. In test mode this signal is used as input and output test signal. P32_INT0 30 I/O PVDD general purpose I/O signal. Can also be used as an interrupt source In test mode this signal is used as input and output test signal. P33_INT1 31 I/O PVDD general purpose I/O signal. Can be used to generate an HZ state on the out- put of the selected interface for the Host communication and to enter into power-down mode without resetting the internal state of PR533. In test mode this signal is used as input and output test signal. P50_SCL 32 I/O DVDD I 2C-bus clock line - open-drain in output mode SDA 33 I/O DVDD I 2C-bus data line - open-drain in output mode P34 34 I/O SVDD general purpose I/O signal or clock signal for the SAM SIGOUT 35 O SVDD contactless commun ication interface output: delivers a serial data stream according to NFCIP-1 and output signal for the SAM. In test mode this signal is used as test signal output. SIGIN 36 I SVDD contactless communication interface input: accepts a digital, serial data stream according to NFCIP-1 and input signal from the SAM. In test mode this signal is used as test signal input. SVDD 37 P output power for SAM power supply. Switched on by Firmware with an over- load detection. Used as a reference voltage for SAM communication. Table 3. PR533 pin description …continued
Rev. 3.6 — 27 October 2014 206436 7 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution [1] Pin types: I= Input, O = Output, I/O = Input/Output, P = Power and G = Ground. 7. Limiting values [1] 1500 , 100 pF; EIA/JESD22-A114-A [2] 0.75 mH, 200 pF; EIA/JESD22-A115-A [3] Field induced model; EIA/JESC22-C101-C RSTPD_N 38 I PVDD reset and power-down: When LOW, internal current sources are switched off, the oscillator is inhibited, and the input pads are disconnected from the out- side world. With a negative edge on this pin the internal reset phase starts. DVDD 39 P digital power supply VBUS 40 P USB power supply. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
- Recommended operating conditions
[1] V SSA, VDDD and VDD(TVDD) shall always be on the same voltage level. [2] Supply voltages below 3 V reduces the perform ance (e.g. the achievable operating distance). mode, VBUS = 5 V in USB power mode. Timings are only given from characterization results.
10.1 Power manageme nt characteristics
10.1.1 Current consumption characteristics
40 between TX1 and TX2 at 13.56 MHz. Table 5. Operating conditions Table 6. Thermal characteristics
[1] I pd is the total currents over all supplies. [2] I DD(PVDD) depends on the overall load at the digital pins. [3] I DD(SVDD) depends on the overall load on VDD(SVDD) pad. [4] I DD(TVDD) depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2. [5] During operation with a typical circui try the overall current is below 100 mA.
10.1.2 Voltage regulator characteristics
[1] The internal regulator is only enabled when the USB interface is selected by I0 and I1.
10.2 Antenna presence se lf test thresholds
cases andet_ithl[1:0] = 10b and for andet_ithh[2:0] = 011b. Table 7. Current consumption characteristics Table 8. Voltage regulator characteristics [1]
Table 9. Antenna presence detection
“27.12 MHz input clock phase noise spectrum mask”. Table 10. Crystal requirements Table 11. Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
10.5 RSTPD_N input pin characteristics
10.6 Input pin characteristi cs for I0, I1 and TESTEN
[1] To minimize power consumption when in soft power-down mode, the limit is V DDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. recommended to connect TESTEN to ground although there is a pull-down included. Table 12. RSTPD_N input pin characteristics Table 13. Input pin characteristics for I0, I1 and TESTEN
10.7 RSTOUT_N output pin characteristics
[1] Data at V DD(PVDD) = 1.8V are only given from characterization results. [2] I OH and IOL give the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance. Table 14. RSTOUT_N output pin characteristics
10.8 Input/output characte ristics for pin P70_IRQ
[1] To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD) 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. [3] Data at V DD(PVDD) = 1.8 V are only given from characterization results. [4] The I OH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance. Table 15. Input/output pin ch aracteristics for pin P70_IRQ
10.9 Input/output pin char acteristics for P30 / UART_RX, P31 / UART_TX,
[1] To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD) 0.4 V. [3] Data at V DD(PVDD) = 1.8 V are only given from characterization results. [4] The I OH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance. Table 16. Input/output pi n characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1
10.10 Input/output pin ch aracteristics for P35
[1] To minimize power consumption when in soft power-down mode, the limit is VDDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. [3] The I OH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance. Table 17. Input/output pin characteristics for P35
10.11 Input/output pi n characteristics for DP and DM
[1] The value does not guarantee the power-down consumptions. To r each the specified power-down consumptions, the limit is 0.4 V. [2] The I OH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance. Table 18. Input/output pin characterist ics for DP and DM for USB interface
Table 19. USB DP/DM differential receiver input levels Table 20. USB DP/DM driver characteristics
0 V differential
[2] The value does not guarantee the power-down consumptions. To r each the specified power-down consumptions, the limit is 0.4 V. Table 21. Input Pin characteristics for DP for HSU interface Table 22. Output Pin characteristi cs for DM for HSU interface
10.12 Input pin characteristics for SCL
[1] To minimize power consumption when in soft power-down mode, the limit is VDDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. dependent of the I2C-bus speed.
10.13 Input/output pin ch aracteristics for SDA
[1] To minimize power consumption when in soft power-down mode, the limit is VDDD 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. dependent of the I2C-bus speed. Table 23. Input/output drain output pin characteristics for SCL I2C interface Table 24. Input/output drain output pin characteristics for SDA I2C interface
10.14 Output pin char acteristics for DELATT
[1] To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD) 0.4 V.
10.15 Input pin charact eristics for SIGIN
[1] To minimize power consumption when in soft power-down mode, the limit is VDD(SVDD) 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
10.16 Output pin char acteristics for SIGOUT
Table 25. Output pin characteristics for DELATT Table 26. Input/output pin characteristics for SIGIN Table 27. Output pin characteristics for SIGOUT
10.17 Input/output pin ch aracteristics for P34
[1] To minimize power consumption when in soft power-down mode, the limit is VDD(SVDD) 0.4 V. [2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V. [3] I OH and IOL specify the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance.
10.18 Output pin charact eristics for LOADMOD
Table 28. Input/output pin characteristics for P34 Table 29. Output pin char acteristics for LOADMOD
10.19 Input pin characteristics for RX
Table 30. Input pin characteristics for RX
13.56 MHz
1.5 V DC offset
[1] The minimum modulation voltage is valid for al l modulation schemes except Miller coded signals.
10.20 Output pin charact eristics for AUX1/AUX2
Table 30. Input pin characteristics for RX …continued Table 31. Output pin characteristics for AUX1/AUX2
10.21 Output pin charact eristics for TX1/TX2
Table 32. Output pin char acteristics for TX1/TX2 Table 33. Output resistance for TX1/TX2
10.22 System reset timing
[1] Dependent on the 27.12 MHz crysta l oscillator startup time. [2] If the t rst pulse is shorter than 20 ns, the device may be only partially reset. Table 34. Reset duration time
10.23 Timing for the I 2C-bus interface
is always present and not dependent of the I2C-bus speed. the falling edge of P50_SCL. Table 35. I 2C-bus timing specification
10.24 Temperature sensor
ensure that the ambient temperature does not exceed 85 C as specified in Table 5 “Operating conditions”. Table 36. Temperature sensor characteristics
27.12 MHz
Table 37. Abbreviations
[1] Revision 3.4 is not available. Table 38. Revision history Modifications: • Template updated.
- Descriptive title updated.
- Alternative descriptive title updated. PR533_SDS v.3.3 20121020 Product short data sheet - PR533_SDS v.3.2 Modifications:
- Section 14.4 “Licenses”: updated PR533_SDS v.3.2 20120306 Product short data sheet - PR5331C3HN_SDS v.3.0 Modifications:
- Section 4 “Ordering information”: updated
- General update to comply full data sheet PR5331C3HN_SDS v.3.0 20110803 Product short data sheet - -
Rev. 3.6 — 27 October 2014 206436 31 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution 14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Rev. 3.6 — 27 October 2014 206436 32 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
14.4 Licenses
14.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP Semiconductors N.V. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.
Rev. 3.6 — 27 October 2014 206436 33 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution Notes
Table 8. Voltage regulator characteristics Table 11. Pin characteristics for 27.12 MHz XTAL Table 13. Input pin characteristics for I0, I1 and Table 15. Input/output pin characteristics for Table 16. Input/output pin characteristics for P30 / Table 18. Input/output pin characteristics for DP Table 19. USB DP/DM differential receiver input levels . .18 Table 21. Input Pin characteristics for DP for HSU Table 22. Output Pin characteristics for DM for HSU Table 23. Input/output drai n output pin characteristics Table 24. Input/output drai n output pin characteristics Table 31. Output pin characteristics for AUX1/AUX2 . . .24 Table 35. I
Rev. 3.6 — 27 October 2014 206436 35 of 36 NXP Semiconductors PR533 USB NFC integrated reader solution 17. Figures Fig 3. 27.12 MHz input clock phase noise spectrum
USB NFC integrated reader solution © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 October 2014 206436 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 10.4 Pin characteristics for 27.12 MHz XTAL
10.6 Input pin characteristics for I0, I1 and
10.8 Input/output characteristics for pin P70_IRQ . 14
10.9 Input/output pin characteristics for P30 /
UART_RX, P31 / UART_TX, P32_INT0,
10.11 Input/output pin characteristics for DP and DM 17
10.20 Output pin characteristics for AUX1/AUX2 . . . 24