PR31100

PR31100 PHILIPS | Alldatasheet

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Highly integrated embedded processor Preliminary specification 1996 Aug 07 INTEGRATED CIRCUITS Version 1.2

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor Version 1.2

21996 Aug 07

PR31100 Processor is a single-chip, low-cost, integrated embedded processor consisting of MIPS R3000 core and system support logic to interface with various types of devices. PR31 100 consists of a MIPS R3000 RISC CPU with 4 KBytes of instruction cache memory and 1 KByte of data cache memory, plus integrated functions for interfacing to numerous system components and external I/O modules. The R3000 RISC CPU is also augmented with a multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols. PR31100 also contains multiple DMA channels and a high-performance and flexible Bus Interface Unit (BIU) for providing an efficient means for transferring data between external system memory, cache memory, the CPU core, and external I/O modules. The types of external memory devices supported include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), Flash memory, read-only memory (ROM), and expansion cards (PCMCIA and/or MagicCard). PR31 100 also contains a System Interface Module (SIM) containing integrated functions for interfacing to numerous external I/O modules such as liquid crystal displays (LCDs), the UCB1100 (which handles most of the analog functions of the system, including sound and telecom codecs and touchscreen ADC), ISDN/high-speed serial, infrared, wireless peripherals, Magicbus, etc. Lastly, PR31100 contains support for implementation of power management, whereby various PR31100 internal modules and external subsystems can be individually (under software control) powered up and down. Figure 1 shows an External Block Diagram of PR31100.

FEATURES

• 32-bit R3000 RISC static CMOS CPU
• 4 KByte instruction cache
• 1 KByte data cache
• Multiply/accumulator
• On-chip peripherals with individual power-down – Multi-channel DMA controller – Bus interface unit – Memory controller for ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA and/or MagicCard – Power management module – Video module – Real-time clock 32.760KHz reference – High-speed serial interface – Infrared module – Dual-UART – SPI bus
• 3.3V supply voltage
• 208-pin LQFP (Low profile quad flat pack)
• 40MHz operation frequency

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE ( °C) AND PACKAGE FREQUENCY (MHz) DRAWING NUMBER PR31100ABC 0 to +70, 208-pin Low Profile Quad Flat Pack 40 LQFP208

1996 Aug 07 3

32 KHz

Figure 1. PR31100 Block Diagram

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 4

Each of the on-chip peripherals consist of: BIU Module

• System memory and PR31100 Bus Interface Unit (BIU) – supports up to 2 banks of physical memory – supports self–refreshing DRAM and SDRAM – programmable parameters for each bank of DRAM or SDRAM (row/column address configuration, refresh, burst modes, etc.)
• programmable chip select memory access – 4 programmable (size, wait states, burst mode control) memory device and general purpose chip selects available for system ROM, SRAM, Flash available for external port expansion registers – 4 programmable (wait states, burst mode control) MagicCard or general purpose chip selects available for (future) MagicCard expansion memory PR31 100 provides the chip select and card detect signals supports card insertion/removal timeouts MagicCard requires minimal number of unique control/status signals per port
• supports up to 2 identical full PCMCIA ports – PR31100 and UCB1100 provide the control signals and accepts the status signals which conform to the PCMCIA version 2.01 standard – appropriate connector keying and level–shifting buffers required for 3.3V versus 5V PCMCIA interface implementations SIU Module
• multi–channel 32–bit DMA controller and System Interface Unit (SIU)
• independent DMA channels for video, Magicbus, SIB to/from UCB1 100 audio/telecom codecs, high–speed serial port, IR UART, and general purpose UART
• address decoding for submodules within System Interface Module (SIM) CPU Module
• R3000 RISC central processing unit core – full 32–bit operation (registers, instructions, addresses) – 32 general purpose 32–bit registers; 32–bit program counter – MIPS RISC Instruction Set Architecture (ISA) supported
• on–chip cache – 4 KByte direct–mapped instruction cache (I–cache) physical address tag and valid bit per cache line programmable burst size instruction streaming mode supported – 1 KByte data cache (D–cache) physical address tag and valid bit per cache line programmable burst size write–through – cache address snoop mode supported for DMA – 4–level deep write buffer
• programmable memory protection – separate read and write protection control for kernel and user space – 8 total protectable regions available, each individually programmable, using breakpoint address, mask, control, and status registers – causes address exception on illegal reads or writes
• high–speed multiplier/accumulator – on–chip hardware multiplier – supports 16x16 or 32x32 multiplier operations, with 64–bit accumulator – existing multiply instructions are enhanced and new multiply and add instructions are added to R3000 instruction set to improve the performance of DSP applications
• CPU interface – handles data bus, address bus, and control interface between CPU core and rest of PR31100 logic Clock Module
• PR31100 supports system–wide single crystal configuration, besides the 32 KHz RTC XTAL (reduces cost, power, and board space)
• common crystal rate divided to generate clock for CPU, video, sound, telecom, UARTs, etc.
• external system crystal rate is vendor–dependent
• independent enabling or disabling of individual clocks under software control, for power management CHI Module
• high–speed serial Concentration Highway Interface (CHI) contains logic for interfacing to external full–duplex serial time–division–multiplexed (TDM) communication peripherals
• supports ISDN line interface chips and other PCM/TDM serial devices
• CHI interface is programmable (number of channels, frame rate, bit rate, etc.) to provide support for a variety of formats
• supports data rates up to 4.096 Mbps
• independent DMA support for CHI receive and transmit Interrupt Module
• contains logic for individually enabling, reading, and clearing all PR31100 interrupt sources
• interrupts generated from internal PR31100 modules or from edge transitions on external signal pins IO Module
• contains support for reading and writing the 7 bi–directional general purpose IO pins and the 32 bi–directional multi–function IO pins
• each IO port can generate a separate positive and negative edge interrupt
• independently configurable IO ports allow PR31100 to support a flexible and wide range of system applications and configurations

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 5

• IR consumer mode – allows control of consumer electronic devices such as stereos, TVs, VCRs, etc. – programmable pulse parameters – external analog LED circuitry
• IRDA communication mode – allows communication with other IRDA devices such as FAX machines, copiers, printers, etc. – supported by UART module within PR31100 – external analog receiver preamp and LED circuitry – data rate = up to 115 Kbps at 1 meter
• IR FSK communication mode – supported by UART module within PR31100 – external analog IR chip(s) perform frequency modulation to generate the desired IR communication mode protocol – data rate = up to 36000 bps at 3 meters
• carrier detect state machine – periodically enables IR receiver to check if a valid carrier is present Magicbus Module
• synchronous, serial 2–wire (clock and data), half–duplex communications protocol
• supports low–cost, low–power peripherals
• supports maximum data rate of 14.75 Mbps
• DMA support for Magicbus receive and transmit Power Module
• power–down modes for individual internal peripheral modules
• serial (SPI port) power supply control interface supported
• power management state machine has 4 states: RUNNING, DOZING, SLEEP , and COMA Serial Interconnect Bus (SIB) Module
• PR31100 contains holding and shift registers to support the serial interface to the UCB1100 and/or other optional codec devices
• interface compatible with slave mode 3 of Crystal CS4216 codec
• synchronous, frame–based protocol
• PR31 100 always master source of clock and frame frequency and phase; programmable clock frequency
• each SIB frame consists of 128 clock cycles, further divided into 2 subframes or words of 64 bits each (supports up to 2 devices simultaneously)
• independent DMA support for audio receive and transmit, telecom receive and transmit
• supports 8–bit or 16–bit mono telecom formats
• supports 8–bit or 16–bit mono or stereo audio formats
• independently programmable audio and telecom sample rates
• CPU read/write registers for subframe control and status System Peripheral Interface (SPI) Module
• provides interface to SPI peripherals and devices
• full–duplex, synchronous serial data transfers (data in, data out, and clock signals)
• PR31 100 supplies dedicated chip select and interrupt for an SPI interface serial power supply
• 8–bit or 16–bit data word lengths for the SPI interface
• programmable SPI baud rate Timer Module
• Real Time Clock (RTC) and Timer
• 40–bit counter (30.517 µsec granularity); maximum uninterrupted time = 388.36 days
• 40–bit alarm register (30.517 µsec granularity)
• 16–bit periodic timer (0.868 µsec granularity); maximum timeout = 56.8 msec
• interrupts on alarm, timer, and prior to RTC roll–over UART Module
• 2 independent full–duplex UARTs
• programmable baud rate generator
• UAR T–A port used for serial control interface to external IR module
• UAR T–B port used for general purpose serial control interface
• UART–A and UAR T–B DMA support for receive and transmit Video Module
• bit–mapped graphics
• supports monochrome, grey scale, or color modes
• time–based dithering algorithm for grey scale and color modes
• supports multiple screen sizes
• supports split and non–split displays
• variable size and relocatable video buffer
• DMA support for fetching image data from video buffer

1996 Aug 07 6

PR31100 and UCB1100 for a total system solution. Figure 2. System Block Diagram

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 7

1 V DD

2 D(0)

3 V SS

4 D(1)

5 D(2)

6 V DD

7 D(3)

8 V SS

9 D(4)

10 V DD

11 D(5)

12 D(6)

13 V SS

14 D(7)

15 V SS

16 D(8)

17 V DD

18 D(9)

19 D(10)

20 V SS

21 D(11)

22 V DD

23 D(12)

24 D(13)

25 V SS

26 D(14)

27 D(15)

28 V DD

30 MFIO(1)

31 MBUSINT

32 MBUSDATA

33 V SS

34 MBUSCLK

35 V DD

36 V DD

37 SIBMCLK

38 V SS

39 SIBSCLK

40 SIBSYNC

41 SIBDIN

42 SIBDOUT

43 V DD

44 SIBIRQ

45 MFIO(0)

46 IO(6)

47 IO(50

48 V SS

53 V DD

54 RXD

55 TXD

56 IO(4)

58 IRIN

59 IROUT

60 V SS

61 V DD

62 CARDET

63 TXPWR

64 IO(3)

65 IO(2)

66 V SS

67 SPICLK

68 SPIIN

69 SPIOUT

70 V DD

71 TESTCPU

72 TESTIN

73 TESTOUT

74 TESTSIU

75 V SS

76 V CC 3

77 BC32K

78 V DD

79 C32KIN

80 C32KOUT

81 V SS

82 PWRCS

83 PWRINT

84 PWROK

86 ONBUTN

89 V DD

90 DISPON

91 FRAME

92 V SS

94 LOAD

96 V SS

97 V DD

98 VDAT(0)

99 VDAT(1)

100 VDAT(2)

101 VDAT(3)

102 V SS

103 IO(1)

104 V DD

108 IO(0)

109 V SS

114 V DD

115 MFIO(2)

116 V DD

119 V SS

127 V DD

128 SYSCLKIN

129 SYSCLKOUT

130 V SS

131 V SS

132 V DD

133 D(31)

134 D(30)

135 V SS

136 D(29)

137 V DD

138 D(28)

139 D(27)

140 V SS

141 D(26)

142 V SS

143 D(250

144 V DD

145 D(24)

146 D(23)

147 V DD

148 D(22)

149 V SS

150 D(21)

151 V DD

152 D(20)

153 D(19)

154 V SS

155 D(18)

156 V DD

157 D(17)

158 V SS

159 D(16)

160 V DD

164 V SS

165 V DD

168 ALE

170 V DD

171 A(12)

172 A(11)

173 V SS

174 A(10)

175 A(9)

176 V DD

177 A(8)

178 A(7)

179 V SS

180 A(6)

181 A(5)

182 V DD

183 A(4)

184 V SS

185 A(3)

186 A(2)

187 V DD

188 A(1)

189 A(0)

190 V SS

191 V SS

196 V DD

200 V SS

201 V DD

202 DCKE

203 V SS

204 DCLKIN

205 DCLKOUT

206 V DD

207 DQMH

208 DQML

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 8

The PR31100 processor contains 208 pins consisting of input, output, bi–directional, and power and ground pins. These pins are used to support various functions. The following sections will describe the function of each pin including any special power–down considerations for each pin. Pins The PR31100 PROCESSOR contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. Of the 136 signal pins, 32 of them are multi–function and can be independently programmed either as IO ports or for an alternate standard/normal function. As an IO port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and negative edge interrupt. See Section 2.3 for a summary of the multi–function IO ports versus their standard functions. PIN # NAME TYPE NAME AND FUNCTION Memory Pins D(31:0) I/O These pins are the data bus for the system. 8–bit SDRAMs should be connected to bits 7:0 and 16–bit SDRAMs and DRAMs should be connected to bits 15:0. All other 16–bit ports should be connected to bits 31:16. Of course, 32–bit ports should be connected to bits 31:0. These pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn–around. A(12:0) O These pins are the address bus for the system. The address lines are multiplexed and can be connected directly to SDRAM and DRAM devices. To generate the full 26–bit address for static devices, an external latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from PR31100’s address bus) are held afterward by PR31100 processor for the remainder of the address bus cycle. 168 ALE O This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating the upper address bits 25:13. 163 /RD O This pin is used as the read signal for static devices. This signal is asserted for reads from /MCS3–0, /CS3–0, /CARD2CS and /CARD1CS for memory and attribute space, and for reads from PR31100 processor accesses if SHOWPR31100 is enabled (for debugging purposes). 169 /WE O This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3–0, /CS3–0, /CARD2CS and /CARD1CS for memory and attribute space, and for writes to DRAM and SDRAM. 199 /CAS0 (/WE0) O This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the write enable signal for D(7:0) for static devices. 198 /CAS1 (/WE1) O This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8) for static devices. 197 /CAS2 (/WE2) O This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for D(23:16) for static devices. 195 /CAS3 (/WE3) O This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for D(31:24) for static devices. 194 /RAS0 O This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs. 193 /RAS1 (/DCS1) O This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs. 192 /DCS0 O This pin is used as the chip select signal for Bank0 SDRAMs. 202 DCKE O This pin is used as the clock enable for SDRAMs. 204 DCLKIN I This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when reading from SDRAM and DRAM devices. 205 DCLKOUT O This pin is the (nominal) 73.728 MHz clock for the SDRAMs. 207 DQMH O This pin is the upper data mask for a 16–bit SDRAM configuration. 208 DQML O This pin is the lower data mask for a 16–bit SDRAM or 8–bit SDRAM configuration. 124–126, 162 /CS3–0 O These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32–bit or 16–bit ports. 120–123 /MCS3–0 O These pins are the MagicCard Chip Select 3 through 0 signals. They only support 16–bit ports. 106, 107 /CARD2CSH,L O These pins are the Chip Select signals for PCMCIA card slot 2.

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 9

PIN # NAME AND FUNCTION TYPENAME Memory Pins (continued) 117, 118 /CARD1CSH,L O These pins are the Chip Select signals for PCMCIA card slot 1. 112 /CARDREG O This pin is the /REG signal for the PCMCIA cards. 110 /CARDIORD O This pin is the /IORD signal for the PCMCIA IO cards. 111 /CARDIOWR O This pin is the /IOWR signal for the PCMCIA IO cards. 115 /CARDDIR O This pin is used to provide the direction control for bi–directional data buffers used for the PCMCIA slot(s). This signal will assert whenever /CARD2CSH or /CARD2CSL or /CARD1CSH or /CARD1CSL is asserted and a read transaction is taking place. 105 /CARD2WAIT I This pin is the card wait signal from PCMCIA card slot 2. 113 /CARD1WAIT I This pin is the card wait signal from PCMCIA card slot 1. Bus Arbitration Pins 167 /DREQ I This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU function has been enabled, then once /DGRNT is asserted, external logic can initiate reads or writes to PR31100 processor registers by driving the appropriate input signals. If the TESTSIU signal is low or the TESTSIU function has not been enabled, then PR31100 memory transactions are halted and certain memory signals will be tri–stated when /DGRNT is asserted in order to allow an external master to access memory. 166 /DGRNT O This pin is asserted in response to /DREQ to inform the external test logic or bus master that it can now begin to drive signals. Clock Pins

128 SYSCLKIN I This pin should be connected along with SYSCLKOUT to an external crystal which is the main

PR31100 clock source.

129 SYSCLKOUT O This pin should be connected along with SYSCLKIN to an external crystal which is the main

PR31100 clock source. 79 C32KIN I This pin along with C32KOUT should be connected to a 32.768 KHz crystal. 80 C32KOUT O This pin along with C32KIN should be connected to a 32.768 KHz crystal. 77 BC32K O This pin is a buffered output of the 32.768 KHz clock. CHI Pins 50 CHIFS I/O This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes. As an output, this pin allows PR31100 to be the master CHI sync source. As an input, this pin allows an external peripheral to be the master CHI sync source and the PR31100 CHI module will slave to this external sync. 49 CHICLK I/O This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output, this pin allows PR31100 to be the master CHI clock source. As an input, this pin allows an external peripheral to be the master CHI clock source and the PR31100 CHI module will slave to this external clock. 52 CHIDOUT O This pin is the CHI serial data output signal. 51 CHIDIN I This pin is the CHI serial data input signal. IO Pins 46, 107, 47, 108, 56, 64, IO(6:0) I/O These pins are general purpose input/output ports. Each port can be independently programmed as an input or output port. Each port can generate a separate positive and negative edge interrupt. Each port can also be independently programmed to use a 16 to 24 msec debouncer. 30, 45 MFIO(1:0) I/O These pins are multi–function input/output ports. Each port can be independently programmed as an input or output port, or can be programmed for multi–function use to support vendor–dependent test signals (for debugging purposes only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other multi–function pins are available for usage as multi–function input/output ports. These pins are named after their respective standard/normal function and are not listed here. Magicbus Pins 34 MBUSCLK I/O This pin is the bi–directional Magicbus clock signal. MBUSCLK is an input signal whenever PR31 100 is in the slave mode and is an output signal whenever PR31100 is in the master mode. 32 MBUSDATA I/O This pin is the bi–directional Magicbus data signal. MBUSDATA is an input signal whenever PR31 100 is in the slave mode and is an output signal whenever PR31100 is in the master mode.

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 10

PIN # NAME AND FUNCTION TYPENAME 31 MBUSINT I This pin is the Magicbus interrupt signal. This signal is used to interrupt PR31100 whenever a peripheral has been attached to or detached from the bus, or whenever a peripheral has initiated an interrupt event. Reset Pins 88 /CPURES I This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a reset in the event that a software problem might hang the CPU core. The pin should also be pulled up to VSTANDBY through an external pull–up resistor. 87 /PON I This pin serves as the Power On Reset signal for PR31100. This signal must remain low when VSTANDBY is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal should never go low unless all power is lost in the system. Power Supply Pins 86 ONBUTN I This pin is used as the On Button for the system. Asserting this signal will cause PWRCS to set to indicate to the System Power Supply to turn power on to the system. PWRCS will not assert if the PWROK signal is low. 82 PWRCS O This pin is used as the chip select for the System Power Supply. When the system is off, the assertion of this signal will cause the System Power Supply to turn VCCDRAM and VCC3 on to power up the system. The Power Supply will latch SPI commands on the falling edge of PWRCS. Power Supply Pins (continued) 84 PWROK I This pin provides a status from the System Power Supply that there is a good source of power in the system. This signal typically will be asserted if there is a Battery Charger supplying current or if the Main Battery is good and the Battery Door is closed. If PWROK is low when the system is powered off, PWRCS will not assert as a result of the user pressing the ONBUTN or an interrupt attempting to wake up the system. If the device is on when the PWROK signal goes low, the software will immediately shut down the system since power is about to be lost. When PWROK goes low, there must be ample warning so that the software can shut down the system before power is actually lost. 83 PWRINT I This pin is used by the System Power Supply to alert the software that some status has changed in the System Power Supply and the software should read the status from the System Power Supply to find out what has changed. These will be low priority events, unlike the PWROK status, which is a high priority emergency case. 76 VCC3 I This pin provides the status of the power supply for the ROM, UCB1100, system buffers, and other transient components in the system. This signal will be asserted by the System Power Supply when PWRCS is asserted, and will always be turned off when the system is powered down. SIB Pins 41 SIBDIN I This pin contains the input data shifted from UCB1100 and/or external codec device. 42 SIBDOUT O This pin contains the output data shifted to UCB1100 and/or external codec device. 39 SIBSCLK O This pin is the serial clock sent to UCB1100 and/or external codec device. The programmable SIBSCLK rate is derived by dividing down from SIBMCLK. 40 SIBSYNC O This pin is the frame synchronization signal sent to UCB1100 and/or external codec device. This frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data. 44 SIBIRQ I This pin is a general purpose input port used for the SIB interrupt source from UCB1100. This interrupt source can be configured to generate an interrupt on either a positive and/or negative edge. 37 SIBMCLK I/O This pin is the master clock source for the SIB logic. This pin is available for use in one of two modes. First, SIBMCLK can be configured as a high–rate output master clock source required by certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main PR31100 system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source, which is asynchronous with respect to CLK2X. Also, for this mode, SIBMCLK can still be optionally used as a high–rate master clock source required by certain external codec devices. SPI Pins 67 SPICLK O This pin is used to clock data in and out of the SPI slave device. 69 SPIOUT O This pin contains the data that is shifted into the SPI slave device. 68 SPIIN I This pin contains the data that is shifted out of the SPI slave device.

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 11

PIN # NAME AND FUNCTION TYPENAME UART and IR Pins 55 TXD O This pin is the UART transmit signal from the UARTA module. 54 RXD I This pin is the UART receive signal to the UARTA module. 59 IROUT O This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if Consumer IR mode is enabled. 58 IRIN I This pin is the UART receive signal to the UARTB module. RXPWR O This pin is the receiver power output control signal to the external communication IR analog circuitry. 62 CARDET I This pin is the carrier detect input signal from the external communication IR analog circuitry. Video Pins 91 FRAME O This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to return it’s pointers to the top of the display. The Video Module asserts FRAME after all the lines of the LCD have been shifted and transferred, producing a full frame of display. 93 DF O This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to toggle every programmable number of LOAD signals.

94 LOAD O This pin is the line synchronization pulse signal between the Video Module and the LCD, and is

used by the LCD to transfer the contents of it’s horizontal line shift register to the LCD panel for display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD. 95 CP O This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and sampled by the LCD on the falling edge of CP. 101, 100, 99, 98 VDAT(3:0) O These pins are the data for the LCD. These signals are directly connected to the LCD for 4–bit non–split displays. For 4–bit split and 8–bit non–split displays, an external register is required to demultiplex the 4–bit data into the desired 8 parallel data lines needed for the LCD. 90 DISPON O This pin is the display–on enable signal for the LCD. Test Pins 74 TESTSIU I This pin allows external logic to initiate read or write transactions to PR31100 registers. The TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and /DGRNT), then external logic can initiate read and write transactions to PR31100 registers. This pin is used for debugging purposes only. 71 TESTCPU I This pin allows numerous internal CPU core signals to be brought to external PR31100 pins, in place of the normal signals assigned to these pins. The CPU core signals assigned to their respective pins during TESTCPU mode are vendor–dependent. The TESTCPU mode is enabled by asserting this TESTCPU signal, and this function is provided for generating test vectors for the CPU core. This pin is used for debugging purposes only. 72 TESTIN I This pin is reserved for vendor–dependent use. This pin is used for debugging purposes only. 73 TESTOUT O This pin is reserved for vendor–dependent use. This pin is used for debugging purposes only. Spare Pins NC4–1 No Connect These pins are reserved for future use and should be left unconnected. Power Supply Pins VDD (34 each) +3.3V These pins are the power pins for PR31100 and should be connected to the digital +3.3V power supply VSTANDBY. VSS (34 each) GND These pins are the ground pins for PR31100 and should be connected to digital ground. NOTE: For some vendor–dependent implementations of PR31100, pin 131 may be used for a filter capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground).

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 12

ELECTRICAL CHARACTERISTICS

VSS = 0V SYMBOL PARAMETER LIMITS UNIT VDD Power supply voltage VSS – 0.5 to 4.5 V VIN Input voltage VSS – 0.5 to VDD + 0.5 V Tstg Storage temperature range –55 to +125 °C Pd Maximum dissipation (Tamb = 70°C) 1 W RECOMMENDED OPERATING CONDITION VSS = 0V SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN TYP MAX UNIT VDD Power supply voltage 3.0 3.3 3.6 V VIN Input voltage VSS – VDD V Topr Operating temperature range 0 – 70 °C DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V. SYMBOL PARAMETER CONDITIONS LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT IDD Operating current VIN = VDD or VSS ; VDD = MAX IOH = IOL = 0 – 110 TBD mA IDDS Static current VIN = VDD or VSS ; VDD = MAX IOH = IOL = 0 – 50 100 µA IL Input leakage current VDD = MAX; VIH = VDD VIL = VSS –10 – 10 µA VIH1 High level input voltage1 VDD = 3.6V VDD × 0.8 – VDD + 0.3 V VIL1 Low level input voltage1 VDD = 3.0V –0.3 – VDD × 0.2 V VIH2 High level input voltage2 VDD = 3.6V 2.4 – VDD + 0.3 V VIL2 Low level input voltage2 VDD = 3.0V –0.3 – 0.6 V VOH1 High level output voltage3 VDD = 3.0; IOH = –4mA VDD – 0.6 – – V VOL1 Low level output voltage3 VDD = 3.0; IOL = 4mA – – VSS + 0.4 V VOH2 High level output voltage4 VDD = 3.0; IOH = –8mA VDD – 0.6 – – V VOL2 Low level output voltage4 VDD = 3.0; IOL = 8mA – – VSS + 0.4 V VOH3 High level output voltage5 VDD = 3.0; IOH = –16mA VDD – 0.6 – – V VOL3 Low level output voltage5 VDD = 3.0; IOL = 16mA – – VSS + 0.4 V VOH4 High level output voltage6 VDD = 3.0; IOH = –24mA VDD – 0.6 – – V VOL4 Low level output voltage6 VDD = 3.0; IOL = 24mA – – VSS + 0.4 V IOZ Off-state leakage current VDD = MAX; VOH = VDD; VOL = VSS TBD – TBD µA NOTES: 1. SYSVLKIN 2. Other inputs 3. D[31:0], /RAS0, /RAS1, /DCS0, /DCKE, DQMH, DQML, /DREQ, /DGRNT , BC32K, VDAT[3:0], CP , LOAD, DF, FRAME, DISPON, VIDDONE, PWRCS, TXD, RXD, /CS0∼3, /MCS0∼3, CHIFS, CHICLK, CHIDOUT, CHIDIN, IO[6:0], SPICLK, SPIOUT , SPIIN, SIBSYNC, SIBOUT , SIBMCLK, SIBCLK, RXPWR, IROUT , /CRAD1WAIT, /CARD2WAIT, MIOX[2:0] 4. A[12:], ALE, /RD, /WE /SAS0∼3, /CARDREG, /IOWR, /CARD1CSL, /CARD1CSH, /CARD2CSL, /CARD2CSH 5. DCLKOUT 6. MBUSCLK, MBUSDATA

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 13

AC ELECTRICAL CHARACTERISTICS PR31100 TIMING – DEFINITION OF AC SPECIFICATION 0.8V 2.0V DELAY SETUP HOLD 2.2V 0.8V 2.2V 0.8V 2.2V 0.8VOUTPUTS INPUTS 0.8VCC 0.2VCC

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 14

Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNITITEM PARAMETER RISING/FALLING MIN MAX UNIT

1 DCLKOUT high time – 5 – ns

2 DCLKOUT low time – 5 – ns

3 DCLKOUT period – 12.5 – ns

4 Delay DCLKOUT to ALE

Rising – 4 ns Falling – 3 ns

4 Delay DCLKOUT to A[12:0] – – 8 ns

4 Delay DCLKOUT to D[31:16] – – 8 ns

4 Delay DCLKOUT to D[15:0] – 1.5 8 ns

4 Delay DCLKOUT to /CS3–0

Rising – 10 ns Falling – 10 ns

4 Delay DCLKOUT to /RD

Risng – 8 ns Falling – 7 ns

4 Delay DCLKOUT to /WE

Rising – 5 ns Falling – 4 ns

4 Delay DCLKOUT to /SAS3–0

Rising – 1.5 ns Falling – 1.5 ns

4 Delay DCLKOUT to /CARDxCSx

Rising – 9 ns Falling – 8 ns

4 Delay DCLKOUT to /CARDDIR

Rising – 12 ns Falling – 11 ns

4 Delay DCLKOUT to /CARDREG

Rising – 9 ns Falling – 10 ns

4 Delay DCLKOUT to /IORD

Rising – 10 ns Falling – 9 ns

4 Delay DCLKOUT to /IOWR

Rising – 9 ns Falling – 9 ns

4 Delay DCLKOUT to /RAS0

Rising – 6 ns Falling – 6 ns

4 Delay DCLKOUT to /RAS1

Rising 1.5 8 ns Falling 1.5 9 ns

4 Delay DCLKOUT to DQMH/L

Rising 1.5 8 ns Falling 1.5 9 ns

4 Delay DCLKOUT to /DCS0

Rising 1.5 7 ns Falling 1.5 6 ns

4 Delay DCLKOUT to DCKE

Rising 1.5 8 ns Falling 1.5 8 ns

4 Delay DCLKOUT to /MCS3–0

Rising – 10 ns Falling – 10 ns

5 D[31:16] to DCLKIN Setup time – 2 – ns

6 D[31:16] to DCLKIN Hold time – 1 – ns

5 D[15:0] to DCLKIN Setup time – 1 – ns

6 D[15:0] to DCLKIN Hold time – 1.5 – ns

7 DCLKOUT to DCLKIN Board Delay time – 0 3 ns

1996 Aug 07 15

Figure 1. Memory Output and Clock Timing Figure 2. Memory Input Timing Figure 3. DCLKOUT to DCLKIN

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 16

Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNITITEM PARAMETER RISING/FALLING MIN MAX UNIT

1 CHICLK high time – 100 – ns

2 CHICLK low time – 100 – ns

3 CHICLK period – 225 – ns

4 Delay CHICLK Rising to CHIDOUT (Master)

Rising – 5 ns Falling – 5 ns

7 Delay CHICLK Falling to CHIDOUT (Master)

Rising – 5 ns Falling – 5 ns

4 Delay CHICLK Rising to CHIFS (Master)

Rising – 5 ns Falling – 5 ns

7 Delay CHICLK Falling to CHIFS (Master)

Rising – 5 ns Falling – 5 ns

4 Delay CHICLK Rising to CHIDOUT (Slave)

Rising – 10 ns Falling – 10 ns

7 Delay CHICLK Falling to CHIDOUT (Slave)

Rising – 10 ns Falling – 10 ns

4 Delay CHICLK Rising to CHIFS (Slave)

Rising – 10 ns Falling – 10 ns

7 Delay CHICLK Falling to CHIFS (Slave)

Rising – 10 ns Falling – 10 ns

5 CHIDIN to CHICLK Rising Setup time (Master) – 20 – ns

6 CHIDIN to CHICLK Rising Hold time (Master) – 20 – ns

8 CHIDIN to CHICLK Falling Setup time (Master) – 20 – ns

9 CHIDIN to CHICLK Falling Hold time (Master) – 20 – ns

5 CHIFS to CHICLK Rising Setup time (Slave) – 20 – ns

6 CHIFS to CHICLK Rising Hold time (Slave) – 20 – ns

8 CHIFS to CHICLK Falling Setup time (Slave) – 20 – ns

9 CHIFS to CHICLK Falling Hold time (Slave) – 20 – ns

5 CHIDIN to CHICLK Rising Setup time (Slave) – 20 – ns

6 CHIDIN to CHICLK Rising Hold time (Slave) – 20 – ns

8 CHIDIN to CHICLK Falling Setup time (Slave) – 20 – ns

9 CHIDIN to CHICLK Falling Hold time (Slave) – 20 – ns

1996 Aug 07 17

Figure 4. CHI Output and Clock Timing (CHITXEDGE = 1) Figure 5. CHI Input Timing (CHIRXEDGE = 1) Figure 6. CHI Output and Clock Timing (CHITXEDGE = 0) Figure 7. CHI Input Timing (CHIRXEDGE = 0)

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 18

Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNITITEM PARAMETER RISING/FALLING MIN MAX UNIT

1 MBUSCLK high time – 10 – ns

2 MBUSCLK low time – 10 – ns

3 MBUSCLK period – 25 – ns

4 Delay MSBUSCLK Rising to MBUSDATA (Master)

Rising – 2 ns Falling – 2 ns

7 Delay MSBUSCLK Falling to MBUSDATA (Master)

Rising – 2 ns Falling – 2 ns

5 MBUSDATA to MBUSCLK Rising Setup time (Slave) – 4 – ns

6 MBUSDATA to MBUSCLK Rising Hold time (Slave) – 5 – ns

8 MBUSDAT A to MBUSCLK Falling Setup time (Slave) – 4 – ns

9 MBUSDAT A to MBUSCLK Falling Hold time (Slave) – 5 – ns

1996 Aug 07 19

Figure 8. Magic Bus Output and Clock Timing (Master, PHAPOL = 1) Figure 9. Magic Bus Input Timing (Slave, RCVPHAPOL = 0) Figure 10. Magic Bus Output and Clock Timing (Master, PHAPOL = 0) Figure 11. Magic Bus Input Timing (Slave, RCVPHAPOL = 1)

1996 Aug 07 20

1 SIBMCLK high time – 20 – ns

2 SIBMCLK low time – 20 – ns

3 SIBMCLK period – 50 – ns

4 Delay SIBMCLK to SIBSCLK Rising – 5 ns

5 Delay SIBMCLK to SIBSCLK Falling – 5 ns

6 Delay SIBSCLK Rising to SIBSYNC

6 Delay SIBSCLK Rising to SIBDOUT

7 SIBDIN to SIBSCLK Rising Setup time – 20 – ns

8 SIBDIN to SIBSCLK Rising Hold time – 0 – ns

Figure 12. SIB CLK Timing Figure 13. SIB Timing

1996 Aug 07 21

1 SPIMCLK high time – 120 – ns

2 SPICLK low time – 120 – ns

3 SPICLK period – 250 – ns

4 Delay SPICLK Rising to SPIOUT Rising – ns

4 Delay SPICLK Rising to SPIOUT Falling – ns

7 Delay SPICLK Falling to SPIOUT Rising – ns

7 Delay SPICLK Falling to SPIOUT Falling – ns

8 SPIIN to SPICLK Rising Setup time – 15 – ns

9 SPIIN to SPICLK Rising Hold time – 15 – ns

5 SPIIN to SPICLK Falling Setup time – 15 – ns

6 SPIIN to SPICLK Falling Hold time – 15 – ns

Figure 14. SPI Timing (PHAPOL = 1) Figure 15. SPI Timing (PHAPOL = 0)

1996 Aug 07 22

1 LOAD Pulse width – 100 1600 ns

2 Delay LOAD Falling to FRAME – 100 3200 ns

3 Delay LOAD Falling to DF – 100 3200 ns

4 Delay LOAD Falling to CP – 100 3200 ns

5 Delay CP Rising to VDAT[3:0] – – 3 ns

6 VDAT to CP Rising Setup – 15 25 ns

7 VDAT to CP Rising Hold – 15 25 ns

Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers. Figure 16. Video Timing, 4 Bit Non-Split LCD Figure 17. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 23

Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNITITEM PARAMETER RISING/FALLING MIN MAX UNIT

1 VSTANDBY to /PON Rising – 50 – ns

2 VSTANDBY to ONBUTN delay time – 2 – s

/PON Figure 18. CPU RESET Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNITITEM PARAMETER RISING/FALLING MIN MAX UNIT 1 /CPURES low time – 10 – ns /CPURES Figure 19.

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 24

LQFP208: 208-PIN PLASTIC LOW PROFILE QUAD FLAT PACKAGE 30.00 28.00 EJECTOR MARK 156 157 105 104 C 1.0 208

1 INDEX MARK

0.20 0.50 0.15 0.625 0.625 (1.40) R0.2 R 0.2 0.50 0.10 0.15 (28.80) (29.00) UNIT = mm (Drawing not to scale)

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor

1996 Aug 07 25

Philips Semiconductors Preliminary specification MIPS PR31100Highly integrated embedded processor Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.