PQFP100

ST92F124_06 STMICROELECTRONICS | Alldatasheet

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Rev. 5 ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMIL Y WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD ■ Memories – Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulat- ed EEPROM) – In-Application Programming (IAP) – 224 general purpose registers (register file) availa- ble as RAM, accumulators or index pointers ■ Clock, Reset and Supply Management – Register-oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP modes – 0-24 MHz Operation (Int . Clock), 4.5-5.5 V range – PLL Clock Generator (3-5 MHz crystal) – Minimum instruction time: 83 ns (24 MHz int. clock) ■ Up to 80 I/O pins ■ Interrupt Management – 4 external fast interrupts + 1 NMI – Up to 16 pins programmable as wake-up or addition- al external interrupt with multi-level interrupt handler ■ DMA controller for reduced processor overhead ■ Timers – 16-bit Timer with 8-bit Prescaler, and Watchdog Tim- er (activated by software or by hardware) – 16-bit Standard Timer that can be used to generate a time base independent of PLL Clock Generator – Two 16-bit independent Extended Function Timers (EFTs) with Prescaler, up to two Input Captures and up to two Output Compares – Two 16-bit Multifunction Timers, with Prescaler, up to two Input Captures and up to two Output Com- pares ■ Communication Interfaces – Serial Peripheral Interfac e (SPI) with Selectable Master/Slave mode – One Multiprotocol Serial Communications Interface with asynchronous and synchronous capabilities – One asynchronous Serial Communications Interface with 13-bit LIN Synch Break generation capability – J1850 Byte Level Protocol Decoder (JBLPD) – Up to two full I²C multiple Master/Slave Interfaces supporting Access Bus – Up to two CAN 2.0B Active interfaces ■ Analog peripheral (low current coupling) – 10-bit A/D Converter with up to 16 robust input chan- nels ■ Development Tools – Free High performance Development environment (IDE) based on Visual Debugger, Assembler, Linker, and C-Compiler; Real Time Operating System (OS- EK OS, CMX) and CAN drivers – Hardware Emulator and Flash Programming Board for development and ISP Flasher for production DEVICE SUMMARY 2) 1) see Section 12.4 on page 407 for important information 2) see Table 71 on page 404 for the list of supported part numbers PQFP100 14x20 LQFP64 14x14 LQFP100 14x14 Features ST92F124R9/1 ST92F124V1 ST92F150CR9/1 ST92F150CV9/1 ST92F150JDV1 ST92F250CV2 FLASH - bytes 64K/128K 128K 64K/128K 64K/128K 128K 256K RAM - bytes 2K/4K 4K 2K/4K 2K/4K 6K 8K E

3 TM - bytes 1K 1K 1K 1K 1K 1K

2 MFT, 2 EFT,

STIM, WD, SCI, SPI, I²C STIM, WD,

2 SCI, SPI, I²C

STIM, WD, SCI, SPI, I²C STIM, WD, STIM, WD, STIM, WD, 2 SCI, SPI, 2 I²C ADC 16 x 10 bits 16 x 10 bits 16 x 10 bits 16 x 10 bits 16 x 10 bits 16 x 10 bits Network Inter- face - LIN Master CAN CAN, LIN Master 2 CAN,J1850, LIN Master CAN, LIN Master

13.7 MFT DMA MASK BIT RESET WHEN MFT0 DMA PRIORITY LEVEL IS SET TO 0 . . . 419

ST92F124/F150/F250 - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92F124/F150/F250 microcontroller is de- veloped and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast con- text switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical applicatio n tasks to get the maxi- mum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power- efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Inter- rupt and DMA controller, and the Memory Man- agement Unit. The MMU allows a single linear ad- dress space of up to 4 Mbytes. Four independent buses are controlled by the Core: a 22-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as ac- cumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. The powerful I/O capabilities demanded by micro- controller applications are fulfilled by the ST92F150/F124 with 48 (64-pin devices) or 77 (100-pin devices) I/O lines dedicated to digital In- put/Output and with 80 I/O lines by the ST92F250. These lines are grouped into up to ten 8-bit I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, an address/data bus for interfacing to the external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O. Two memory spaces are available to support this wide range of configurations: a combined Program/ Data Memory Space and the internal Register File, which includes the control and status registers of the on-chip peripherals.

1.1.2 External Memory Interface

100-pin devices have a 22-bit external address bus allowing them to address up to 4M bytes of ex- ternal memory.

1.1.3 On-chip Peripherals

Two 16-bit Multifunction Timers, each with an 8 bit Prescaler and 12 operating modes allow simple use for complex waveform generation and meas- urement, PWM functions and many other system timing functions by the usage of the two associat- ed DMA channels for each timer. Two Extended Function Timers provide further timing and signal generation capabilities. A Standard Timer can be used to generate a sta- ble time base independent from the PLL. An I 2C interface (two in the ST92F250 device) pro- vides fast I2C and Access Bus support. The SPI is a synchronous serial interface for Mas- ter and Slave device communication. It supports single master and multimaster systems. A J1850 Byte Level Protocol Decoder is available (ST92F150JDV1 device only) for communicating with a J1850 network. The bxCAN (basic extended) interface (two in the ST92F150JDV1 device) supports 2.0B Active pro- tocol. It has 3 transmit mailboxes, 2 independent receive FIFOs and 8 filters. In addition, there is an 16 channel Analog to Digital Converter with integral sample and hold, fast con- version time and 10-bit resolution. There is one Multiprotocol Serial Communications Interface with an integral generator, asynchronous and synchronous capabilit y (fully programmable format) and associated address/wake-up option, plus two DMA channels. On 100-pin devices, there is an additional asyn- chronous Serial Communications interface with 13-bit LIN Synch Break generation capability. Finally, a programmable PLL Clock Generator al- lows the usage of standard 3 to 5 MHz crystals to obtain a large range of internal frequencies up to 24 MHz. Low power Run (SLOW), Wait For Inter- rupt, low power Wait For Interrupt, STOP and HALT modes are also available.

Figure 1. ST92F124R9: Architectural Block Diagram

2 Kbytes

64 Kbytes

1 Kbyte

Figure 2. ST92F124V1: Architectural Block Diagram

4 Kbytes

128 Kbytes

Figure 3. ST92F150C(R/V)1/9: Architectural Block Diagram

• Not available on 64-pin version.

Figure 4. ST92F150JDV1: Architectural Block Diagram

6 Kbytes

Figure 5. ST92F250CV2: Architectural Block Diagram

8 Kbytes

256 Kbytes

ST92F124/F150/F250 - GENERAL DESCRIPTION

1.2 PIN DESCRIPTION

AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (RW ), and Data signals are valid for memory transfers. DS. Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS . During a read cycle, Data In must be valid pri- or to the trailing edge of DS . When the ST9 ac- cesses on-chip memory, DS is held high during the whole memory cycle. RESET. Reset (input, active low). The ST9 is ini- tialised by the Reset sign al. With the deactivation of RESET , program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. RW . Read/Write (output, 3-state). Read/Write de- termines the direction of data transfer for external memory transactions. RW is low when writing to external memory, and high for all other transac- tions. OSCIN, OSCOUT. Oscillator (inp ut and output). These pins connect a parallel-resonant crystal, or an external source to th e on-chip clock oscillator and buffer. OSCIN is the input of the oscillator in- verter; OSCOUT is the outp ut of the oscillator in- verter. HW0SW1. When connected to V DD through a 1K pull-up resistor, the software watchdog option is selected. When connected to V SS through a 1K pull-down resistor, the hardware watchdog option is selected. VPWO. This pin is the output line of the J1850 pe- ripheral (JBLPD). It is available only on some de- vices. RX1/WKUP6. Receive Data input of CAN1 and Wake-up line 6. Available only on some devices. When the CAN1 peripheral is disabled, a pull-up resistor is connected internally to this pin. TX1. Transmit Data output of CAN1. Available on some devices. P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or CMOS compatible). 11 lines (64-pin devices) or 22 lines (100-pin devices) providing the external memory interface for addressing 2K or 4M bytes of external memory. P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/ Output, TTL or CMOS compatible) . I/O lines grouped into I/O ports of 8 bits, bit programmable under software control as general purpose I/O or as alternate functions. Additional I/O Port Lines available on 100-pin ver- sions only. P3.0, P6[7:6] Additional I/O Port Lines available on ST92F250 version only. AV DD. Analog VDD of the Analog to Digital Con- verter (common for ADC 0 and ADC 1). AVDD can be switched off when the ADC is not in use. AV SS. Analog V SS of the Analog to Digital Con- verter (common for ADC 0 and ADC 1). VDD. Main Power Supply Voltage. Four pins are available on 100-pin versions, two on 64-pin ver- sions. The pins are internally connected. VSS. Digital Circuit Ground. Four pins are availa- ble on 100-pin versions, two on 64-pin versions. The pins are internally connected. VTEST Power Supply Voltage for Flash test pur- poses. This pin must be kept to 0 in user mode. VREG. Stabilization capacitors for the internal volt- age regulator. The user must connect external sta- bilization capacitors to these pins. Refer to Figure 16.

1.2.1 I/O Port Alternate Functions

Each pin of the I/O ports of the ST92F124/F150/ F250 may assume software programmable Alter- nate Functions as shown in Section 1.4.

1.2.2 Termination of Unused Pins

For unused pins, input mode is not recommended. These pins must be kept at a fixed voltage using the output push pull mode of the I/O or an external pull-up or pull-down resistor.

Figure 6. ST92F124R9/R1: Pin Configuration (Top-view LQFP64)

Figure 7. ST92F124V1: Pin Configuration (Top-view PQFP100)

• VTEST must be kept low in standard operating mode.

Figure 8. ST92F124V1: Pin Configuration (Top-view LQFP100)

• VTEST must be kept low in standard operating mode.

Figure 9. ST92F150: Pin Configuration (Top-view LQFP64) ** VTEST must be kept low in standard operating mode.

Figure 10. ST92F150C: Pin Configuration (Top-view PQFP100)

• VTEST must be kept low in standard operating mode.

Figure 11. ST92F150JD: Pin Configuration (Top-view PQFP100)

• VTEST must be kept low in standard operating mode.

Figure 12. ST92F150C: Pin Configuration (Top-view LQFP100)

• VTEST must be kept low in standard operating mode.

Figure 13. ST92F150JD: Pin Configuration (Top-view LQFP100)

• VTEST must be kept low in standard operating mode.

Figure 14. ST92F250: Pin Configuration (Top-view PQFP100)

• VTEST must be kept low in standard operating mode.

Figure 15. ST92F250: Pin Configuration (Top-view LQFP100)

• VTEST must be kept low in standard operating mode.

Table 1. ST92F124/F150/F250 Power Supply Pins Table 2. ST92F124/F150/F250 Primary Function Pins

1.3 VOLTAGE REGULATOR

age regulator and a Low-power regulator. the serial inductance to less than 60nH. Figure 16. Recommended Connections for V IMPORTANT: The VREG pin cannot be used to drive external devices. Figure 17. Minimum Required Connections for VREG work can also be connected to these pins. L = Ferrite bead for EMI protection. Suggested type: Murata BLM18BE601FH1: (Imp. 600 Ω at 100 MHz).

1.4 I/O PORTS

used or programmed as bidirectional. by programming the relevant PxC2.n control bit. are implemented: Standard and High Hysteresis. present on ports P4[7:6] and P6[5:4]. DD+0.3 Volt, to avoid direct junction biasing. Table 3. I/O Port Characteristics Legend: WPU = Weak Pull-Up, OD = Open Drain.

ST92F124/F150/F250 - GENERAL DESCRIPTION Note 1: Port 3.0 and Port6 [7:6] present on ST92F250 version only. How to Configure the I/O Ports To configure the I/O ports, use the information in Table 3, Table 4 and the Port Bit Configuration Ta- ble in the I/O Ports Chapter (See page 153). Input Note = the hardware characteristics fixed for each port line in Table 3. – If Input note = TTL/CMOS, either TTL or CMOS input level can be selected by software. – If Input note = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger. Alternate Functions (AF) = More than one AF cannot be assigned to an I/O pin at the same time: An alternate function can be selected as follows. AF Inputs: – AF is selected implicitly by enabling the corre- sponding peripheral. Exception to this are ADC inputs which must be explicitly selected as AF in- put by software. AF Outputs or Bidirectional Lines: – In the case of Outputs or I/Os, AF is selected ex- plicitly by software. Example 1: SCI-M input AF: SIN, Port: P5.2. Schmitt Trigger input. Write the port configuration bits: P5C2.2=1 P5C1.2=0 P5C0.2 =1 Enable the SCI peripheral by software as de- scribed in the SCI chapter. Example 2: SCI-M output AF: SOUT, Port: P5.3, Push-Pull/OD output. Write the port configuration bits (for AF OUT PP): P5C2.3=0 P5C1.3=1 P5C0.3 =1 Example 3: External Memory I/O AF: A0/D0, Port : P0.0, Input Note: TTL/CMOS in- put. Write the port configuration bits: P0C2.0=1 P0C1.0=1 P0C0.0 =1 Example 4: Analog input AF: AIN8, Port : 7.0, Analog input. Write the port configuration bits: P7C2.0=1 P7C1.0=1 P7C0.0 =1

1.5 Alternate Functions for I/O Ports

All the ports in the following table are useable for general purpose I/O (input, output or bidirectional). Table 4. I/O Port Alternate Functions

ST92F124/F150/F250 - GENERAL DESCRIPTION P2.5 23 38 35 TINPB1 I Multifunction Timer 1 - Input B P2.6 24 39 36 TOUTA1 O Multifunction Timer 1 - Output A P2.7 25 40 37 TOUTB1 O Multifunction Timer 1 - Output B P3.0 2) -7 37 0 P3.1 - 24 21 ICAPB0 I Ext. Timer 0 - Input Capture B P3.2 - 25 22 ICAPA0 I Ext. Timer 0 - Input Capture A OCMPA0 O Ext. Timer 0 - Output Compare A P3.3 - 26 23 OCMPB0 O Ext. Timer 0 - Output Compare B P3.4 - 27 24 EXTCLK0 I Ext. Timer 0 - Input Clock SS I SPI - Slave Select P3.5 14 28 25 MISO I/O SPI - Mast er Input/Slave Output Data P3.6 15 29 26 MOSI I/O SPI - Master Output/Slave Input Data P3.7 16 30 27 SCK I SPI - Serial Input Clock WKUP0 I Wake-up Line 0 SCK O SPI - Serial Output Clock P4.0 - 14 11 ICAPA1 I Ext. Timer 1 - Input Capture A P4.1 - 15 12 CLOCK2 O CLOCK2 internal signal P4.2 - 16 13 OCMPA1 O Ext. Timer 1 - Output Compare A P4.3 - 19 16 ICAPB1 I Ext. Timer 1 - Input Capture B OCMPB1 O Ext. Timer 1 - Output Compare B P4.4 - 20 17 EXTCLK1 I Ext. Timer 1 - Input Clock WKUP4 I Wake-up Line 4 P4.5 10 21 18 EXTRG I ADC Ext. Trigger STOUT O Standard Timer Output P4.6 11 22 19 SDA0 I/O I 2C 0 Data P4.7 12 23 20 WKUP1 I Wake-up Line 1 SCL0 I/O I 2C 0 Clock P5.0 1 6 3 WAIT I External Wait Request WKUP5 I Wake-up Line 5 TX0 2) O CAN 0 output P5.1 2 7 4 WKUP6 I Wake-up Line 6 RX0 2) I CAN 0 input WDOUT O Watchdog Timer Output P5.2 3 8 5 SIN0 I SCI-M - Serial Data Input WKUP2 I Wake-up Line 2 P5.3 4 9 6 WDIN I Watchdog Timer Input SOUT O SCI-M - Serial Data Output Port Name Pin No. Alternate Functions LQFP64 PQFP100 LQFP100

ST92F124/F150/F250 - GENERAL DESCRIPTION P5.4 5 10 7 TXCLK I SCI-M - Transmit Clock Input CLKOUT O SCI-M - Clock Output P5.5 6 11 8 RXCLK I SCI-M - Receive Clock Input WKUP7 I Wake-up Line 7 P5.6 7 12 9 DCD I SCI-M - Data Carrier Detect WKUP8 I Wake-up Line 8 P5.7 8 13 10 WKUP9 I Wake-up Line 9 RTS O SCI-M - Request To Send P6.0 43 67 64 INT0 I External Interrupt 0 INT1 I External Interrupt 1 CLOCK2/8 O CLOCK2 divided by 8 P6.1 - 68 65 INT6 I External Interrupt 6 RW O Read/Write P6.2 44 69 66 INT2 I External Interrupt 2 INT4 I External Interrupt 4 DS2 O Data Strobe 2 P6.3 45 70 67 INT3 I External Interrupt 3 INT5 I External Interrupt 5 P6.4 46 71 68 NMI I Non Maskable Interrupt P6.5 47 72 69 WKUP10 I Wake-up Line 10 VPWI 2) I JBLPD input INTCLK O Internal Main Clock P6.62) -4 94 6 P6.72) -5 04 7 P7.0 51 84 81 AIN8 I Analog Data Input 8 CK_AF I Clock Alternative Source P7.1 52 85 82 AIN9 I Analog Data Input 9 P7.2 53 86 83 AIN10 I Analog Data Input 10 P7.3 54 87 84 AIN11 I Analog Data Input 11 P7.4 55 88 85 WKUP3 I Wake-up Line 3 AIN12 I Analog Data Input 12 P7.5 56 89 86 AIN13 I Analog Data Input 13 WKUP11 I Wake-up Line 11 P7.6 57 90 87 AIN14 I Analog Data Input14 WKUP12 I Wake-up Line 12 P7.7 58 91 88 AIN15 I Analog Data Input 15 WKUP13 I Wake-up Line 13 Port Name Pin No. Alternate Functions LQFP64 PQFP100 LQFP100

ST92F124/F150/F250 - GENERAL DESCRIPTION Note1: The ST92F150-EMU2 emulator does not emulate ADC channels from AIN0 to AIN7 and ex- tended function timers because they are not imple- mented on the emulator chip. See also Section 13.8 on page 423. Note 2: Available on some devices only. Note 3: For the ST92F250 device, since A[18:17] share the same pins as SDA1 and SCL1 of I²C_1, these address bits are not available when the I²C_1 is in use (when I2CCR.PE bit is set). P8.0 - 74 71 AIN0 I Analog Data Input 0 WKUP14 I Wake-up Line 14 P8.1 - 75 72 AIN1 I Analog Data Input 1 WKUP15 I Wake-up Line 15 P8.2 - 76 73 AIN2 I Analog Data Input 2 P8.3 - 77 74 AIN3 I Analog Data Input 3 P8.4 - 78 75 AIN4 I Analog Data Input 4 P8.5 - 79 76 AIN5 I Analog Data Input 5 P8.6 - 80 77 AIN6 I Analog Data Input 6 P8.7 - 81 78 AIN7 I Analog Data Input 7 P9.0 - 98 95 RDI 2) I SCI-A Receive Data Input P9.1 - 99 96 TDO 2) O SCI-A Transmit Data Output P9.2 - 100 97 A16 O Address bit 16 P9.3 - 1 98 A17 3) O Address bit 17 SDA12) I/O I²C 1 Data P9.4 - 2 99 A18 3) O Address bit 18 SCL12) I/O I²C 1 Clock P9.5 - 3 100 A19 O Address bit 19 P9.6 - 4 1 A20 O Address bit 20 P9.7 - 5 2 A21 O Address bit 21 Port Name Pin No. Alternate Functions LQFP64 PQFP100 LQFP100

ST92F124/F150/F250 - GENERAL DESCRIPTION

1.6 OPERATING MODES

To optimize the performance versus the power consumption of the device, the ST92F124/F150/ F250 supports different operating modes that can be dynamically selected depending on the per- formance and functionality requirements of the ap- plication at a given moment. RUN MODE: This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). SLOW MODE: Power consumption can be signifi- cantly reduced by running the CPU and the pe- ripherals at reduced clock speed using the CPU Prescaler and CCU Clock Divider. WAIT FOR INTERRUPT MODE: The Wait For In- terrupt (WFI) instruction suspends program exe- cution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the pe- ripheral and interrupt controller keep running at a frequency depending on the CCU programming. LOW POWER WAIT FOR INTERRUPT MODE : Combining SLOW mode and Wait For Interrupt mode it is possible to reduce the power consump- tion by more than 80%. STOP MODE : When the STOP is requested by executing the STOP bit writing sequence (see dedicated section on Wake-up Management Unit paragraph), and if NMI is kept low, the CPU and the peripherals stop operating. Operations resume after a wake-up line is activated (16 wake-up lines plus NMI pin). See the RCCU and Wake-up Man- agement Unit paragraphs in the following for the details. The difference with the HALT mode con- sists in the way the CPU exits this state: when the STOP is executed, the status of the registers is re- corded, and when the system exits from the STOP mode the CPU continues the execution with the same status, without a system reset. When the MCU enters STOP mode the Watchdog stops counting. After the MCU exits from STOP mode, the Watchdog resumes counting from where it left off. When the MCU exits from STOP mode, the oscil- lator, which was sleeping too, requires about 5 ms to restart working proper ly (at a 4 MHz oscillator frequency). An internal counter is present to guar- antee that all operations after exiting STOP Mode, take place with the clock stabilised. The counter is active only when the oscillation has already taken place. This means that 1-2 ms must be added to take into account the first phase of the oscillator restart. In STOP mode, the oscillator is stopped. There- fore, if the PLL is used to provide the CPU clock before entering STOP mode, it will have to be se- lected again when the MCU exits STOP mode. HALT MODE: When executing the HALT instruc- tion, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode.

2 DEVICE ARCHITECTURE

2.1 CORE ARCHITECTURE

2.2 MEMORY SPACES

2.2.1 Register File

to Group F (R240 to R255), see Figure 20. Figure 18. Single Program and Data Memory Address Space

Figure 19. Register Groups Figure 20. Page Pointer for Group F mapping Figure 21. Addressing the Register File

64 PAGES

2.2.2 Register Addressing

dressed in Working Register mode. third register of page 5 (R242). Table 5. Register File Organization

2.3 SYSTEM REGISTERS

description of the PORT[5:0] Data registers. Table 6. System Registers (Group E)

2.3.1 Central Interrupt Control Register

tailed description of the ST9 interrupt philosophy. Bit 7 = GCEN: Global Counter Enable. then this bit has no effect. Bit 6 = TLIP: Top Level Interrupt Pending. Bit 5 = TLI: Top Level Interrupt bit. on the TLNM bit in the NICR Register. (described in the Interrupt chapter). Bit 4 = IEN: Interrupt Enable . operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. Bit 3 = IAM: Interrupt Arbitration Mode. Bits 2:0 = CPL[2:0]: Current Priority Level. stored until required in the NICR register.

ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d)

2.3.2 Flag Register

The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h) Bit 7 = C: Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate ( rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Com- plement Carry Flag (ccf) instruction. Bit 6 = Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc , rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical ( and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec, decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. Bit 5 = S: Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 = V: Overflow Flag. The Overflow flag is affected by the same instruc- tions as the Zero and Sign flags. When set, the Overflow flag indicates that a two's- complement number, in a re sult register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in two’s-complement notation. Bit 3 = DA: Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust ( da) operation can perform its function correctly. The DA flag cannot normally be used as a test condi- tion by the programmer. Bit 2 = H: Half Carry Flag. The H flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust ( da) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 = DP: Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory ( sdm) and Set Program Memory ( spm) instructions. Re- fer to the Memory Management Unit for further de- tails. C Z S V DA H - DP

ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note: In the current ST9 devices, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redun- dant. It must be kept to 1 with a Sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers.

2.3.3 Register Pointing Techniques

Two registers within the System register group, are used as pointers to the working registers. Reg- ister Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. The Set Register Po inter instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. The block number should always be an even number in single 16-register mode. The 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3 will be interpreted as srp #2 and will al- In single 16-register mode, the working registers are referred to as r0 to r15 . In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form “Rxxx”.

ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-re gister mode it indicates the 8-register block to which r0 to r7 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. The bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero. POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) This register is only used in the twin register point- ing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. The bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero. RG4 RG3 RG2 RG1 RG0 RPS 0 0 RG4 RG3 RG2 RG1 RG0 RPS 0 0

ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d)

2.3.4 Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers depends on the pe- ripherals present in the specific ST9 device. In oth- er words, pages only exist if the relevant peripher- al is present. The paged registers are addressed using the nor- mal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. Th is register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the in- terrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh) Bits 7:2 = PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. Bits 1:0: Reserved. Forced by hardware to 0.

2.3.5 Mode Register

The Mode Register allows control of the following operating parameters: – Selection of internal or external System and User Stack areas, – Management of the clock frequency, – Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h) Bit 7 = SSP: System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 = USP: User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (re- set state). Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2. This bit controls the divide-by-2 circuit operating on the crystal oscillator clock (CLOCK1). 0: Clock divided by 1 1: Clock divided by 2 Bits 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not availa- ble. Bit 0 = HIMP: High Impedance Enable. When a port is programmed as Address and Data lines to interface external Memory, these lines and the Memory interface cont rol lines (AS, DS, R/W) can be forced into the High Impedance state. 0: External memory interface lines in normal state 1: High Impedance state. PP5 PP4 PP3 PP2 PP1 PP0 0 0 SSP USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP

ST92F124/F150/F250 - DEVICE ARCHITECTURE Note: Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If the memory access ports are declared as an ad- dress AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines.

2.3.6 Stack Pointers

Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the “bottom” of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is “pushed” in and post-incremented when data is “popped” out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix “u”. To use a stack in- struction for a word, the suffix “w” is added. These suffixes may be combined. When bytes (or words) are “popped” out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. Thus, when data is “popped” from a stack area, the stack con- tents remain unchanged. Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. System Stack The System Stack is used for the temporary stor- age of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: – Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENCSR bit in the EMR2 register is set, then the Code Segment Register is also pushed onto the System Stack. – Subroutine Calls When a call instruction is executed, only the PC is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. – Link Instruction The link or linku instructions create a C lan- guage stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for address- ing a stack in memory. When stacking in the Reg- ister File, the User Stac k Pointer High Register, R236, becomes redundant but must be consid- ered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the sta ck is in the Register File. The upper byte must then be considered as re- served and must not be used as a general purpose register. The stack pointer registers are located in the Sys- tem Group of the Register File, this is illustrated in Table 6. Stack Location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the Register File as a stacking area. Group D is a good location for a stack in the Reg- ister File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group.

ST92F124/F150/F250 - DEVICE ARCHITECTURE

2.4 MEMORY ORGANIZATION

Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes; each seg- ment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (inter- nal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is intern al and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map.

2.5 MEMORY MANAGEMENT UNIT

may be written and read by the user program. Figure 26. Page 21 Registers

2.6 ADDRESS SPACE EXTENSION

2.6.1 Addressing 16-Kbyte Pages

Data memory space if no DMA is being performed. 22-bit address (see Figure 27). Figure 27. Addressing via DPR[3:0]

2 MSB

14 LSB

2.6.2 Addressing 64-Kbyte Segments

Three registers are used: CSR, ISR, and DMASR. given by the virtual 16-bit address (see Figure 28).

2.7 MMU REGISTERS

2.7.1 DPR[3:0]: Data Page Registers

2.7.1.1 Data Page Register Relocation

Figure 28. Addressing via CSR, ISR, and DMASR

ST92F124/F150/F250 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. Bits 7:0 = DPR0_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set. Bits 7:0 = DPR1_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh. DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set. Bits 7:0 = DPR2_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set. Bits 7:0 = DPR3_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh. DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3

ST92F124/F150/F250 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d)

2.7.2 CSR: Code Segment Register

This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are imple- mented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. CODE SEGMENT REGISTER (CSR) R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h) Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = CSR_[5:0]: These bits define the 64- Kbyte memory segment (among 64) which con- tains the code being executed. These bits are used as the most significant address bits (A21-16).

2.7.3 ISR: Interrupt Segment Register

INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined ISR and ENCSR bit (EMR2 register) are also de- scribed in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64- Kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16). The ISR is used to extend the address space in two cases: – Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. See also the Interrupts chapter. – During DMA transactions between the peripheral and memory when the PS bit of the DAPR regis- ter is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA trans- action.

2.7.4 DMASR: DMA Segment Register

DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = DMASR_[5:0]: These bits define the 64- Kbyte Memory segment (among 64) used when a DMA transaction is performed between the periph- eral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the ad- dress. 0 0 CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0 0 0 ISR_5 ISR_4 ISR_ 3I S R _ 2I S R _ 1I S R _ 0

00 DMA

SR_5 DMA SR_4 DMA SR_3 DMA SR_2 DMA SR_1 DMA SR_0

Figure 29. Memory Addressing Scheme (example)

ST92F124/F150/F250 - DEVICE ARCHITECTURE

2.8 MMU USAGE

2.8.1 Normal Program Execution

Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. Writing to the CSR is allowed when it is not be- ing used, i.e during an interrupt service routine if ENCSR is reset. Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the rou- tine is written without pr ior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-Kbyte seg- ment, then calls/rets should be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR[3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 0- 3. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of exter- nal memory, and as ports 0, 1 and 9 are required to address it, their data registers are unused.

2.8.2 Interrupts

The ISR register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENC- SR bit in the EMR2 register (R246 on Page 21). If this bit is reset (def ault condition), the CPU works in original ST9 co mpatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service rou- tines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector ta- ble and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion.

2.8.3 DMA

Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be pro- grammed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one refer- enced by the DMASR (when the PS bit is set).

3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

3.1 INTRODUCTION

used for EEPROM Hardware Emulation. by an embedded Program/Erase Controller. E3 TM can be written in blocks of 16 bytes. Figure 30. Flash Memory Structure (Example for 64K Flash device)

48 Kbytes

8 Kbytes (Reserved)

Figure 31. Flash Memory Structure (Example for 128K Flash device)

3.2 FUNCTIONAL DESCRIPTION

3.2.1 Structure

3.2.2 EEPROM Emulation

Table 7. Memory Structure for 64K Flash device Table 8. Memory Structure for 128K Flash device

Table 9. Memory Structure for 256K Flash device

3.2.3 Operation

E3 TM write operations are forbidden. (device dependent) to generate an interrupt INTx. Figure 32. Control and Status Register Map. quence is generated automatically by hardware.

3.2.4 E3 TM Update Operation

tained in the specified address. that becomes the new current one.

Figure 33. Hardware Emulation Flow

3.2.5 Important note on Flash Erase Suspend

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

3.3 REGISTER DESCRIPTION

3.3.1 Control Registers

FLASH CONTROL REGISTER (FCR) Address: 224000h / 221000h- Read/Write Reset value: 0000 0000 (00h) The Flash Control Register is used to enable all the operations for the Flash and the TestFlash memories. Bit 7 = FWMS: Flash Write Mode Start (Read/ Write). This bit must be set to start each write/erase oper- ation in Flash memory. At the end of the write/ erase operation or during a Sector Erase Suspend this bit is automatically reset. To resume a sus- pended Sector Erase operation, this bit must be set again. Resetting this bit by software does not stop the current write operation. 0: No effect 1: Start Flash write Bit 6 = FPAGE: Flash Page program (Read/Write). This bit must be set to select the Page Program operation in Flash memory. This bit is automatical- ly reset at the end of the Page Program operation. The Page Program operation allows to program “0”s in place of “1”s. From 1 to 16 bytes can be en- tered (in any order, no need for an ordered ad- dress sequence) before starting the execution by setting the FWMS bit. All the addresses must be- long to the same page (only the 4 LSBs of address can change). Data to be programmed and ad- dresses in which to program must be provided (through an LD instruction, for example). Data contained in page addresses that are not entered are left unchanged. 0: Deselect page program 1: Select page program Bit 5 = FCHIP: Flash CHIP erase (Read/Write). This bit must be set to select the Chip Erase oper- ation in Flash memory. This bit is automatically re- set at the end of the Chip Erase operation. The Chip Erase operation erases all the Flash lo- cations to FFh. The operation is limited to Flash code: sectors F0-F3 (or F0-F5 for the ST92F250), TestFlash and E3 TM excluded. The execution starts by setting the FWMS bit. It is not necessary to pre-program the sectors to 00h, because this is done automatically. 0: Deselect chip erase 1: Select chip erase Bit 4 = FBYTE: Flash byte program (Read/Write). This bit must be set to select the Byte Program op- eration in Flash memory. This bit is automatically reset at the end of the Byte Program operation. The Byte Program operation allows “0”s to be pro- grammed in place of “1”s. Data to be programmed and an address in which to program must be pro- vided (through an LD instruction, for example) be- fore starting execution by setting bit FWMS. 0: Deselect byte program 1: Select byte program Bit 3 = FSECT: Flash sector erase (Read/Write). This bit must be set to select the Sector Erase op- eration in Flash memory. This bit is automatically reset at the end of the Sector Erase operation. The Sector Erase operation erases all the Flash locations to FFh. From 1 to 6 sectors (F0-F5) can be simultaneously erased. These sectors can be entered before starting the execution by setting the FWMS bit. An address located in the sector to erase must be provided (through an LD instruc- tion, for example), while the data to be provided is don’t care. It is not necessary to pre-program the sectors to 00h, because this is done automatically. 0: Deselect sector erase 1: Select sector erase Bit 2 = FSUSP: Flash sector erase suspend (Read/Write). This bit must be set to suspend the current Sector Erase operation in Flash memory in order to read data to or from program data to a sector not being erased. The FSUSP bit must be reset (and FWMS must be set again) to resume a suspended Sector Erase operation. The Erase Suspend operation resets the Flash memory to normal read mode (automatically reset- ting bit FBUSY) in a maximum time of 15µs. 76543 210 FWMS FPAGE FCHIP FBYTE FSECT FSUSP PROT FBUSY

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) When in Erase Suspend the memory accepts only the following operations: Read, Erase Resume and Byte Program. Updating the E3 TM memory is not possible during a Flash Erase Suspend. 0: Resume sector erase when FWMS is set again. 1: Suspend Sector erase Bit 1 = PROT: Set Protection (Read/Write). This bit must be set to select the Set Protection op- eration. This bit is automatically reset at the end of the Set Protection operation. The Set Protection operation allows “0”s in place of “1”s to be programmed in the four Non Volatile Protection registers. From 1 to 4 bytes can be en- tered (in any order, no need for an ordered ad- dress sequence) before starting the execution by setting the FWMS bit. Data to be programmed and addresses in which to program must be provided (through an LD instruction, for example). Protec- tion contained in addresses that are not entered are left unchanged. 0: Deselect protection 1: Select protection Bit 0 = FBUSY: Flash Busy (Read Only). This bit is automatically set during Page Program, Byte Program, Sector Erase or Set Protection op- erations when the first address to be modified is latched in Flash memory, or during Chip Erase op- eration when bit FWMS is set. When this bit is set every read access to the Flash memory will output invalid data (FFh equivalent to a NOP instruction), while every write access to the Flash memory will be ignored. At the end of the write operations or during a Sector Erase Suspend this bit is automat- ically reset and the memory returns to read mode. After an Erase Resume this bit is automatically set again. The FBUSY bit remains high for a maxi- mum of 10 µs after Power-Up and when exiting Power-Down mode, meaning that the Flash mem- ory is not yet ready to be accessed. 0: Flash not busy 1: Flash busy E3 TM CONTROL REGISTER (ECR) Address: 224001h /221001h- Read/Write Reset value: 000x x000 (xxh) The E3 TM Control Register is used to enable all the operations for the E3 TM memory. The ECR also contains two bits (WFIS and FEIEN) that are related to both Flash and E3 TM memories. Bit 7 = EWMS: E3 TM Write Mode Start. This bit must be set to start every write/erase oper- ation in the E3 TM memory. At the end of the write/ erase operation this bit is automatically reset. Re- setting by software this bit does not stop the cur- rent write operation. 0: No effect 1: Start E3 TM write Bit 6 = EPAGE: E3 TM page update. This bit must be set to select the Page Update op- eration in E3 TM memory. The Page Update opera- tion allows to write a ne w content: both “0”s in place of “1”s and “1”s in place of “0”s. From 1 to 16 bytes can be entered (in any order, no need for an ordered address sequence) before starting the ex- ecution by setting bit EWMS. All the addresses must belong to the same page (only the 4 LSBs of address can change). Data to be programmed and addresses in which to program must be provided (through an LD instruction, for example). Data contained in page addresses that are not entered are left unchanged. This bit is automatically reset at the end of the Page Update operation. 0: Deselect page update 1: Select page update Bit 5 = ECHIP: E3 TM chip erase. This bit must be set to select the Chip Erase oper- ation in the E3 TM memory. The Chip Erase opera- tion allows to erase all the E3 TM locations to FFh. The execution starts by setting bit EWMS. This bit is automatically reset at the end of the Chip Erase operation. 0: Deselect chip erase 1: Select chip erase Bit 4:3 = Reserved. 765 4 3 2 1 0 EWMS EPAGE ECHIP WFIS FEIEN EBUSY

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) Bit 2 = WFIS: Wait For Interrupt Status. If this bit is reset, the WFI instruction puts the Flash macrocell in Stand-by mode (immediate read possible, but higher consumption: 100 µA); if it is set, the WFI instruction puts the Flash macro- cell in Power-Down mode (recovery time of 10 µs needed before reading, but lower consumption: 10µA). The Stand-by mode or the Power-Down mode will be entered only at the end of any current Flash or E3 TM write operation. In the same way following an HALT or a STOP in- struction, the Memory enters Power-Down mode only after the completion of any current write oper- ation. 0: Flash in Stand-by mode on WFI 1: Flash in Power-Down mode on WFI Note: HALT or STOP mode can be exited without problems, but the user should take care when ex- iting WFI Power Down mode. If WFIS is set, the user code must reset the XT_DIV16 bit in the R242 register (page 55) before executing the WFI instruction. When exiting WFI mode, this gives the Flash enough time to wake up before the interrupt vector fetch. Bit 1 = FEIEN: Flash & E3 TM Interrupt enable. This bit selects the source of interrupt channel INTx between the external interrupt pin and the Flash/ E3 TM End of Write interrupt. Refer to the In- terrupt chapter for the channel number. 0: External interrupt enabled 1: Flash & E3 TM Interrupt enabled Bit 0 = EBUSY: E3 TM Busy (Read Only). This bit is automatically set during a Page Update operation when the first address to be modified is latched in the E3 TM memory, or during Chip Erase operation when bit EWMS is set. At the end of the write operation or during a Sector Erase Suspend this bit is automatically reset and the memory re- turns to read mode. When this bit is set every read access to the E3 TM memory will output invalid data (FFh equivalent to a NOP instruction), while every write access to the E3 TM memory will be ignored. At the end of the write operation this bit is automat- ically reset and the memory returns to read mode. Bit EBUSY remains high for a maximum of 10ms after Power-Up and when exiting Power-Down mode, meaning that the E3 TM memory is not yet ready to be accessed. 0: E3 TM not busy 1: E3 TM busy

3.3.2 Status Registers

Two Status Registers (FESR[1:0] are available to check the status of the current write operation in Flash and E3 TM memories. During a Flash or an E3 TM write operation any at- tempt to read the memo ry under modification will output invalid data (FFh equivalent to a NOP in- struction). This means that the Flash memory is not fetchable when a write operation is active: the write operation commands must be given from an- other memory ( E3 TM , internal RAM, or external memory). FLASH & E3 TM STATUS REGISTER 0 (FESR0) Address: 224002h /221002h -Read/Write Reset value: 0000 0000 (00h) Bit 7 = FEERR: Flash or E3 TM write ERRor (Read/ Write). This bit is set by hardware when an error occurs during a Flash or an E3 TM write operation. It must be cleared by software. 0: Write OK 1: Flash or E3 TM write error Bit 6:0 = FESS[6:0]. Flash and E3 TM Sectors Sta- tus Bits (Read Only). These bits are set by hardware and give the status of the 7 Flash and E3 TM sectors. – FESS6 = TestFlash and OTP – FESS5:4 = E3 TM sectors For 128K and 64K Flash devices: – FESS3:0 = Flash sectors (F3:0) For the ST92F250 (256K): – FESS3 gives the status of F5, F4 and F3 sectors: the status of all these three sectors are ORed on this bit – FESS2:0 = Flash sectors (F2:0) 76543210 FEERR FESS6 FESS5 FESS4 FESS3 FESS2 FESS1 FESS0

Bit 7 = ERER. Erase error (Read Only). curs during a Flash or an E3 TM write operation. Bit 6 = PGER. Program error (Read Only). the old sector is full (see AN1152 for more details). curring again when that byte is internally moved. of the FESR0 register is cleared by software. Table 10. Sector Status Bits

3.4 WRITE OPERATION EXAMPLE

tion bit. Any latched address and data will be reset. Table 11. Flash Write Operations Table 12. E3 TM Write Operations

3.5 PROTECTION STRATEGY

from 231FFCh to 231FFFh (see Figure 34). ways protected against write access. Figure 34. Protection Register Map

3.5.1 Non Volatile Registers

one time programmable by the user. quently to the Protection Registers. Bit 6 = APRO: FLASH access protection. Bit 5 = APBR: TestFlash access protection. is fetched from an external memory.

1 APRO APBR APEE APEX PWT2 PWT1 PWT0

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) PROTECTION STRATEGY (Cont’d) Bit 2:0 = PWT[2:0]: Password Attempt 2-0. If the TMDIS bit in the NVWPR register (231FFDh) is programmed to 0, every time a Set Protection operation is executed with Program Addresses equal to NVPWD1-0 (231FFE-Fh), the two provid- ed Program Data are compared with the NVPWD1-0 content; if there is not a match one of PWT2-0 bits is automatically programmed to 0: when these three bits are all programmed to 0 the test modes are disabled forever. In order to inten- tionally disable test modes forever, it is sufficient to set a random Password and then to make 3 wrong attempts to enter it. NON VOLATILE WRITE PROTECTION REGIS- TER (NVWPR) Address: 231FFDh - Read/Write Delivery value: 1111 1111 (FFh) Bit 7 = TMDIS: Test mode disable (Read Only). This bit, if set to 1, allows to bypass all the protec- tions in test and EPB modes. If programmed to 0, on the contrary, all the protections remain active also in test mode. The only way to enable the test modes if this bit is programmed to 0, is to execute the Set Protection operation with Program Ad- dresses equal to NVPWD1-0 (231FFF-Eh) and Program Data matching with the content of NVPWD1-0. This bit is read only: it is automatically programmed to 0 when NVPWD1-0 are written for the first time. 0: Test mode disabled 1: Test mode enabled Bit 6 = PWOK: Password OK (Read Only). If the TMDIS bit is programmed to 0, when the Set Protection operation is executed with Program Ad- dresses equal to NVPWD[1:0] and Program Data matching with NVPWD[1:0] content, the PWOK bit is automatically programmed to 0. When this bit is programmed to 0 TMDIS protection is bypassed and the test and EPB modes are enabled. 0: Password OK 1: Password not OK Bit 5 = WPBR: TestFlash Write Protection. This bit, if programmed at 0, disables any write ac- cess to the TestFlash, the OTP and the protection registers. This protection cannot be temporarily disabled. 0: TestFlash write protection on 1: TestFlash write protection off Note: it is strongly advised to never program the WPBR bit in the NVWPR register, as this will pre- vent any further write access to the protection reg- isters. Bit 4 = WPEE: E3 TM Write Protection. This bit, if programmed to 0, disables any write ac- cess to the E3 TM address space. This protection can be temporary disabled by executing the Set Protection operation and writing 1 into this bit. To restore the protection, reset the micro or execute another Set Protection operation on this bit. E3 TM write protection on 1: E3 TM write protection off Note: a read access to the NVWPR register re- stores any protection previously enabled. Bit 3 = WPRS3: FLASH Sectors 5-3 Write Protec- tion. This bit, if programmed to 0, disables any write ac- cess to the Flash sector 3 (and sectors 4 and 5 when available) address space(s). This protection can be temporary disabled by executing the Set Protection operation and writing 1 into this bit. To restore the protection, reset the micro or execute another Set Protection operation on this bit. 0: FLASH Sectors 5-3 write protection on 1: FLASH Sectors 5-3 write protection off Note: a read access to the NVWPR register re- stores any protection previously enabled. Bit 2:0 = WPRS[2:0]: FLASH Sectors 2-0 Write Protection. These bits, if programmed to 0, disable any write access to the 3 Flash sectors address spaces. These protections can be temporary disabled by executing the Set Protection operation and writing 1 into these bits. To restore the protection, reset the micro or execute another Set Protection oper- ation on this bit. 0: FLASH Sectors 2-0 write protection on 1: FLASH Sectors 2-0 write protection off Note: a read access to the NVWPR register re- stores any protection previously enabled. 7 6 5 4 3210 TMDIS PWOK WPBR WPEE WPRS3 WPRS2 WPRS1 WPRS0

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) PROTECTION STRATEGY (Cont’d) NON VOLATILE PASSWORD (NVPWD1-0) Address: 231FFF-231FFEh - Write Only Delivery value: 1111 1111 (FFh) Bit 7:0 = PWD[7:0]: Password bits 7:0 (Write On- ly). These bits must be programmed with the Non Vol- atile Password that must be provided with the Set Protection operation to disable (first write access) or to reenable (second write access) the test and EPB modes. The first write access fixes the pass- word value and resets the TMDIS bit of NVWPR (231FFDh). The second wr ite access, with Pro- gram Data matching with NVPWD[1:0] content, re- sets the PWOK bit of NVWPR. These two registers can be accessed only in write mode (a read access returns FFh).

3.5.2 Temporary Unprotection

On user request the memory can be configured so as to allow the temporary unprotection also of all access protections bits of NVAPR (write protection bits of NVWPR are always temporarily unprotecta- ble). Bit APEX can be temporarily disabled by execut- ing the Set Protection operation and writing 1 into this bit, but only if this write instruction is executed from an internal memory (Flash and Test Flash ex- cluded). Bit APEE can be temporarily disabled by execut- ing the Set Protection operation and writing 1 into this bit, but only if this write instruction is executed from the memory itself to unprotect ( E3 TM). Bits APRO and APBR can be temporarily disabled through a direct write at NVAPR location, by over- writing at 1 these bits, but only if this write instruc- tion is executed from the memory itself to unpro- tect. To restore the access protections, reset the micro or execute another Set Protection operation by writing 0 to the desired bits. Note: To restore all the protections previously en- abled in the NVAPR or NVWPR register, read the corresponding register. When an internal memory (Flash, TestFlash or E3 TM) is protected in access, also the data access through a DMA of a peripheral is forbidden (it re- turns FFh). To read data in DMA mode from a pro- tected memory, first it is necessary to temporarily unprotect that memory. The temporary unprotection allows also to update a protected code. Refer to the following figures to manage the Test/ EPB, Access and Write protection modes. 76543210 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0

Figure 37. WRITE Mode Protection

3.6 FLASH IN-SYSTEM PROGRAMMING

through a serial interface (SCI0). code reads the Reset vector. tion is executed, waiting for a hardware Reset.

3.6.1 Code Update Routine

internal RAM starting from address 200010h. Table 13. SCI0 Registers (page 24) initialization (CLKOUT0) as Alternate Functions.

Figure 38. Flash in-system Programming.

4 REGISTER AND MEMORY MAP

4.1 INTRODUCTION

4.2 MEMORY CONFIGURATION

ble on-chip memory, is fully available to the user.

4.2.1 Reset Vector Location

4.2.2 Location of Vector for External Watchdog

Table 14. User Routine Parameters the user routine is not called. 000008h 1 byte ms rate at 2 MHz.

Figure 39. ST92F150/F250 External Memory Map

Figure 40. ST92F124/F150/F250 TESTFLASH and E3 TM Memory Map

Figure 41. ST92F124/F150 Internal Memory Map (64K versions)

Figure 42. ST92F124/F150 Internal Memory Map (128K versions)

• Available on ST92F150 versions only. Reserved area on ST92F124 version .

Figure 43. ST92F250 Internal Memory Map (256K version)

4.3 ST92F124/F150/F250 REGISTER MAP

– Registers common to other functions. rupt Vector table do not overlap. Table 15. Common Registers

Table 16. Group F Pages Register Map

ST92F124/F150/F250 - REGISTER AND MEMORY MAP * Available on some devices only Reg. Page 41 42 43 48 49 50 51 52 53 54 55 57 60 61 62 63 R255 CAN_1* CAN_1* Port 9* CAN_0* CAN_0* CAN_0* CAN_0* CAN_0* CAN_0* CAN_0* Res. WUIMU STANDARD INTERRUPT CHANNELS AD10 AD10 AD10 R254 R253 R252 R251 Port 8* R250 R249 R248 Res. R247 Res. R246 RCCU R245 R244 Res R243 R242 R241 R240

Table 17. Detailed Register Map

ST92F124/F150/F250 - REGISTER AND MEMORY MAP I/O Port R240 P4C0 Port 4 Configuration Register 0 FD 151 R241 P4C1 Port 4 Configuration Register 1 00 R242 P4C2 Port 4 Configuration Register 2 00 I/O Port R244 P5C0 Port 5 Configuration Register 0 FF R245 P5C1 Port 5 Configuration Register 1 00 R246 P5C2 Port 5 Configuration Register 2 00 I/O Port R248 P6C0 Port 6 Configuration Register 0 xx11 1111 R249 P6C1 Port 6 Configuration Register 1 xx00 0000 R250 P6C2 Port 6 Configuration Register 2 xx00 0000 R251 P6DR Port 6 Data Register xx11 1111 I/O Port R252 P7C0 Port 7 Configuration Register 0 FF R253 P7C1 Port 7 Configuration Register 1 00 R254 P7C2 Port 7 Configuration Register 2 00 R255 P7DR Port 7 Data Register FF

7 SPI

R240 SPDR0 SPI Data Register 00 260 R241 SPCR0 SPI Control Register 00 260 R242 SPSR0 SPI Status Register 00 261 R243 SPPR0 SPI Prescaler Register 00 261 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP MFT1 R240 REG0HR1 Capture Load Register 0 High xx 202 R241 REG0LR1 Capture Load Register 0 Low xx 202 R242 REG1HR1 Capture Load Register 1 High xx 202 R243 REG1LR1 Capture Load Register 1 Low xx 202 R244 CMP0HR1 Compare 0 Register High 00 202 R245 CMP0LR1 Compare 0 Register Low 00 202 R246 CMP1HR1 Compare 1 Register High 00 202 R247 CMP1LR1 Compare 1 Register Low 00 202 R248 TCR1 Timer Control Register 00 203 R249 TMR1 Timer Mode Register 00 204 R250 T_ICR1 External I nput Control Register 00 205 R251 PRSR1 Prescaler Register 00 205 R252 OACR1 Output A Control Register 00 206 R253 OBCR1 Output B Control Register 00 207 R254 T_FLAGR1 Flags Register 00 207 R255 IDMR1 Interrupt/DMA Mask Register 00 209 R244 DCPR1 DMA Counter Pointer Register xx 202 R245 DAPR1 DMA Address Pointer Register xx 202 R246 T_IVR1 Interrupt Vector Register xx 202 R247 IDCR1 Interrupt/DMA Control Register C7 202 MFT0,1 R248 IOCR I/O Connection Register FC 211 MFT0 R240 DCPR0 DMA Counter Pointer Register xx 209 R241 DAPR0 DMA Address Pointer Register xx 210 R242 T_IVR0 Interrupt Vector Register xx 210 R243 IDCR0 Interrupt/DMA Control Register C7 211 R240 REG0HR0 Capture Load Register 0 High xx 202 R241 REG0LR0 Capture Load Register 0 Low xx 202 R242 REG1HR0 Capture Load Register 1 High xx 202 R243 REG1LR0 Capture Load Register 1 Low xx 202 R244 CMP0HR0 Compare 0 Register High 00 202 R245 CMP0LR0 Compare 0 Register Low 00 202 R246 CMP1HR0 Compare 1 Register High 00 202 R247 CMP1LR0 Compare 1 Register Low 00 202 R248 TCR0 Timer Control Register 00 203 R249 TMR0 Timer Mode Register 00 204 R250 T_ICR0 External I nput Control Register 00 205 R251 PRSR0 Prescaler Register 00 205 R252 OACR0 Output A Control Register 00 206 R253 OBCR0 Output B Control Register 00 207 R254 T_FLAGR0 Flags Register 00 207 R255 IDMR0 Interrupt/DMA Mask Register 00 209 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP

11 STIM

R240 STH Counter High Byte Register FF 166 R241 STL Counter Low Byte Register FF 166 R242 STP Standard Timer Prescaler Register FF 166 R243 STC Standard Timer Control Register 14 166

20 I2C_0

R240 I2DCCR I 2C Control Register 00 273 R241 I2CSR1 I 2C Status Register 1 00 274 R242 I2CSR2 I 2C Status Register 2 00 276 R243 I2CCCR I 2C Clock Control Register 00 277 R244 I2COAR1 I 2C Own Address Register 1 00 277 R245 I2COAR2 I 2C Own Address Register 2 00 278 R246 I2CDR I 2C Data Register 00 278 R247 I2CADR I 2C General Call Address A0 278 R248 I2CISR I 2C Interrupt Status Register xx 279 R249 I2CIVR I 2C Interrupt Vector Register xx 280 R250 I2CRDAP Receiver DMA Source Addr. Pointer xx 280 R251 I2CRDC Receiver DMA Transaction Counter xx 280 R252 I2CTDAP Transmitter DMA Source Addr. Pointer xx 281 R253 I2CTDC Transmitter DM A Transaction Counter xx 281 R254 I2CECCR Extended Clock Control Register 00 281 R255 I2CIMR I 2C Interrupt Mask Register x0 282 MMU R240 DPR0 Data Page Register 0 xx 46 R241 DPR1 Data Page Register 1 xx 46 R242 DPR2 Data Page Register 2 xx 46 R243 DPR3 Data Page Register 3 xx 46 R244 CSR Code Segment Register 00 47 R248 ISR Interrupt Segment Register xx 47 R249 DMASR DMA Segment Register xx 47 EXTMI R245 EMR1 External Memory Register 1 80 148 R246 EMR2 External Memory Register 2 1F 149 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP

22 I2C_1*

R240 I2DCCR I 2C Control Register 00 273 R241 I2CSR1 I 2C Status Register 1 00 274 R242 I2CSR2 I 2C Status Register 2 00 276 R243 I2CCCR I 2C Clock Control Register 00 277 R244 I2COAR1 I 2C Own Address Register 1 00 277 R245 I2COAR2 I 2C Own Address Register 2 00 278 R246 I2CDR I 2C Data Register 00 278 R247 I2CADR I 2C General Call Address A0 278 R248 I2CISR I 2C Interrupt Status Register xx 279 R249 I2CIVR I 2C Interrupt Vector Register xx 280 R250 I2CRDAP Receiver DMA Source Addr. Pointer xx 280 R251 I2CRDC Receiver DMA Transaction Counter xx 280 R252 I2CTDAP Transmitter DMA Source Addr. Pointer xx 281 R253 I2CTDC Transmitter DM A Transaction Counter xx 281 R254 I2CECCR Extended Clock Control Register 00 281 R255 I2CIMR I 2C Interrupt Mask Register x0 282

23 JBLPD*

R240 STATUS Status Register 40 305 R241 TXDATA Transmit Data Register xx 306 R242 RXDATA Receive Data Register xx 307 R243 TXOP Transmit Opcode Register 00 307 R244 CLKSEL System Frequency Selection Register 00 312 R245 CONTROL Control Register 40 312 R246 PADDR Physical Address Register xx 313 R247 ERROR Error Register 00 314 R248 IVR Interrupt Vector Register xx 316 R249 PRLR Priority Level Register 10 316 R250 IMR Interrupt Mask Register 00 316 R251 OPTIONS Options and Register Group Selection 00 318 R252 CREG0 Current Register 0 xx 320 R253 CREG1 Current Register 1 xx 320 R254 CREG2 Current Register 2 xx 320 R255 CREG3 Current Register 4 xx 320 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP

24 SCI-M

R240 RDCPR0 Receiver DMA Transaction Counter Pointer xx 227 R241 RDAPR0 Receiver DMA Source Address Pointer xx 227 R242 TDCPR0 Transmitter DMA Transaction Counter Pointer xx 227 R243 TDAPR0 Transmitter DMA Destination Address Pointer xx 227 R244 S_IVR0 Interrupt Vector Register xx 229 R245 ACR0 Address/Data Compare Register xx 229 R246 IMR0 Interrupt Mask Register x0 229 R247 S_ISR0 Interrupt Status Register xx 229 R248 RXBR0 Receive Buffer Register xx 231 R248 TXBR0 Transmitter Buffer Register xx 231 R249 IDPR0 Interrupt/DMA Priority Register xx 232 R250 CHCR0 Character Configuration Register xx 233 R251 CCR0 Clock Configuration Register 00 234 R252 BRGHR0 Baud Rate Generator High Reg. xx 235 R253 BRGLR0 Baud Rate Generator Low Register xx 235 R254 SICR0 Synchronous Input Control 03 235 R255 SOCR0 Synchronous Output Control 01 236

26 SCI-A*

R240 SCISR SCI Status Register C0 245 R241 SCIDR SCI Data Register xx 248 R242 SCIBRR SCI Baud Rate Register xx 248 R243 SCICR1 SCI Control Register 1 xx 246 R244 SCICR2 SCI Control Register 2 00 247 R245 SCIERPR SCI Extended Receive Prescaler Register 00 249 R246 SCIETPR SCI Extended Trans mit Prescaler Register 00 249 R255 SCICR3 SCI Control Register 3 00 247

28 EFT0*

R240 IC1HR0 Input Capt ure 1 High Register xx 181 R241 IC1LR0 Input Capture 1 Low Register xx 181 R242 IC2HR0 Input Capt ure 2 High Register xx 181 R243 IC2LR0 Input Capture 2 Low Register xx 181 R244 CHR0 Counter High Register FF 182 R245 CLR0 Counter Low Register FC 182 R246 ACHR0 Alternate Counter High Register FF 182 R247 ACLR0 Alternate Counter Low Register FC 182 R248 OC1HR0 Output Compare 1 High Register 80 183 R249 OC1LR0 Output Compare 1 Low Register 00 183 R250 OC2HR0 Output Compare 2 High Register 80 183 R251 OC2LR0 Output Compare 2 Low Register 00 183 R252 CR1_0 Control Register 1 00 185 R253 CR2_0 Control Register 2 00 185 R254 SR0 Status Register 00 185 R255 CR3_0 Control Register 3 00 185 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP

29 EFT1*

R240 IC1HR1 Input Capt ure 1 High Register xx 181 R241 IC1LR1 Input Capture 1 Low Register xx 181 R242 IC2HR1 Input Capt ure 2 High Register xx 181 R243 IC2LR1 Input Capture 2 Low Register xx 181 R244 CHR1 Counter High Register FF 182 R245 CLR1 Counter Low Register FC 182 R246 ACHR1 Alternate Counter High Register FF 182 R247 ACLR1 Alternate Counter Low Register FC 182 R248 OC1HR1 Output Compare 1 High Register 80 183 R249 OC1LR1 Output Compare 1 Low Register 00 183 R250 OC2HR1 Output Compare 2 High Register 80 183 R251 OC2LR1 Output Compare 2 Low Register 00 183 R252 CR1_1 Control Register 1 00 185 R253 CR2_1 Control Register 2 00 185 R254 SR1 Status Register 00 185 R255 CR3_1 Control Register 3 00 185 CAN1* Control/ Status R240 CMCR CAN Master Control Register 02 343 R241 CMSR CAN Master Status Register 02 344 R242 CTSR CAN Transmit Control Register 00 344 R243 CTPR CAN Transmit Priority Register 00 345 R244 CRFR0 CAN Receive FIFO Register 0 00 346 R245 CRFR1 CAN Receive FIFO Register 1 00 346 R246 CIER CAN Interrupt Enable Register 00 346 R247 CESR CAN Error Status Register 00 347 R248 CEIER CAN Error Interrupt Enable Register 00 347 R249 TECR Transmit Error Counter Register 00 348 R250 RECR Receive Error Counter Register 00 348 R251 CDGR CAN Diagnosis Register 00 348 R252 CBTR0 CAN Bit Timing Register 0 00 349 R253 CBTR1 CAN Bit Timing Register 1 23 349 R255 CFPSR Filter page Select Register 00 349 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN1* Receive FIFO 0 R240 MFMI Mailbox Filter Match Index 00 351 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 CAN1* Receive FIFO 1 R240 MFMI Mailbox Filter Match Index 00 351 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN1 * Tx Mailbox 0 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 CAN1 * Tx Mailbox 1 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN1 * Tx Mailbox 2 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register x0 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352

42 CAN1 *

See “Page Mapping for CAN 0 / CAN 1” on page 357 Filter Configuration Acceptance Filters 7:0 (5 register pages) I/O Port 8 * R248 P8C0 Port 8 Configuration Register 0 03 151 R249 P8C1 Port 8 Configuration Register 1 00 R250 P8C2 Port 8 Configuration Register 2 00 R251 P8DR Port 8 Data Register FF I/O Port 9 * R252 P9C0 Port 9 Configuration Register 0 00 R253 P9C1 Port 9 Configuration Register 1 00 R254 P9C2 Port 9 Configuration Register 2 00 R255 P9DR Port 9 Data Register FF CAN0* Control/ Status R240 CMCR CAN Master Control Register 02 343 R241 CMSR CAN Master Status Register 02 344 R242 CTSR CAN Transmit Control Register 00 344 R243 CTPR CAN Transmit Priority Register 00 345 R244 CRFR0 CAN Receive FIFO Register 0 00 346 R245 CRFR1 CAN Receive FIFO Register 1 00 346 R246 CIER CAN Interrupt Enable Register 00 346 R247 CESR CAN Error Status Register 00 347 R248 CEIER CAN Error Interrupt Enable Register 00 347 R249 TECR Transmit Error Counter Register 00 348 R250 RECR Receive Error Counter Register 00 348 R251 CDGR CAN Diagnosis Register 00 348 R252 CBTR0 CAN Bit Timing Register 0 00 349 R253 CBTR1 CAN Bit Timing Register 1 23 349 R255 CFPSR Filter page Select Register 00 349 Page (Dec) Block Reg. No. Register Name

Description

Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN0* Receive FIFO 0 R240 MFMI Mailbox Filter Match Index 00 351 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 CAN0* Receive FIFO 1 R240 MFMI Mailbox Filter Match Index 00 351 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN0* Tx Mailbox 0 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 CAN0* Tx Mailbox 1 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP CAN0* Tx Mailbox 2 R240 MCSR Mailbox Control Status Register 00 350 R241 MDLC Mailbox Data Length Control Register xx 352 R242 MIDR0 Mailbox Identifier Register 0 xx 351 R243 MIDR1 Mailbox Identifier Register 1 xx 351 R244 MIDR2 Mailbox Identifier Register 2 xx 351 R245 MIDR3 Mailbox Identifier Register 3 xx 351 R246 MDAR0 Mailbox Data Register 0 xx 352 R247 MDAR1 Mailbox Data Register 1 xx 352 R248 MDAR2 Mailbox Data Register 2 xx 352 R249 MDAR3 Mailbox Data Register 3 xx 352 R250 MDAR4 Mailbox Data Register 4 xx 352 R251 MDAR5 Mailbox Data Register 5 xx 352 R252 MDAR6 Mailbox Data Register 6 xx 352 R253 MDAR7 Mailbox Data Register 7 xx 352 R254 MTSLR Mailbox Time Stamp Low Register xx 352 R255 MTSHR Mailbox Time Stamp High Register xx 352

54 CAN0*

“Page Mapping for CAN 0 / CAN 1” on page 357 Filter Configuration Acceptance Filters 7:0 (5 register pages)

55 RCCU

R240 CLKCTL Clock Control Register 00 134 R241 VRCTR Voltage Regulator Control Register 0x 134 R242 CLK_FLAG Clock Flag Register 64,48, 28 or 08 135 R246 PLLCONF PLL Configuration Register xx 135

57 WUIMU

R249 WUCTRL Wake-Up Control Register 00 118 R250 WUMRH Wake-Up Mask Register High 00 119 R251 WUMRL Wake-Up Mask Register Low 00 119 R252 WUTRH Wake-Up Trigger Register High 00 120 R253 WUTRL Wake-Up Trigger Register Low 00 120 R254 WUPRH Wake-Up Pending Register High 00 120 R255 WUPRL Wake-Up Pending Register Low 00 120

60 STD

R245 SIMRH Interrupt Mask Register High (Ch. I to L) 00 109 R246 SIMRL Interrupt Mask Register Low (Ch. E to H) 00 109 R247 SITRH Interrupt Trigger R egister High (Ch. I to L) 00 109 R248 SITRL Interrupt Trigger Register Low (Ch. E to H) 00 109 R249 SIPRH Interrupt Pending R egister High (Ch. I to L) 00 109 R250 SIPRL Interrupt Pending R egister Low (Ch. E to H) 00 109 R251 SIVR Interrupt Vector Register (Ch. E to L) xE 110 R252 SIPLRH Interrupt Priority Register High (Ch. I to L) FF 110 R253 SIPLRL Interrupt Priority Register Low (Ch. E to H) FF 110 R254 SFLAGRH Interrupt Flag R egister High (Ch. I to L) 00 111 R255 SIFLAGRL Interrupt Flag Register Low (Ch. E to H) 00 111 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP ADC R240 D0HR Channel 0 Data High Register xx 366 R241 D0LR Channel 0 Data Low Register x0 366 R242 D1HR Channel 1 Data High Register xx 366 R243 D1LR Channel 1 Data Low Register x0 366 R244 D2HR Channel 2 Data High Register xx 366 R245 D2LR Channel 2 Data Low Register x0 366 R246 D3HR Channel 3 Data High Register xx 366 R247 D3LR Channel 3 Data Low Register x0 366 R248 D4HR Channel 4 Data High Register xx 367 R249 D4LR Channel 4 Data Low Register x0 367 R250 D5HR Channel 5 Data High Register xx 367 R251 D5LR Channel 5 Data Low Register x0 367 R252 D6HR Channel 6 Data High Register xx 367 R253 D6LR Channel 6 Data Low Register x0 367 R254 D7HR Channel 7 Data High Register xx 367 R255 D7LR Channel 7 Data Low Register x0 367 R240 D8HR Channel 8 Data High Register xx 368 R241 D8LR Channel 8 Data Low Register x0 368 R242 D9HR Channel 9 Data High Register xx 368 R243 D9LR Channel 9 Data Low Register x0 368 R244 D10HR Channel 10 Data High Register xx 368 R245 D10LR Channel 10 Data Low Register x0 368 R246 D11HR Channel 11 Data High Register xx 368 R247 D11LR Channel 11 Data Low Register x0 368 R248 D12HR Channel 12 Data High Register xx 369 R249 D12LR Channel 12 Data Low Register x0 369 R250 D13HR Channel 13 Data High Register xx 369 R251 D13LR Channel 13 Data Low Register x0 369 R252 D14HR Channel 14 Data High Register xx 369 R253 D14LR Channel 14 Data Low Register x0 369 R254 D15HR Channel 15 Data High Register xx 369 R255 D15LR Channel 15 Data Low Register x0 369 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

ST92F124/F150/F250 - REGISTER AND MEMORY MAP Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. * Available on some devices only

63 ADC

R243 CRR Compare Result Register 0x 370 R244 LTAHR Channel A Lower Threshold High Register xx 370 R245 LTALR Channel A Lower Threshold Low Register x0 370 R246 LTBHR Channel B Lower Threshold High Register xx 370 R247 LTBLR Channel B Lower Threshold Low Register x0 371 R248 UTAHR Channel A Upper Threshold High Register xx 371 R249 UTALR Channel A Upper Threshold Low Register x0 371 R250 UTBHR Channel B Upper Threshold High Register xx 371 R251 UTBLR Channel B Upper Threshold Low Register x0 371 R252 CLR1 Control Logic Register 1 0F 372 R253 CLR2 Control Logic Register 2 A0 372 R254 AD_ICR Interrupt Control Register 0F 373 R255 AD_IVR Interrupt Vector Register x2 374 Page (Dec) Block Reg. No. Register Name Description Reset Value Hex. Doc. Page

5 INTERRUPTS

5.1 INTRODUCTION

5.1.1 On-Chip Peripheral Interrupt Sources

5.1.1.1 Dedicated Channels

located in their peripheral register page.

5.1.1.2 Standard Channels

mapped to the INTxx interrupt channel group.

3 TM/FLASH

5.1.1.3 External Interrupts

to the INTxx interrupt channel group in page 0.

5.1.1.4 Top Level Interrupt (TLI)

through a vector table mapped in Memory. Figure 44. Interrupt Response

5.2 INTERRUPT VECTORING

Service Routine automatically. (defined by the programmer). if it is mapped to one of the INTxx channels). ISR register, thus allowing 8-bit vector addressing.

ST92F124/F150/F250 - INTERRUPTS The Top Level Interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR). If an external watchdog is used, refer to the Regis- ter and Memory Map section for details on using vector locations 0006h to 0009h. Otherwise loc- tions 0006h to 0007h must contain FFFFh. With one Interrupt Vector register, it is possible to address several interrupt se rvice routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. Note: The first 256 locations of the memory seg- ment pointed to by ISR can contain program code.

5.2.1 Divide by Zero trap

The Divide by Zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required. Warning. Although the Divide by Zero Trap oper- ates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET ).

5.2.2 Segment Paging During Interrupt

The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the inter- rupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all inte rrupt service routines is thus limited to 64K bytes. ST9+ mode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the in- terrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the con- tents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service rou- tines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increas ed, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is differ- ent. ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped Registers PC, FLAGR PC, FLAGR, CSR Max. Code Size for interrupt service routine 64KB Within 1 segment No limit Across segments

5.3 INTERRUPT PRIORITY LEVELS

(TLI) or non-maskable (TLNM).

5.4 PRIORITY LEVEL ARBITRATION

ing to the selected Arbitration Mode. Level Interrupt overrides every other priority.

5.4.1 Priority Level 7 (Lowest)

5.4.2 Maximum Depth of Nesting

including the Top Level Interrupt request.

5.4.3 Simultaneous Interrupts

Table 18. Daisy Chain Priority

5.4.4 Dynamic Priority Level Modification

ing the CPL during its execution. See Figure 45.

Figure 45. Example of Dynamic Priority

5.5 ARBITRATION MODES

mode is the standard interrupt arbitration mode. quired, depending on the request priority levels.

5.5.1 Concurrent Mode

– The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – The Flag register is pushed onto system stack. the Vector Table, pointed to by the IVR. – The Flag register is popped from system stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – If ENCSR is reset, CSR is used instead of ISR. executed during the interrupt service routine). cause undesirable interrupt response sequences.

Figure 46. Simple Example of a Sequence of Interrupt Requests with:

terminated, thus making the outermost routine fail. Figure 47. Complex Example of a Sequence of Interrupt Requests with:

7 MAIN

5.5.2 Nested Mode

is 3, the bit 3 will be set). the priority level of the suspended routine. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – The Flag register is pushed onto system stack. the Vector Table, pointed to by the IVR. Figure 48. Simple Example of a Sequence of Interrupt Requests with:

5.6 EXTERNAL INTERRUPTS

Table 19. External Interrupt Channel Grouping Figure 50. Priority Level Examples the odd (lower) priority level. Figure 50 shows an example of priority levels. ternal interrupts and vectors. Table 20. Multiplexed Interrupt Sources SPIS bit in the SPCR0 register (R241 Page 7). registers both for peripheral and interrupts.

3 TM/Flash INT4

Figure 51. External Interrupt Control Bits and Vectors

• Only four interrupt pins are available. Refer to Table 19 for I/O pin mapping.

5.7 STANDARD INTERRUPTS (CAN AND SCI-A)

ping is shown in the following table. Table 21. Interrupt Channel Assignment

5.7.1 Functional Description

hardware when the interrupt is acknowledged. the SIPLRL and SIPLRH control registers. el (the LSB of priority level is one). See Figure 52. Figure 52. Priority Level Examples has the highest priority pending interrupt request. the corresponding overrun flag is set.

Figure 53. Standard Interrupt (Channels E to I) Control Bits and Vectors

ST92F124/F150/F250 - INTERRUPTS

5.7.2 IMPORTANT NOTE ON STANDARD

Refer to Section 13.4 on page 413.

5.8 TOP LEVEL INTERRUPT

The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high (the reset condition) the source is the external pin NMI. If it is low, the source is the Timer/ Watchdog End Of Count. When the source is the NMI external pin, the control bit EIVR.TLTEV (R246.3; Page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. When the selected event occurs, the CICR.TLIP bit (R230.6) is set. Depending on the mask situation, a Top Level Interrupt request may be generated. Two kinds of masks are available, a Maskable mask and a Non-Maskable mask. The first mask is the CICR.TLI bit (R230.5): it can be set or cleared to enable or disable respectively the Top Level Inter- rupt request. If it is enabled, the global Enable In- terrupt bit, CICR.IEN (R230.4) must also be ena- bled in order to allow a Top Level Request. The second mask NICR.TLNM (R247.7) is a set- only mask. Once set, it enables the Top Level In- terrupt request independently of the value of CICR.IEN and it cannot be cleared by the pro- gram. Only the processor RESET cycle can clear this bit. This does not prevent the user from ignor- ing some sources due to a change in TLIS. The Top Level Interrupt Service Routine cannot be interrupted by any other interrupt or DMA request, in any arbitration mode, not even by a subsequent Top Level Interrupt request. Warning. The interrupt machine cycle of the Top Level Interrupt does not clear the CICR.IEN bit, and the corresponding iret does not set it. Fur- thermore the TLI never modifies the CPL bits and the NICR register.

5.9 DEDICATED ON-CHIP PERIPHERAL

Some of the on-chip peripherals have their own specific interrupt unit containing one or more inter- rupt channels, or DMA channels. Please refer to the specific peripheral chapter for the description of its interrupt features and control registers. The on-chip peripheral interrupts are controlled by the following bits: – Interrupt Pending bit (IP). Set by hardware when the Trigger Event occurs. Can be set/ cleared by software to generate/cancel pending interrupts and give the status for Interrupt polling. – Interrupt Mask bit (IM). If IM = “0”, no interrupt request is generated. If IM =“1” an interrupt re- quest is generated whenever IP = “1” and CICR.IEN = “1”. – Priority Level (PRL, 3 bits). These bits define the current priority level, PRL=0: the highest pri- ority, PRL=7: the lowest priority (the interrupt cannot be acknowledged) – Interrupt Vector Register (IVR, up to 7 bits). The IVR points to the vector table which itself contains the interrupt routine start address.

Figure 54. Top Level Interrupt Structure

5.10 INTERRUPT RESPONSE TIME

is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. INTCLK cycle before the sampling time. write operation has been performed. and MUL instructions) or 45 for other instructions. added if the CSR is pushed (ENCSR =1).

ST92F124/F150/F250 - INTERRUPTS

5.11 INTERRUPT REGISTERS

CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-b it Multifunction Timer pe- ripheral. 0: MFT disabled 1: MFT enabled Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when Top Level Inter- rupt (TLI) trigger event occurs. It is cleared by hardware when a TLI is acknowledged. It can also be set by software to implement a software TLI. 0: No TLI pending 1: TLI pending Bit 5 = TLI: Top Level Interrupt. This bit is set and cleared by software. 0: A Top Level Interrupt is generared when TLIP is set, only if TLNM=1 in the NICR register (inde- pendently of the value of the IEN bit). 1: A Top Level Interrupt request is generated when IEN=1 and the TLIP bit are set. Bit 4 = IEN: Interrupt Enable. This bit is cleared by the interrupt machine cycle (except for a TLI). It is set by the iret instruction (except for a return from TLI). It is set by the EI instruction. It is cleared by the DI instruction. 0: Maskable interrupts disabled 1: Maskable Interrupts enabled Note: The IEN bit can also be changed by soft- ware using any instruction that operates on regis- ter CICR, however in this case, take care to avoid spurious interrupts, since IEN cannot be cleared in the middle of an interrupt arbitration. Only modify the IEN bit when interrupts are disabled or when no peripheral can generate interrupts. For exam- ple, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequence DI; POP CICR to make sure that no interrupts are be- ing arbitrated when CICR is modified. Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software. 0: Concurrent Mode 1: Nested Mode Bits 2:0 = CPL[2:0]: Current Priority Level. These bits define the Current Priority Level. CPL=0 is the highest priority. CPL=7 is the lowest priority. These bits may be modified directly by the interrupt hardware when Nested Interrupt Mode is used. EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 = TED1: INTD1 Trigger Event Bit 6 = TED0: INTD0 Trigger Event Bit 5 = TEC1: INTC1 Trigger Event Bit 4 = TEC0: INTC0 Trigger Event Bit 3 = TEB1: INTB1 Trigger Event Bit 2 = TEB0: INTB0 Trigger Event Bit 1 = TEA1: INTA1 Trigger Event Bit 0 = TEA0: INTA0 Trigger Event These bits are set and cleared by software. 0: Select falling edge as interrupt trigger event 1: Select rising edge as interrupt trigger event GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = IPD0: INTD0 Interrupt Pending bit Bit 5 = IPC1: INTC1 Interrupt Pending bit Bit 4 = IPC0: INTC0 Interrupt Pending bit Bit 3 = IPB1: INTB1 Interrupt Pending bit Bit 2 = IPB0: INTB0 Interrupt Pending bit Bit 1 = IPA1: INTA1 Interrupt Pending bit Bit 0 = IPA0: INTA0 Interrupt Pending bit These bits are set by hardware on occurrence of a trigger event (as specified in the EITR register) and are cleared by hardware on interrupt acknowl- edge. They can also be set by software to imple- ment a software interrupt. 0: No interrupt pending 1: Interrupt pending EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR) R244 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 = IMD1: INTD1 Interrupt Mask Bit 6 = IMD0: INTD0 Interrupt Mask Bit 5 = IMC1: INTC1 Interrupt Mask Bit 4 = IMC0: INTC0 Interrupt Mask Bit 3 = IMB1: INTB1 Interrupt Mask Bit 2 = IMB0: INTB0 Interrupt Mask Bit 1 = IMA1: INTA1 Interrupt Mask Bit 0 = IMA0: INTA0 Interrupt Mask These bits are set and cleared by software. 0: Interrupt masked 1: Interrupt not masked (an interrupt is generated if the IPxx and IEN bits = 1) EXTERNAL INTERRUPT PRIORITY LEVEL REGISTER (EIPLR) R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bits 7:6 = PL2D, PL1D: INTD0, D1 Priority Level. Bis 5:4 = PL2C, PL1C: INTC0, C1 Priority Level. Bits 3:2 = PL2B, PL1B: INTB0, B1 Priority Level. Bits 1:0 = PL2A, PL1A: INTA0, A1 Priority Level. These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by hardware at 0 for Channels A0, B0, C0 and D0 and at 1 for Channels A1, B1, C1 and D1. IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0 PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A PL2x PL1x Hardware bit Priority 00 0 0 (Highest) 01 0 10 0 11 0 7 (Lowest)

ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h) Bits 7:4 = V[7:4]: Most significant nibble of Exter- nal Interrupt Vector. These bits are not initialized by reset. For a repre- sentation of how the full vector is generated from V[7:4] and the selected external interrupt channel, refer to Figure 51. Bit 3 = TLTEV: Top Level Trigger Event bit. This bit is set and cleared by software. 0: Select falling edge as NMI trigger event 1: Select rising edge as NMI trigger event Bit 2 = TLIS: Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source (the IA0S bit must be set in this case) 1: NMI is TL interrupt source Bit 1 = IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source (the TLIS bit must be set in this case) 1: External Interrupt pin is INTA0 source Bit 0 = EWEN: External Wait Enable. This bit is set and cleared by software. 0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external memory access cycle). Note: For more details on Wait mode refer to the section describing the WAITN pin in the External Memory Chapter. NESTED INTERRUPT CONTROL (NICR) R247 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 = TLNM: Top Level Not Maskable. This bit is set by software and cleared only by a hardware reset. 0: Top Level Interrupt Maskable. A top level re- quest is generated if the IEN, TLI and TLIP bits 1: Top Level Interrupt Not Maskable. A top level request is generated if the TLIP bit =1 Bits 6:0 = HL[6:0]: Hold Level x These bits are set by hardware when, in Nested Mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the Top Level interrupt request). They are cleared by hardware at the iret execution when the routine at level x is recovered. V7 V6 V5 V4 TLTEV TLIS IAOS EWEN TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0

ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) INTERRUPT MASK REGISTER HIGH (SIMRH) R245 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:1 = Reserved. Bit 0 = IMI0 Channel I Mask bit The IMI0 bit is set and cleared by software to ena- ble or disable interrupts on channel I0 . 0: Interrupt masked 1: An interrupt is generated if the IPI0 bit is set in the SIPRH register. INTERRUPT MASK REGISTER LOW (SIMRL) R246 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:0 = IMxx Channel E to H Mask bits The IMxx bits are set and cleared by software to enable or disable on channel xx interrupts. 0: Interrupt masked 1: An interrupt is generated if the corresponding IPxx bit is set in the SIPRL register. INTERRUPT TRIGGER EVENT REGISTER HIGH (SITRH) R247 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:1 = Reserved. Bit 0 = ITEI0 Channel I0 Trigger Event This bit is set and cleared by software to define the polarity of the channel I0 trigger event 0: The I0 pending bit will be set on the falling edge of the interrupt line 1: The I0 pending bit will be set on the rising edge of the interrupt line Note: The ITEI0 bit must be set to enable the SCI- A interrupt as the SCI-A interrupt event is a rising edge event. INTERRUPT TRIGGER EVENT REGISTER LOW (SITRL) R248 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:0 = ITExx Channel E to H Trigger Event The ITExx bits are set and cleared by software to define the polarity of the channel xx trigger event 0: The corresponding pending bit will be set on the falling edge of the interrupt line 1: The corresponding pending bit will be set on the rising edge of the interrupt line Note: The ITExx bits must be set to enable the CAN interrupts as the CAN interrupt events are ris- ing edge events. Note: If either a rising or a falling edge occurs on the interrupt lines during a write access to the ITER register, the pending bit will not be set. INTERRUPT PENDING REGISTER HIGH (SIPRH) R249 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:1 = Reserved. Bit 0 = IPI0 Channel I0 Pending bit The IPI0 bit is set by hardware on occurrence of the trigger event. (as specified in the ITR register) and is cleared by hardware on interrupt acknowl- edge. 0 : No interrupt pending 1 : Interrupt pending ---- - - - I M I 0 IMH1 IMH0 IMG1 IMG0 IMF1 IMF0 IME1 IME0 ITEH1 ITEH0 ITEG1 ITEG0 ITEF1 ITEF0 ITEE1 ITEE0 ---- - - - I P I 0

ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) INTERRUPT PENDING REGISTER LOW (SIPRL) R250 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) Bits 7:0 = IPxx Channel E-H Pending bits The IPxx bits are set by hardware on occurrence of the trigger event. (as specified in the ITR regis- ter) and are cleared by hardware on interrupt ac- knowledge. 0 : No interrupt pending 1 : Interrupt pending Note: IPR bits may be set by the user to imple- ment a software interrupt. STANDARD INTERRUPT VECTOR REGISTER (SIVR) R251 - Read/Write Register Page: 60 Reset value: xxx1 1110 (xE) Bits 7:5 = V[7:5] MSBs of Channnel E to L inter- rupt vector address These bits are not initialized by reset. For a repre- sentation of how the full vector is generated from V[7:5], refer to Figure 53. Bits 4:1 = W[3:0] Arbitration Winner Bits These bits are set and cleared by hardware de- pending upon the channel which emerges as a winner as shown in the following table. At the start of interrupt/DMA arbitration (IC0 = 0) the W[3:0] bits are latched. They remain stable through the entire arbitration cycle. Even if a inter- rupt of higher priority comes after the start of int/ DMA arbitration, the SIVR register is not updated. This new request will be ta ken into account in the next arbitration cycle. Bit 0 = Reserved, fixed by hardware to 0. INTERRUPT PRIORITY LEVEL REGISTER HIGH (SIPLRH) R252 - Read/Write Register Page: Page 60 Reset Value : 1111 1111 Bits 1:0 = PL2I, PL1I: INTI0, I1 Priority Level. These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by hardware at 0 for even channels and at 1 for odd channels IPH1 IPH0 IPG1 IPG0 IPF1 IPF0 IPE1 IPE0 V7 V6 V5 W3 W2 W1 W0 0 Interrupt Channel pair W[3:0] INTE0 INTE1 0000 0001 INTF0 INTF1 0010 0011 INTG0 INTG1 0100 0101 INTH0 INTH1 0110 0111 INTI0 1000 -- - --- P L 2 I P L 1 I

Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level. Bits 5:4 = PL2G, PL1G: INTG0, G1 Priority Level. Bits 3:2 = PL2F, PL1F: INTF0, F1 Priority Level. Bits 1:0 = PL2E, PL1E: INTE0, E1 Priority Level. These bits are set and cleared by software. Table 22. PL Bit Assignment Table 23. PL bit Meaning the SIPRL register has been cleared.

Table 25. Standard Interrupt Channel Register map (Page 60)

5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)

5.12.1 Introduction

lines mapped on external pins of the device).

5.12.2 Main Features

pendent. Refer to the device pinout description. Figure 55. Wake-Up Lines / Interrupt Management Unit Block Diagram Note 1: The reset signal on the Stop bit is stronger than the set signal.

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.12.3 Functional Description

5.12.3.1 Interrupt Mode

To configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH) 2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH) 3. Set bit 7 of EIMR (R244 Page 0) and EITR (R242 Page 0) registers of the CPU: so an interrupt coming from one of the 16 lines can be correctly acknowledged 4. Reset the WKUP-INT bit in the WUCTRL regis- ter to disable Wake-up Mode 5. Set the ID1S bit in the WUCTRL register to enable the 16 wake-up lines as external inter- rupt source lines.

5.12.3.2 Wake-up Mode Selection

To configure the 16 lines as wake-up sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH). 2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH). 3. Set, as for Interrupt Mode selection, bit 7 of EIMR and EITR registers only if an interrupt routine is to be executed after a wake-up event. Otherwise, if the wake-up event only restarts the execution of the code from where it was stopped, the INTD1 interrupt channel must be masked. 4. Since the RCCU can generate an interrupt request when exiting from STOP mode, take care to mask it even if the wake-up event is only to restart code execution. 5. Set the WKUP-INT bit in the WUCTRL register to select Wake-up Mode 6. Set the ID1S bit in the WUCTRL register to enable the 16 wake-up lines as external inter- rupt source lines. This is not mandatory if the wake-up event does not require an interrupt response. 7. Write the sequence 1,0,1 to the STOP bit of the WUCTRL register with three consecutive write operations. This is the STOP bit setting sequence. To detect if STOP Mode was entered or not, im- mediately after the STOP bit setting sequence, poll the RCCU EX_STP bit (R242.7, Page 55) and the STOP bit itself.

5.12.3.3 STOP Mode Entry Conditions

Assuming the ST9 is in Run mode: during the STOP bit setting sequence the following cases may occur: Case 1: NMI = 0, wrong STOP bit setting se- quence This can happen if an Interrupt/DMA request is ac- knowledged during the STOP bit setting se- quence. In this case polling the STOP and EX_STP bits will give: STOP = 0, EX_STP = 0 This means that the ST9 did not enter STOP mode due to a bad STOP bit setting sequence: the user must retry the sequence. Case 2: NMI = 0, correct STOP bit setting se- quence In this case the ST9 enters STOP mode. There are two ways to exit STOP mode: 1. A wake-up interrupt (not an NMI interrupt) is acknowledged. That implies: STOP = 0, EX_STP = 1 This means that the ST9 entered and exited STOP mode due to an external wake-up line event. 2. A NMI rising edge woke up the ST9. This implies: STOP = 1, EX_STP = 1 This means that the ST9 entered and exited STOP mode due to an NMI (rising edge) event. The user should clear the STOP bit via software.

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) Case 3: NMI = 1 (NMI kept high during the 3rd write instruction of the sequence), bad STOP bit setting sequence The result is the same as Case 1: STOP = 0, EX_STP = 0 This means that the ST9 did not enter STOP mode due to a bad STOP bit setting sequence: the user must retry the sequence. Case 4: NMI = 1 (NMI kept high during the 3rd write instruction of the sequence), correct STOP bit setting sequence In this case: STOP = 1, EX_STP = 0 This means that the ST9 did not enter STOP mode due to NMI being kept high. The user should clear the STOP bit via software. Note: If NMI goes to 0 before resetting the STOP bit, the ST9 will not enter STOP mode. Case 5: A rising edge on the NMI pin occurs during the STOP bit setting sequence. The NMI interrupt will be acknowledged and the ST9 will not enter STOP mode. This implies: STOP = 0, EX_STP = 0 This means that the ST9 did not enter STOP mode due to an NMI interrupt serviced during the STOP bit setting sequence. At the end of NMI routine, the user must re-enter the sequence: if NMI is still high at the end of the sequence, the ST9 can not enter STOP mode (See “NMI Pin Management” on page 116.). Case 6: A wake-up event on the external wake- up lines occurs during the STOP bit setting se- quence There are two possible cases: 1. Interrupt requests to the CPU are disabled: in this case the ST9 will not enter STOP mode, no interrupt service rout ine will be executed and the program execution continues from the instruction following the STOP bit setting sequence. The status of STOP and EX_STP bits will be again: STOP = 0, EX_STP = 0 The application can determine why the ST9 did not enter STOP mode by polling the pending bits of the external lines (at least one must be at 1). 2. Interrupt requests to CPU are enabled: in this case the ST9 will not enter STOP mode and the interrupt service routi ne will be executed. The status of STOP and EX_STP bits will be again: STOP = 0, EX_STP = 0 The interrupt service routine can determine why the ST9 did not enter STOP mode by polling the pending bits of the external lines (at least one must be at 1). If the MCU really exits from STOP Mode, the RCCU EX_STP bit is still set and must be reset by software. Otherwise, if NM I was high or an Inter- rupt/DMA request was acknowledged during the STOP bit setting sequence, the RCCU EX_STP bit is reset. This means that the MCU has filtered the STOP Mode entry request. The WKUP-INT bit can be used by an interrupt routine to detect and to distinguish events coming from Interrupt Mode or from Wake-up Mode, allow- ing the code to execute different procedures. To exit STOP mode, it is sufficient that one of the 16 wake-up lines (not masked) generates an event: the clock restarts after the delay needed for the oscillator to restart. The same effect is obtained when a rising edge is detected on the NMI pin, which works as a 17th wake-up line. Note: After exiting from STOP Mode, the software can successfully reset the pending bits (edge sen- sitive), even though the corresponding wake-up line is still active (high or low, depending on the Trigger Event register programming); the user must poll the external pin status to detect and dis- tinguish a short event from a long one (for example keyboard input with keystrokes of varying length).

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.12.3.4 NMI Pin Management

On the CPU side, if TLTEV=1 (Top Level Trigger Event, bit 3 of register R246, page 0) then a rising edge on the NMI pin will set the TLIP bit (Top Level Interrupt Pending bit, R230.6). At this point an in- terrupt request to the CPU is given either if TL- NM=1 (Top Level Not Maskable bit, R247.7 - once set it can only be cleared by RESET) or if TLI=1 and IEN=1 (bits R230.5, R230.4). Assuming that the application uses a non-maska- ble Top Level Interrupt (TLNM=1): in this case, whenever a rising edge occurs on the NMI pin, the related service routine will be executed. To service further Top Level Interrupt Requests, it is neces- sary to generate a new rising edge on the external NMI pin. The following summarizes some typical cases: – If the ST9 is in STOP mode and a rising edge on the NMI pin occurs, the ST9 will exit STOP mode and the NMI serv ice routine will be exe- cuted. – If the ST9 is in Run mode and a rising edge oc- curs on the NMI pin: the NMI service routine is executed and then the ST9 restarts the execu- tion of the main program. Now, suppose that the user wants to enter STOP mode with NMI still at 1. The ST9 will not enter STOP mode and it will not execute an NMI routine be- cause there were no transitions on the exter- nal NMI line. – If the ST9 is in run mode and a rising edge on NMI pin occurs during the STOP bit setting se- quence: the NMI interrupt will be acknowledged and the ST9 will not enter STOP mode. At the end of the NMI routine, the user must re-enter the sequence: if NMI is still high at the end of the sequence, the ST9 can not enter STOP mode (see previous case). – If the ST9 is in run mode and the NMI pin is high: if NMI is forced low just before the third write in- struction of the STOP bit setting sequence then the ST9 will enter STOP mode.

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.12.4 Programming Considerations

The following paragraphs give some guidelines for designing an application program.

5.12.4.1 Procedure for Entering/Exiting STOP

1. Program the polarity of the trigger event of external wake-up lines by writing registers WUTRH and WUTRL. 2. Check that at least one mask bit (registers WUMRH, WUMRL) is equal to 1 (so at least one external wake-up line is not masked). 3. Reset at least the unmasked pending bits: this allows a rising edge to be generated on the INTD1 channel when the trigger event occurs (an interrupt on channel INTD1 is recognized when a rising edge occurs). 4. Set the ID1S bit in the WUCTRL register and set the WKUP-INT bit. 5. To generate an interrupt on channel INTD1, bits EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7, Page 0) must be set and bit EIPR.7 must be reset. Bits 7 and 6 of register R245, Page 0 must be written with the desired priority level for interrupt channel INTD1. 6. Reset the STOP bit in register WUCTRL and the EX_STP bit in the CLK_FLAG register (R242.7, Page 55). Refer to the RCCU chapter. 7. To enter STOP mode, write the sequence 1, 0, 1 to the STOP bit in the WUCTRL register with three consecutive write operations. 8. The code to be executed just after the STOP sequence must check the status of the STOP and RCCU EX_STP bits to determine if the ST9 entered STOP mode or not (See “Wake-up Mode Selection” on page 114. for details). If the ST9 did not enter in STOP mode it is necessary to reloop the procedure from the beginning, oth- erwise the procedure continues from next point. 9. Poll the wake-up pending bits to determine which wake-up line caused the exit from STOP mode. 10.Clear the wake-up pending bit that was set.

5.12.4.2 Simultaneous Setting of Pending Bits

It is possible that several simultaneous events set different pending bits. In order to accept subse- quent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this operation allows a rising edge to be generated on the INTD1 line (if there is at least one more pend- ing bit set and not masked) and so to set EIPR.7 bit again. A further interrupt on channel INTD1 will be serviced depending on the status of bit EIMR.7. Two possible situations may arise: 1. The user chooses to reset all pending bits: no further interrup t requests will be generated on channel INTD1. In this case the user has to: – Reset EIMR.7 bit (to avoid generating a spuri- ous interrupt request during the next reset op- eration on the WUPRH register) – Reset WUPRH register using a read-modify- write instruction (AND, BRES, BAND) – Clear the EIPR.7 bit – Reset the WUPRL register using a read-mod- ify-write instruction (AND, BRES, BAND) 2. The user chooses to keep at least one pending bit active: at least one additional interrupt request will be generated on the INTD1 chan- nel. In this case the user has to reset the desired pending bits with a read-modify-write instruction (AND, BRES, BAND). This operation will generate a rising edge on the INTD1 chan- nel and the EIPR.7 bit will be set again. An interrupt on the INTD1 channel will be serviced depending on the status of EIMR.7 bit.

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.12.5 Register Description

WAKE-UP CONTROL REGISTER (WUCTRL) R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 2 = STOP: Stop bit. To enter STOP Mode, write the sequence 1,0,1 to this bit with three consecutive write operations. When a correct sequence is recognized, the STOP bit is set and the RCCU puts the MCU in STOP Mode. The software sequence succeeds only if the following conditions are true: – The NMI pin is kept low, – The WKUP-INT bit is 1, – All unmasked pending bits are reset – At least one mask bit is equal to 1 (at least one external wake-up line is not masked). Otherwise the MCU cannot enter STOP mode, the program code continues executing and the STOP bit remains cleared. The bit is reset by hardware if, while the MCU is in STOP mode, a wake-up interrupt comes from any of the unmasked wake-up lines. The bit is kept high if, during STOP mode, a rising edge on NMI pin wakes up the ST9. In this case the user should reset it by software. The STOP bit is at 1 in the four following cases (See “Wake-up Mode Selection” on page 114. for details): – After the first write instruction of the sequence (a 1 is written to the STOP bit) – At the end of a successful sequence (i.e. after the third write instruction of the sequence) – The ST9 entered and exited STOP mode due to a rising edge on the NMI pin. In this case the EX_STP bit in the CLK_FLAG is at 1 (see RCCU chapter). – The ST9 did not enter STOP mode due to the NMI pin being kept high. In this case RCCU bit EX_STP is at 0 Note: The STOP request generated by the WUIMU (that allows the ST9 to enter STOP mode) is ORed with the external STOP pin (active low). This means that if the external STOP pin is forced low, the ST9 will enter STOP mode independently of the status of the STOP bit. WARNINGS: – Writing the sequence 1,0,1 to the STOP bit will enter STOP mode only if no other register write instructions are executed during the sequence. If Interrupt or DMA requests (which always perform register write operations) are acknowledged dur- ing the sequence, the ST9 will not enter STOP mode: the user must re-enter the sequence to set the STOP bit. – Whenever a STOP request is issued to the MCU, a few clock cycles are needed to enter STOP mode (see RCCU chapter for further details). Hence the execution of the instruction following the STOP bit setting sequence might start before entering STOP mode: if such instruction per- forms a register write operation, the ST9 will not enter in STOP mode. In order to avoid to execute register write instructions after a correct STOP bit setting sequence and before entering the STOP mode, it is mandatory to execute 3 NOP instructions after the STOP bit setting sequence. Refer to Section 13.2 on page 409. Bit 1 = ID1S: Interrupt Channel INTD1 Source. This bit is set and cleared by software. It enables the 16 wake-up lines as external inter- rupt sources. This bit must be set to 1 to enable the wake-up lines. WARNING: To avoid spurious interrupt requests on the INTD1 channel due to changing the inter- rupt source, use this procedure to modify the ID1S bit: 1. Mask the INTD1 interrupt channel (bit 7 of reg- ister EIMR - R244, Page 0 - reset to 0). 2. Set the ID1S bit. 3. Clear the IPD1 interrupt pending bit (bit 7 of register EIPR - R243, Page 0) 4. Remove the mask on INTD1 (bit EIMR.7=1). Bit 0 = WKUP-INT: Wakeup Interrupt. This bit is set and cleared by software. 0: The 16 external wakeup lines can be used to generate interrupt requests 1: The 16 external wake-up lines to work as wake- up sources for exiting from STOP mode ----- S T O P I D 1 S W K U P - I N T

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH ( WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the correspond- ing WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: – If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are gener- ated. – If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. If WUMx is reset, no wake-up events can be gen- erated. WAKE-UP MASK REGISTER LOW (WUMRL) R251 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUM[7:0]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the correspond- ing WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: – If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are gener- ated. – If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. If WUMx is reset, no wake-up events can be gen- erated. WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8 WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0

ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER HIGH (WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity Bits These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set on the falling edge of the input wake-up line . 1: The corresponding WUPx pending bit will be set on the rising edge of the input wake-up line. WAKE-UP TRIGGER REGISTER LOW (WUTRL) R253 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set on the falling edge of the input wake-up line. 1: The corresponding WUPx pending bit will be set on the rising edge of the input wake-up line. WARNING 1. As the external wake-up lines are edge trig- gered, no glitches must be generated on these lines. 2. If either a rising or a falling edge on the external wake-up lines occurs while writing the WUTRLH or WUTRL registers, the pending bit will not be set. WAKE-UP PENDING REGISTER HIGH (WUPRH) R254 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by software. They can be set by software to implement a software inter- rupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occured WAKE-UP PENDING REGISTER LOW (WUPRL) R255 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by software. They can be set by software to implement a software inter- rupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occured Note: To avoid losing a trigger event while clear- ing the pending bits, it is recommended to use read-modify-write instructions (AND, BRES, BAND) to clear them.

5.12.6 Important Note On WUIMU

Refer to Section 13.2 on page 409. WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8 WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0 WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8 WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0

6 ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.1 INTRODUCTION

between peripherals and memory or Register File. isters are allocated for the Pointer and Counter.

6.2 DMA PRIORITY LEVELS

can be acknowledged when the CPL=0. the DMA transaction is not interruptable. Figure 56. DMA Data Transfer

6.3 DMA TRANSACTIONS

that have still to be performed. be located in the Register File. Figure 57. DMA Between Register File and Peripheral

bit DCPR.RM (bit 0 of DCPR) must be cleared. of DAPR) must be cleared or set respectively. if the top level interrupt service is in progress. Figure 58. DMA Between Memory and Peripheral

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d)

6.4 DMA CYCLE TIME

The interrupt and DMA arbitration protocol func- tions completely asynchronously fr om instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al- lows it. A DMA transfer with the Register file requires 8 CPUCLK cycles. A DMA transfer with memory requires 16 CPUCLK cycles, plus any required wait states.

6.5 SWAP MODE

An extra feature which may be found on the DMA channels of some peripherals (e.g. the MultiFunc- tion Timer) is the Swap mode. This feature allows transfer from two DMA tables alternatively. All the DMA descriptors in the Register File are thus dou- bled. Two DMA transaction counters and two DMA address pointers allow the definition of two fully in- dependent tables (they only have to belong to the same space, Register File or Memory). The DMA transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the DMA controller automatically swaps to the other table (table 1) by pointing to the other DMA descriptors. In this case, the DMA mask (DM bit) control bit is not cleared, but the End Of Block interrupt request is generated to allow the optional updating of the first data table (table 0). Until the swap mode is disabled, the DMA control- ler will continue to swap between DMA Table 0 and DMA Table 1. n

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.6 DMA REGISTERS

As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may be different from those found in the peripheral chapters. DMA COUNTER POINTER REGISTER (DCPR) Read/Write Address set by Peripheral Reset value: undefined Bit 7:1 = C[7:1]: DMA Transaction Counter Point- er. Software should write the pointer to the DMA Transaction Counter in these bits. Bit 0 = RM: Register File/Memory Selector. This bit is set and cleared by software. 0: DMA transactions are with memory (see also DAPR.DP) 1: DMA transactions are with the Register File GENERIC EXTERNAL PERIPHERAL INTER- RUPT AND DMA CONTROL (IDCR) Read/Write Address set by Peripheral Reset value: undefined Bit 5 = IP: Interrupt Pending. This bit is set by hardware when the Trigger Event occurs. It is cleared by hardware when the request is acknowledged. It can be set/cleared by software in order to generate/cancel a pending request. 0: No interrupt pending 1: Interrupt pending Bit 4 = DM: DMA Request Mask. This bit is set and cleared by software. It is also cleared when the transaction counter reaches zero (unless SWAP mode is active). 0: No DMA request is generated when IP is set. 1: DMA request is generated when IP is set Bit 3 = IM: End of block Interrupt Mask. This bit is set and cleared by software. 0: No End of block interrupt request is generated when IP is set 1: End of Block interrupt is generated when IP is set. DMA requests depend on the DM bit value as shown in the table below. Bit 2:0 = PRL[2:0]: Source Priority Level. These bits are set and cleared by software. Refer to Section 6.2 DMA PRIO RITY LEVELS for a de- scription of priority levels. DMA ADDRESS POINTER REGISTER (DAPR) Read/Write Address set by Peripheral Reset value: undefined Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer Software should write the pointer to the DMA Ad- dress Register(s) in these bits. Bit 0 = PS: Memory Segment Pointer Selector: This bit is set and cleared by software. It is only meaningful if DCPR.RM=0. 0: The ISR register is used to extend the address of data transferred by DMA (see MMU chapter). 1: The DMASR register is used to extend the ad- dress of data transferred by DMA (see MMU chapter). C7 C6 C5 C4 C3 C2 C1 RM IP DM IM PRL2 PRL1 PRL0 DM IM Meaning

10 A DMA request generated without End of Block

interrupt when IP=1

11 A DMA request generated with End of Block in-

terrupt when IP=1

00 No End of block interrupt or DMA request is

generated when IP=1

01 An End of block Interrupt is generated without

associated DMA request (not used) PRL2 PRL1 PRL0 Source Priority Level 0 0 0 0 Highest 0011 0102 0113 1004 1015 1106 1 1 1 7 Lowest A7 A6 A5 A4 A3 A2 A1 PS

7 RESET AND CLOCK CONTROL UNIT (RCCU)

7.1 INTRODUCTION

manages the internal clock signals. Wake-Up Interrupt Manager Unit description).

7.2 CLOCK CONTROL UNIT

7.2.1 Clock Control Unit Overview

can divide the CLOCK1 input clock signal by two. Figure 59. Clock Control Unit Simplified Block Diagram

Figure 60. ST92F124/F150/F250 Clock Distribution Diagram

7.3 CLOCK MANAGEMENT

This is a System Register (R235, Group E). prescaler factors are handled by this register. This is a Paged Register (R240, Page 55). This is a Paged Register (R242, Page 55). well as control bits for clock selection. This is a Paged Register (R246, Page 55). PLL management is programmed in this register. Figure 61. Clock Control Unit Programming LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode. WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode. XTSTOP (CLK_FLAG) automatically stops the crystal oscillator when the CK_AF clock is present and selected.

7.3.1 PLL Clock Multiplier Programming

cycle signal to the PLL multiplier circuit. programmed to 111, the PLL is switched off. CLK_FLAG Register selects the multiplier clock. in Electrical Characteristics section. below which the functionality is not guaranteed.

7.3.2 PLL Free Running Mode

CONF register (R246, page55). Table 26. Free Running Clock Frequency

7.3.3 CPU Clock Prescaling

for the instruction executer of the ST9 CPU core. ripherals are doing most of the work. level is stretched to replace the missing cycles. Figure 62. CPU Clock Prescaling

7.3.4 Peripheral Clock

7.3.5 Low Power Modes

WFI are illustrated in Figure 63 and Figure 64. actually present on the CK_AF pin. setting the appropriate bits.

7.3.6 Interrupt Generation

ble on the specific device). generated with a high to low transition. Table 27. Summary of Operating Modes using main Crystal Controlled Oscillator WFI If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.

Figure 63. Example of Low Power mode programming in WFI using CK_AF external clock

2 MHz

20 MHz

Figure 64. Example of Low Power mode programming in WFI using CLOCK2/16

12 MHz

125 KHz

ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

7.4 CLOCK CONTROL REGISTERS

MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h) *Note: This register contains bits which relate to other functions; these are described in the chapter dealing with Device Architecture. Only those bits relating to Clock functions are described here. Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2. This bit controls the divide by 2 circuit which oper- ates on CLOCK1. 0: No division of CLOCK1 1: CLOCK1 is internally divided by 2 Bits 4:2 = PRS[2:0]: Clock Prescaling. These bits define the prescaler value used to pres- cale CPUCLK from INTCLK. When these three bits are reset, the CPUCLK is not prescaled, and is equal to INTCLK; in all other cases, the internal clock is prescaled by the value of these three bits plus one. CLOCK CONTROL REGISTER (CLKCTL) R240 - Read/Write Register Page: 55 Reset Value: 0000 0000 (00h) Bit 7 = INT_SEL: Interrupt Selection. 0: The external interrupt channel input signal is se- lected (Reset state) 1: Select the internal RCCU interrupt as the source of the interrupt request Bits 6:4 = Reserved for test purposes Must be kept reset for normal operation. Bit 3 = SRESEN: Software Reset Enable. 0: The HALT instruction turns off the quartz, the PLL and the CCU 1: A Reset is generated when HALT is executed Bit 2 = CKAF_SEL: Alternate Function Clock Se- lect. 0: CK_AF clock not selected 1: Select CK_AF clock Note: To check if the selection has actually oc- curred, check that CKAF_ST is set. If no clock is present on the CK_AF pin, the selection will not occur. Bit 1 = WFI_CKSEL: WFI Clock Select. This bit selects the clock used in Low power WFI mode if LPOWFI = 1. 0: INTCLK during WFI is CLOCK2/16 1: INTCLK during WFI is CK_AF, providing it is present. In effect this bit sets CKAF_SEL in WFI mode WARNING: When the CK_AF is selected as Low Power WFI clock but the crystal is not turned off (R242.4 = 0), after exiting from the WFI, CK_AF will be still selected as syst em clock. In this case, reset the R240.2 bit to switch back to the crystal oscillator clock. Bit 0 = LPOWFI: Low Power mode during Wait For Interrupt. 0: Low Power mode during WFI disabled. When WFI is executed, the CPUCLK is stopped and INTCLK is unchanged 1: The ST9 enters Low Power mode when the WFI instruction is executed. The clock during this state depends on WFI_CKSEL VOLTAGE REGULATOR CONTROL REGISTER (VRCTR) R241 - Read/Write Register Page: 55 Reset Value: 0000 0x00 (0xh) Bit 7-4 = Reserved, must be kept at 0. Bit 3 = VROFF_REG: Voltage Regulator OFF state. This bit is set and cleared by software. 0: Main Voltage Regulator (VR) on 1: Main VR off. In this state the Main Regulator has zero power consumption, and the PLL is auto- matically deselected. This bit must be set for the RTC mode. Bit 2 = Reserved. Bit 1-0 = Reserved, must be kept at 0. - - DIV2 PRS2 PRS1 PRS0 - - INT_S EL --- SRE- SEN CKAF_S EL WFI_CKS EL LPOW FI 0 000 VROFF _REG -0 0

wait for the oscillator to restart correctly. Bit 7 = EX_STP: External Stop flag. CLK_FLAG register, this bit will still be read as 0. Next reading will give 1 as result. Bit 6 = WDGRES: Watchdog reset flag. Bit 5 = SOFTRES: Software Reset Flag. last reset event generator was a Flash LVD reset. Table 28. Reset Flags Bit 4 = XTSTOP: External Stop Enable. Bit 3 = XT_DIV16: CLOCK/16 Selection. is generated when the bit is toggled. lected (depending on bit 0). be selected as system clock source. Bit 0 = CSU_CKSEL: CSU Clock Select. stored in this bit speeds up the PLL’s locking. dependently by the LOCK bit.

out needing to have the LOCK bit equal to ‘1’). Bits 5:4 = MX[1:0]: PLL Multiplication Factor. Refer to Table 29 for multiplier settings. Bits 2:0 = DX[2:0]: PLL output clock divider factor. Refer to Table 30 for divider settings. Table 29. PLL Multiplication Factors Table 30. PLL Divider Factors

000 P L L C L O C K / 1

001 P L L C L O C K / 2

010 P L L C L O C K / 3

011 P L L C L O C K / 4

100 P L L C L O C K / 5

101 P L L C L O C K / 6

110 P L L C L O C K / 7

111 CLOCK2

Figure 65. RCCU General Timing

7.5 CRYSTAL OSCILLATOR

are an inverting circuit, polarised at the trip point. through a feedback resistor. followed in turn by a schmitt-triggered buffer. Section 11 ELECTRICAL CHARACTERISTICS). out or when an external reset is applied. Figure 66. Crystal Oscillator Table 31. Maximum R crystal only (not ceramic resonator). Figure 67. Internal Oscillator Schematic Figure 68. External Clock when using low drive crystals.

5 MHz 80 130

4 MHz 120 200

3 MHz 220 370

Murata Electronics CERALOCK resonators have been tested with the ST92F150 at 3, 3.68, 4 and 5 MHz. These recommended resonators have built-in capacitors (see Table 32). The test circuit is shown in Figure 69. Figure 69. Test Circuit Table 32 shows the recommended conditions at different frequencies. Table 32. Obtained Results mended for standard applications. tailled PCB evaluation regarding layout. apply a coating film to avoid humidity problems.

5 CSTCR5M00G55A-R0 39 39 0

4 CSTCR4M00G55A-R0 39 39 0

3 CSTCC3M00G56A-R0 47 47 0

3.68 CSTCC3M68G56A-R0 47 47 0

7.6 RESET/STOP MANAGER

– A Watchdog end of count condition. ware initiated reset will leave both these bits reset. Up or High impedance input. See Section 7.3. driven low, a Reset cycle is initiated. Figure 70. Oscillator Start-up Sequence and Reset Timing

code (AAh, 55h) written to the appropriate register. chip reset generated by the Timer/Watchdog. control then passes to the user program. depending on the Boot memory contents. Vector located in the lowest two bytes of memory.

7.6.1 Reset Pin Timing

first rising edge of CLOCK1). nal Program memory with wait cycles insertion. the internal voltage supply is stabilized at 3.3V. Figure 71. Recommended Signal to be Applied Figure 72. Reset Pin Input Structure

8 EXTERNAL MEMORY INTERFACE (EXTMI)

8.1 INTRODUCTION

also affected by WCR - R252 Page 0. clock phases, named T1 and T2. ble until the following T1 phase. phase T2 only during an external memory access. Figure 73. Page 21 Registers

ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)

8.2 EXTERNAL MEMORY SIGNALS

The access to external memory is made using the AS, DS, RW, Port 0, Port1, Port9, DS2 and WAIT signals described below. Refer to Figure 76.

8.2.1 AS: Address Strobe

AS (Output, Active low, Tristate) is active during the System Clock high-level phase of each T1 memory cycle: an AS rising edge indicates that Memory Address and Read/Write Memory control signals are valid. A S is released in high-impedance during the bus acknowledge cycle or under the processor control by setting the HIMP bit (MODER.0, R235). Under Reset, AS is held high with an internal weak pull-up. The behavior of this signal is also affected by the MC, ASAF, ETO, LAS[1:0] and UAS[1:0] bits in the EMR1 or EMR2 registers. Refer to the Register description. 8.2.2 DS : Data Strobe DS (Output, Active low, Tristate) is active during the internal clock high-level phase of each T2 memory cycle. During an external memory read cycle, the data on Port 0 must be valid before the DS rising edge. During an external memory write cycle, the data on Port 0 are output on the falling edge of DS and they are valid on the rising edge of DS. When the internal memory is accessed DS is kept high during the whole memory cycle. DS is released in high-impedance during bus ac- knowledge cycle or under processor control by set- ting the HIMP bit (MODER.0, R235). Under Reset status, DS is held high with an internal weak pull-up. The behavior of this signal is also affected by the LDS[2:0], UDS[2:0], DS2EN and MC bits in the EMR1 or WCR register. Refer to the Register de- scription.

8.2.3 RW: Read/Write

RW (Output, Active low, Tristate) identifies the type of memory cycle: RW=”1” identifies a memory read cycle, RW =”0” identifies a memory write cy- cle. It is defined at the beginning of each memory cycle and it remains st able until the following memory cycle. RW is released in high-impedance during bus ac- knowledge cycle or under processor control by setting the HIMP bit (MODER). Under Reset status, RW is held high with an inter- nal weak pull-up. The behavior of this signal is affected by the MC and ETO bits in the EMR1 register. Refer to the Register description.

8.2.4 DS2: Data Strobe 2

This additional Data Strobe pin (Alternate Function Output, Active low, Tristate) allows two different external memories to be connected to the ST9, the upper memory block (A21=1 typically RAM) and the lower memory block (A21=0 typically ROM) without any external logic. The selection between the upper and lower memory blocks depends on the A21 address pin value. The upper memory block is controlled by the DS pin while the lower memory block is controlled by the DS2 pin. When the internal memory is ad- dressed, DS2 is kept high during the whole mem- ory cycle. DS2 is enabled via software as the Alter- nate Function output of the associated I/O port bit. DS2 is released in high-impedance during bus ac- knowledge cycle or under processor control by setting the HIMP bit (MODER.0, r235). The behavior of this signal is also affected by the DS2EN bit in the EMR1 register. Refer to the Reg- ister description.

8.2.5 PORT 0

port, it has the same features as a regular port. tiplexed Address (8 LSB: A[7:0]) / Data bus D[7:0].

8.2.6 PORT 1

port, it has the same features as a regular port.

8.2.7 PORT 9 [7:2]

the 6 MSB of the address (A[21:16]). I²C_1 is in use (when I2CCR.PE bit is set). Figure 74. Application Example (MC=0) Figure 75. Application Example (MC=1)

2 Mbytes

Figure 76. External memory Read/Write with a programmable wait

Figure 77. Effects of DS2EN on the behavior of DS and DS2

8.2.8 WAIT: External Memory Wait

ternal clock cycle is added to the memory cycle. Figure 78. External memory Read/Write sequence with external wait request (WAIT

ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)

8.3 REGISTER DESCRIPTION

EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h) Bit 7 = Reserved. Bit 6 = MC: Mode Control. 0: AS , DS and RW pins have the standard ST9 for- mat. 1: AS pin becomes ALE, Address Load Enable. This signal indicates to the external address latch that a valid address is put on AD[7:0]. When ALE is high, the multiplexed address/data bus AD[7:0] carries the LSBs of the memory ad- dress, which must be latched on the falling edge of this signal. DS becomes OEN, Output ENable: When this signal is low, the external memory should put the data on the multiplexed address/data bus AD[7:0]. The data is sampled by the microcon- troller on the rising edge of the OEN signal. RW pin becomes WEN, Write ENable: when this signal is low, the multiplexed address/data bus AD[7:0] carries the data to be written in the ex- ternal memory. The external memory should sample the data on the rising edge of the WEN signal. Bit 5 = DS2EN: Data Strobe 2 enable. 0: The DS pin is active for any external memory access (lower and upper memory block). The DS2 pin remains high. 1: If the lower memory block is addressed, the DS2 pin outputs the standard DS signal, while the DS pin stays high during the whole memory cycle. If the upper memory block is addressed, DS2 is forced to “1” during the whole memory cycle. Refer to Figure 77 Bit 4 = ASAF: Address Strobe as Alternate Func- tion. Depending on the device, AS can be either a ded- icated pin or a port Alternate Function. This bit is used only in the second case. 0: AS Alternate function disabled. 1: AS Alternate Function enabled. Bit 3 = Reserved, must be kept cleared. Bit 2 = ETO: External toggle. 0: The external memory interface pins (AS, DS, DS2, RW, Port0, Port1, Port9) toggle only if an access to external memory is performed. 1: When the internal memory protection is dis- abled, the above pins (except DS which never toggles during internal memory accesses) tog- gle during both internal and external memory accesses. Bit 1 = BSZ: Bus size. 0: All outputs use the standard low-noise output buffers. 1: P4[7:6], P6[5:4] use high-drive output buffers Bit 0 = Reserved. Caution: External memory must be correctly ad- dressed before and after a write operation on the EMR1 register. For example, if code is fetched from external memory using the standard ST9 ex- ternal memory interface configuration (MC=0), setting the MC bit will cause the device to behave unpredictably. X MC DS2EN ASAF 0 ETO BSZ X

ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0001 1111 (1Fh) Bit 7 = Reserved. Bit 6 = ENCSR: Enable Code Segment Register. This bit affects the ST9 CPU behavior whenever an interrupt request is issued. 0: The CPU works in original ST9 compatibility mode concerning stack frame during interrupts. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. The drawback is that it is not possible for an interrupt service routine to per- form inter-segment calls or jumps: these instruc- tions would update the CSR, which, in this case, is not used (ISR is used instead). The code seg- ment size for all interrupt service routines is thus limited to 64K bytes. 1: If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also re- store CSR from the stack. This approach allows interrupt service routines to access the entire 4Mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. Bit 5 = DPRREM: Data Page Registers remapping 0: The locations of the four MMU (Memory Man- agement Unit) Data Page Registers (DPR0, DPR1, DPR2 and DPR3) are in page 21. 1: The four MMU Data Page Registers are swapped with that of the Data Registers of ports 0-3. Refer to Figure 73 Bit 4 = MEMSEL: Memory Selection. Warning: Must be kept at 1. Bit 3:2 = LAS[1:0]: Lower memory address strobe stretch. These two bits contain the number of wait cycles (from 0 to 3) to add to the System Clock to stretch AS during external lower memory block accesses (A21=”0”). The reset value is 3. - ENCSR DPRREM MEMSEL LAS1 LAS0 UAS1 UAS0

ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) Bit 1:0 = UAS[1:0]: Upper memory address strobe stretch. These two bits contain the number of wait cycles (from 0 to 3) to add to the System Clock to stretch AS during external upper memory block accesses (A21=1). The reset value is 3. Caution: The EMR2 register cannot be written during an interrupt service routine. WAIT CONTROL REGISTER (WCR) R252 - Read/Write Register Page: 0 Reset Value: 0111 1111 (7Fh) Bit 7 = Reserved, forced by hardware to 0. Bit 6 = WDGEN: Watchdog Enable. For a description of this bit, refer to the Timer/ Watchdog chapter. Caution: Clearing this bit has the effect of setting the Timer/Watchdog to Watchdog mode. Unless this is desired, it must be set to “1”. Bit 5:3 = UDS[2:0]: Upper memory data strobe stretch. These bits contain the number of INTCLK cycles to be added automatically to DS for external upper memory block accesses. UDS = 0 adds no addi- tional wait cycles. UDS = 7 adds the maximum 7 INTCLK cycles (reset condition). Bit 2:0 = LDS[2:0]: Lower memory data strobe stretch. These bits contain the number of INTCLK cycles to be added automatically to DS for external lower memory block accesses. LDS = 0 adds no addi- tional wait cycles, LDS = 7 adds the maximum 7 INTCLK cycles (reset condition). Note 1: The number of clock cycles added refers to INTCLK and NOT to CPUCLK. Note 2: The distinction between the Upper memo- ry block and the Lower memory block allows differ- ent wait cycles between the first 2 Mbytes and the second 2 Mbytes, and allows 2 different data strobe signals to be used to access 2 different memories. Typically, the RAM will be located above address 0x200000 and the ROM below address 0x1FFFFF, with different access times (see Figure 74). Caution: The reset value of the Wait Control Reg- ister gives the maximum number of Wait cycles for external memory. To get optimum performance from the ST9, the user should write the UDS[2:0] and LDS[2:0] bits to 0, if the external addressed memories are fast enough.

0 WDGEN UDS2 UDS1 UDS0 LDS2 LDS1 LDS0

9 I/O PORTS

9.1 INTRODUCTION

mitt trigger ports, no selection is possible.

9.2 SPECIFIC PORT CONFIGURATIONS

specific port styles and reset values.

9.3 PORT CONTROL REGISTERS

memory or “accumulator” locations. Figure 79. I/O Register Map

ST92F124/F150/F250 - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- less devices, and can be redefined under software control. Bidirectional ports without weak pull-ups are set in high impedance during reset. To ensure proper levels during reset, these ports must be externally connected to either V DD or V SS through external pull-up or pull-down resistors. Other reset conditions ma y apply in specific ST9 devices.

9.4 INPUT/OUTPUT BIT CONFIGURATION

By programming the control bits PxC0.n and PxC1.n (see Figure 80) it is possible to configure bit Px.n as Input, Output, Bidirectional or Alternate Function Output, where X is the number of the I/O port, and n the bit within the port (n = 0 to 7). When programmed as input, it is possible to select the input level as TTL or CMOS compatible by pro- gramming the relevant PxC2.n control bit. This option is not available on Schmitt trigger ports. The output buffer can be programmed as push- pull or open-drain. A weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). Each pin of an I/O port may assume software pro- grammable Alternate Functions (refer to the de- vice Pin Description and to Section 9.5 ALTER- NATE FUNCTION ARCHITECTURE). To output signals from the ST9 peripherals, the port must be configured as AF OUT. On ST9 devices with A/D Converter(s), configure the ports used for analog inputs as AF IN. The basic structure of the bit Px.n of a general pur- pose port Px is shown in Figure 81. Independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal Data Bus to the Output Master Latches. When the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the Input Latch) is transferred to the internal Data Bus. When Px.n is programmed as an Input: (See Figure 82). – The Output Buffer is forced tristate. – The data present on the I/O pin is sampled into the Input Latch at the beginning of each instruc- tion execution. – The data stored in the Output Master Latch is copied into the Output Slave Latch at the end of the execution of each instruction. Thus, if bit Px.n is reconfigured as an Output or Bidirectional, the data stored in the Outp ut Slave Latch will be re- flected on the I/O pin.

Figure 80. Control Bits Table 33. Port Bit Configuration Table (n = 0, 1... 7; X = port number) (1) For A/D Converter inputs.

9.5 ALTERNATE FUNCTION ARCHITECTURE

9.5.1 Pin Declared as I/O

9.5.2 Pin Declared as an Alternate Function

Figure 86. A/D Input Configuration

9.5.3 Pin Declared as an Alternate Function

Alternate Function Output by software. always be present on the alternate function input.

9.6 I/O STATUS AFTER WFI, HALT AND RESET

10 ON-CHIP PERIPHERALS

10.1 TIMER/WATCHDOG (WDT)

in the first section of the data sheet.

10.1.1 Introduction

Figure 87. Timer/Watchdog Block Diagram

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

10.1.2 Functional Description

10.1.2.1 External Signals

The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to Section 10.1.3.1 on page 159. The WDIN Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – Retriggerable Input Mode The WDOUT output pin can be used to generate a square wave or a Pulse Width Modulated signal. An interrupt, generated when the WDT is running as the 16-bit Timer/Counter, can be used as a Top Level Interrupt or as an interrupt source connected to channel A0 of the external interrupt structure (replacing the INT0 interrupt input). The counter can be driven either by an external clock, or internally by INTCLK divided by 4.

10.1.2.2 Initialisation

The prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be loaded with initial val- ues before starting the Timer/Counter. If this is not done, counting will start with reset values.

10.1.2.3 Start/Stop

The ST_SP bit enables downcounting. When this bit is set, the Timer will start at the beginning of the following instruction. Rese tting this bit stops the counter. If the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the Timer registers (WDTRL, WDTRH). A new constant can be written in the WDTRH, WDTRL, WDTPR registers while the counter is running. The new value of the WDTRH, WDTRL registers will be loaded at the next End of Count (EOC) condition while the new value of the WDTPR register will be effective immediately. End of Count is when the counter is 0. When Watchdog mode is enabled the state of the ST_SP bit is irrelevant.

10.1.2.4 Single/Continuous Mode

The S_C bit allows selection of single or continu- ous mode.This Mode bit can be written with the Timer stopped or running. It is possible to toggle the S_C bit and start the counter with the same in- struction. Single Mode On reaching the End Of Count condition, the Timer stops, reloads the constant, and resets the Start/ Stop bit. Software can check the current status by reading this bit. To restart the Timer, set the Start/ Stop bit. Note: If the Timer constant has been modified dur- ing the stop period, it is reloaded at start time. Continuous Mode On reaching the End Of Count condition, the coun- ter automatically reloads the constant and restarts. It is stopped only if the Start/Stop bit is reset.

10.1.2.5 Input Section

If the Timer/Counter input is enabled (INEN bit) it can count pulses input on the WDIN pin. Other- wise it counts the internal clock/4. For instance, when INTCLK = 24MHz, the End Of Count rate is: 2.79 seconds for Maximum Count (Timer Const. = FFFFh, Prescaler Const. = FFh) 166 ns for Minimum Count (Timer Const. = 0000h, Prescaler Const. = 00h) The Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – Retriggerable Input Mode The mode is configurable in the WDTCR.

10.1.2.6 Event Counter Mode

In this mode the Timer is driven by the external clock applied to the input pin, thus operating as an event counter. The event is defined as a high to low transition of the input signal. Spacing between trailing edges should be at least 8 INTCLK periods (or 333ns with INTCLK = 24MHz). Counting starts at the next input event after the ST_SP bit is set and stops when the ST_SP bit is reset.

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

10.1.2.7 Gated Input Mode

This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input pin is high, the Tim- er counts. When it is low, counting stops. The maximum input pin frequency is equivalent to INTCLK/8.

10.1.2.8 Triggerable Input Mode

The Timer (clocked intern ally by INTCLK/4) is started by the following sequence: – setting the Start-Stop bit, followed by – a High to Low transition on the input pin. To stop the Timer, reset the ST_SP bit.

10.1.2.9 Retriggerable Input Mode

In this mode, the Timer (clocked internally by INTCLK/4) is started by setting the ST_SP bit. A High to Low transition on the input pin causes counting to restart from the initial value. When the Timer is stopped (ST_SP bit reset), a High to Low transition of the input pin has no effect.

10.1.2.10 Timer/Counter Output Modes

Output modes are selected by means of the OUT- EN (Output Enable) and OUTMD (Output Mode) bits of the WDTCR register. No Output Mode (OUTEN = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTEN = “1”, OUTMD = “0”) The Timer outputs a signal with a frequency equal to half the End of Count repetition rate on the WD- OUT pin. With an INTCLK frequency of 20MHz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. Pulse Width Modulated Output Mode (OUTEN = “1”, OUTMD = “1”) The state of the WROUT bit is transferred to the output pin (WDOUT) at the End of Count, and is held until the next End of Count condition. The user can thus generate PWM signals by modifying the status of the WROUT pin between End of Count events, based on software counters decre- mented by the Timer Watchdog interrupt.

10.1.3 Watchdog Timer Operation

This mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. The Watchdog, when enabled, resets the MCU, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. The appli- cation program must be designed so as to correct- ly write to the WDTLR Watchdog register at regu- lar intervals during all phases of normal operation.

10.1.3.1 Hardware Watchdog/Software

The HW0SW1 pin (when available) selects Hard- ware Watchdog or Software Watchdog. If HW0SW1 is held low: – The Watchdog is enabled by hardware immedi- ately after an external reset. (Note: Software re- set or Watchdog reset have no effect on the Watchdog enable status). – The initial counter value (FFFFh) cannot be mod- ified, however software can change the prescaler value on the fly. – The WDGEN bit has no effect. (Note: it is not forced low). If HW0SW1 is held high, or is not present: – The Watchdog can be enabled by resetting the WDGEN bit.

10.1.3.2 Starting the Watchdog

In Watchdog mode the Timer is clocked by INTCLK/4. If the Watchdog is software enabled, the time base must be written in the timer registers before enter- ing Watchdog mode by resetting the WDGEN bit. Once reset, this bit cannot be changed by soft- ware. If the Watchdog is hardware enabled, the time base is fixed by the reset value of the registers. Resetting WDGEN causes the counter to start, re- gardless of the value of the Start-Stop bit. In Watchdog mode, only the Prescaler Constant may be modified. If the End of Count condition is reached a System Reset is generated.

10.1.3.3 Preventing Watchdog System Reset

starts from the preset value. WDTLR register between the writing operations.

10.1.3.4 Non-Stop Operation

Continuous Mode, driven by the internal clock. this context it is meaningless. Figure 88. Watchdog Timer Mode

10.1.4 WDT Interrupts

source for channel A0 of the external interrupt logic. the appropriate interrupt pending bit. Figure 89. Interrupt Sources Table 34. Interrupt Configuration interrupts), only the INTA0 interrupt is taken into account.

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

10.1.5 Register Description

The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional control bits are mapped in the fol- lowing registers on Page 0: Watchdog Mode Enable, (WCR.6) Top Level Interrupt Selection, (EIVR.2) Interrupt A0 Channel Selection, (EIVR.1) Note: The registers containing these bits also con- tain other functions. Only the bits relevant to the operation of the Timer/Watchdog are shown here. Counter Register This 16-bit register (WDTLR, WDTHR) is used to load the 16-bit counter value. The registers can be read or written “on the fly”. TIMER/WATCHDOG HIGH REGISTER (WDTHR) R248 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bits 7:0 = R[15:8] Counter Most Significant Bits. TIMER/WATCHDOG LOW REGISTER (WDTLR) R249 - Read/Write Register Page: 0 Reset value: 1111 1111b (FFh) Bits 7:0 = R[7:0] Counter Least Significant Bits. TIMER/WATCHDOG PRESCALER REGISTER (WDTPR) R250 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bits 7:0 = PR[7:0] Prescaler value. A programmable value from 1 (00h) to 256 (FFh). Warning: In order to prevent incorrect operation of the Timer/Watchdog, the prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be ini- tialised before starting the Timer/Watchdog. If this is not done, counting will start with the reset (un-in- itialised) values. WATCHDOG TIMER CONTROL REGISTER (WDTCR) R251- Read/Write Register Page: 0 Reset value: 0001 0010 (12h) Bit 7 = ST_SP: Start/Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting (see Warning above) Bit 6 = S_C: Single/Continuous. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bits 5:4 = INMD[1:2]: Input mode selection bits. These bits select the input mode: R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN INMD1 INMD2 INPUT MODE 0 0 Event Counter 0 1 Gated Input (Reset value) 1 0 Triggerable Input 1 1 Retriggerable Input

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable. This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: The output is toggled at every End of Count 1: The value of the WROUT bit is transferred to the output pin on every End Of Count if OUTEN=1. Bit 1 = WROUT: Write Out. The status of this bit is transferred to the Output pin when OUTMD is set; it is user definable to al- low PWM output (on Reset WROUT is set). Bit 0 = OUTEN: Output Enable bit. This bit is set and cleared by software. 0: Disable output 1: Enable output WAIT CONTROL REGISTER (WCR) R252 - Read/Write Register Page: 0 Reset value: 0111 1111 (7Fh) Bit 6 = WDGEN: Watchdog Enable (active low). Resetting this bit via software enters the Watch- dog mode. Once reset, it cannot be set any more by the user program. At System Reset, the Watch- dog mode is disabled. Note: This bit is ignored if the Hardware Watchdog option is enabled by pin HW0SW1 (if available). EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h) Bit 2 = TLIS: Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source Bit 1 = IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Warning: To avoid spurious interrupt requests, the IA0S bit should be accessed only when the in- terrupt logic is disabled (i.e. after the DI instruc- tion). It is also necessary to clear any possible in- terrupt pending requests on channel A0 before en- abling this interrupt channel. A delay instruction (e.g. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the IA0S write instruction. Other bits are described in the Interrupt section. x W D G E N xxxxxx xxxxx T L I S I A 0 S x

10.2 STANDARD TIMER (STIM)

10.2.1 Introduction

connected as Alternate Function of an I/O port bit. or Pulse Width Modulated signal. one of the external interrupt channels. Counter Underflow, whenever 00h is reached. Figure 90. Standard Timer Block Diagram

STANDARD TIMER (STIM) STANDARD TIMER (Cont’d)

10.2.2 Functional Description

10.2.2.1 Timer/Counter control

Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the beginning of the next instruc- tion. Resetting this bit will stop the counter. If the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the Standard Timer registers during the stop peri- od. In this case, the new constant will be loaded as soon as counting is restarted. A new constant can be written in STH, STL, STP registers while the counter is running. The new value of the STH and STL registers will be loaded at the next End of Count condition, while the new value of the STP register will be loaded immedi- ately. WARNING: In order to prevent incorrect counting of the Standard Timer, the prescaler (STP) and counter (STL, STH) registers must be initialised before the starting of the timer. If this is not done, counting will start with the reset values (STH=FFh, STL=FFh, STP=FFh). Single/Continuous Mode. The S-C bit (STC.6) selects between the Single or Continuous mode. SINGLE MODE: at the End of Count, the Standard Timer stops, reloads the constant and resets the Start/Stop bit (the user programmer can inspect the timer current status by reading this bit). Setting the Start/Stop bit will restart the counter. CONTINUOUS MODE: At the End of the Count, the counter automatically reloads the constant and re- starts. It is only stopped by resetting the Start/Stop bit. The S-C bit can be written either with the timer stopped or running. It is possible to toggle the S-C bit and start the Standard Timer with the same in- struction.

10.2.2.2 Time Base Generator

The INEN bit in the STC register selects the clock source (refer to RCCU section). When the INEN bit is reset, INTCLK/4 is selected as clock input. When the INEN bit is set, CLOCK2/1024 is select- ed as clock input. In this case, INMD1 and INMD2 bits in the STC register must always be kept at 0 to select the event counter mode. This mode allows the Standard Timer to generate a stable time base independent from PLL programming.

10.2.2.3 Standard Timer Output Modes

OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTMD1 = “0”, OUTMD2 = “1”) The Standard Timer toggles the state of the STOUT pin on every End Of Count condition. With INTCLK = 24MHz, this allows generation of a square wave with a period ranging from 333ns (STP = STH = STL = 00h) to 5.59 seconds (STP = STH = STL = FFh). PWM Output Mode (OUTMD1 = “1”) The value of the OUTMD2 bit is transferred to the STOUT output pin at the End Of Count. This al- lows the user to generate PWM signals, by modi- fying the status of OUTMD2 between End of Count events, based on software counters decremented on the Standard Timer interrupt.

10.2.3 Interrupt Selection

The Standard Timer may generate an interrupt re- quest at every End of Count. Bit 2 of the STC register (INTS) selects the inter- rupt source between the Standard Timer interrupt and the external interrupt pin. Thus the Standard Timer Interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. If INTS is set to “1”, the Standard Timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every End of Count. Note: When enabling or disabling the Standard Timer Interrupt (writing INTS in the STC register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. To avoid this spurious interrupt request, the INTS bit should be accessed only when the interrupt log- ic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. A delay instruction (i.e. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the INTS write instruction.

STANDARD TIMER (STIM) STANDARD TIMER (Cont’d)

10.2.4 Register Description

COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE REGISTER (STL) R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bits 7:0 = ST.[7:0]: Counter Low Byte. Writing to the STH and STL registers allows the user to enter the standard timer constant from 1 (0000h) to 65536 (FFFFh). Reading these regis- ters provides the counter's current value. Thus it is possible to read the counter on-the-fly. STANDARD TIMER PRESCALER REGISTER (STP) R242 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bits 7:0 = STP.[7:0]: Prescaler. The Prescaler value for the Standard Timer is pro- grammed into this register. When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256 STANDARD TIMER CONTROL REGISTER (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h) Bit 7 = ST-SP: Start-Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting Bit 6 = S-C: Single-Continuous Mode Select. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bits 5:4 = INMD[1:2] Bit 3 = INEN These 3 bits select the clock source. Bit 2 = INTS: Interrupt Selection. 0: Standard Timer interrupt enabled 1: Standard Timer interrupt is disabled and the ex- ternal interrupt pin is enabled. Bits 1:0 = OUTMD[1:2]: Output Mode Selection. These bits select the output functions as described in Section 10.2.2.3. ST-SP S-C INMD1 INMD2 INEN INTS OUTMD1 OUTMD2 INMD1 INMD2 INEN Clock input

001 CLOCK2/1024

00 No output mode

01 Square wave output mode

10.3 EXTENDED FUNCTION TIMER (EFT)

10.3.1 Introduction

driven by a programmable prescaler. put waveforms (output compare and PWM).

10.3.2 Main Features

■ Global Timer interrupt (EFTI). The Block Diagram is shown in Figure 91. Table 35. EFT Pin Naming conventions

10.3.3 Functional Description

10.3.3.1 Counter

most significant byte (MSB). least significant byte (LSB). the free running counter to the FFFCh value. pending on the CC[1:0] bits.

Figure 91. Timer Block Diagram

16 BIT

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MSB first, then the LSB value is buffered automatically. This buffered value rema ins unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LSB of the count value at the time of the read. An overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set – EFTIS bit of the CR3 register is set. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done by: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cl eared by accesses to ACLR register. This feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the reset count (MCU awakened by a Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit determines the type of level transition on the external clock pin EXT- CLK that will trigger the free running counter. The counter is synchron ised with the falling edge of INTCLK. At least four falling edges of the INTCLK must oc- cur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the INTCLK fre- quency. LSB is bufferedRead MSBAt t0 Read LSB Returns the buffered LSB value at t0At t0 +Dt Other instructions Beginning of the sequence Sequence completed

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition detected by the ICAPi pin (see figure 5). ICi Rregister is a read-only register. The active transition is software programmable through the IEDGi bit of the Control Register (CRi). Timing resolution is one count of the free running counter: (INTCLK/CC[1:0]). Procedure To use the input capture function select the follow- ing in the CR2 register: – Select the timer clock (CC[1:0] (see Table 36). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit, if ICAP2 is active. And select the following in the CR1/CR3 register: – To enable both ICAP1 & ICAP2 interrupts, set the ICIE bit in the CR1 register (in this case, the IC1IE & IC2IE enable bits are not significant). To enable only one ICAP interrupt, reset the ICIE bit and set the IC1IE (or IC2IE) bit. Note: If ICIE is reset and both IC1IE & IC2IE are set, both interrupts are enabled. In all cases, set the EFTIS bit to enable timer in- terrupts globally – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit if ICAP1 is active. When an input capture occurs: – ICFi bit is set. – The IC iR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 96). – A timer interrupt is generated under the following two conditions : 1. If the ICIE bit (for both ICAP1 & ICAP2) and the EFTIS bit are set. Note: If the ICIE bit is set, the status of the IC1IE/IC2IE bits in the CR3 register is not sig- nificant. 2. If the ICIE bit is reset and the IC1IE and /or IC2IE bits are set and the EFTIS bit is set. Otherwise, the interrupt remains pending until the related enable bits are set. Clearing the Input Capture interrupt request is done by: 1. An access (read or write) to the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Note: After reading the ICiHR register, transfer of input capture data is inhibited until the ICiLR regis- ter is also read. The ICiR register always contains the free running counter value which corresponds to the most re- cent input capture. MS Byte LS Byte ICiRI C iHR IC iLR

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2. This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the free run- ning counter each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (INTCLK/CC[1:0]). Procedure To use the output compare function, select the fol- lowing in the CR2 register: – Set the OC iE bit if an output is needed, the OC- MPi pin is then dedicated to the output compare function. – Select the timer clock (CC[1:0] see Table 36). Select the following in the CR1/CR3 register: – Select the OLVL i bit to be applied to the OCMP pins after the match occurs. – To enable both OCMP1 & OCMP2 interrupts, set the OCIE bit in the CR1 register (in this case, the OC1IE & OC2IE enable bits are not significant). To enable only one OCMP interrupt, reset the OCIE bit and set the OC1IE (or OC2IE) bit. Note: If OCIE is reset and both OC1IE & OC2IE are set, both interrupts are enabled. In all cases, set the EFTIS bit to enable timer in- terrupts globally. When a match is found: – The OCFi bit is set. – The OCMPi pin takes the OLVLi bit value (the OCMPi pin latch is forced low during reset and stays low until a valid compare changes it to the OLVLi level). – A timer interrupt is generated under the following two conditions : 1. If the OCIE bit (for both OCMP1 & OCMP2) and the EFTIS bit are set. Note: If the OCIE bit is set, the status of the OC1IE/OC2IE bits in the CR3 register is not significant. 2. If the OCIE bit is reset and the OC1IE and /or OC2IE bits are set and the EFTIS bit is set. Otherwise, the interrupt remains pending until the related enable bits are set. Clearing the output compare interrupt request is done by: – An access (read or write) to the SR register while the OCFi bit is set. – An access (read or write) to the OC iLR register. Note: After a write access to the OC iHR register, the output compare function is inhibited until the OCiLR register is also written. If the OCiE bit is not set, the OCMP i pin is a gen- eral I/O port and the OLVL i bit will not appear when match is found but an interrupt could be gen- erated if the OCIE bit is set. The value in the 16-bit OC iR register and the OLVLi bit should be changed after each success- ful comparison in order to control an output wave- form or establish a new elapsed timeout. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: ∆t = Desired output compare period (in seconds) INTCLK = Internal clock frequency CC[1:0] = Timer clock prescaler The following procedure is recommended to pre- vent the OCFi bit from being set between the time it is read and the write to the OC iR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). MS Byte LS Byte OCiRO C iHR OC iLR ∆ OCiR = ∆t * INTCLK (CC1.CC0)

Figure 97. Output Compare Block Diagram Figure 98. Output Compare Timing Diagram, Internal Clock Divided by 2

16 BIT FREE RUNNING

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.3.5 Forced Compare Mode

In this section i may represent 1 or 2. The following bits of the CR1 register are used: When the FOLV1 bit is set, the OLVL1 bit is copied to the OCMP1 pin if PWM and OPM are both cleared. When the FOLV2 bit is set, the OLVL2 bit is copied to the OCMP2 pin. The OLVLi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). Notes: – The OCFi bit is not set when FOLVi is set, and thus no interrupt request is generated. – The OCFi bit can be set if OCiR = Counter and an interrupt can be generated if enabled. This can be avoided by writing in the OCiHR register. The output compare function is inhibited till OCiLR is also written. – The Input Capture function works in Forced com- pare mode. To disable it, read the ICiHR register. Input capture will be inhibited till ICiLR is read.

10.3.3.6 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use one pulse mode, select the following in the the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit. And select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedi- cated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 36). Load the OC1R register with the value corre- sponding to the length of the pulse (see the formu- la in Section 10.3.3.7). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin. When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 99). Notes: – The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. – The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set or ICIE is reset and IC1IE is set. The IC1R regis- ter will have the value FFFCh. – When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. – When One Pulse Mode (OPM) and Forced Com- pare 1 mode (FOLV1) bits are set then OPM is the active mode – Forced Compare 2 mode works in OPM – Input Capture 2 function works in OPM – When OC1R = FFFCh in OPM, then a pulse of width FFFCh is generated – If IC1HR register is read in OPM before an active edge of ICAP1, then OPM is inhibited till IC1LR is also read. FOLV2 FOLV1 OLVL2 OLVL1 event occurs Counter is initialized to FFFCh OCMP1 = OLVL2 Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One pulse mode cycle

Figure 99. One Pulse Mode Timing

0010 FFFC

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.3.7 Pulse Width Modulation Mode

Pulse Width Modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode uses the com- plete Output Compare 1 function plus the OC2R register. Procedure To use pulse width modulation mode select the fol- lowing in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful com- parison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful com- parison with OC2R register. And select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock CC[1:0] bits (see Table 36). Load the OC2R register with the value corre- sponding to the period of the signal. Load the OC1R register with the value corre- sponding to the length of the pulse if (OLVL1=0 and OLVL2=1). If OLVL1=1 and OLVL2=0 the length of the pulse is the difference between the OC2R and OC1R registers. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: – t = Desired output compare period (seconds) INTCLK = Internal clock frequency – CC1-CC0 = Timer clock prescaler The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 100). Notes: – After a write instruction to the OC iHR register, the output compare function is inhibited until the OCiLR register is also written. – The OCF1 bit cannot be set by hardware in PWM mode, but the OCF2 bit is set every time the counter matches the OC2R register. – The Input Capture function is available in PWM mode. – When Counter = OC2R, then the OCF2 bit will be set. This can generate an interrupt if OCIE is set or OCIE is reset and OC2IE is set. This interrupt is useful in applications where the pulse-width or period needs to be changed interactively. – When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active mode. – The value loaded in register OC2R must always be greater than the value in register OC1R in or- der to produce meaningful waveforms. Note that 0000h is considerred to be greater than FFFCh or FFFDh or FFFEh or FFFFh. – When OC1R >OC2R, no waveform will be gen- erated. – When OC2R = OC1R, a square waveform will be generated as in Figure 100 – When OC2R is loaded with FFFC (the counter reset value) then no waveform will be generated & the counter will remain stuck at FFFC. – When OC1R is loaded with FFFC (the counter reset value) then the waveform will be generated as in Figure 100 – When FOLV1 bit is set and PWM bit is set, then PWM mode is the active one. But if FOLV2 bit is set then the OLVL2 bit will appear on OCMP2 (when OC2E bit = 1). OCiR Value = t * INTCLK CC[1:0] - 5 Counter Counter is reset to FFFCh OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle

Figure 100. Pulse Width Modulation Mode Timing

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.4 Interrupt Management

The interrupts of the Extended Function Timer are mapped on one of the eight External Interrupt Channels of the microcontroller (refer to the “Inter- rupts” chapter). The three interrupt sources are mapped on the same interrupt channel. To use them, the EFTIS bit must be set) Each External Interrupt Channel has: – A trigger control bit in the EITR register (R242 - Page 0), – A pending bit in the EIPR register (R243 - Page 0), – A mask bit in the EIMR register (R244 - Page 0). Program the interrupt prio rity level using the EI- PLR register (R245 - Page 0). For a description of these registers refer to the “Interrupts” and “DMA” chapters. Using the external interrupt channel for all EFT interrupts To use the interrupt features, perform the following sequence: – Set the priority level of the interrupt channel used (EIPLR register) – Select the interrupt trigger edge as rising edge (set the corresponding bit in the EITR register) – Set the EFTIS bit of the CR3 register to select the peripheral interrupt sources – Set the OCIE (or OC1IE/OC2IE bits) and/or ICIE (or IC1IE/IC2IE bits and/or TOIE bit(s) in the CR1 register to enable interrupts – In the EIPR register, reset the pending bit of the interrupt channel used by the peripheral inter- rupts to avoid any spurious interrupt requests be- ing performed when the mask bit is set – Set the mask bits of the interrupt channels used to enable the MCU to acknowledge the interrupt requests of the peripheral. – Clear all EFT interrupt flags by reading the Sta- tus, Input Capture Low, Output Compare Low and Counter Low Registers. Caution: 1. It is mandatory to clear all EFT interrupt flags simultaneously at least once before exiting an EFT timer interrupt routine (the SR register must = 00h at some point during the interrupt routine), otherwise no interrupts can be issued on that channel anymore. Refer to the following assembly code for an interrupt sequence example. 2. Since a loop statement is needed inside the IT routine, the user must avoid situations where an interrupt event period is narrower than the duration of the interrupt treatment. Otherwise nested interrupt mode must be used to serve higher priority requests.

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Note: A single access (read/write) to the SR regis- ter at the beginning of the interrupt routine is the first step needed to clear all the EFT interrupt flags. In a second step, the lower bytes of the data registers must be accessed if the corresponding flag is set. It is not necessary to access the SR register between these instructions, but it can done. ; INTERRUPT ROUTINE EXAMPLE push R234 ; Save current page spp #28 ; Set EFT page L6: cp R254,#0 ; while E0_SR is not cleared jxz L7 tm R254,#128 ; Check Input Capture 1 flag jxz L2 ; else go to next test ld r1,R241 ; Dummy read to clear IC1LR ; Insert your code here L2: tm R254,#16 ; Check Input Capture 2 flag jxz L3 ; else go to next test ld r1,R243 ; Dummy read to clear IC2LR ; Insert your code here L3: tm R254,#64 ; Check Input Compare 1 flag jxz L4 ; else go to next test ld r1,R249 ; Dummy read to clear OC1LR ; Insert your code here L4: tm R254,#8 ; Check Input Compare 2 flag jxz L5 ; else go to next test ld r1,R251 ; Dummy read to clear OC1LR ; Insert your code here L5: tm R254,#32 ; Check Input Overflow flag jxz L6 ; else go to next test ld r1,R245 ; Dummy read to clear Overflow flag ; Insert your code here jx L6 L7: pop R234 ; Restore current page iret

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d)

10.3.5 Register Description

Each Timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the counter and the alternate counter. Notes: 1. In the register description on the following pag- es, register and page numbers are given using the example of Timer 0. On devices with more than one timer, refer to the device register map for the adresses and page numbers. 2. To work correctly with register pairs, it is strong- ly recommended to use single byte instructions. Do not use word in structions to access any of the 16-bit registers. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) R240 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) R241 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). INPUT CAPTURE 2 HIGH REGISTER (IC2HR) R242 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) R243 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) COUNTER HIGH REGISTER (CHR) R244 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) R245 - Read/Write Register Page: 28 Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) R246 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) R247 - Read/Write Register Page: 28 Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in the SR register. MSB LSB MSB LSB MSB LSB MSB LSB

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) R248 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) R249 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) R250 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) R251 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. MSB LSB MSB LSB MSB LSB MSB LSB

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 1 (CR1) R252 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt enabling depends on the IC1IE and IC2IE bits in the CR3 register. 1: An interrupt is generated whenever the ICF1 or ICF2 bit in the SR register is set. The IC1IE and IC2IE bits in the CR3 register do not have any effect in this case. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt generation depends on the OC1IE and OC2IE bits in the CR3 register. 1: An interrupt is generated whenever the OCF1 or OCF2 bit in the SR register is set. The OC1IE and OC2IE bits in the CR3 rgister do not have any effect in this case. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. 0: No effect. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin. Bit 3 = FOLV1 Forced Output Compare 1. 0: No effect. 1: Forces OLVL1 to be copied to the OCMP1 pin. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OC2E is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 7 = OC1E Output Compare 1 Enable. Bit 6 = OC2E Output Compare 2 Enable. 0: One Pulse Mode is not active. contents of the OC1R register. Bit 4 = PWM Pulse Width Modulation. Bits 3:2 = CC[1:0] Clock Control. Table 36. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. 0: A falling edge triggers the free running counter. 1: A rising edge triggers the free running counter.

00 INTCLK / 4

01 INTCLK / 2

10 INTCLK / 8

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) STATUS REGISTER (SR) R254 - Read Only Register Page: 28 Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) reg- ister. Bit 5 = TOF Timer Overflow. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR reg- ister, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) reg- ister. Bit 2:0 = Reserved, forced by hardware to 0. CONTROL REGISTER 3 (CR3) R255 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) Bit 7 = IC1IE Input Capture1 interrupt enable This bit is not significant if the ICIE bit in the CR1 register is set. 0: ICAP1 interrupt disabled 1: ICAP1 interrupt enabled Bit 6 = OC1IE output compare 1 interrupt enable This bit is not significant if the OCIE bit in the CR1 register is set. 0: OCMP1 interrupt disabled 1: OCMP1 interrupt enabled Bit 5 = IC2IE input capture 2 interrupt enable This bit is not significant if the ICIE bit in the CR1 register is set. 0: ICAP2 interrupt disabled 1: ICAP2 interrupt enabled Bit 4= OC2IE output compare 2 interrupt enable This bit is not significant if the OCIE bit in the CR1 register is set. 0: OCMP2 interrupt disabled 1: OCMP2 interrupt enabled Bits 3:1 = Reserved, must be kept cleared. Bit 0 = EFTIS Global Timer Interrupt Selection. 0: Select External interrupt. 1: Select Global Timer Interrupt. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 IC1IE OC1IE IC2IE OC2IE 0 0 0 EFTIS

Table 37. Extended Function Timer Register Map

10.4 MULTIFUNCTION TIMER (MFT)

10.4.1 Introduction

put clock may be INTCLK/3 or an external source. pare at a fixed repetition rate. combined operating mode is available. some devices to control other on-chip peripherals. Figure 101. MFT Simplified Block Diagram

Figure 102. Detailed Block Diagram

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.2 Functional Description

The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR).

10.4.2.1 Trigger Events

A trigger event may be generated by software (by setting either the CP0 or the CP1 bits in the T_FLAGR register) or by an external source which may be programmed to respond to the rising edge, the falling edge or both by programming bits A0- A1 and B0-B1 in the T_ICR register. This trigger event can be used to perform a capture or a load, depending on the Timer mode (configured using the bits in Table 41). An event on the TxINA input or setting the CP0 bit triggers a capture to, or a load from the REG0R register (except in Bicapture mode, see Section 10.4.2.11). An event on the TxINB input or setting the CP1 bit triggers a capture to, or a load from the REG1R register. In addition, in the special case of "Load from REG0R and monitor on REG1R", it is possible to use the TxINB input as a trigger for REG0R."

10.4.2.2 One Shot Mode

When the counter generates an overflow (in up- count mode), or an underflow (in down-count mode), that is to say when an End Of Count condi- tion is reached, the counter stops and no counter reload occurs. The counter may only be restarted by an external trigger on TxINA or B or a by soft- ware trigger on CP0 only. One Shot Mode is en- tered by setting the CO bit in TMR.

10.4.2.3 Continuous Mode

Whenever the counter reaches an End Of Count condition, the counting sequence is automatically restarted and the counter is reloaded from REG0R (or from REG1R, when se lected in Biload Mode). Continuous Mode is entered by resetting the C0 bit in TMR.

10.4.2.4 Triggered And Retriggered Modes

A triggered event may be generated by software (by setting either the CP0 or the CP1 bit in the T_FLAGR register), or by an external source which may be programmed to respond to the rising edge, the falling edge or both, by programming bits A0-A1 and B0-B1 in T_ICR. In One Shot and Triggered Mode, every trigger event arriving before an End Of Count, is masked. In One Shot and Retriggered Mode, every trigger received while the counter is running, automatical- ly reloads the counter from REG0R. Triggered/Re- triggered Mode is set by the REN bit in TMR. The TxINA input refers to REG0R and the TxINB input refers to REG1R. WARNING. If the Triggered Mode is selected when the counter is in Continuous Mode, every trigger is disabled, it is not therefore possible to synchronise the counting cycle by hardware or software.

10.4.2.5 Gated Mode

In this mode, counting takes place only when the external gate input is at a logic low level. The se- lection of TxINA or TxINB as the gate input is made by programming the IN0-IN3 bits in T_ICR.

10.4.2.6 Capture Mode

The REG0R and REG1R registers may be inde- pendently set in Capture Mode by setting RM0 or RM1 in TMR, so that a capture of the current count value can be performed either on REG0R or on REG1R, initiated by software (by setting CP0 or CP1 in the T_FLAGR register) or by an event on the external input pins. WARNING. Care should be taken when two soft- ware captures are to be performed on the same register. In this case, at least one instruction must be present between the first CP0/CP1 bit set and the subsequent CP0/CP1 bit reset instructions.

10.4.2.7 Up/Down Mode

The counter can count up or down depending on the state of the UDC bit (Up/Down Count) in TCR, or on the configuration of the external input pins, which have priority over UDC (see Input pin as- signment in T_ICR). The UDCS bit returns the counter up/down current status (see also the Up/ Down Autodiscrimination mode in the Input Pin Assignment Section).

10.4.2.8 Free Running Mode

10.4.2.9 Monitor Mode

10.4.2.10 Autoclear Mode

Mode, through the CCP0 and CCMP0 bits in TCR.

10.4.2.11 Bi-value Mode

Table 38. Bi-value Modes REG0R as a reload register (RM0 reset in TMR). of BM bit, the first reload is always from REG0R).

configured by the A0 bit in the T_FLAGR register.

10.4.2.12 Parallel Mode

nected to the system clock line. are driven by the same frequency in parallel mode.

10.4.2.13 Autodiscriminator Mode

effect in this configuration. Figure 103. Parallel Mode Description

10.4.3 Input Pin Assignment

Table 39. Input Pin Function twice the prescaler clock period (INTCLK/3). the system clock (INTCLK) period.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.3.1 TxINA = I/O - TxINB = I/O

Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR regis- ter.

10.4.3.2 TxINA = I/O - TxINB = Trigger

The signal applied to input pin B acts as a trigger signal on REG1R register. The prescaler clock is internally generated and the up/down selection may be made only by software via the UDC (Soft- ware Up/Down) bit in the TCR register.

10.4.3.3 TxINA = Gate - TxINB = I/O

The signal applied to input pin A acts as a gate sig- nal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). The counter clock is internally generated and the up/down con- trol may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

10.4.3.4 TxINA = Gate - TxINB = Trigger

Both input pins A and B are connected to the timer, with the resulting effect of combining the actions relating to the previously described configurations. 10.4.3.5 TxINA = I/O - TxINB = Ext. Clock The signal applied to input pin B is used as the ex- ternal clock for the prescaler. The up/down selec- tion may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

10.4.3.6 TxINA = Trigger - TxINB = I/O

The signal applied to input pin A acts as a trigger for REG0R, initiating the action for which the reg- ister was programmed (i.e. a reload or capture). The prescaler clock is internally generated and the up/down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR register. (*) The timer is in One shot mode and REGOR in Reload mode 10.4.3.7 TxINA = Gate - TxINB = Ext. Clock The signal applied to input pin B, gated by the sig- nal applied to input pin A, acts as external clock for the prescaler. The up/down control may be made only by software action through the UDC bit in the TCR register.

10.4.3.8 TxINA = Trigger - TxINB = Trigger

The signal applied to input pin A (or B) acts as trig- ger signal for REG0R (or REG1R), initiating the action for which the register has been pro- grammed. The counter clock is internally generat- ed and the up/down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.3.9 TxINA = Clock Up - TxINB = Clock

The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are external. Setting the UDC bit in the TCR register has no effect in this configuration, and input pin B has priority on input pin A.

10.4.3.10 TxINA = Up/Down - TxINB = Ext Clock

An High (or Low) level applied to input pin A sets the counter in the up (or down) count mode, while the signal applied to input pin B is used as clock for the prescaler. Setting the UDC bit in the TCR reg- ister has no effect in this configuration.

10.4.3.11 TxINA = Trigger Up - TxINB = Trigger

Up/down control is performed through both input pins A and B. A edge on input pin A sets the up count mode, while a edge on input pin B (which has priority on input pin A) sets the down count mode. The counter clock is internally generated, and setting the UDC bit in the TCR register has no effect in this configuration.

10.4.3.12 TxINA = Up/Down - TxINB = I/O

An High (or Low) level of the signal applied on in- put pin A sets the counter in the up (or down) count mode. The counter clock is internally generated. Setting the UDC bit in the TCR register has no ef- fect in this configuration.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.3.13 Autodiscrimination Mode

The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the counter clock are both external. Thus, if the ris- ing edge of TxINB arrives when TxINA is at a low level, the timer is incremented (no action if the ris- ing edge of TxINB arrives when TxINA is at a high level). If the falling edge of TxINB arrives when TxINA is at a low level, the timer is decremented (no action if the falling edge of TxINB arrives when TxINA is at a high level). Setting the UDC bit in the TCR register has no ef- fect in this configuration. 10.4.3.14 TxINA = Trigger - TxINB = Ext. Clock The signal applied to input pin A acts as a trigger signal on REG0R, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin B is used as the clock for the prescaler. (*) The timer is in One shot mode and REG0R in reload mode 10.4.3.15 TxINA = Ext. Clock - TxINB = Trigger The signal applied to input pin B acts as a trigger, performing a capture on REG1R, while the signal applied to input pin A is used as the clock for the prescaler.

10.4.3.16 TxINA = Trigger - TxINB = Gate

The signal applied to input pin A acts as a trigger signal on REG0R, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin B acts as a gate signal for the internal clock (i.e. the counter runs only when the gate signal is at a low level).

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.4 Output Pin Assignment

Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for the outputs and the actions to be per- formed. Each of the two output pins can be driven from any of the three possible sources: – Compare Register 0 event logic – Compare Register 1 event logic – Overflow/Underflow event logic. Each of these three sources can cause one of the following four actions on any of the two outputs: – Nop – Set – Reset – Toggle Furthermore an On Chip Event signal can be driv- en by two of the three sources: the Over/Under- flow event and Compare 0 event by programming the CEV bit of the OACR register and the OEV bit of OBCR register respectively. This signal can be used internally to synchronise another on-chip pe- ripheral. Output Waveforms Depending on the programming of OACR and OB- CR, the following example waveforms can be gen- erated on TxOUTA and TxOUTB pins. For a configuration where TxOUTA is driven by the Over/Underflow (OUF) and the Compare 0 event (CM0), and TxOUTB is driven by the Over/Under- flow and Compare 1 event (CM1): OACR is programmed with TxOUTA preset to “0”, OUF sets TxOUTA, CM0 resets TxOUTA and CM1 does not affect the output. OBCR is programmed with TxOUTB preset to “0”, OUF sets TxOUTB, CM1 resets TxOUTB while CM0 does not affect the output. For a configuration where TxOUTA is driven by the Over/Underflow, by Compare 0 and by Compare 1; TxOUTB is driven by both Compare 0 and Com- pare 1. OACR is programmed with TxOUTA pre- set to “0”. OUF toggles Output 0, as do CM0 and CM1. OBCR is programmed with TxOUTB preset to “1”. OUF does not affect the output; CM0 resets TxOUTB and CM1 sets it. OACR = [101100X0] OBCR = [111000X0] T0OUTA T0OUTB OUF COMP1 OUF COMP1 OUF COMP0 OUF COMP0 OACR = [010101X0] OBCR = [100011X1] T0OUTA T0OUTB COMP1 COMP1 OUF OUF COMP0 COMP0 COMP0 COMP0 COMP1 COMP1

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF sets TxOUTA while CM0 resets it, and CM1 has no effect. OBCR is programmed with Tx- OUTB preset to “1”. OUF toggles TxOUTB, CM1 sets it and CM0 has no effect. For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by Compare 0 and 1. OACR is pro- grammed with TxOUTA preset to “0”. OUF sets TxOUTA, CM0 resets it and CM1 has no effect. OBCR is programmed with TxOUTB preset to “0”. OUF has no effect, CM0 sets TxOUTB and CM1 toggles it. Output Waveform Samples In Biload Mode TxOUTA is programmed to monitor the two time intervals, t1 and t2, of the Biload Mode, while Tx- OUTB is independent of the Over/Underflow and is driven by the different values of Compare 0 and Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF toggles the output and CM0 and CM1 do not affect TxOUTA. OBCR is programmed with TxOUTB preset to “0”. OUF has no effect, while CM1 resets TxOUTB and CM0 sets it. Depending on the CM1/CM0 values, three differ- ent sample waveforms have been drawn based on the above mentioned configuration of OBCR. In the last case, with a different programmed value of OBCR, only Compare 0 drives TxOUTB, toggling the output. Note (*) Depending on the CMP1R/CMP0R values OACR = [101100X0] OBCR = [000111X0] T0OUTA T0OUTB OUF OUFCOMP0 COMP0 COMP0 COMP0 COMP1 COMP1

10.4.5 Interrupt and DMA

10.4.5.1 Timer Interrupt

Table 40. Timer Interrupt Structure MR.7) which masks all interrupts.

10.4.5.2 Timer DMA

mask bits in the IDMR register.

10.4.5.3 DMA Pointers

Figure 104. Pointer Mapping for Transfers

Figure 105. Pointer Mapping for Register to

10.4.5.4 DMA Transaction Priorities

gardless of the other Timer internal sources, i.e. curs between the two byte transfers.

10.4.5.5 DMA Swap Mode

condition occurs, the block transfer is completed. related to the correct channel).

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

10.4.5.6 DMA End Of Block Interrupt Routine

An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two channels. As a consequence, they will be serviced only when no DMA request occurs, and will be subject to a possible OUF Interrupt request, which has higher priority. The following is a typical EOB procedure (with swap mode enabled): – Test Toggle bit and Jump. – Reload Pointers (odd or even depending on tog- gle bit status). – Reset EOB bit: this bit must be reset only after the old pair of pointers has been restored, so that, if a new EOB condition occurs, the next pair of pointers is ready for swapping. – Verify the software protection condition (see Section 10.4.5.7). – Read the corresponding Overrun bit: this con- firms that no DMA request has been lost in the meantime. – Reset the corresponding pending bit. – Reenable DMA with the corresponding DMA mask bit (must always be done after resetting the pending bit) – Return. WARNING: The EOB bits are read/write only for test purposes. Writing a logical “1” by software (when the SWEN bit is set) will cause a spurious interrupt request. These bits are normally only re- set by software.

10.4.5.7 DMA Software Protection

A second EOB condition may occur before the first EOB routine is completed, this would cause a not yet updated pointer pair to be addressed, with con- sequent overwriting of memory. To prevent these errors, a protection mechanism is provided, such that the attempted setting of the EOB bit before it has been reset by software will cause the DMA mask on that channel to be reset (DMA disabled), thus blocking any further DMA operation. As shown above, this mask bit should always be checked in each EOB routine, to ensure that all DMA transfers are properly served.

10.4.6 Register Description

Note: In the register description on the following pages, register and page numbers are given using the example of Timer 0. On devices with more than one timer, refer to the device register map for the adresses and page numbers.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (MSB). CAPTURE LOAD 0 LOW REGISTER (REG0LR) R241 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (LSB). CAPTURE LOAD 1 HIGH REGISTER (REG1HR) R242 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (MSB). CAPTURE LOAD 1 LOW REGISTER (REG1LR) R243 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (LSB). COMPARE 0 HIGH REGISTER (CMP0HR) R244 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the MSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 0 LOW REGISTER (CMP0LR) R245 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the LSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 1 HIGH REGISTER (CMP1HR) R246 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the MSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 1 LOW REGISTER (CMP1LR) R247 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the LSB of the 16-bit value to be compared to the Up/Down counter content. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 = CEN: Counter enable. This bit is ANDed with the Global Counter Enable bit (GCEN) in the CICR register (R230). The GCEN bit is set after the Reset cycle. 0: Stop the counter and prescaler 1: Start the counter and prescaler (without reload). Note: Even if CEN=0, capture and loading will take place on a trigger event. Bit 6 = CCP0: Clear on capture. 0: No effect 1: Clear the counter and reload the prescaler on a REG0R or REG1R capture event Bit 5 = CCMP0: Clear on Compare. 0: No effect 1: Clear the counter and reload the prescaler on a CMP0R compare event Bit 4 = CCL: Counter clear. This bit is reset by hardware after being set by software (this bit always returns “0” when read). 0: No effect 1: Clear the counter without generating an inter- rupt request Bit 3 = UDC: Up/Down software selection. If the direction of the counter is not fixed by hard- ware (TxINA and/or TxINB pins, see par. 10.3) it can be controlled by software using the UDC bit. 0: Down counting 1: Up counting Bit 2 = UDCS: Up/Down count status. This bit is read only and indicates the direction of the counter. 0: Down counting 1: Up counting Bit 1 = OF0: OVF/UNF state. This bit is read only. 0: No overflow or underflow occurred 1: Overflow or underflow occurred during a Cap- ture on Register 0 Bit 0 = CS Counter Status. This bit is read only and indicates the status of the counter. 0: Counter halted 1: Counter running CEN CCP0 CCMP0 CCL UDC UDCS OF0 CS

Bit 7 = OE1: Output 1 enable. Bit 6 = OE0: Output 0 enable. 1: Enable the Output 0 (TxOUTA pin). to select the timer operating mode (see Table 41). Table 41. Timer Operating Modes Bit 2 = ECK Timer clock control. Bit 1 = REN: Retrigger mode. Bit 0 = CO: Continous/One shot mode.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL REGISTER (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bits 7:4 = IN[3:0]: Input pin function. These bits are set and cleared by software. Bits 3:2 = A[0:1]: TxINA Pin event. These bits are set and cleared by software. Bits 1:0 = B[0:1]: TxINB Pin event. These bits are set and cleared by software. PRESCALER REGISTER (PRSR) R251 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register holds the preset value for the 8-bit prescaler. The PRSR content may be modified at any time, but it will be l oaded into the prescaler at the following prescaler underflow, or as a conse- quence of a counter reload (either by software or upon external request). Following a RESET condition, the prescaler is au- tomatically loaded with 00h, so that the prescaler divides by 1 and the ma ximum counter clock is generated (Crystal oscillator clock frequency divid- ed by 6 when MODER.5 = DIV2 bit is set). The binary value programmed in the PRSR regis- ter is equal to the divider value minus one. For ex- ample, loading PRSR with 24 causes the prescal- er to divide by 25. IN3 IN2 IN1 IN0 A0 A1 B0 B1 IN[3:0] bits TxINA Pin Function TxINB Input Pin Function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used Gate Gate not used Trigger Gate Trigger Clock Up Up/Down Trigger Up Up/Down Autodiscr. Trigger Ext. Clock Trigger not used Trigger not used Trigger Ext. Clock not used Ext. Clock Trigger Clock Down Ext. Clock Trigger Down not used Autodiscr. Ext. Clock Trigger Gate A0 A1 TxINA Pin Event No operation Falling edge sensitive Rising edge sensitive Rising and falling edges B0 B1 TxINB Pin Event No operation Falling edge sensitive Rising edge sensitive Rising and falling edges P7 P6 P5 P4 P3 P2 P1 P0

Bits 7:6 = C0E[0:1]: COMP0 action bits. list of actions that can be configured. Bits 5:4 = C1E[0:1]: COMP1 action bits. list of actions that can be configured. Bits 3:2 = OUE[0:1]: OVF/UNF action bits. actions that can be configured. Table 42. Output A Action Bits – xx stands for C0, C1 or OU. Bit 1 = CEV: On-Chip event on CMP0R. This bit is set and cleared by software. Bit 0 = OP: TxOUTA preset value.

00 S e t

10 R e s e t

11 N O P

Bits 7:6 = C0E[0:1]: COMP0 Action Bits. the list of actions that can be configured. Bits 5:4 = C0E[0:1]: COMP1 Action Bits. the list of actions that can be configured. Bits 3:2 = OUE[0:1]: OVF/UNF Action Bits. for the list of actions that can be configured. Table 43. Output B Action Bits – xx stands for C0, C1 or OU. Bit 1 = OEV: On-Chip event on OVF/UNF. This bit is set and cleared by software. Bit 0 = OP: TxOUTB preset value.

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 = CP0: Capture 0 flag. This bit is set by hardware after a capture on REG0R register. An interrupt is generated de- pending on the value of the GTIEN, CP0I bits in the IDMR register and the A0 bit in the T_FLAGR register. The CP0 bit must be cleared by software. Setting by software acts as a software load/cap- ture to/from the REG0R register. 0: No Capture 0 event 1: Capture 0 event occurred Bit 6 = CP1: Capture 1 flag. This bit is set by hardware after a capture on REG1R register. An interrupt is generated de- pending on the value of the GTIEN, CP0I bits in the IDMR register and the A0 bit in the T_FLAGR register. The CP1 bit must be cleared by software. Setting by software acts as a capture event on the REG1R register, except when in Bicapture mode. 0: No Capture 1 event 1: Capture 1 event occurred Bit 5 = CM0: Compare 0 flag. This bit is set by hardware after a successful com- pare on the CMP0R register. An interrupt is gener- ated if the GTIEN and CM0I bits in the IDMR reg- ister are set. The CM0 bit is cleared by software. 0: No Compare 0 event 1: Compare 0 event occurred Bit 4 = CM1: Compare 1 flag. This bit is set after a successful compare on CMP1R register. An interrupt is generated if the GTIEN and CM1I bits in the IDMR register are set. The CM1 bit is cleared by software. 0: No Compare 1 event 1: Compare 1 event occurred Bit 3 = OUF: Overflow/Underflow. This bit is set by hardware after a counter Over/ Underflow condition. An interrupt is generated if GTIEN and OUI=1 in the IDMR register. The OUF bit is cleared by software. 0: No counter overflow/underflow 1: Counter overflow/underflow Bit 2 = OCP0: Overrun on Capture 0. This bit is set by hardware when more than one INT/DMA requests occur before the CP0 flag is cleared by software or whenever a capture is sim- ulated by setting the CP0 flag by software. The OCP0 flag is cleared by software. 0: No capture 0 overrun 1: Capture 0 overrun Bit 1 = OCM0: Overrun on compare 0. This bit is set by hardware when more than one INT/DMA requests occur before the CM0 flag is cleared by software.The OCM0 flag is cleared by software. 0: No compare 0 overrun 1: Compare 0 overrun Bit 0 = A0: Capture interrupt function. This bit is set and cleared by software. 0: Configure the capture interrupt as an OR func- tion of REG0R/REG1R captures 1: Configure the capture interrupt as an AND func- tion of REG0R/REG1R captures Note: When A0 is set, both CP0I and CP1I in the IDMR register must be set to enable both capture interrupts. CP0 CP1 CM0 CM1 OUF OCP0 OCM0 A0

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 = GTIEN: Global timer interrupt enable. This bit is set and cleared by software. 0: Disable all Timer interrupts 1: Enable all timer Timer Interrupts from enabled sources Bit 6 = CP0D: Capture 0 DMA mask. This bit is set by software to enable a Capt0 DMA transfer and cleared by hardware at the end of the block transfer. 0: Disable capture on REG0R DMA 1: Enable capture on REG0R DMA Bit 5 = CP0I: Capture 0 interrupt mask. 0: Disable capture on REG0R interrupt 1: Enable capture on REG0R interrupt (or Capt0 DMA End of Block interrupt if CP0D=1) Bit 4 = CP1I: Capture 1 interrupt mask. This bit is set and cleared by software. 0: Disable capture on REG1R interrupt 1: Enable capture on REG1R interrupt Bit 3 = CM0D: Compare 0 DMA mask. This bit is set by software to enable a Comp0 DMA transfer and cleared by hardware at the end of the block transfer. 0: Disable compare on CMP0R DMA 1: Enable compare on CMP0R DMA Bit 2 = CM0I: Compare 0 Interrupt mask. This bit is set and cleared by software. 0: Disable compare on CMP0R interrupt 1: Enable compare on CMP0R interrupt (or Comp0 DMA End of Block interrupt if CM0D=1) Bit 1 = CM1I: Compare 1 Interrupt mask. This bit is set and cleared by software. 0: Disable compare on CMP1R interrupt 1: Enable compare on CMP1R interrupt Bit 0 = OUI: Overflow/Underflow interrupt mask. This bit is set and cleared by software. 0: Disable Overflow/Underflow interrupt 1: Enable Overflow/Underflow interrupt DMA COUNTER POINTER REGISTER (DCPR) R240 - Read/Write Register Page: 9 Reset value: undefined Bits 7:2 = DCP[7:2]: MSBs of DMA counter regis- ter address. These are the most significant bits of the DMA counter register address programmable by soft- ware. The DCP2 bit may also be toggled by hard- ware if the Timer DMA section for the Compare 0 channel is configured in Swap mode. Bit 1 = DMA-SRCE: DMA source selection. This bit is set and cleared by hardware. 0: DMA source is a Capture on REG0R register 1: DMA destination is a Compare on CMP0R reg- ister Bit 0 = REG/MEM: DMA area selection. This bit is set and cleared by software. It selects the source and destination of the DMA area 0: DMA from/to memory 1: DMA from/to Register File GTIEN CP0D CP0I CP1I CM0D CM0I CM1I OUI DCP7 DCP6 DCP5 DCP4 DCP3 DCP2 DMA SRCE REG/ MEM

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined Bits 7:2 = DAP[7:2]: MSB of DMA address regis- ter location. These are the most significant bits of the DMA ad- dress register location programmable by software. The DAP2 bit may also be toggled by hardware if the Timer DMA section for the Compare 0 channel is configured in Swap mode. Note: During a DMA transfer with the Register File, the DAPR is not used; however, in Swap mode, DAP2 is used to point to the correct table. Bit 1 = DMA-SRCE: DMA source selection. This bit is fixed by hardware. 0: DMA source is a Capture on REG0R register 1: DMA destination is a Compare on the CMP0R register Bit 0 = PRG/DAT: DMA memory selection. This bit is set and cleared by software. It is only meaningful if DCPR.REG/MEM=0. 0: The ISR register is used to extend the address of data transferred by DMA (see MMU chapter). 1: The DMASR register is used to extend the ad- dress of data transferred by DMA (see MMU chapter). INTERRUPT VECTOR REGISTER (T_IVR) R242 - Read/Write Register Page: 9 Reset value: xxxx xxx0 This register is used as a vector, pointing to the 16-bit interrupt vectors in memory which contain the starting addresses of the three interrupt sub- routines managed by each timer. Only one Interrupt Vector Register is available for each timer, and it is able to manage three interrupt groups, because the 3 least significant bits are fixed by hardware depending on the group which generated the interrupt request. In order to determine which request generated the interrupt within a group, the T_FLAGR register can be used to check the relevant interrupt source. Bits 7:3 = V[4:0]: MSB of the vector address. These bits are user programmable and contain the five most significant bits of the Timer interrupt vec- tor addresses in memory. In any case, an 8-bit ad- dress can be used to indicate the Timer interrupt vector locations, because they are within the first 256 memory locations (see Interrupt and DMA chapters). Bits 2:1 = W[1:0]: Vector address bits. These bits are equivalent to bit 1 and bit 2 of the Timer interrupt vector addresses in memory. They are fixed by hardware, depending on the group of sources which generated the interrupt request as follows:. Bit 0 = This bit is forced by hardware to 0. DAP7 DAP6 DAP5 DAP4 DAP3 DAP2 DMA SRCE PRG /DAT REG/MEM PRG/DAT DMA Source/Destination ISR register used to address memory DMASR register used to address memory Register file Register file V4 V3 V2 V1 V0 W1 W0 0 W1 W0 Interrupt Source Overflow/Underflow even interrupt Not available Capture event interrupt Compare event interrupt

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) Bit 7 = CPE: Capture 0 EOB. This bit is set by hardware when the End Of Block condition is reached during a Capture 0 DMA op- eration with the Swap mode enabled. When Swap mode is disabled (SWEN bit = “0”), the CPE bit is forced to 1 by hardware. 0: No end of block condition 1: Capture 0 End of block Bit 6 = CME: Compare 0 EOB. This bit is set by hardware when the End Of Block condition is reached during a Compare 0 DMA op- eration with the Swap mode enabled. When the Swap mode is disabled (SWEN bit = “0”), the CME bit is forced to 1 by hardware. 0: No end of block condition 1: Compare 0 End of block Bit 5 = DCTS: DMA capture transfer source. This bit is set and cleared by software. It selects the source of the DMA operation related to the channel associated with the Capture 0. Note: The I/O port source is available only on spe- cific devices. 0: REG0R register 1: I/O port. Bit 4 = DCTD: DMA compare transfer destination. This bit is set and cleared by software. It selects the destination of the DMA operation related to the channel associated with Compare 0. Note: The I/O port destination is available only on specific devices. 0: CMP0R register 1: I/O port Bit 3 = SWEN: Swap function enable. This bit is set and cleared by software. 0: Disable Swap mode 1: Enable Swap mode for both DMA channels. Bits 2:0 = PL[2:0]: Interrupt/DMA priority level. With these three bits it is possible to select the In- terrupt and DMA priority level of each timer, as one of eight levels (see Interrupt/DMA chapter). I/O CONNECTION REGISTER (IOCR) R248 - Read/Write Register Page: 9 Reset value: 1111 1100 (FCh) Bits 7:2 = not used. Bit 1 = SC1: Select connection odd. This bit is set and cleared by software. It selects if the TxOUTA and TxINA pins for Timer 1 and Timer 3 are connected on-chip or not. 0: T1OUTA / T1INA and T3OUTA/ T3INA uncon- nected 1: T1OUTA connected internally to T1INA and T3OUTA connected internally to T3INA Bit 0 = SC0: Select connection even. This bit is set and cleared by software. It selects if the TxOUTA and TxINA pins for Timer 0 and Timer 2 are connected on-chip or not. 0: T0OUTA / T0INA and T2OUTA/ T2INA uncon- nected 1: T0OUTA connected internally to T0INA and T2OUTA connected internally to T2INA Note: Timer 1 and 2 are available only on some devices. Refer to the device block diagram and register map. CPE CME DCTS DCTD SWEN PL2 PL1 PL0 SC1 SC0

10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

10.5.1 Introduction

change with a wide range of external equipment. al expansion and Synchronous.

10.5.2 Main Features

address interrupt generation. – 5, 6, 7, or 8 bit word length. – Complete status reporting capabilities. – Line break generation and detection. Figure 106. SCI-M Block Diagram

10.5.3 Functional Description

(1X, 16X) and in the protocol used. Figure 107. SCI -M Functional Schematic Note: Some pins may not be available on some devices. Refer to the device Pinout Description.

10.5.4 SCI-M Operating Modes

10.5.4.1 Asynchronous Mode

sampled 16 times per clock period. ator output) is set to suit.

10.5.4.2 Asynchronous Mode with

each data bit is sampled once per clock period. INTCLK periods between clock and data. the SCI on the rising edge of the receive clock. Figure 108. Sampling Times in Asynchronous Format

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.3 Serial Expansion Mode

This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data is being transmitted on the CLKOUT pin (the Da ta Envelope). Data is latched on the rising edge of this clock. Whenever the SCI is to receive data in serial port expansion mode, the clock must be supplied ex- ternally, and be synchronous with the transmitted data. The SCI latches the incoming data on the ris- ing edge of the received clock, which is input on the RXCLK pin.

10.5.4.4 Synchronous Mode

This mode is used to access an external synchro- nous peripheral, dummy start/stop bits are not in- cluded in the data frame. Polarity, stand-by level and active edges of I/O signals are fully and sepa- rately programmable for both inputs and outputs. It's necessary to set the SMEN bit of the Synchro- nous Input Control Register (SICR) to enable this mode and all the related extra features (otherwise disabled). The transmitter will provide the clock waveform only during the period when the data is being transmitted via the CLKOUT pin, which can be en- abled by setting both the XTCLK and OCLK bits of the Clock Configuration Register. Whenever the SCI is to receive data in synchronous mode, the clock waveform must be supplied externally via the RXCLK pin and be synchronous with the data. For correct receiver operation, the XRX bit of the Clock Configuration Register must be set. Two external signals, Request-To-Send and Data- Carrier-Detect (RTS/DCD), can be enabled to syn- chronise the data exchange between two serial units. The RTS output becomes active just before the first active edge of CLKOUT and indicates to the target device that the MCU is about to send a synchronous frame; it returns to its stand-by state following the last active edge of CLKOUT (MSB transmitted). The DCD input can be considered as a gate that filters RXCLK and informs the MCU that a trans- mitting device is transmitting a data frame. Polarity of RTS/DCD is individually programmable, as for clocks and data. The data word is programmable from 5 to 8 bits, as for the other modes; parity, address/9th, stop bits and break cannot be inserted into the transmitted frame. Programming of the related bits of the SCI control registers is irrelevant in Synchronous Mode: all the corresponding interrupt requests must, in any case, be masked in order to avoid in- correct operation during data reception.

Figure 109. SCI -M Operating Modes Note: In all operating modes, the Least Significant Bit is transmitted/received first.

10.5.5 Serial Frame Format

condition is detected as a high to low transition. chronous modes. LSB are transmitted first. to indicate that the data is an address (bit set). tional data bit or to mark control words (9th bit). Figure 110. SCI Character Formats

10.5.5.1 Data transfer

the program into the Transmitter Buffer Register. unused most significant bits will be set. the transmitter/receiver clock. INTCLK or the Receiver clock input via RXCLK. plete word length and until the SB bit is Reset. frame for the Synchronous mode. Figure 113 for these different configurations. Table 44. Address Interrupt Modes

10.5.6 Clocks And Serial Transmission Rates

vided in the 3 other modes (CD set). spectively (see Figure 115). in accordance with the setting of the CD bit. Input Clock frequency divided by the Divisor value. 0 or 1 will stop the divider.

10.5.7 SCI -M Initialization Procedure

new value and start counting. clock are internally synchronized to INTCLK. Figure 114. SCI-M Baud Rate Generator Initialization Sequence

Table 45. SCI-M Baud Rate Generator Divider Values Example 1 Table 46. SCI-M Baud Rate Generator Divider Values Example 2

10.5.8 Input Signals

input to the SCI receiver shift register. INTCLK. The use of the TXCLK pin is optional. riod before the first active edge of the input clock.

10.5.9 Output Signals

SCI transmitter in all operating modes. enables the Serial Expansion Mode. disables it for PLM applications. level can be programmed high or low. Figure 115. Receiver and Transmitter Clock Frequencies

0 INTCLK/4 16x mode

0 INTCLK/2 16x mode

10.5.10 Interrupts and DMA

10.5.10.1 Interrupts

SCI peripheral are illustrated in Figure 116. mer during the Interrupt Service routine. er vectors to be resolved to an 8 byte block size. more details relating to Synchronous mode. Table 47. SCI Interrupt Internal Priority

Table 48. SCI-M Interrupt Vectors Figure 116. SCI-M Interrupts: Example of Typical Usage

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.10.2 DMA

Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA Reception To perform a DMA transfer in reception mode: 1. Initialize the DMA co unter (RDCPR) and DMA address (RDAPR) registers 2. Enable DMA by setting the RXD bit in the IDPR register. 3. DMA transfer is started when data is received by the SCI. DMA Transmission To perform a DMA transfer in transmission mode: 1. Initialize the DMA counter (TDCPR) and DMA address (TDAPR) registers. 2. Enable DMA by setting the TXD bit in the IDPR register. 3. DMA transfer is started by writing a byte in the Transmitter Buffer register (TXBR). If this byte is the first data byte to be transmitted, the DMA counter and address registers must be initialized to begin DMA transmission at the sec- ond byte. Alternatively, DMA transfer can be start- ed by writing a dummy byte in the TXBR register. DMA Interrupts When DMA is active, the Received Data Pending and the Transmitter Shift Register Empty interrupt sources are replaced by the DMA End Of Block re- ceive and transmit interrupt sources. Note: To handle DMA transfer correctly in trans- mission, the BSN bit in the IMR register must be cleared. This selects the Transmitter Shift Register Empty event as the DMA interrupt source. The transfer of the last byte of a DMA data block will be followed by a DMA End Of Block transmit or receive interrupt, setting the TXEOB or RXEOB bit. A typical Transmission End Of Block interrupt rou- tine will perform the following actions: 1. Restore the DMA counter register (TDCPR). 2. Restore the DMA address register (TDAPR). 3. Clear the Transmitter Shift Register Empty bit TXSEM in the S_ISR register to avoid spurious interrupts. 4. Clear the Transmitte r End Of Block (TXEOB) pending bit in the IMR register. 5. Set the TXD bit in the IDPR register to enable DMA. 6. Load the Transmitter Buffer Register (TXBR) with the next byte to transmit. The above procedure handles the case where a further DMA transfer is to be performed. Error Interrupt Handling If an error interrupt occurs while DMA is enabled in reception mode, DMA transfer is stopped. To resume DMA transfer, the error interrupt han- dling routine must clear the corresponding error flag. In the case of an Overrun error, the routine must also read the RXBR register. Character Search Mode with DMA In Character Search Mode with DMA, when a character match occurs, this character is not trans- ferred. DMA continues with the next received char- acter. To avoid an Overru n error occurring, the Character Match interrupt service routine must read the RXBR register.

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.11 Register Description

The SCI-M registers are located in the following pages in the ST9: SCI-M number 0: page 24 (18h) SCI-M number 1: page 25 (19h) (when present) The SCI is controlled by the following registers: Address Register R240 (F0h) Receiver DMA Transaction Counter Pointer Register R241 (F1h) Receiver DMA Source Address Pointer Register R242 (F2h) Transmitter DMA Transac tion Counter Pointer Register R243 (F3h) Transmitter DMA Desti nation Address Pointer Register R244 (F4h) Interrupt Vector Register R245 (F5h) Address Compare Register R246 (F6h) Interrupt Mask Register R247 (F7h) Interrupt Status Register R248 (F8h) Receive Buffer Register same Address as Transmitter Buffer Register (Read Only) R248 (F8h) Transmitter Buffer Register same Addr ess as Receive Buffer Register (Write only) R249 (F9h) Interrupt/DMA Priority Register R250 (FAh) Character Configuration Register R251 (FBh) Clock Configuration Register R252 (FCh) Baud Rate Generator High Register R253 (FDh) Baud Rate Generator Low Register R254 (FEh) Synchronous Input Control Register R255 (FFh) Synchronous Output Control Register

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer. These bits contain the address of the receiver DMA transaction counter in the Register File. Bit 0 = RR/M: Receiver Register File/Memory Se- lector. 0: Select Memory space as destination. 1: Select the Register File as destination. RECEIVER DMA ADDRESS POINTER (RDAPR) R241 - Read/Write Reset value: undefined Bit 7:1 = RA[7:1]: Receiver DMA Address Pointer. These bits contain the address of the pointer (in the Register File) of the receiver DMA data source. Bit 0 = RPS: Receiver DMA Memory Pointer Se- lector. This bit is only significant if memory has been se- lected for DMA transfers (RR/M = 0 in the RDCPR register). 0: Select ISR register for receiver DMA transfers address extension. 1: Select DMASR register for receiver DMA trans- fers address extension. TRANSMITTER DMA COUNTER POINTER (TDCPR) R242 - Read/Write Reset value: undefined Bit 7:1 = TC[7:1]: Transmitter DMA Counter Point- er. These bits contain the address of the transmitter DMA transaction counter in the Register File. Bit 0 = TR/M: Transmitter Register File/Memory Selector. 0: Select Memory space as source. 1: Select the Register File as source. TRANSMITTER DMA ADDRESS POINTER (TDAPR) R243 - Read/Write Reset value: undefined Bit 7:1 = TA[7:1]: Transmitter DMA Address Point- er. These bits contain the address of the pointer (in the Register File) of the transmitter DMA data source. Bit 0 = TPS: Transmitter DMA Memory Pointer Se- lector. This bit is only significant if memory has been se- lected for DMA transfers (TR/M = 0 in the TDCPR register). 0: Select ISR register for transmitter DMA transfers address extension. 1: Select DMASR regist er for transmitter DMA transfers address extension. RC7 RC6 RC5 RC4 RC3 RC2 RC1 RR/M RA7 RA6 RA5 RA4 RA3 RA2 RA1 RPS TC7 TC6 TC5 TC4 TC3 TC2 TC1 TR/M TA7 TA6 TA5 TA4 TA3 TA2 TA1 TPS

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable interrupt vector bits for trans- mitter and receiver. Bit 2:1 = EV[2:1]: Encoded Interrupt Source. Both bits EV2 and EV1 are read only and set by hardware according to the interrupt source. Bit 0 = D0: This bit is forced by hardware to 0. ADDRESS/DATA COMPARE REGISTER (ACR) R245 - Read/Write Reset value: undefined Bit 7:0 = AC[7:0]: Address/Compare Character . With either 9th bit address mode, address after break mode, or character search, the received ad- dress will be compared to the value stored in this register. When a valid address matches this regis- ter content, the Receiver Address Pending bit (RXAP in the S_ISR register) is set. After the RXAP bit is set in an addressed mode, all received data words will be transferred to the Receiver Buff- er Register. V7 V6 V5 V4 V3 EV2 EV1 0 EV2 EV1 Interrupt source 0 0 Receiver Error (Overrun, Framing, Parity) 0 1 Break Detect or Address Match

10 Received Data Pending/Receiver DMA

11 Transmitter buffer or shift register empty

transmitter DMA End of Block AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 Bit 7 = BSN: Buffer or shift register empty inter- rupt. This bit selects the source of the transmitter regis- ter empty interrupt. 0: Select a Shift Register Empty as source of a Transmitter Register Empty interrupt. 1: Select a Buffer Register Empty as source of a Transmitter Register Empty interrupt. Bit 6 = RXEOB: Received End of Block. This bit is set by hardware only and must be reset by software. RXEOB is set after a receiver DMA cycle to mark the end of a data block. 0: Clear the interrupt request. 1: Mark the end of a received block of data. Bit 5 = TXEOB: Transmitter End of Block. This bit is set by hardware only and must be reset by software. TXEOB is set after a transmitter DMA cycle to mark the end of a data block. 0: Clear the interrupt request. 1: Mark the end of a transmitted block of data. Bit 4 = RXE: Receiver Error Mask. 0: Disable Receiver error interrupts (OE, PE, and FE pending bits in the S_ISR register). 1: Enable Receiver error interrupts. Bit 3 = RXA: Receiver Address Mask. 0: Disable Receiver Address interrupt (RXAP pending bit in the S_ISR register). 1: Enable Receiver Address interrupt. Bit 2 = RXB: Receiver Break Mask. 0: Disable Receiver Break interrupt (RXBP pend- ing bit in the S_ISR register). 1: Enable Receiver Break interrupt. Bit 1 = RXDI: Receiver Data Interrupt Mask. 0: Disable Receiver Data Pending and Receiver End of Block interrupts (RXDP and RXEOB pending bits in the S_ISR register). 1: Enable Receiver Data Pending and Receiver End of Block interrupts. Note: RXDI has no effect on DMA transfers. Bit 0 = TXDI: Transmitter Data Interrupt Mask. 0: Disable Transmitter Buffer Register Empty, Transmitter Shift Register Empty, or Transmitter End of Block interrupts (TXBEM, TXSEM, and TXEOB bits in the S_ISR register). 1: Enable Transmitter Buffer Register Empty, Transmitter Shift Register Empty, or Transmitter End of Block interrupts. Note: TXDI has no effect on DMA transfers. BSN RXEOB TXEOB RXE RXA RXB RXDI TXDI

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined Bit 7 = OE: Overrun Error Pending. This bit is set by hardware if the data in the Receiv- er Buffer Register was not read by the CPU before the next character was transferred into the Receiv- er Buffer Register (the previous data is lost). 0: No Overrun Error. 1: Overrun Error occurred. Bit 6 = FE: Framing Error Pending bit. This bit is set by hardware if the received data word did not have a valid stop bit. 0: No Framing Error. 1: Framing Error occurred. Note: In the case where a framing error occurs when the SCI is programmed in address mode and is monitoring an address, the interrupt is as- serted and the corrupted data element is trans- ferred to the Receiver Buffer Register. Bit 5 = PE: Parity Error Pending. This bit is set by hardware if the received word did not have the correct even or odd parity bit. 0: No Parity Error. 1: Parity Error occurred. Bit 4 = RXAP: Receiver Address Pending. RXAP is set by hardware after an interrupt ac- knowledged in the address mode. 0: No interrupt in address mode. 1: Interrupt in address mode occurred. Note: The source of this interrupt is given by the couple of bits (AMEN, AM) as detailed in the IDPR register description. Bit 3 = RXBP: Receiver Break Pending bit. This bit is set by hardware if the received data in- put is held low for the fu ll word transmission time (start bit, data bits, parity bit, stop bit). 0: No break received. 1: Break event occurred. Bit 2 = RXDP: Receiver Data Pending bit. This bit is set by hardware when data is loaded into the Receiver Buffer Register. 0: No data received. 1: Data received in Receiver Buffer Register. Bit 1 = TXBEM: Transmitter Buffer Register Emp- ty. This bit is set by hardware if the Buffer Register is empty. 0: No Buffer Register Empty event. 1: Buffer Register Empty. Bit 0 = TXSEM: Transmitter Shift Register Empty. This bit is set by hardware if the Shift Register has completed the transmission of the available data. 0: No Shift Register Empty event. 1: Shift Register Empty. Note: The Interrupt Status Register bits can be re- set but cannot be set by the user. The interrupt source must be cleared by resetting the related bit when executing the interrupt service routine (natu- rally the other pending bits should not be reset). OE FE PE RXAP RXBP RXDP TXBEM TXSEM

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined Bit 7:0 = RD[7:0]: Received Data. This register stores the data portion of the re- ceived word. The data will be transferred from the Receiver Shift Register into the Receiver Buffer Register at the end of the word. All receiver inter- rupt conditions will be updated at the time of trans- fer. If the selected character format is less than 8 bits, unused most significant bits will forced to “1”. Note: RXBR and TXBR are two physically differ- ent registers located at the same address. TRANSMITTER BUFFER REGISTER (TXBR) R248 - Write only Reset value: undefined Bit 7:0 = TD[7:0]: Transmit Data. The ST9 core will load the data for transmission into this register. The SCI will transfer the data from the buffer into the Shift Register when availa- ble. At the transfer, the Transmitter Buffer Register interrupt is updated. If the selected word format is less than 8 bits, the unused most significant bits are not significant. Note: TXBR and RXBR are two physically differ- ent registers located at the same address. RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined Bit 7 = AMEN: Address Mode Enable. This bit, together with the AM bit (in the CHCR reg- ister), decodes the desired addressing/9th data bit/character match operation. In Address mode the SCI monitors the input serial data until its address is detected Note: Upon reception of address, the RXAP bit (in the Interrupt Status Register) is set and an inter- rupt cycle can begin. The address character will not be transferred into the Receiver Buffer Regis- ter but all data following the matched SCI address and preceding the next address word will be trans- ferred to the Receiver Buffer Register and the proper interrupts updated. If the address does not match, all data following this unmatched address will not be transferred to the Receiver Buffer Reg- ister. In any of the cases the RXAP bit must be reset by software before the next word is transferred into the Buffer Register. When AMEN is reset and AM is set, a useful char- acter search function is performed. This allows the SCI to generate an interrupt whenever a specific character is encountered (e.g. Carriage Return). Bit 6 = SB: Set Break. 0: Stop the break transmission after minimum break length. 1: Transmit a break following the transmission of all data in the Transmitter Shift Register and the Buffer Register. Note: The break will be a low level on the transmit- ter data output for at least one complete word for- mat. If software does not reset SB before the min- imum break length has finished, the break condi- tion will continue until software resets SB. The SCI terminates the break condition with a high level on the transmitter data output for one transmission clock period. Bit 5 = SA: Set Address. If an address/9th data bit mode is selected, SA val- ue will be loaded for transmission into the Shift Register. This bit is cleared by hardware after its load. 0: Indicate it is not an address word. 1: Indicate an address word. Note: Proper procedure would be, when the Transmitter Buffer Register is empty, to load the value of SA and then load the data into the Trans- mitter Buffer Register. Bit 4 = RXD: Receiver DMA Mask. This bit is reset by hardware when the transaction counter value decrements to zero. At that time a receiver End of Block interrupt can occur. 0: Disable Receiver DMA request (the RXDP bit in the S_ISR register can request an interrupt). 1: Enable Receiver DMA request (the RXDP bit in the S_ISR register can request a DMA transfer). Bit 3 = TXD: Transmitter DMA Mask. This bit is reset by hardware when the transaction counter value decrements to zero. At that time a transmitter End Of Block interrupt can occur. 0: Disable Transmitter DMA request (TXBEM or TXSEM bits in S_ISR can request an interrupt). 1: Enable Transmitter DMA request (TXBEM or TXSEM bits in S_ISR can request a DMA trans- fer). Bit 2:0 = PRL[2:0]: SCI Interrupt/DMA Priority bits. The priority for the SCI is encoded with (PRL2,PRL1,PRL0). Priority level 0 is the highest, while level 7 represents no priority. When the user has defined a priority level for the SCI, priorities within the SCI are hardware defined. These SCI internal priorities are: AMEN SB SA RXD TXD PRL2 PRL1 PRL0 AMEN AM 0 0 Address interrupt if 9th data bit = 1 0 1 Address interrupt if character match

10 Address interrupt if character match

and 9th data bit =1

11 Address interrupt if character match

with word immediately following Break Receiver DMA request highest priority Transmitter DMA request Receiver interrupt Transmitter interrupt lowest priority9

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION REGISTER (CHCR) R250 - Read/Write Reset value: undefined Bit 7 = AM: Address Mode. This bit, together with the AMEN bit (in the IDPR register), decodes the desired addressing/9th data bit/character match operation. Please refer to the table in the IDPR register description. Bit 6 = EP: Even Parity. 0: Select odd parity (when parity is enabled). 1: Select even parity (when parity is enabled). Bit 5 = PEN: Parity Enable. 0: No parity bit. 1: Parity bit generated (transmit data) or checked (received data). Note: If the address/9th bit is enabled, the parity bit will precede the address/ 9th bit (the 9th bit is never included in the parity calculation). Bit 4 = AB: Address/9th Bit. 0: No Address/9th bit. 1: Address/9th bit included in the character format between the parity bit and the first stop bit. This bit can be used to address the SCI or as a ninth data bit. Bit 3:2 = SB[1:0]: Number of Stop Bits.. Bit 1:0 = WL[1:0]: Number of Data Bits AM EP PEN AB SB1 SB0 WL1 WL0 SB1 SB0 Number of stop bits in 16X mode in 1X mode 00 1 1 01 1 . 5 2 10 2 2 11 2 . 5 3 WL1 WL0 Data Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CLOCK CONFIGURATION REGISTER (CCR) R251 - Read/Write Reset value: 0000 0000 (00h) Bit 7 = XTCLK This bit, together with the OCLK bit, selects the source for the transmitter clock. The following ta- ble shows the coding of XTCLK and OCLK. Bit 6 = OCLK This bit, together with the XTCLK bit, selects the source for the transmitter clock. The following ta- ble shows the coding of XTCLK and OCLK. Bit 5 = XRX: External Receiver Clock Source. 0: External receiver clock source not used. 1: Select the external receiver clock source. Note: The external receiver clock frequency must be 16 times the data rate, or equal to the data rate, depending on the status of the CD bit. Bit 4 = XBRG: Baud Rate Generator Clock Source. 0: Select INTCLK for the baud rate generator. 1: Select the external receiver clock for the baud rate generator. Bit 3 = CD: Clock Divisor. The status of CD will determine the SCI configura- tion (synchronous/asynchronous). 0: Select 16X clock mode for both receiver and transmitter. 1: Select 1X clock mode for both receiver and transmitter. Note: In 1X clock mode, the transmitter will trans- mit data at one data bit per clock period. In 16X mode each data bit period will be 16 clock periods long. Bit 2 = AEN: Auto Echo Enable. 0: No auto echo mode. 1: Put the SCI in auto echo mode. Note: Auto Echo mode has the following effect: the SCI transmitter is disconnected from the data- out pin SOUT, which is driven directly by the re- ceiver data-in pin, SIN. The receiver remains con- nected to SIN and is operational, unless loopback mode is also selected. Bit 1 = LBEN: Loopback Enable. 0: No loopback mode. 1: Put the SCI in loopback mode. Note: In this mode, the transmitter output is set to a high level, the receiver input is disconnected, and the output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. All interrupt sources (transmitter and receiver) are operational. Bit 0 = STPEN: Stick Parity Enable. 0: The transmitter and t he receiver will follow the parity of even parity bit EP in the CHCR register. 1: The transmitter and the receiver will use the op- posite parity type selected by the even parity bit EP in the CHCR register. XTCLK OCLK XRX XBRG CD AEN LBEN STPEN XTCLK OCLK Pin Function 0 0 Pin is used as a general I/O 0 1 Pin = TXCLK (used as an input)

10 Pin = CLKOUT (outputs the Baud

Rate Generator clock) Pin = CLKOUT (outputs the Serial expansion and synchronous mode clock) EP SPEN Parity (Transmitter & Receiver) 0 (odd) 0 Odd 1 (even) 0 Even 0 (odd) 1 Even 1 (even) 1 Odd

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) BAUD RATE GENERATOR HIGH REGISTER (BRGHR) R252 - Read/Write Reset value: undefined BAUD RATE GENERATOR LOW REGISTER (BRGLR) R253 - Read/Write Reset value: undefined Bit 15:0 = Baud Rate Generator MSB and LSB. The Baud Rate generator is a programmable di- vide by “N” counter which can be used to generate the clocks for the transmitter and/or receiver. This counter divides the clock input by the value in the Baud Rate Generator Register. The minimum baud rate divisor is 2 and the maximum divisor is 16-1. After initialization of the baud rate genera- tor, the divisor value is immediately loaded into the counter. This prevents potentially long random counts on the initial load. If set to 0 or 1, the Baud Rate Generator is stopped. SYNCHRONOUS INPUT CONTROL (SICR) R254 - Read/Write Reset value: 0000 0011 (03h) Bit 7 = SMEN: Synchronous Mode Enable. 0: Disable all features relating to Synchronous mode (the contents of SICR and SOCR are ig- nored). 1: Select Synchronous mode with its programmed I/O configuration. Bit 6 = INPL: SIN Input Polarity. 0: Polarity not inverted. 1: Polarity inverted. Note: INPL only affects received data. In Auto- E c h o m o d e S O U T = S I N e v e n i f I N P L i s s e t . I n Loop-Back mode the state of the INPL bit is irrele- vant. Bit 5 = XCKPL: Receiver Clock Polarity. 0: RXCLK is active on the rising edge. 1: RXCLK is active on the falling edge. Note: XCKPL only affects the receiver clock. In Auto-Echo mode CLKOUT = RXCLK independ- ently of the XCKPL status. In Loop-Back the state of the XCKPL bit is irrelevant. Bit 4 = DCDEN: DCD Input Enable. 0: Disable hardware synchronization. 1: Enable hardware synchronization. Note: When DCDEN is set, RXCLK drives the re- ceiver section only during the active level of the DCD input (DCD works as a gate on RXCLK, in- forming the MCU that a transmitting device is sending a synchronous frame to it). Bit 3 = DCDPL: DCD Input Polarity. 0: The DCD input is active when LOW. 1: The DCD input is active when HIGH. Note: DCDPL only affects the gating activity of the receiver clock. In Auto-Echo mode RTS = DCD in- dependently of DCDPL. In Loop-Back mode, the state of DCDPL is irrelevant. Bit 2 = INPEN: All Input Disable. 0: Enable SIN/RXCLK/DCD inputs. 1: Disable SIN/RXCLK/DCD inputs. Bit 1:0 = “Don't Care” 15 8 BG15 BG14 BG13 BG12 BG11 BG10 BG9 BG8 BG7 BG6 BG5 BG4 BG3 BG2 BG1 BG0 SMEN INPL XCKPL DCDEN DCDPL INPEN X X

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) SYNCHRONOUS OUTPUT CONTROL (SOCR) R255 - Read/Write Reset value: 0000 0001 (01h) Bit 7 = OUTPL: SOUT Output Polarity. 0: Polarity not inverted. 1: Polarity inverted. Note: OUTPL only affects the data sent by the transmitter section. In Auto-Echo mode SOUT = SIN even if OUTPL=1. In Loop-Back mode, the state of OUTPL is irrelevant. Bit 6 = OUTSB: SOUT Output Stand-By Level. 0: SOUT stand-by level is HIGH. 1: SOUT stand-by level is LOW. Bit 5 = OCKPL: Transmitter Clock Polarity. 0: CLKOUT is active on the rising edge. 1: CLKOUT is active on the falling edge. Note: OCKPL only affects the transmitter clock. In Auto-Echo mode CLKOUT = RXCLK independ- ently of the state of OCKPL. In Loop-Back mode the state of OCKPL is irrelevant. Bit 4 = OCKSB: Transmitter Clock Stand-By Lev- el. 0: The CLKOUT stand-by level is HIGH. 1: The CLKOUT stand-by level is LOW. Bit 3 = RTSEN: RTS and SDS Output Enable. 0: Disable the RTS and SDS hardware synchroni- sation. 1: Enable the RTS and SDS hardware synchroni- sation. Notes: – When RTSEN is set, the RTS output becomes active just before the first active edge of CLK- OUT and indicates to target device that the MCU is about to send a synchronous frame; it returns to its stand-by value just after the last active edge of CLKOUT (MSB transmitted). – When RTSEN is set, the SDS output becomes active high and indicates to the target device that the MCU is about to send the first bit of a syn- chronous frame on the Serial Output Pin (SOUT); it returns to low level as soon as the second bit is sent on the Serial Output Pin (SOUT). In this way a positive pulse is generated each time that the first bit of a synchronous frame is present on the Serial Output Pin (SOUT). Bit 2 = RTSPL: RTS Output Polarity. 0: The RTS output is active when LOW. 1: The RTS output is active when HIGH. Note: RTSPL only affects the RTS activity on the output pin. In Auto-Echo mode RTS = DCD inde- pendently from the RTSPL value. In Loop-Back mode RTSPL value is 'Don't Care'. Bit 1 = OUTDIS: Disable all outputs. This feature is available on specific devices only (see device pin-out description). When OUTDIS=1, all output pins (if configured in Alternate Function mode ) will be put in High Im- pedance for networking. 0: SOUT/CLKOUT/enabled 1: SOUT/CLKOUT/RTS put in high impedance Bit 0 = “Don't Care” OUTP L OUTS B OCKP L OCKS B RTSE N RTS PL OUT DIS X

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)

10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)

10.6.1 Introduction

The Asynchronous Serial Communications Inter- face (SCI-A) offers a flex ible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI-A offers a very wide range of baud rates using two baud rate generator sys- tems.

10.6.2 Main Features

■ Full duplex, asynchronous communications ■ NRZ standard format (Mark/Space) ■ Dual baud rate generator systems ■ Independently programmable transmit and receive baud rates up to 700K baud. ■ Programmable data word length (8 or 9 bits) ■ Receive buffer full, Transmit buffer empty and End of Transmission flags ■ Two receiver wake-up modes: – Address bit (MSB) – Idle line ■ Muting function for multiprocessor configurations ■ Separate enable bits for Transmitter and Receiver ■ Three error detection flags: – Overrun error – Noise error – Frame error ■ Five interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected ■ Parity control: – Transmits parity bit – Checks parity of received data byte ■ Reduced power consumption mode ■ LIN Master: 13-bit LIN Synch Break generation capability

10.6.3 General Description

The interface is externally connected to another device by two pins (see Figure 118): – TDO: Transmit Data Output. When the trans- mitter is disabled, the output pin is in high im- pedance. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. – RDI: Receive Data Input is the serial data in- put. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: – An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is com- plete. This interface uses two types of baud rate genera- tors: – A conventional type for commonly-used baud rates, – An extended type with a prescaler offering a very wide range of baud rates even with non- standard oscillator frequencies.

Figure 117. SCI-A Block Diagram

10.6.4 Functional Description

for the definitions of each bit.

10.6.4.1 Serial Data Format

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. tra “1” bit to acknowledge the start bit. Figure 118. Word Length Programming

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) be- tween the internal bus and the transmit shift regis- ter (see Figure 117). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR and the SCIETPR registers. – Set the TE bit to send an idle frame as first trans- mission. – Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the SCIDR regis- ter without overwriting the previous data. This flag generates an interrupt if the TIE bit is set in the SCICR2 register and the IMI0 bit is set in the SIMRH register. When a transmission is taking place, a write in- struction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write in- struction to the SCIDR register places the data di- rectly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the IMI0 bit is set in the SIMRH register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. LIN Transmission The same procedure has to be applied with the fol- lowing differences: – Clear the M bit to configure 8-bit word length – Set the LINE bit to enter LIN Master mode. In this case, setting the SBK bit will send 13 low bits. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 118). As long as the SBK bit is set, the SCI sends break frames to the TDO pin. After clearing this bit by software, the SCI inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a trans- mission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, i.e. before writing the next byte in the SCIDR.

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character Reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) be- tween the internal bus and the received shift regis- ter (see Figure 117). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR and the SCIERPR registers. – Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and the IMI0 bit is set in the SIMRH register. – The error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI han- dles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an iterrupt if the ILIE bit is set and the IMI0 bit is set in the SIMRH register. Overrun Error An overrun error occurs when a character is re- ceived when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and the IMI0 bit is set in the SIMRH register. The OR bit is reset by an access to the SCISR reg- ister followed by a SCIDR register read operation. Noise Error Oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SCISR register read oper- ation followed by a SCIDR register read operation. Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read oper- ation followed by a SCIDR register read operation.

Figure 119. SCI Baud Rate and Extended Prescaler Block Diagram

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) (see SCT[2:0] bits) (see SCR[2:0] bits) All this bits are in the SCIBRR register. Example: If f CPU is 24 MHz and if PR=13 and TR=RR=2, the transmit and receive baud rates are 57700 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is en- abled.

10.6.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional Baud Rate Genera- tor retains industry stan dard software compatibili- ty. The extended Baud Rate Generator block diagram is described in the Figure 119. The output clock rate sent to the transmitter or to the receiver will be the ou tput from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register. Note: The extended prescaler is activated by set- ting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows: with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register)

10.6.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurat ions it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an ad- dress. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. SB : Start Bit STB : Stop Bit PB : Parity Bit Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit Tx = (16 *PR)*TR fCPU Rx = (16*PR)*RR fCPU Tx = 16*ETPR*(PR*TR) fCPU Rx = 16*ERPR*(PR*TR) fCPU M Bit PCE Bit SCI Frame 0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB |

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.7 Parity definition

Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the in- terface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is se- lected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is gen- erated if PCIE is set in the SCICR1 register.

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Register Description

STATUS REGISTER (SCISR) R240 - Read Only Register Page: 26 Reset Value: 1100 0000 (C0h) Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the SCICR2 register. It is cleared by a software se- quence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift regis- ter as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by a software se- quence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by hardware when RE=0 or by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is de- tected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line oc- curs). This bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SCISR regis- ter followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by hardware when RE=0 by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. It is cleared by hardware when RE=0 by a software sequence (an access to the SCISR regis- ter followed by a read to the SCIDR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. TDRE TC RDRF IDLE OR NF FE PE

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) Bit 0 = PE Parity error. This bit is set by hardware when a parity error oc- curs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An inter- rupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error CONTROL REGISTER 1 (SCICR1) R243 - Read/Write Register Page: 26 Reset Value: x000 0000 (x0h) Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1. Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark Bit 2 = PCE Parity control enable. This bit selects the hardware parity control (gener- ation and detection). When the parity control is en- abled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on receive data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmis- sion). 0: Parity control disabled 1: Parity control enabled Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled Note: The ITEI0 bit in the SITRH register (See In- terrupts Chapter) must be set to enable the SCI-A interrupt as the SCI-A interrupt is a rising edge event. R8 T8 SCID M WAKE PCE PS PIE

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) R244 - Read/Write Register Page: 26 Reset Value: 0000 0000 (00h) Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register Bit 6 = TCIE Transmission complete interrupt ena- ble This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in the SCISR register Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR register Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is in high impedance 1: Transmitter is enabled Note: during transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled, it resets the RDRF, IDLE, OR, NF and FE bits of the SCISR register 1: Receiver is enabled and begins searching for a start bit Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Notes: – If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. – The ITEI0 bit in the SITRH register (See Inter- rupts Chapter) must be set to enable the SCI-A interrupt as the SCI-A interrupt is a rising edge event. CONTROL REGISTER 3 (SCICR3) R255 - Read/Write Register Page: 26 Reset Value: 0000 0000 (00h) Bit 7 = Reserved Bit 6 = LINE LIN mode Enable. This bit is set and cleared by software. 0: LIN master mode disabled 1: LIN master mode enabled LIN master mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in the SCICR2 register. In transmission, the LIN Synch Break low phase duration is shown as be- low: Bits 5:0 = Reserved TIE TCIE RIE ILIE TE RE RWU SBK - L I N E ----- - LINE M Number of low bits sent during a LIN Synch Break 00 1 0 01 1 1 10 1 3 11 1 4 9

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) R241 - Read/Write Register Page: 26 Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift reg- ister (see Figure 117). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 117). BAUD RATE REGISTER (SCIBRR) R242 - Read/Write Register Page: 26 Reset Value: 00xx xxxx (xxh) Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al Baud Rate Generator mode. Note: This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the (TR*ETPR) dividing factor. Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. Note: This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the (RR*ERPR) dividing factor. DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 PR Prescaling factor SCP1 SCP0 10 0 30 1 41 0 13 1 1 TR Dividing Factor SCT2 SCT1 SCT0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 RR Dividing Factor SCR2 SCR1 SCR0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) R245 - Read/Write Register Page: 26 Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bits 7:1 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 119) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended Baud Rate Generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) R246 - Read/Write Register Page: 26 Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bits 7:1 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 119) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended Baud Rate Generator is not used af- ter a reset.

10.6.6 Important Notes on SCI-A

Refer to Section 13.4 on page 413 and Section 13.5 on page 413. ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0 ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0

10.7 SERIAL PERIPHERAL INTERFACE (SPI)

10.7.1 Introduction

which devices may be either masters or slaves.

10.7.2 Main Features

■ Maximum slave mode frequency = INTCLK/2. ■ Master mode fault protection capability.

10.7.3 General Description

grammed as alternate function output. must be programmed with the same timing mode. Figure 120. Serial Peripheral Interface Master/Slave

Figure 121. Serial Peripheral Interface Block Diagram

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d)

10.7.4 Functional Description

Figure 121 shows the serial peripheral interface (SPI) block diagram. This interface contains 4 dedicated registers: – A Control Register (SPCR) – A Prescaler Register (SPPR) – A Status Register (SPSR) – A Data Register (SPDR) Refer to the SPCR, SPPR, SPSR and SPDR reg- isters in Section 10.7.6for the bit definitions.

10.7.4.1 Master Configuration

In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Define the serial clock baud rate by setting/re- setting the DIV2 bit of SPPR register, by writ- ing a prescaler value in the SPPR register and programming the SPR0 & SPR1 bits in the SPCR register. – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 123). –T h e S S pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPOE bits must be set (they remain set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and the MISO pin is a data input. Transmit Sequence The transmit sequence begins when a byte is writ- ten the SPDR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIS and SPIE bits are set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the SPDR register is read, the SPI peripheral returns this buffered val- ue. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPSR register while the SPIF bit is set 2. A read of the SPDR register. Note: While the SPIF bit is se t, all writes to the SPDR register are inhibited until the SPSR regis- ter is read.

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d)

10.7.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPPR register and SPR0 & SPR1 bits in the SPCR is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure 123. –T h e S S pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPOE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIS and SPIE bits are set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the SPDR register is read, the SPI peripheral returns this buffered val- ue. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPSR register while the SPIF bit is set. 2. A read of the SPDR register. Notes: While the SPIF bit is set, all writes to the SPDR register are inhibited until the SPSR regis- ter is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 10.7.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the SPDR register between each data byte transfer to av oid a write collision (see Section 10.7.4.4).

10.7.4.3 Data Transfer Format

ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. master and the slave device. be driven by the master device. clock edge before the capture clock edge. the occurrence of the first clock transition. currence of the second clock transition. each byte transmitted (see Figure 122). Figure 122. CPHA / SS Timing Diagram

Figure 123. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the SPI Timing table in the Electrical Characteristics Section.

10.7.4.4 Write Collision Error

the software write will be unsuccessful. ternal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 124. Clearing the WCOL bit (Write Collision Flag) Software Sequence

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d)

10.7.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPOE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPSR register while the MODF bit is set. 2. A write to the SPCR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPOE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPOE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.

10.7.4.6 Overrun Condition

An overrun condition occurs, when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPDR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.

10.7.4.7 Single Master and Multimaster Configurations

that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 125. Single Master Configuration

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d)

10.7.5 Interrupt Management

The interrupt of the Serial Peripheral Interface is mapped on one of the eight External Interrupt Channels of the microcontroller (refer to the “Inter- rupts” chapter). Each External Interrupt Channel has: – A trigger control bit in the EITR register (R242 - Page 0), – A pending bit in the EIPR register (R243 - Page0), – A mask bit in the EIMR register (R244 - Page 0). Program the interrupt prio rity level using the EI- PLR register (R245 - Page 0). For a description of these registers refer to the “Interrupts” and “DMA” chapters. To use the interrupt feature, perform the following sequence: – Set the priority level of the interrupt channel used for the SPI (EIPRL register) – Select the interrupt trigger edge as rising edge (set the corresponding bit in the EITR register) – Set the SPIS bit of the SPCR register to select the peripheral interrupt source – Set the SPIE bit of the SPCR register to enable the peripheral to perform interrupt requests – In the EIPR register, reset the pending bit of the interrupt channel used by the SPI interrupt to avoid any spurious interrupt requests being per- formed when the mask bit is set – Set the mask bit of the interrupt channel used to enable the MCU to acknowledge the interrupt re- quests of the peripheral. Note: In the interrupt routine, reset the related pending bit to avoid the interrupt request that was just acknowledged being proposed again. Then, after resetting the pending bit and before the IRET instruction, check if the SPIF and MODF interrupt flags in the SPSR register) are reset; oth- erwise jump to the beginning of the routine. If, on return from an interrupt routine, the pending bit is reset while one of the interrupt flags is set, no in- terrupt is performed on that channel until the flags are set. A new interrupt request is performed only when a flag is set with the other not set.

10.7.5.1 Register Map

Depending on the device, one or two Serial Pe- ripheral interfaces can be present. The previous table summarizes the position of the registers of the two peripherals in the register map of the mi- crocontroller. Address Page Name SPI0 R240 (F0h) 7 DR0 R241 (F1h) 7 CR0 R242 (F2h) 7 SR0 R243 (F3h) 7 PR0 SPI1 R248 (F8h) 7 DR1 R249 (F9h) 7 CR1 R250 (FAh) 7 SR1 R251 (FBh) 7 PR1

10.7.6 Register Description

directly into the shift register for transmission. Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. Bit 6 = SPOE Serial peripheral output enable. (see Section 10.7.4.5 Master Mode Fault). Bit 5 = SPIS Interrupt Selection. This bit is set and cleared by software. (see Section 10.7.4.5 Master Mode Fault). Bit 3 = CPOL Clock polarity. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 = SPR[1:0] Serial peripheral rate. rial clock when the device is a master. These 2 bits have no effect in slave mode. Table 49. Serial Peripheral Baud Rate

Bit 7 = SPIF Serial Peripheral data transfer flag. followed by a read or write to the SPDR register). proved by a clearing sequence. nal device has been completed. SPDR register are inhibited. Bit 6 = WCOL Write Collision status. Bit 4 = MODF Mode Fault flag. Bits 7:5 = Reserved, forced by hardware to 0. Bit 4 = DIV2 Divider enable. This bit is set and cleared by software. Bit 3 = Reserved. forced by hardware to 0. Bits 2:0 = PRS[2:0] Prescaler Value. DIV2=0. Refer to Figure 121. These bits have no effect in slave mode. Table 50. Prescaler Baud Rate

10.8 I2C BUS INTERFACE

10.8.1 Introduction

The I2C bus Interface serves as an interface be- tween the microcontroller and the serial I2C bus. It provides both multimaster and slave functions with both 7-bit and 10-bit address modes; it controls all I 2C bus-specific sequencing, protocol, arbitration, timing and supports both standard (100KHz) and fast I2C modes (400KHz). Using DMA, data can be transferred with minimum use of CPU time. The peripheral uses two external lines to perform the protocols: SDA, SCL.

10.8.2 Main Features

■ Parallel-bus/I2C protocol converter ■ Multi-master capability ■ 7-bit/10-bit Addressing ■ Standard I2C mode/Fast I2C mode ■ Transmitter/Receiver flag ■ End-of-byte transmission flag ■ Transfer problem detection ■ Interrupt generation on error conditions ■ Interrupt generation on transfer request and on data received I2C Master Features: ■ Start bit detection flag ■ Clock generation ■ I2C bus busy flag ■ Arbitration Lost flag ■ End of byte transmission flag ■ Transmitter/Receiver flag ■ Stop/Start generation I2C Slave Features: ■ Stop bit detection ■ I2C bus busy flag ■ Detection of misplaced start or stop condition ■ Programmable I 2C Address detection (both 7- bit and 10-bit mode) ■ General Call address programmable ■ Transfer problem detection ■ End of byte transmission flag ■ Transmitter/Receiver flag. Interrupt Features: ■ Interrupt generation on error condition, on transmission request and on data received ■ Interrupt address vector for each interrupt source ■ Pending bit and mask bit for each interrupt source ■ Programmable interrupt priority respects the other peripherals of the microcontroller ■ Interrupt address vector programmable DMA Features: ■ DMA both in transmission and in reception with enabling bits ■ DMA from/toward both Register File and Memory ■ End Of Block interrupt sources with the related pending bits

Figure 126. I2C Interface Block Diagram

10.8.3 Functional Description

in Section 10.8.7. for the bit definitions. lection of the operating mode is made by software. ports revert to being standard I/O port pins. The I2C interface has sixteen internal registers.

I2C BUS INTERFACE (Cont’d) The following seven registers are used to handle the interrupt and the DMA features: – Interrupt Status Register I2CISR – Interrupt Mask Register I2CIMR – Interrupt Vector Register I2CIVR – Receiver DMA Address Pointer Register I2CRDAP – Receiver DMA Transaction Counter Register I2CRDC – Transmitter DMA Address Pointer Register I2CTDAP – Transmitter DMA transaction Counter Register I2CTDC The interface can decode both addresses: – Software programmable 7-bit General Call address – I 2C address stored by software in the I2COAR1 register in 7-bit address mode or stored in I2COAR1 and I2COAR2 registers in 10-bit ad- dress mode. After a reset, the interface is disabled. IMPORTANT: 1. To guarantee correct operation, before enabling the peripheral (while I2CCR.PE=0), configure bit7 and bit6 of the I2COAR2 register according to the internal clock INTCLK (for example 11xxxxxxb in the range 14 - 30 MHz). 2. Bit7 of the I2CCR register must be cleared.

10.8.3.1 Mode Selection

2C mode, the interface can operate in the four following modes: – Master transmitter/receiver – Slave transmitter/receiver By default, it operates in slave mode. This interface automatically switches from slave to master after a start condition is generated on the bus and from master to slave in case of arbitration loss or stop condition generation. In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, it is able to recognize its own ad- dress (7 or 10-bit), as stored in the I2COAR1 and I2COAR2 registers and (when the I2CCR.ENGC bit is set) the General Call address (stored in I2CADR register). It never recognizes the Start Byte (address byte 01h) whatever its own address is. Data and addresses are transferred in 8 bits, MSB first. The first byte(s) following the start condition contain the address (one byte in 7-bit mode, two bytes in 10-bit mode). The address is always transmitted in master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Acknowledge is enabled and disabled by software. Refer to Figure 127.

Figure 127. I2C BUS Protocol registers directly or via the DMA. Data Register after a data byte is received. rising edge of the SCL clock.

10.8.4 I2C State Machine

bit7 of I2CCR register must be cleared.

10.8.4.1 I2C Slave Mode

address (if selected by software). two most significant bits of the address. ACK bit of the control register (I2CCR) is set.

I2C BUS INTERFACE (Cont’d) Next, depending on the data direction bit (least significant bit of the address byte), and after the generation of an acknowledge, the slave must go in sending or receiving mode. In 10-bit mode, after receiving the address se- quence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave Receiver Following the address reception and after I2CSR1 register has been read, the slave receives bytes from the SDA line into the Shift Register and sends them to the I2CDR register. After each byte it generates an acknowledge bit if the I2CCR.ACK bit is set. When the acknowledge bit is sent, the I2CSR1.BTF flag is set and an interrupt is generat- ed if the I2CCR.ITE bit is set (see Figure 128 Transfer sequencing EV2). Then the interface waits for a read of the I2CSR1 register followed by a read of the I2CDR register, or waits for the DMA to complete. Slave Transmitter Following the address reception and after I2CSR1 register has been read, the slave sends bytes from the I2CDR register to the SDA line via the internal shift register. When the acknowledge bit is received, the I2CCR.BTF flag is set and an interrupt is generated if the I2CCR.ITE bit is set (see Figure 128 Transfer sequencing EV3). The slave waits for a read of the I2CSR1 register followed by a write in the I2CDR register or waits for the DMA to complete, both holding the SCL line low (except on EV3-1). Error Cases – BERR: Detection of a Stop or a Start condition during a byte transfer. The I2CSR2.BERR flag is set and an interrupt is generated if I2CCR.ITE bit is set. If it is a stop then the state machine is reset. If it is a start then the state machine is reset and it waits for the new slave address on the bus. – AF: Detection of a no-acknowledge bit. The I2CSR2.AF flag is set and an interrupt is generated if the I2CCR.ITE bit is set. Note: In both cases, SCL line is not stretched low; however, the SDA line, due to possible «0» bits transmitted last, can remain low. It is then neces- sary to release both lines by software. Other Events – ADSL: Detection of a Start condition after an ac- knowledge time-slot. The state machine is reset and starts a new proc- ess. The I2CSR1.ADSL flag bit is set and an in- terrupt is generated if the I2CCR.ITE bit is set. The SCL line is stretched low. – STOPF: Detection of a Stop condition after an acknowledge time-slot. The state machine is reset. Then the I2CSR2.STOPF flag is set and an interrupt is generated if the I2CCR.ITE bit is set. How to release the SDA / SCL lines Check that the I2CSR1.BUSY bit is reset. Set and subsequently clear the I2 CCR.STOP bit while the I2CSR1.BTF bit is set; then the SDA/SCL lines are released immediately after the transfer of the cur- rent byte. This will also reset the state machine; any subse- quent STOP bit (EV4) will not be detected. 10.8.4.2 I 2C Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed. Setting the I2CCR.START bit while the I2CSR1.BUSY bit is cleared causes the interface to generate a Start condition. Once the Start condition is generated, the periph- eral is in master mode (I2CSR1.M/SL=1) and I2CSR1.SB (Start bit) flag is set and an interrupt is generated if the I2CCR.ITE bit is set (see Figure 128 Transfer sequencing EV5 event). The interface waits for a read of the I2CSR1 regis- ter followed by a write in the I2CDR register with the Slave address, holding the SCL line low.

I2C BUS INTERFACE (Cont’d) Then the slave address is sent to the SDA line. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the I2CSR1.EVF and I2CSR1.ADD10 bits to be set by hardware with interrupt generation if the I2CCR.ITE bit is set. Then the master waits for a read of the I2CSR1 register followed by a writ e in the I2CDR register, holding the SCL line low (see Figure 128 Trans- fer sequencing EV9). Then the second address byte is sent by the interface. After each address byte, an acknowledge clock pulse is sent to the SCL line if the I2CSR1.EVF and – I2CSR1.ADD10 bit (if first header) – I2CSR2.ADDTX bit (if address or second head- er) are set, and an interrupt is generated if the I2CCR.ITE bit is set. The peripheral waits for a read of the I2CSR1 reg- ister followed by a write into the Control Register (I2CCR) by holding the SCL line low (see Figure 128 Transfer sequencing EV6 event). If there was no acknowledge (I2CSR2.AF=1), the master must stop or re start the communication (set the I2CCR.START or I2CCR.STOP bits). If there was an acknowledge, the state machine enters a sending or receiving process according to the data direction bit (least significant bit of the ad- dress), the I2CSR1.BTF flag is set and an interrupt is generated if I2CCR.ITE bit is set (see Transfer sequencing EV7, EV8 events). If the master loses the arbitration of the bus there is no acknowledge, the I2CSR2.AF flag is set and the master must set the START or STOP bit in the control register (I2CCR).The I2CSR2.ARLO flag is set, the I2CSR1.M/SL flag is cleared and the proc- ess is reset. An interrupt is generated if I2CCR.ITE is set. Master Transmitter: The master waits for the microcontroller to write in the Data Register (I2CDR) or it waits for the DMA to complete both holding the SCL line low (see Transfer sequencing EV8). Then the byte is received into the shift register and sent to the SDA line. When the acknowledge bit is received, the I2CSR1.BTF flag is set and an interrupt is generated if the I2CCR.ITE bit is set or the DMA is requested. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver: The master receives a byte from the SDA line into the shift register and sends it to the I2CDR regis- ter. It generates an acknowledge bit if the I2CCR.ACK bit is set and an interrupt if the I2CCR.ITE bit is set or a DMA is requested (see Transfer sequencing EV7 event). Then it waits for the microcontroller to read the Data Register (I2CDR) or waits for the DMA to complete both holding SCL line low. Error Cases ■ BERR: Detection of a Stop or a Start condition during a byte transfer. The I2CSR2.BERR flag is set and an interrupt is generated if I2CCR.ITE is set. ■ AF: Detection of a no acknowledge bit The I2CSR2.AF flag is set and an interrupt is generated if I2CCR.ITE is set. ■ ARLO: Arbitration Lost The I2CSR2.ARLO flag is set, the I2CSR1.M/SL flag is cleared and the process is reset. An interrupt is generated if the I2CCR.ITE bit is set. Note: In all cases, to resume communications, set the I2CCR.START or I2CCR.STOP bits. Events generated by the I 2C interface ■ STOP condition When the I2CCR.STOP bit is set, a Stop condition is generated after the transfer of the current byte, the I2CSR1.M/SL flag is cleared and the state machine is reset. No interrupt is generated in master mode at the detection of the stop condition. ■ START condition When the I2CCR.START bit is set, a start condition is generated as soon as the I 2C bus is free. The I2CSR1.SB flag is set and an interrupt is generated if the I2CCR.ITE bit is set.

Figure 128. Transfer Sequencing EV1: EVF=1, ADSL=1, cleared by reading SR1 register. STOP=1, STOP=0 the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register. Figure 129. Event Flags and Interrupt Generation

I2C BUS INTERFACE (Cont’d)

10.8.5 Interrupt Features

The I2Cbus interface has three interrupt sources related to “Error Condition”, “Peripheral Ready to Transmit” and “Data Received”. The peripheral uses the ST9+ interrupt internal protocol without requiring the use of the external interrupt channel. Dedicated registers of the pe- ripheral should be loaded with appropriate values to set the interrupt vector (see the description of the I2CIVR register), the interrupt mask bits (see the description of the I2CIMR register) and the in- terrupt priority and pending bits (see the descrip- tion of the I2CISR register). The peripheral also has a global interrupt enable (the I2CCR.ITE bit) that must be set to enable the interrupt features. Moreover there is a global inter- rupt flag (I2CSR1.EVF bit) which is set when one of the interrupt events occurs (except the End Of Block interrupts - see the DMA Features section). The “Data Received” interrupt source occurs after the acknowledge of a received data byte is per- formed. It is generated when the I2CSR1.BTF flag is set and the I2CSR1.TRA flag is zero. If the DMA feature is enabled in receiver mode, this interrupt is not generated and the same inter- rupt vector is used to send a Receiving End Of Block interrupt (See the DMA feature section). The “Peripheral Ready To Transmit” interrupt source occurs as soon as a data byte can be transmitted by the peripheral. It is generated when the I2CSR1.BTF and the I2CSR1.TRA flags are set. If the DMA feature is enabled in transmitter mode, this interrupt is not generated and the same inter- rupt vector is used to send a Transmitting End Of Block interrupt (See the DMA feature section). The “Error condition” interrupt source occurs when one of the following condition occurs: – Address matched in Slave mode while I2CCR.ACK=1 (I2CSR1.ADSL and I2CSR1.EVF flags = 1) – Start condition generated (I2CSR1.SB and I2CSR1.EVF flags = 1) – No acknowledge received after byte transmis- sion (I2CSR2.AF and I2CSR1.EVF flags = 1) – Stop detected in Slave mode (I2CSR2.STOPF and I2CSR1.EVF flags = 1) – Arbitration lost in Master mode (I2CSR2.ARLO and I2CSR1.EVF flags = 1) – Bus error, Start or Stop condition detected during data transfer (I2CSR2.BERR and I2CSR1.EVF flags = 1) – Master has sent the header byte (I2CSR1.ADD10 and I2CSR1.EVF flags = 1) – Address byte successfully transmitted in Master mode. (I2CSR1.EVF = 1 and I2CSR2.ADDTX=1) Each interrupt source has a dedicated interrupt address pointer vector stored in the I2CIVR regis- ter. The five more significant bits of the vector ad- dress are programmable by the customer, where- as the three less significant bits are set by hard- ware depending on the interrupt source: – 010: error condition detected – 100: data received – 110: peripheral ready to transmit The priority with respect to the other peripherals is programmable by setting the PRL[2:0] bits in the I2CISR register. The lowest interrupt priority is ob- tained by setting all the bi ts (this priority level is never acknowledged by the CPU and is equivalent to disabling the interrupts of the peripheral); the highest interrupt priority is programmed by reset- ting all the bits. See the Interrupt and DMA chap- ters for more details. The internal priority of the interrupt sources of the peripheral is fixed by ha rdware with the following order: “Error Condition” (highest priority), “Data Received”, “Peripheral Ready to Transmit”. Note: The DMA has the highest priority over the interrupts; moreover the “Transmitting End Of Block” interrupt has the same priority as the “Pe- ripheral Ready to Transmit” interrupt and the “Re- ceiving End Of Block” interrupt has the same prior- ity as the “Data received” interrupt. Each of these three interrupt sources has a pend- ing bit (IERRP, IRXP, ITXP) in the I2CISR register that is set by hardware when the corresponding in- terrupt event occurs. An interrupt request is per- formed only if the corresponding mask bit is set (IERRM, IRXM, ITXM) in the I2CIMR register and the peripheral has a proper priority level. The pending bit has to be reset by software.

I2C BUS INTERFACE (Cont’d) Note: Until the pending bit is reset (while the cor- responding mask bit is set), the peripheral proc- esses an interrupt request. So, if at the end of an interrupt routine the pending bit is not reset, anoth- er interrupt request is performed. Note: Before the end of the transmission and re- ception interrupt routines, the I2CSR1.BTF flag bit should be checked, to acknowledge any interrupt requests that occurred during the interrupt routine and to avoid masking subsequent interrupt re- quests. Note: The “Error” event interrupt pending bit (I2CISR.IERRP) is forced high when the error event flags are set (ADD10, ADSL and SB flags of the I2CSR1 register; SCLF, ADDTX, AF, STOPF, ARLO and BERR flags of the I2CSR2 register). Moreover the Transmitting End Of Block interrupt has the same priority as the “Peripheral Ready to Transmit” interrupt and the Receiving End Of Block interrupt has the same priority as the “Data received” interrupt.

10.8.6 DMA Features

The peripheral can use the ST9+ on-chip Direct Memory Access (DMA) channels to provide high- speed data transaction between the peripheral and contiguous locations of Register File, and Memory. The transactions can occur from and to- ward the peripheral. The maximum number of transactions that each DMA channel can perform is 222 if the register file is selected or 65536 if memory is selected. The control of the DMA fea- tures is performed using registers placed in the pe- ripheral register page (I2CISR, I2CIMR, I2CRDAP, I2CRDC, I2CTDAP, I2CTDC). Each DMA transfer consists of three operations: – A load from/to the peripheral data register (I2CDR) to/from a location of Register File/Mem- ory addressed through the DMA Address Regis- ter (or Register pair) – A post-increment of the DMA Address Register (or Register pair) – A post-decrement of the DMA transaction coun- ter, which contains the number of transactions that have still to be performed. The priority level of the DMA features of the I interface with respect to the other peripherals and the CPU is the same as programmed in the I2CISR register for the interrupt sources. In the in- ternal priority level order of the peripheral, the “Er- ror” interrupt sources have higher priority, followed by DMA, “Data received” and “Receiving End Of Block” interrupts, “Peripheral Ready to Transmit” and “Transmitting End Of Block”. Refer to the Interrupt and DMA chapters for details on the priority levels. The DMA features are enabled by setting the cor- responding enabling bits (RXDM, TXDM) in the I2CIMR register. It is possible to select also the di- rection of the DMA transactions. Once the DMA transfer is completed (the transac- tion counter reaches 0 value), an interrupt request to the CPU is generated. This kind of interrupt is called “End Of Block”. The peripheral sends two different “End Of Block” interrupts depending on the direction of the DMA (Receiving End Of Block - Transmitting End Of Block). These interrupt sources have dedicated interrupt pending bits in the I2CIMR register (REOBP, TEOBP) and they are mapped on the same interrupt vectors as re- spectively “Data Received” and “Peripheral Ready to Transmit” interrupt sources. The same corre- spondence exists about the internal priority be- tween interrupts. Note: The I2CCR.ITE bit has no effect on the End Of Block interrupts. Moreover, the I2CSR1.EVF flag is not set by the End Of Block interrupts.

I2C BUS INTERFACE (Cont’d)

10.8.6.1 DMA between Peripheral and Register

If the DMA transaction is made between the pe- ripheral and the Register File, one register is required to hold the DMA Address and one to hold the DMA transaction counter. These two registers must be located in the Regis- ter File: – the DMA Address Register in the even ad- dressed register, – the DMA Transaction Counter in the following register (odd address). They are pointed to by the DMA Transaction Counter Pointer Register (I2CRDC register in re- ceiving, I2CTDC register in transmitting) located in the peripheral register page. In order to select the DMA transaction with the Register File, the control bit I2CRDC.RF/MEM in receiving mode or I2CT DC.RF/MEM in transmit- ting mode must be set. The transaction Counter Register must be initial- ized with the number of DMA transfers to perform and will be decremented after each transaction. The DMA Address Register must be initialized with the starting address of the DMA table in the Regis- ter File, and it is increas ed after each transaction. These two registers must be located between ad- dresses 00h and DFh of the Register File. When the DMA occurs between Peripheral and Register File, the I2CTDAP register (in transmis- sion) and the I2CRDAP one (in reception) are not used.

10.8.6.2 DMA between Peripheral and Memory

If the DMA transaction is made between the pe- ripheral and Memory, a register pair is required to hold the DMA Address and another register pair to hold the DMA Transaction counter. These two pairs of registers must be located in the Register File. The DMA Address pair is pointed to by the DMA Address Pointer Register (I2CRDAP register in reception, I2CTDAP register in transmission) lo- cated in the peripheral register page; the DMA Transaction Counter pair is pointed to by the DMA Transaction Counter Pointer Register (I2CRDC register in reception, I2CTDC register in transmis- sion) located in the peripheral register page. In order to select the DMA transaction with the Memory Space, the control bit I2CRDC.RF/MEM in receiving mode or I2CTDC.RF/MEM in transmit- ting mode must be reset. The Transaction Counter registers pair must be in- itialized with the number of DMA transfers to per- form and will be decremen ted after each transac- tion. The DMA Address register pair must be ini- tialized with the starting address of the DMA table in the Memory Space, and it is increased after each transaction. These two register pairs must be located between addresses 00h and DFh of the Register File.

10.8.6.3 DMA in Master Receive

To correctly manage the reception of the last byte when the DMA in Master Receive mode is used, the following sequence of operations must be per- formed: 1. The number of data bytes to be received must be set to the effective number of bytes minus one byte. 2. When the Receiving End Of Block condition occurs, the I2CCR.STOP bit must be set and the I2CCR.ACK bit must be reset. The last byte of the reception sequence can be re- ceived either using inte rrupts/polling or using DMA. If the user wants to receive the last byte us- ing DMA, the number of bytes to be received must be set to 1, and the DMA in reception must be re- enabled (IMR.RXDM bit set) to receive the last byte. Moreover the Receiving End Of Block inter- rupt service routine must be designed to recognize and manage the two different End Of Block situa- tions (after the first sequence of data bytes and af- ter the last data byte).

I2C BUS INTERFACE (Cont’d)

10.8.7 Register Description

IMPORTANT: 1. To guarantee correct operation, before enabling the peripheral (while I2CCR.PE=0), configure bit7 and bit6 of the I2COAR2 register according to the internal clock INTCLK (for example 11xxxxxxb in the range 14 - 30 MHz). 2. Bit7 of the I2CCR register must be cleared. I 2C CONTROL REGISTER (I2CCR) R240 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Bit 7:6 = Reserved Must be cleared Bit 5 = PE Peripheral Enable. This bit is set and cleared by software. 0: Peripheral disabled (reset value) 1: Master/Slave capability Notes: – When I2CCR.PE=0, all the bits of the I2CCR register and the I2CSR1-I2CSR2 registers ex- cept the STOP bit are reset. All outputs will be re- leased while I2CCR.PE=0 – When I2CCR.PE=1, the corresponding I/O pins are selected by hardware as alternate functions (open drain). – To enable the I 2C interface, write the I2CCR reg- ister TWICE with I2CCR.PE=1 as the first write only activates the interface (only I2CCR.PE is set). – When PE=1, the FREQ[2:0] and EN10BIT bits in the I2COAR2 and I2CADR registers cannot be written. The value of these bits can be changed only when PE=0. Bit 4 = ENGC General Call address enable. Setting this bit the peripheral works as a slave and the value stored in the I2CADR register is recog- nized as device address. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (I2CCR.PE=0). 0: The address stored in the I2CADR register is ignored (reset value) 1: The General Call address stored in the I2CADR register will be acknowledged Note: The correct value (usually 00h) must be written in the I2CADR register before enabling the General Call feature. Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (I2CCR.PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). – In master mode: 0: No start generation 1: Repeated start generation – In slave mode: 0: No start generation (reset value) 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (I2CCR.PE=0). 0: No acknowledge returned (reset value) 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. It is not cleared when the interface is disabled (I2CCR.PE=0). In slave mode, this bit must be set only when I2CSR1.BTF=1. – In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. – In slave mode: 0: No stop generation (reset value) 1: Release SCL and SDA lines after the current byte transfer (I2CSR1.BTF=1). In this mode the STOP bit has to be cleared by software. 0 0 PE ENGC START ACK STOP ITE

I2C BUS INTERFACE (Cont’d) Bit 0 = ITE Interrupt Enable. The ITE bit enables the generation of interrupts. This bit is set and cleared by software and cleared by hardware when the interface is disabled (I2CCR.PE=0). 0: Interrupts disabled (reset value) 1: Interrupts enabled after any of the following con- ditions: – Byte received or to be transmitted (I2CSR1.BTF and I2CSR1.EVF flags = 1) – Address matched in Slave mode while I2CCR.ACK=1 (I2CSR1.ADSL and I2CSR1.EVF flags = 1) – Start condition generated (I2CSR1.SB and I2CSR1.EVF flags = 1) – No acknowledge received after byte transmis- sion (I2CSR2.AF and I2CSR1.EVF flags = 1) – Stop detected in Slave mode (I2CSR2.STOPF and I2CSR1.EVF flags = 1) – Arbitration lost in Master mode (I2CSR2.ARLO and I2CSR1.EVF flags = 1) – Bus error, Start or Stop condition detected during data transfer (I2CSR2.BERR and I2CSR1.EVF flags = 1) – Master has sent header byte (I2CSR1.ADD10 and I2CSR1.EVF flags = 1) – Address byte successfully transmitted in Mas- ter mode. (I2CSR1.EVF = 1 and I2CSR2.ADDTX = 1) SCL is held low when the ADDTX flag of the I2CSR2 register or the ADD10, SB, BTF or ADSL flags of I2CSR1 register are set (See Figure 128) or when the DMA is not complete. The transfer is suspended in all cases except when the BTF bit is set and the DMA is enabled. In this case the event routine must suspend the DMA transfer if it is required. I 2C STATUS REGISTER 1 (I2CSR1) R241 - Read Only Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Note: Some bits of this register are reset by a read operation of the register. Care must be taken when using instructions that work on single bit. Some of them perform a read of all the bits of the register before modifying or testing the wanted bit. So oth- er bits of the register could be affected by the op- eration. In the same way, the test/compare operations per- form a read operation. Moreover, if some interrupt events occur while the register is read, the corresponding flags are set, and correctly read, but if the read operation resets the flags, no interrupt request occurs. Bit 7 = EVF Event Flag. This bit is set by hardware as soon as an event ( listed below or described in Figure 128) occurs. It is cleared by software when all event conditions that set the flag are cleared. It is also cleared by hardware when the interface is disabled (I2CCR.PE=0). 0: No event 1: One of the following events has occurred: – Byte received or to be transmitted (I2CSR1.BTF and I2CSR1.EVF flags = 1) – Address matched in Slave mode while I2CCR.ACK=1 (I2CSR1.ADSL and I2CSR1.EVF flags = 1) – Start condition generated (I2CSR1.SB and I2CSR1.EVF flags = 1) – No acknowledge received after byte transmis- sion (I2CSR2.AF and I2CSR1.EVF flags = 1) – Stop detected in Slave mode (I2CSR2.STOPF and I2CSR1.EVF flags = 1) – Arbitration lost in Master mode (I2CSR2.ARLO and I2CSR1.EVF flags = 1) – Bus error, Start or Stop condition detected during data transfer (I2CSR2.BERR and I2CSR1.EVF flags = 1) – Master has sent header byte (I2CSR1.ADD10 and I2CSR1.EVF flags = 1) EVF ADD10 TRA BUSY BTF ADSL M/SL SB

I2C BUS INTERFACE (Cont’d) – Address byte successfully transmitted in Mas- ter mode. (I2CSR1.EVF = 1 and I2CSR2.ADDTX=1) Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set when the master has sent the first byte in 10-bit address mode. An interrupt is gener- ated if ITE=1. It is cleared by software reading I2CSR1 register followed by a write in the I2CDR register of the second address byte. It is also cleared by hard- ware when peripheral is disabled (I2CCR.PE=0) or when the STOPF bit is set. 0: No ADD10 event occurred. 1: Master has sent first address byte (header). Bit 5 = TRA Transmitter/ Receiver. When BTF flag of this register is set and also TRA=1, then a data byte has to be transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after the STOPF flag of I2CSR2 register is set, loss of bus arbitration (ARLO flag of I2CSR2 register is set) or when the interface is disabled (I2CCR.PE=0). 0: A data byte is received (if I2CSR1.BTF=1) 1: A data byte can be transmitted (if I2CSR1.BTF=1) Bit 4 = BUSY Bus Busy. It indicates a communication in progress on the bus. The detection of the communications is al- ways active (even if the peripheral is disabled). This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. This in formation is still updated when the interface is disabled (I2CCR.PE=0). 0: No communication on the bus 1: Communication ongoing on the bus Bit 3 = BTF Byte Transfer Finished. This bit is set by hardware as soon as a byte is cor- rectly received or before the transmission of a data byte with interrupt generation if ITE=1. It is cleared by software reading I2CSR1 register followed by a read or write of I2CDR register or when DMA is complete. It is also cleared by hardware when the interface is disabled (I2CCR.PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. BTF is cleared by reading I2CSR1 register followed by writing the next byte in I2CDR register or when DMA is complete. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading I2CSR1 reg- ister followed by reading the byte from I2CDR register or when DMA is complete. The SCL line is held low while I2CSR1.BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware if the received slave ad- dress matches the I2COAR1/I2COAR2 register content or a General Call address. An interrupt is generated if ITE=1. It is cleared by software reading I2CSR1 register or by hardware when the interface is disabled (I2CCR.PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (Start condition generated on the lines after the I2CCR.START bit is set). It is cleared by hardware after detecting a Stop condi- tion on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (I2CCR.PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start Bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write of START=1 if the bus is free). An interrupt is gener- ated if ITE=1. It is cleared by software reading I2CSR1 register followed by writing the address byte in I2CDR register. It is also cleared by hard- ware when the interface is disabled (I2CCR.PE=0). The SCL line is held low while SB=1. 0: No Start condition 1: Start condition generated

I2C BUS INTERFACE (Cont’d) I2C STATUS REGISTER 2 (I2CSR2) R242 - Read Only Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Note: Some bits of this register are reset by a read operation of the register. Care must be taken when using instructions that work on single bit. Some of them perform a read of all the bits of the register before modifying or testing the wanted bit. So oth- er bits of the register could be affected by the op- eration. In the same way, the test/compare operations per- form a read operation. Moreover, if some interrupt events occur while the register is read, the corresponding flags are set, and correctly read, but if the read operation resets the flags, no interrupt request occurs. Bits 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = ADDTX Address or 2nd header transmitted in Master mode. This bit is set by hardware when the peripheral, enabled in Master mode, has received the ac- knowledge relative to: – Address byte in 7-bit mode – Address or 2nd header byte in 10-bit mode. 0: No address or 2nd header byte transmitted 1: Address or 2nd header byte transmitted. Bit 4 = AF Acknowledge Failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading I2CSR2 register after the falling edge of the acknowledge SCL pulse, or by hardware when the interface is disa- bled (I2CCR.PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure detected 1: A data or address byte was not acknowledged Bit 3 = STOPF Stop Detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge. An interrupt is generated if ITE=1. It is cleared by software reading I2CSR2 register or by hardware when the interface is disabled (I2CCR.PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected (while slave receiver) Bit 2 = ARLO Arbitration Lost. This bit is set by hardware when the interface (in master mode) loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading I2CSR2 register or by hardware when the interface is disabled (I2CCR.PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 1 = BERR Bus Error. This bit is set by hardware when the interface de- tects a Start or Stop condition during a byte trans- fer. An interrupt is generated if ITE=1. It is cleared by software reading I2CSR2 register or by hardware when the interface is disabled (I2CCR.PE=0). The SCL line is not held low while BERR=1. Note: If a misplaced start condition is detected, also the ARLO flag is set; moreover, if a misplaced stop condition is placed on the acknowledge SCL pulse, also the AF flag is set. 0: No Start or Stop condition detected during byte transfer 1: Start or Stop condition detected during byte transfer Bit 0 = GCAL General Call address matched. This bit is set by hardware after an address matches with the value stored in the I2CADR reg- ister while ENGC=1. In the I2CADR the General Call address must be placed before enabling the peripheral. It is cleared by hardware after the detection of a Stop condition, or when the peripheral is disabled (I2CCR.PE=0). 0: No match 1: General Call address matched. 0 0 ADDTX AF STOPF ARLO BERR GCAL

I2C BUS INTERFACE (Cont’d) I2C CLOCK CONTROL REGISTER (I2CCCR) R243 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Bit 7 = FM/SM Fast/Standard I2C mode. This bit is used to select between fast and stand- ard mode. See the description of the following bits. It is set and cleared by software. It is not cleared when the peripheral is disabled (I2CCR.PE=0) Bits 6:0 = CC[6:0] 9-bit divider programming Implementation of a programmable clock divider. These bits and the CC[8:7] bits of the I2CECCR register select the speed of the bus (F SCL) de- pending on the I2C mode. They are not cleared when the interface is disa- bled (I2CCR.PE=0). Refer to the Electrical Characteristics section for the table of values (Table 70 on page 399). Note: The programmed frequency is available with no load on SCL and SDA pins. I2C OWN ADDRESS REGISTER 1 (I2COAR1) R244 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) 7-bit Addressing Mode Bits 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the inter- face. They are not cleared when the interface is disa- bled (I2CCR.PE=0). Bit 0 = ADD0 Address direction bit. This bit is don’t care; the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (I2CCR.PE=0). Note: Address 01h is always ignored. 10-bit Addressing Mode Bits 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I 2Cbus address of the interface. They are not cleared when the interface is disa- bled (I2CCR.PE=0). FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

I2C BUS INTERFACE (Cont’d) I2C OWN ADDRESS REGISTER 2 (I2COAR2) R245 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Bits 7:6,4 = FREQ[2:0] Frequency bits. IMPORTANT: To guarantee correct operation, set these bits before enabling the interface (while I2CCR.PE=0). These bits can be set only when the interface is disabled (I2CCR.PE=0). To configure the interface to I 2C specified delays, se lect the value corre- sponding to the microcontroller internal frequency INTCLK. Note: If an incorrect value, with respect to the MCU internal frequency, is written in these bits, the timings of the peri pheral will not meet the I bus standard requirements. Note: The FREQ[2:0] = 100, 101, 110, 111 config- urations must not be used. Bit 5 = EN10BIT Enable 10-bit I2Cbus mode. When this bit is set, the 10-bit I2Cbus mode is en- abled. This bit can be written only when the peripheral is disabled (I2CCR.PE=0). 0: 7-bit mode selected 1: 10-bit mode selected Bits 4:3 = Reserved. Bits 2:1 = ADD[9:8] Interface address. These are the most significant bits of the I 2Cbus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (I2CCR.PE=0). Bit 0 = Reserved. I2C DATA REGISTER (I2CDR) R246 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Bits 7:0 = DR[7:0] I2C Data. – In transmitter mode: I2CDR contains the next byte of data to be trans- mitted. The byte transmission begins after the microcontroller has written in I2CDR or on the next rising edge of the clock if DMA is complete. – In receiver mode: I2CDR contains the last byte of data received. The next byte receipt begins after the I2CDR read by the microcontroller or on the next rising edge of the clock if DMA is complete. GENERAL CALL ADDRESS (I2CADR) R247 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 1010 0000 (A0h) Bits 7:0 = ADR[7:0] Interface address. These bits define the I 2Cbus General Call address of the interface. It must be written with the correct value depending on the use of the peripheral.If the peripheral is used in I 2C bus mode, the 00h value must be loaded as General Call address. The customer could load the register with other values. The bits can be written only when the peripheral is disabled (I2CCR.PE=0) The ADR0 bit is don’t care; the interface acknowl- edges either 0 or 1. Note: Address 01h is always ignored. FREQ1 FREQ0 EN10BIT FREQ2 0 ADD9 ADD8 0 INTCLK Range (MHz) FREQ2 FREQ1 FREQ0 2.5 - 6 0 0 0 6- 10 0 0 1 10- 14 0 1 0 14 - 24 0 1 1 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

I2C BUS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (I2CISR) R248 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 1xxx xxxx (xxh) Bit 7 = Reserved. Must be kept at 1 Bits 6:4 = PRL[2:0] Interrupt/DMA Priority Bits. The priority is encoded with these three bits. The value of “0” has the highest priority, the value “7” has no priority. After the setting of this priority lev- el, the priorities between the different Interrupt/ DMA sources is hardware defined according with the following scheme: – Error condition Interrupt (If DMASTOP=1) (High- est priority) – Receiver DMA request – Transmitter DMA request – Error Condition Interrupt (If DMASTOP=0 – Data Received/Receiver End Of Block – Peripheral Ready To Transmit/Transmitter End Of Block (Lowest priority) Bit 3 = Reserved. Must be cleared. Bit 2 = IERRP Error Condition pending bit 0: No error 1: Error event detected (if ITE=1) Note: The Interrupt pending bits can be reset by writing a “0” but is not possible to write a “1”. It is mandatory to clear the interrupt source by writing a “0” in the pending bit when executing the interrupt service routine. When serving an interrupt routine, the user should reset ONLY the pending bit related to the served interrupt routine (and not reset the other pending bits). To detect the specific error condition that oc- curred, the flag bits of the I2CSR1 and I2CSR2 register should be checked. Note: The IERRP pending bit is forced high when- the error event flags are set (ADSL and SB flags in the I2CSR1 register, SCLF, ADDTX, AF, STOPF, ARLO and BERR flags in the I2CSR2 register). If at least one flag is set, the application code should not reset the IERRP bit. Bit 1 = IRXP Data Received pending bit 0: No data received 1: data received (if ITE=1). Bit 0 = ITXP Peripheral Ready To Transmit pend- ing bit 0: Peripheral not ready to transmit 1: Peripheral ready to transmit a data byte (if ITE=1).

1 PRL2 PRL1 PRL0 0 IERRP IRXP ITXP

I2C BUS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (I2CIVR) R249 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: Undefined Bits 7:3 = V[7:3] Interrupt Vector Base Address. User programmable interrupt vector bits. These are the five more significant bits of the interrupt vector base address. They must be set before en- abling the interrupt features. Bits 2:1 = EV[2:1] Encoded Interrupt Source. These Read-Only bits are set by hardware accord- ing to the interrupt source: – 01: error condition detected – 10: data received – 11: peripheral ready to transmit Bit 0 = Reserved. Forced by hardware to 0. RECEIVER DMA SOURCE ADDRESS POINTER REGISTER (I2CRDAP) R250 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: Undefined Bits 7:1 = RA[7:1] Receiver DMA Address Pointer. I2CRDAP contains the address of the pointer (in the Register File) of the Receiver DMA data source when the DMA is selected between the peripheral and the Memory Space. Otherwise, (DMA between peripheral and Register file), this register has no meaning. See Section 10.8.6.1 for more details on the use of this register. Bit 0 = RPS Receiver DMA Memory Pointer Selec- tor. If memory has been selected for DMA transfer (I2CRDC.RF/MEM = 0) then: 0: Select ISR register for Receiver DMA transfer address extension. 1: Select DMASR register for Receiver DMA trans- fer address extension. RECEIVER DMA TRANSACTION COUNTER REGISTER (I2CRDC) R251 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: Undefined Bits 7:1 = RC[7:1] Receiver DMA Counter Pointer. I2CRDC contains the address of the pointer (in the Register File) of the DM A receiver transaction counter when the DMA between Peripheral and Memory Space is selected. Otherwise (DMA be- tween Peripheral and Register File), this register points to a pair of registers that are used as DMA Address register and DMA Transaction Counter. more details on the use of this register. Bit 0 = RF/MEM Receiver Register File/ Memory Selector. 0: DMA towards Memory 1: DMA towards Register file V7 V6 V5 V4 V3 EV2 EV1 0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RPS RC7 RC6 RC5 RC4 RC3 RC2 RC1 RF/MEM

I2C BUS INTERFACE (Cont’d) TRANSMITTER DMA SOURCE ADDRESS POINTER REGISTER (I2CTDAP) R252 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: Undefined Bits 7:1= TA[7:1] Transmit DMA Address Pointer. I2CTDAP contains the address of the pointer (in the Register File) of the Transmitter DMA data source when the DMA between the peripheral and the Memory Space is selected. Otherwise (DMA between the peripheral and Register file), this reg- ister has no meaning. See Section 10.8.6.2 for more details on the use of this register. Bit 0 = TPS Transmitter DMA Memory Pointer Se- lector. If memory has been selected for DMA transfer (I2CTDC.RF/MEM = 0) then: 0: Select ISR register for transmitter DMA transfer address extension. 1: Select DMASR register for transmitter DMA transfer address extension. TRANSMITTER DMA TRANSACTION COUN- TER REGISTER (I2CTDC) R253 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: Undefined Bits 7:1 = TC[7:1] Transmit DMA Counter Pointer. I2CTDC contains the address of the pointer (in the Register File) of the DMA transmitter transaction counter when the DMA between Peripheral and Memory Space is selected. Otherwise, if the DMA between Peripheral and Register File is selected, this register points to a pair of registers that are used as DMA Address register and DMA Transac- tion Counter. more details on the use of this register. Bit 0 = RF/MEM Transmitter Register File/ Memo- ry Selector. 0: DMA from Memory 1: DMA from Register file EXTENDED CLOCK CONTROL REGISTER (I2CECCR) R254 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 0000 0000 (00h) Bits 7:2 = Reserved. Must always be cleared. Bits 1:0 = CC[8:7] 9-bit divider programming Implementation of a programmable clock divider. These bits and the CC[6:0] bits of the I2CCCR reg- ister select the speed of the bus (F SCL). For a description of the use of these bits, see the I2CCCR register. They are not cleared when the interface is disa- bled (I2CCCR.PE=0). TA7 TA6 TA5 TA4 TA3 TA2 TA1 TPS TC7 TC6 TC5 TC4 TC3 TC2 TC1 RF/MEM 0 0 0 0 0 0 CC8 CC7

I2C BUS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (I2CIMR) R255 - Read / Write Register Page: 20 (I2C_0) or 22 (I2C_1) Reset Value: 00xx 0000 (x0h) Bit 7 = RXDM Receiver DMA Mask. 0: DMA reception disable. 1: DMA reception enable RXDM is reset by hardware when the transaction counter value decrements to zero, that is when a Receiver End Of Block interrupt is issued. Bit 6 = TXDM Transmitter DMA Mask. 0: DMA transmission disable. 1: DMA transmission enable. TXDM is reset by hardware when the transaction counter value decrements to zero, that is when a Transmitter End Of Block interrupt is issued. Bit 5 = REOBP Receiver DMA End Of Block Flag. REOBP should be reset by software in order to avoid undesired interrupt routines, especially in in- itialization routine (after reset) and after entering the End Of Block interrupt routine.Writing “0” in this bit will cancel the interrupt request Note: REOBP can only be written to “0”. 0: End of block not reached. 1: End of data block in DMA receiver detected Bit 4 = TEOBP Transmitter DMA End Of Block TE- OBP should be reset by software in order to avoid undesired interrupt routines, especially in initializa- tion routine (after reset) and after entering the End Of Block interrupt routine.Writing “0” will cancel the interrupt request. Note: TEOBP can only be written to “0”. 0: End of block not reached 1: End of data block in DMA transmitter detected. Bit 3 = Reserved. This bit must be cleared. Bit 2 = IERRM Error Condition interrupt mask bit. This bit enables/ disables the Error interrupt. 0: Error interrupt disabled. 1: Error Interrupt enabled. Bit 1 = IRXM Data Received interrupt mask bit. This bit enables/ disables the Data Received and Receive DMA End of Block interrupts. 0: Interrupts disabled 1: Interrupts enabled Note: This bit has no effect on DMA transfer Bit 0 = ITXM Peripheral Ready To Transmit inter- rupt mask bit. This bit enables/ disables the Peripheral Ready To Transmit and Transmit DMA End of Block inter- rupts. 0: Interrupts disabled 1: Interrupts enabled Note: This bit has no effect on DMA transfer. RXDM TXDM REOBP TEOBP 0 IERRM IRXM ITXM

Table 51. I2C BUS Register Map and Reset Values

10.8.8 IMPORTANT NOTES ON I2C

J1850 Byte Level Protocol Decoder (JBLPD)

10.9 J1850 Byte Level Protocol Decoder (JBLPD)

10.9.1 Introduction

The JBLPD is used to exchange data between the ST9 microcontroller and an external J1850 trans- ceiver I.C. The JBLPD transmits a string of variable pulse width (VPW) symbols to the transceiver. It also re- ceives VPW encoded symbols from the transceiv- er, decodes them and places the data in a register. In-frame responses of type 0, 1, 2 and 3 are sup- ported and the appropriate normalization bit is generated automatically. The JBLPD filters out any incoming messages which it does not care to receive. It also includes a programmable external loop delay. The JBLPD uses two signals to communicate with the transceiver: – VPWI (input) – VPWO (output)

10.9.2 Main Features

■ SAE J1850 compatible ■ Digital filter ■ In-Frame Responses of type 0, 1, 2, 3 supported with automatic normalization bit ■ Programmable External Loop Delay ■ Diagnostic 4x time mode ■ Diagnostic Local Loopback mode ■ Wide range of MCU internal frequencies allowed ■ Low power consumption mode (JBLPD suspended) ■ Very low power consumption mode (JBLPD disabled) ■ Don’t care message filter ■ Selectable VPWI input polarity ■ Selectable Normalization Bit symbol form ■ 6 maskable interrupts ■ DMA transmission and reception with End Of Block interrupts

Figure 130. JBLPD Byte Level Protocol Decoder Block Diagram

10.9.3 Functional Description

10.9.3.1 J1850 protocol symbols

or a passive state (logic low level on VPWO). An idle J1850 bus is in a passive state. ration depending on the symbol being transmitted. Each symbol is placed directly next to another. predominate during bus arbitration. the last bit is an active state. (including the invalid bit symbol) was recognized. chronize the VPW decoder to the invalid bit edges. J1850 bus or inverted with respect to it. Table 52. J1850 Symbol definitions Table 53. J1850 VPW Mode Timing Value (Tv)

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.3.2 Transmitting Messages

This section describes the general procedures used by the JBLPD to successfully transmit J1850 frames of data out the VPWO pin. The first five sub-sections describe the procedures used for transmitting the specific transmit data types. The last section goes into the details of the transmitted symbol timing, synchronizing of symbols received from the external J1850 bus, and how data bit ar- bitration works. The important concept to note for transmitting data is: the activity sent over the VPWO line should be timed with respect to the levels and transitions seen on the filtered VPWI line. The J1850 bus is a multiplexed bus, and the VPWO & VPWI pins interface to this bus through a transceiver I.C. Therefore, the propagation delay through the transceiver I.C. and external bus filter- ing must be taken into account when looking for transmitted edges to appear back at the receiver. The external propagation delay for an edge sent out on the VPWO line, to be detected on the VPWI line is denoted as T p-ext and is programmable be- tween 0 and 31 µs nominal via the JDLY[4:0] bits in CONTROL register. The transmitter VPW encoder sets the proper level to be sent out the VPWO line. It then waits for the corresponding level transition to be reflected back at the VPW decoder input. Taking into account the external loop delay (T p-ext) and the digital filter delay, the encoder will time its output to remain at this level so that the received symbol is at the correct nominal symbol time (refer to “Transmit Opcode Queuing” section). If arbitra- tion is lost at any time during bit 0 or bit 1 transmis- sion, then the VPWO line goes passive. At the end of the symbol time on VPWO, the encoder chang- es the state of VPWO if any more information is to be transmitted. It then times the new state change from the receiver decoder output. Note that depending on the symbol (especially the SOF, NB0, NB1 symbols) the decoder output may actually change to the desired state before the transmit is attempted. It is important to still syn- chronize off the decoder output to time the VPWO symbol time. A detailed description of the JBLPD opcodes can be find in the description of the OP[2:0] bits in the TXOP register. Message Byte String Transmission (Type 0 IFR) Message byte transmitting is the outputting of data bytes on the VPWO pin that occurs subsequent to a received bus idle condition. All message byte strings start with a SOF symbol transmission, then one or more data bytes are transmitted. A CRC byte is then transmitted followed by an EOD sym- bol (see Figure 131) to complete the transmission. If transmission is queued while another frame is being received, then the JBLPD will time an Inter- Frame Separation (IFS) time (Tv6) before com- mencing with the SOF character. The user program will decide at some point that it wants to initiate a message byte string. The user program writes the TXDATA register with the first message data byte to be transmitted. Next, the TXOP register is written with the MSG opcode if more than one data byte is contained within the message, or with MSG+CRC opcode if one data byte is to be transmitted. The action of writing the TXOP register causes the TRDY bit to be cleared signifying that the TXDATA register is full and a corresponding opcode has been queued. The JBLPD must wait for an EOF nominal time period at which time data is transferred from the TXDATA register to the transmit shift register. The TRDY bit is again set since the TXDATA register is empty. The JBLPD should also begin transmission if an- other device begins transmitting early. As long as an EOF minimum time period elapses, the JBLPD should begin timing and asserting the SOF symbol with the intention of arbitrating for the bus during the transmission of the first data byte. If a transmit is requested during an incoming SOF symbol, the JBLPD should be able to synchronize itself to the incoming SOF up to a time of Tv1 max. (96 µs) into the SOF symbol before declaring that it was too late to arbitrate for this frame.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) If the J1850 bus was IDLE at the time the first data byte and opcode are written, the transmitter will immediately transfer data from the TXDATA regis- ter to the transmit shift register. The TRDY bit will once again be set signifying the readiness to ac- cept a new data byte. The second data byte can then be written followed by the respective opcode. In the case of the last data byte, the TXOP register should be written with the MSG+CRC opcode. The transmitter will transmit th e internally generated CRC after the last bit of the data byte. Once the TRDY bit is set signifying the acceptance of the last data byte, the first byte of the next message can be queued by writing the TXDATA register fol- lowed by a TXOP register write. The block will wait until the current data and the CRC data byte are sent out and a new IFS has expired before trans- mitting the new data. This is the case even if IFR data reception takes place in the interim. Lost arbitration any time during the transfer of type 0 data will be honoured by immediately relinquish- ing control to the higher priority message. The TLA bit in the STATUS register is set accordingly and an interrupt will be gener ated assuming the TLA_M bit in the IMR register is set. It is responsi- bility of the user progra m to re-send the message beginning with the first byte if desired. This may be done at any time by rewriting only the TXOP regis- ter if the TXDATA contents have not changed. Any transmitted data and CRC bytes during the transmit frame will also be received and trans- ferred to the RXDATA register if the corresponding message filter bit is set in the FREG[0:31] regis- ters. If the corresponding bit is not set in FREG[0:31], then the transmitted data is also not transferred to RXDATA. Also, the RDRF will not get set during frame and receive events such as RDOF & EODM. NOTE: The correct procedure for transmitting is to write first the TXDATA register and then the TXOP register except during DMA transfers (see Section

10.9.6.4 DMA Management in Transmission

Mode). Transmitting a Type 1 IFR The user program will dec ide to transmit an IFR type 1 byte in response to a message which is cur- rently being received (See Figure 132). It does so by writing the IFR1 opcode to the TXOP register. Transmitting IFR data type 1 requires only a single write of the TXOP register with the IFR1 opcode set. The MLC[3:0] bits should be set to the proper “byte-received-count-required-before-IFR’ing” val- ue. If no error conditions (IBD, IFD, TRA, RBRK or CRCE) exist to prevent transmission, the JBLPD peripheral will then transmit out the contents of the PADDR register at the next EOD nominal time pe- riod or at a time greater than the EOD minimum time period if a falling edge is detected on filtered J1850 bus line signifying another transmitter is be- ginning early. The NB1 symbol precedes the PAD- DR register value and is followed with an EOF de- limiter. The TRDY flag is cleared on the write of the TXOP register. The TRDY bit is set once the NB1 begins transmitting. Although the JBLPD should never lose arbitration for data in the IFR portion of a type 1 frame, higher priority messages are always honoured under the rules of arbitration. If arbitration is lost then the VPWO line is set to the passive state. The TLA bit in the STATUS register is set accordingly and an interrupt will be generated if enabled. The IFR1 is not retried. It is lost if the JBLPD peripheral loses arbitration. Also, the data that made it out on the bus will be received in the RXDATA register if not put into sleep mode. Note that for the transmitter to synchronize to the incoming signals of a frame, an IFR should be queued before an EODM is re- ceived for the present frame.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Transmitting a Type 2 IFR The user program will decide to transmit an IFR type 2 byte in response to a message which is cur- rently being received (See Figure 133). It does so by writing the IFR2 opcode to the TXOP register. Transmitting IFR data type 2 requires only a single write of the TXOP register with the IFR2 opcode set. The MLC[3:0] bits can also be set to check for message length errors. If no error conditions (IBD, IFD, TRA, RBRK or CRCE) exist to prevent trans- mission, the JBLPD will tr ansmit out the contents of the PADDR register at the next EOD nominal time period or after an EOD minimum time period if a rising edge is detected on the filtered VPWI line signifying another transmitter beginning early. The NB1 symbol precedes the PADDR register value and is followed with an EOF delimiter. The TRDY flag will be cleared on the write of the TXOP regis- ter. The TRDY bit is set once the NB1 begins transmitting. Lost arbitration for this case is a normal occur- rence since type 2 IFR data is made up of single bytes from multiple responders. If arbitration is lost the VPWO line is released and the JBLPD waits until the byte on the VPWI line is completed. Note that the IFR that did make it out on the bus will be received in the RXDATA register if it is not put into sleep mode. Then, the JBLPD re-attempts to send its physical address immediately after the end of the last byte. The TLA bit is not set if arbitration is lost and the user program does not need to re- queue data or an opcod e. The JBLPD will re-at- tempt to send its PADDR register contents until it successfully does so or the 12-byte frame maxi- mum is reached if NFL=0. If NFL=1, then re-at- tempts to send an lFR2 are executed until can- celled by the CANCEL opcode or a JBLPD disa- ble. Note that for the transmitter to synchronize to the incoming signals of a frame, an IFR should be queued before an EODM is received for the present frame. Transmitting a Type 3 lFR Data String The user program will decide to transmit an IFR type 3 byte string in response to a message which is currently being received (See Figure 134 ). It does so by writing the IFR3 or IFR3+CRC opcode to the TXOP register. Transmitting IFR data type 3 is similar to transmitting a message, in that the TX- DATA register is written with the first data byte fol- lowed by a TXOP register write. For a single data byte IFR3 transmission, the TXOP register would be written with IFR3+CRC opcode set. The MLC[3:0] bits can also be set to a proper value to check for message length errors before enabling the IFR transmit. If no error conditions (IBD, IFD, TRA, RBRK or CRCE) exist to prevent transmission, the JBLPD will wait for an EOD nominal time period on the fil- tered VPWI line (or for at least an EOD minimum time followed by a rising edge signifying another transmitter beginning early) at which time data is transferred from the TXDATA register to the trans- mit shift register. The TRDY bit is set since the TX- DATA register is empty. A NB0 symbol is output on the VPWO line followed by the data byte and possibly the CRC byte if a IFR3+CRC opcode was set. Once the first IFR3 byte has been successfully transmitted, successive IFR3 bytes are sent with TXDATA/TXOP write sequences where the MLC[3:O] bits are don’t cares. The final byte in the IFR3 string must be transmitted with the IFR3+CRC opcode to trigger the JBLPD to ap- pend the CRC byte to the string. The user program may queue up the next message opcode se- quence once the TRDY bit has been set. Although arbitration should never be lost for data in the IFR portion of a type 3 frame, higher priority messages are always honoured under the rules of arbitration. If arbitration is lost then the block should relinquish the bus by taking the VPWO line to the passive state. In this case the TLA bit in the STATUS register is se t, and an interrupt will be generated if enabled. Note also, that the IFR data that did make it out on the bus will be received in the RXDATA register if not in sleep mode. Note that for the transmitter to synchronize to the in- coming signals of a frame, an IFR should be queued before an EODM is received for the cur- rent frame.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Transmit Opcode Queuing The JBLPD has the capability of queuing opcode transmits written to the TXOP register until J1850 bus conditions are in a correct state for the trans- mit to occur. For example, a MSGx opcode can be queued when the JBLPD is presently receiving a frame (or transmitting a MSG+CRC opcode) or an IFRx opcode can be queued when currently re- ceiving or transmitting the message portion of a frame. Queuing a MSG or MSG+CRC opcode for the next frame can occur while another frame is in progress. A MSGx opcode is written to the TXOP register when the present frame is past the point where arbitration for control of the bus for this frame can occur. The JBLPD will wait for a nomi- nal IFS symbol (or EOFmin if another node begins early) to appear on the VPWI line before com- mencing to transmit this queued opcode. The TRDY bit for the queued opcode will remain clear until the EOFmin is detected on the VPWI line where it will then get set. Queued MSGx transmits for the next frame do not get cancelled for TLA, IBD, IFD or CRCE errors that occur in the present frame. An RBRK error will cancel a queued op- code for the next frame. Queuing an IFRx opcode for the present frame can occur at any time after the detection of the be- ginning of an SOF character from the VPWI line. The queued IFR will wait for a nominal EOD sym- bol (or EODmin if another node begins early) be- fore commencing to transmit the IFR. A queued IFR transmit will be cancelled on IBD, lFD, CRCE, RBRK errors as well as on a correct message length check error or frame length limit violation if these checks are enabled. Transmit Bus Timing, Arbitration, and Syn- chronization The external J1850 bus on the other side of the transceiver I.C. is a single wire multiplex bus with multiple nodes transmitting a number of different types of message frames. Each node can transmit at any time and synchronization and arbitration is used to determine who wins control of the trans- mit. It is the obligation of the JBLPD transmitter section to synchronize off of symbols on the bus, and to place only nominal symbol times onto the bus within the accuracy of the peripheral (+/- 1 µs). To transmit proper symbols the JBLPD must know what is going on out on the bus. Fortunately, the JBLPD has a receiver pin which tells the transmit- ter about bus activity. Due to characteristics of the J1850 bus and the eight-clock digital filter, the sig- nals presented to the VPW symbol decoder are delayed a certain amount of time behind the actual J1850 bus. Also, due to wave shaping and other signal conditioning of the transceiver I.C. the ac- tions of the VPWO pin on the transmitter take time to appear on the bus itself. The total external J1850 bus delays are defined in the SAE J1850 standard as nominally 16 µs. The nominal 16 µs loop delay will actually vary between different transceiver I.C’s. The JBLPD peripheral thus in- cludes a programmability of the external loop de- lay in the bit positions JDLY[4:0]. This assures only nominal transmit symbols are placed on the bus by the JBLPD. The method of transmitting for the JBLPD includes interaction between the transmitter and the receiv- er. The transmitter starts a symbol by placing the proper level (active or passive) on its VPWO pin. The transmitter then waits for the corresponding pin transition (inverted, of course) at the VPW de- coder input. Note that th e level may actually ap- pear at the input before the transmitter places the value on the VPWO pin. Timing of the remainder of the symbol starts when the transition is detect- ed. Refer to Figure 136, Case 1. The symbol time- out value is defined as: SymbolTimeout = NominalSymbolTime - ExternalLoop- Delay - 8 µs NominalSymbolTime = Tv Symbol time ExternalLoopDelay = defined via JDLY[4:0] 8 µs = Digital Filter Bit-by-bit arbitration must be used to settle the conflicts that occur when multiple nodes attempt to transmit frames simultaneously. Arbitration is ap- plied to each data bit symbol transmitted starting after the SOF or NBx symbol and continuing until the EOD symbol. During simultaneous transmis- sions of active and passive states on the bus, the resultant state on the bus is the active state. If the JBLPD detects a received symbol from the bus that is different from the symbol being transmitted, then the JBLPD will discontinue its transmit opera- tion prior to the start of the next bit. Once arbitra- tion has been lost, the VPWO pin must go passive within one period of the prescaled clock of the pe- ripheral. Figure 135 shows 3 nodes attempting to arbitrate for the bus with Node B eventually win- ning with the highest priority data.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Use of symbol and bit synchronization is an inte- gral part of the J1850 bus scheme. Therefore, tight coupling of the encoder and decoder functions is required to maintain synchronization during trans- mits. Transmitted symbols and bits are initiated by the encoder and are timed through the decoder to realize synchronization. Figure 136 exemplifies synchronization with 3 examples for an SOF sym- bol and JDLY[4:0] = 01110b. Case 1 shows a single transmitter arbitrating for the bus. The VPWO pin is asserted, and 14µs later the bus transitions to an active state. The 14µs de- lay is due to the nominal delay through the exter- nal transceiver chip. The signal is echoed back to the transceiver through the VPWI pin, and pro- ceeds through the digital filter. The digital filter has a loop delay of 8 clock cycles with the signal finally presented to the decoder 22 µs after the VPWO pin was asserted. The decoder waits 178 µs be- fore issuing a signal to the encoder signifying the end of the symbol. The VPWO pin is de-asserted producing the nominal SOF bit timing (22 µs + 178µs = 200 µs). Case 2 shows a condition where 2 transmitters at- tempt to arbitrate for the bus at nearly the same time with a second transmitter, TX2, beginning slightly earlier than the VPWO pin. Since the JBLPD always times symbols from its receiver perspective, 178µs after the decoder sees the ris- ing edge it issues a signal to the encoder to signify the end of the SOF. Nominal SOF timings are maintained and the JBLPD re-synchronizes to TX2. Case 3 again shows an example of 2 transmitters attempting to arbitrate for the bus at nearly the same time with the VPWO pin starting earlier than TX2. In this case TX2 is required to re-synchronize to VPWO. All 3 examples exemplify how bus timings are driv- en from the receiver perspective. Once the receiv- er detects an active bus, the transmitter symbol timings are timed minus the transceiver and digital filter delays (i.e. SOF = 200 µs - 14µs - 8µs = 178µs). This synchronization and timing off of the VPWI pin occurs for every symbol while transmit- ting. This ensures true arbitration during data byte transmissions.

10.9.3.3 Receiving Messages

Data is received from th e external analog trans- ceiver on the VPWI pin. VPWI data is immediately passed through a digital filter that ignores all puls- es that are less than 7µs. Pulses greater than or equal to 7µs and less than 34µs are flagged as invalid bits (IBD) in the ERROR register. Once data passes through the filter, all delimiters are stripped from the data stream and data bits are shifted into the receive shift register by the decod- er logic. The first byte received after a valid SOF character is compared with the flags contained in FREG[0:31]. If the compare indicates that this message should be received, then the receive shift register contents are moved to the receive data register (RXDATA) for the user program to access. The Receive Data Register Full bit (RDRF) is set to indicate that a complete byte has been received. For each byte that is to be received in a frame, once an entire byte has been received, the receive shift register contents are moved to the receive data register (RXDATA). All data bits re- ceived, including CRC bits, are transferred to the RXDATA register. The Receive Data Register Full bit (RDRF) is set to indicate that a complete byte has been received. If the first byte after a valid SOF indicates non-re- ception of this frame, then the current byte in the receive shift register is inhibited from being trans- ferred to the RXDATA register and the RDRF flag remains clear (see the “Received Message Filter- ing” section). Also, no flags associated with receiv- ing a message (RDOF, CRCE, IFD, IBD) are set. A CRC check is kept on a ll bytes that are trans- ferred to the RXDATA register during message byte reception (succeed ing an SOF symbol) and IFR3 reception (succeeding an NB0 symbol). The CRC is initialized on receip t of the first byte that follows an SOF symbol or an NB0 symbol. The CRC check concludes on receipt of an EODM symbol. The CRC error bit (CRCE), therefore, gets set after the EODM symbol has been recognized. Refer to the “SAE Recommended Practice - J1850” manual for more information on CRCs.

array and the FREG[31].7 bit is bit 255). The I.D. be active at least until the filter comparison. will be reflected in the RXDATA register. the condition of the message transmit. Figure 137. I.D. Byte and Message Filter Array use

10.9.3.4 Sleep Mode

2) The J1850 bus line (after the filter) is passive. lows the user to not have to listen while talking.

10.9.3.5 Normalization Bit symbol selection

symbol timings used. Refer to Table 54.

10.9.3.6 VPWI input line management

POL bit description for more details.

10.9.3.7 Loopback mode

external VPWI pin is ignored (Refer to Figure 138). Table 54. Normalization Bit configurations

Figure 138. Local Loopback structure

10.9.3.8 Peripheral clock management

symbols timings in transmission and in reception. MCU Internal Freq. = 1MHz * (FREQ[5:0] + 1). user program must disable the JBLPD. could lose synchronization with the J1850 bus.

10.9.4 Peripheral Functional Modes

CONTROL register, as shown in Table 55. Table 55. JBLPD functional modes able or unable to transmit or receive messages.

10.9.4.1 JBLPD Enabled

10.9.4.2 JBLPD Suspended (Low Power Mode)

JBLPD is stopped except the decoder logic. chronized with the J1850 bus.

10.9.4.3 JBLPD Disabled (Very Low Power

JBLPD is stopped until the bit is reset by software. ter are forced to their reset value. bit. It can be set only after the JDIS bit is reset.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.5 Interrupt Features

The JBLPD has six interrupt sources that it han- dles using the internal interrupts protocol. Other two interrupt sources (REOB and TEOB) are relat- ed to the DMA feature (See Section 10.9.6 DMA Features). No external interrupt channel is used by the JBLPD. The dedicated registers of the JBLPD should be loaded with appropriate values to set the interrupt vector (see the description of the IVR register), the interrupt mask bits (see the description of the IMR register) and the interrupt pending bits (see the de- scription of the STATUS and PRLR registers). The interrupt sources are as follows: – The ERROR interrupt is generated when the ER- ROR bit of the STATUS register is set. This bit is set when the following events occur: Trans- mitter Timeout, Transmitter Data Underflow, Receiver Data Overfl ow, Transmit Request Aborted, Received Break Symbol, Cyclic Re- dundancy Check Error, Invalid Frame Detect, Invalid Bit Detect (a more detailed description of these events is given in the description of the ERROR register). – The TLA interrupt is generated when the trans- mitter loses the arbitration (a more detailed de- scription of this condition is given in the TLA bit description of the STATUS register). – The EODM interrupt is generated when the JBLPD detects a passive level on the VPWI line longer than the minimum time accepted by the standard for the End Of Data symbol (a more detailed description of this condition is given in the EODM bit description of the STATUS regis- ter). – The EOFM interrupt is generated when the JBLPD detects a passive level on the VPWI line longer than the minimum time accepted by the standard for the End Of Frame symbol (a more detailed description of this condition is given in the EOFM bit description of the STATUS regis- ter). – The RDRF interrupt is generated when a com- plete data byte has been received and placed in the RXDATA register (see also the RDRF bit description of the STATUS register). – The REOB (Receive End Of Block) interrupt is generated when receiving using DMA and the last byte of a sequence of data is read from the JBLPD. – The TRDY interrupt is generated by two condi- tions: when the TXOP register is ready to ac- cept a new opcode for transmission; when the transmit state machine accepts the opcode for transmission (a more detailed description of this condition is given in the TRDY bit description of the STATUS register). – The TEOB (Transmit End Of Block) interrupt is generated when transmitting using DMA and the last byte of a sequence of data is written to the JBLPD.

10.9.5.1 Interrupt Management

To use the interrupt features the user has to follow these steps: – Set the correct priority level of the JBLPD – Set the correct interrupt vector – Reset the Pending bits – Enable the required interrupt source Note: It is strongly recommended to reset the pending bits before un-masking the related inter- rupt sources to avoid spurious interrupt requests. The priority with respect the other ST9 peripherals is programmable by the user setting the three most significant bits of the Interrupt Priority Level register (PRLR). The lowest interrupt priority is ob- tained by setting all the bi ts (this priority level is never acknowledged by the CPU and is equivalent to disabling the interrupts of the JBLPD); the high- est interrupt priority is programmed resetting the bits. See the Interrupt and DMA chapters of the datasheet for more details. When the JBLPD interrupt priority is set, the prior- ity between the internal interrupt sources is fixed by hardware as shown in Table 56.

to Section 10.9.6 DMA Features). Table 56. JBLPD internal priority levels Table 57. JBLPD interrupt vectors set in the IMR register and the JBLPD has priority. reset, another interrupt request is performed. tion of the STATUS and PRLR registers.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.6 DMA Features

The JBLPD can use the ST9 on-chip Direct Mem- ory Access (DMA) channels to provide high-speed data transactions between the JBLPD and contig- uous locations of Register File and Memory. The transactions can occur from and toward the JBLPD. The maximum number of transactions that each DMA channel can perform is 222 with Regis- ter File or 65536 with Memory. Control of the DMA features is performed using registers located in the JBLPD register page (IVR, PRLR, IMR, RDAPR, RDCPR, TDAPR, TDCPR). The priority level of the DMA features of the JBLPD with respect to the other ST9 peripherals and the CPU is the same as programmed in the PRLR register for the interrupt sources. In the in- ternal priority level order of the JBLPD, depending on the value of the DMASUSP bit in the OPTIONS register, the DMA may or may not have a higher priority than the interrupt sources. Refer to the Interrupt and DMA chapters of the da- tasheet for details on priority levels. The DMA features are enabled by setting the ap- propriate enabling bits (RXD_M, TXD_M) in the IMR register. It is also possible to select the direc- tion of the DMA transactions. Once the DMA table is completed (the transaction counter reaches 0 value), an interrupt request to the CPU is generated if the related mask bit is set (RDRF_M bit in reception, TRDY_M bit in trans- mission). This kind of interrupt is called “End Of Block”. The peripheral sends two different “End Of Block” interrupts depending on the direction of the DMA (Receiving End Of Block (REOB) - Transmit- ting End Of Block (TEOB)). These interrupt sourc- es have dedicated interrupt pending bits in the PRLR register (REOBP, TEOBP) and they are mapped to the same interrupt vectors: “Receive Data Register Full (RDRF )” and “Transmit Ready (TRDY)” respectively. The same correspondence exists for the internal priority between interrupts and interrupt vectors.

10.9.6.1 DMA between JBLPD and Register File

If the DMA transaction is made between the JBLPD and the Register File, one register is re- quired to hold the DMA Address and one to hold the DMA transaction counter. These two registers must be located in the Register File: the DMA Ad- dress Register in an even addressed register, the DMA Transaction Counter in the following register (odd address). They are pointed to by the DMA Transaction Counter Pointer Register (RDCPR register in receiving, TD CPR register in transmit- ting) located in the JBLPD register page. To select DMA transactions with the Register File, the control bits RDCPR .RF/MEM in receiving mode or TDCPR.RF/MEM in transmitting mode must be set. The transaction Counter Register must be initial- ized with the number of DMA transfers to perform and it will be decremented after each transaction. The DMA Address Register must be initialized with the starting address of the DMA table in the Regis- ter File, and it is incremented after each transac- tion. These two registers must be located between addresses 00h and DFh of the Register File. When the DMA occurs between JBLPD and Reg- ister File, the TDAPR register (in transmission) and the RDAPR register (in reception) are not used.

10.9.6.2 DMA between JBLPD and Memory

If the DMA transaction is made between the JBLPD and Memory, a register pair is required to hold the DMA Address and another register pair to hold the DMA Transaction counter. These two pairs of registers must be located in the Register File. The DMA Address pair is pointed to by the DMA Address Pointer Registers (RDAPR register in reception, TDAPR register in transmission) lo- cated in the JBLPD register page; the DMA Trans- action Counter pair is pointed to by the DMA Transaction Counter Pointer Registers (RDCPR register in reception, TDCPR register in transmis- sion) located in the JBLPD register page. To select DMA transactions with Memory Space, the control bits RDCPR .RF/MEM in receiving mode or TDCPR.RF/MEM in transmitting mode must be reset. The Transaction Counter register pair must be ini- tialized with the number of DMA transfers to per- form and it will be decremented after each transac- tion. The DMA Address register pair must be ini- tialized with the starting address of the DMA table in Memory Space, and it is incremented after each transaction. These two register pairs must be lo- cated between addresses 00h and DFh of the Register File.

10.9.6.3 DMA Management in Reception Mode

IMR register must be set (by software). that have still to be performed. ware resetting the RXD_M bit. Figure 139. DMA in Reception Mode

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) DMA in transmission is performed when the TRDY bit of the STATUS register is set (by hardware). The TRDY bit is reset as soon as the DMA cycle is finished. To enable the DMA feature, the TXD_M bit in the IMR register must be set (by software). Compared to reception, in transmission each DMA request performs the transfer of either a single byte or a couple of bytes depending on the value of the Transmit Opcode bits (TXOP.OP[2:0]) writ- ten during the DMA transfer. The table of values managed by the DMA must be a sequence of opcode bytes (that will be written in the TXOP register by the DMA) each one followed by a data byte (that will be written in the TXDATA register by the DMA) if the opcode needs it (see Figure 140). Each DMA cycle consists of the following transfers for a total of three/six operations that are per- formed with minimum use of CPU time: – A load to the JBLPD Transmit Opcode register (TXOP) from a location of Register File/Memory addressed through the DMA Address Register (or Register pair); – A post-increment of the DMA Address Register (or Register pair); – A post-decrement of the DMA transaction coun- ter, which contains the number of transactions that have still to be performed; and if the Transmit Opcode placed in TXOP re- quires a datum: – A load to the peripheral data register (TXDATA) from a location of Register File/Memory ad- dressed through the DMA Address Register (or Register pair); it is the next location in the TX- DATA transfer cycle; – A post-increment of the DMA Address Register (or Register pair); – A post-decrement of the DMA transaction coun- ter, which contains the number of transactions that have still to be performed. Note: When the TEOBP pending bit is set (at the end of the last DMA transfer), the transmission DMA enable bit (TXD_M) is automatically reset by hardware. However, the DMA can be disabled by software resetting the TXD_M bit. Note: When using DMA, the TXOP byte is written before the TXDATA register. This order is accept- ed by the JBLPD only when the DMA in transmis- sion is enabled. Note: The DMA request acknowledge could de- pend on the priority level stored in the PRLR regis- ter. In the same way, some time can occur be- tween the transfer of the first byte and the transfer of the second one if another interrupt or DMA re- quest with higher priority occurs.

10.9.6.5 DMA Suspend mode

In the JBLPD it is possible to suspend or not to suspend the DMA transfer while some J1850 pro- tocol events occur. The selection between the two modes is done by programming the DMASUSP bit of the OPTIONS register. If the DMASUSP bit is set (DMA suspended mode), while the ERROR or TLA flag is set, the DMA transfers are suspended, to allow the user program to handle the event condition. If the DMASUSP bit is reset (DMA not suspended mode), the previous flags have no effect on the DMA transfers.

Figure 140. DMA in Transmission Mode

10.9.7 Register Description

mapped in a single page of the ST9 register file. The ST9 Register File page used is 23 (17h). ity with future versions of the JBLPD. Figure 141. JBLPD Register Map

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.7.1 Un-Stacked Registers

STATUS REGISTER (STATUS) R240 - Read/Write Register Page: 23 Reset Value: 0100 0000 (40h) The bits of this register indicate the status of the JBLPD peripheral. This register is forced to its reset value after the MCU reset and while the CONTROL.JDIS bit is set. While the CONTROL.JE bit is reset, all bits ex- cept IDLE are forced to their reset values. Bit 7 = ERR Error Flag. The ERR bit indicates that one or more bits in the ERROR register have been set. As long as any bit in the ERROR register remains set, the ERR bit re- mains set. When all the bits in the ERROR register are cleared, then the ERR bit is reset by hardware. The ERR bit is also cleared on reset or while the CONTROL.JE bit is reset, or while the CON- TROL.JDIS bit is set. If the ERR_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: No error 1: One or more errors have occurred Bit 6 = TRDY Transmit Ready Flag. The TRDY bit indicates that the TXOP register is ready to accept another opcode for transmission. The TRDY bit is set when the TXOP register is empty and it is cleared whenever the TXOP regis- ter is written (by softwa re or by DMA). TRDY will be set again when the transmit state machine ac- cepts the opcode for transmission. When attempting to transmit a data byte without using DMA, two writes are required: first a write to TXDATA, then a write to the TXOP. – If a byte is written into the TXOP which results in TRA getting set, then the TRDY bit will immedi- ately be set. – If a TLA occurs and the opcode for which TRDY is low is scheduled for this frame, then TRDY will go high, if the opcode is scheduled for the next frame, then TRDY will stay low. – If an IBD, IFD or CRCE error condition occurs, then TRDY will be set and any queued transmit opcode scheduled to transmit in the present frame will be cancelled by the JBLPD peripher- al. A MSGx opcode scheduled to be sent in the next frame will not be cancelled for these errors, so TRDY would not get set. – An RBRK error condition cancels all transmits for this frame or any successive frames, so the TRDY bit will always be immediately set on an RBRK condition. TRDY is set on reset or while CONTROL.JE is re- set, or while the CONTROL.JDIS bit is set. If the TRDY_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: TXOP register not ready to receive a new op- code 1: TXOP register ready to receive a new opcode Bit 5 = RDRF Receive Data Register Full Flag. RDRF is set when a complete data byte has been received and transferred from the serial shift regis- ter to the RXDATA register. RDRF is cleared when the RXDATA register is read (by software or by DMA). RDRF is also cleared on reset or while CONTROL.JE is reset, or while CONTROL.JDIS bit is set. If the RDRF_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: RXDATA register doesn’t contain a new data 1: RXDATA register contains a new data Bit 4 = TLA Transmitter Lost Arbitration. The TLA bit gets set when the transmitter loses ar- bitration while transmitting messages or type 1 and 3 IFRs. Lost arbitration for a type 2 IFR does not set the TLA bit. (Type 2 messages require re- tries of the physical address if the arbitration is lost until the frame length is reached (if NFL=0)). The TLA bit gets set when, while transmitting a MSG, MSG+CRC, IFR1, IFR3, or IFR3+CRC, the decod- ed VPWI data bit symbol received does not match the VPWO data bit symbol that the JBLPD is at- tempting to send out. If arbitration is lost, the VPWO line is switched to its passive state and nothing further is transmitted until an end-of-data (EOD) symbol is detected on the VPWI line. Also, any queued transmit opcode scheduled for trans- mission during this frame is cancelled (but the TRA bit is not set). The TLA bit can be cleared by software writing a logic “zero” in the TLA position. TLA is also cleared on reset or while CONTRO L.JE is reset, or while CONTROL.JDIS bit is set. If the TLA_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: The JBLPD doesn’t lose arbitration 1: The JBLPD loses arbitration ERR TRDY RDRF TLA RDT EODM EOFM IDLE

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 3 = RDT Receive Data Type. The RDT bit indicates the type of data which is in the RXDATA register: message byte or IFR byte. Any byte received after an SOF but before an EODM is considered a message byte type. Any byte received after an SOF, EODM and NBx is an IFR type. RDT gets set or cleared at the same time that RDRF gets set. RDT is cleared on reset or while CONTROL.JE is reset, or while CONTROL.JDIS bit is set. 0: Last RXDATA byte was a message type byte 1: Last RXDATA byte was a IRF type byte Bit 2 = EODM End of Data Minimum Flag. The EODM flag is set when the JBLPD decoded VPWI pin has been in a passive state for longer that the minimum Tv3 symbol time unless the EODM is inhibited by a sleep, filter or CRCE, IBD, IFD or RBRK error condition during a frame. EODM bit does not get set when in the sleep mode or when a message is filtered. The EODM bit can be cleared by software writing a logic “zero” in the EO DM position. EODM is cleared on reset, while CONTROL.JE is reset or while CONTROL.JDIS bit is set. If the EODM_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: No EOD symbol detected 1: EOD symbol detected Note: The EODM bit is not an error flag. It means that the minimum time related to the passive Tv3 symbol is passed. Bit 1 = EOFM End of Frame Minimum Flag. The EOFM flag is set when the JBLPD decoded VPWI pin has been in a passive state for longer that the minimum Tv4 symbol time. EOFM will still get set at the end of filtered frames or frames where sleep mode was invoked. Consequently, multiple EOFM flags may be encountered be- tween frames of interest. The EOFM bit can be cleared by software writing a logic “zero” in the EOFM position. EOFM is cleared on reset, while CONTROL.JE is reset or while CONTROL.JDIS bit is set. If the EOFM_M bit of the IMR register is set, when this bit is set an interrupt request occurs. 0: No EOF symbol detected 1: EOF symbol detected Note: The EOFM bit is not an error flag. It means that the minimum time related to the passive Tv4 symbol is passed. Bit 0 = IDLE Idle Bus Flag IDLE is set when the JBLPD decoded VPWI pin recognized an IFS symbol. That is, an idle bus is when the bus has been in a passive state for long- er that the Tv6 symbol time. The IDLE flag will re- main set as long as the decoded VPWI pin is pas- sive. IDLE is cleared when the decoded VPWI pin transitions to an active state. Note that if the VPWI pin remains in a passive state after JE is set, then the IDLE bit may go high sometime before a Tv6 symbol is timed on VPWI (since VPWI timers may be active when JE is clear). IDLE is cleared on reset or while the CON- TROL.JDIS bit is set. 0: J1850 bus not in idle state 1: J1850 bus in idle state JBLPD TRANSMIT DATA REGISTER (TXDATA) R241- Read/Write Register Page: 23 Reset Value: xxxx xxxx (xxh) The TXDATA register is an eight bits read/write register in which the data to be transmitted must be placed. A write to TXDATA merely enters a byte into the register. To initiate an attempt to transmit the data, the TXOP register must also be written. When the TXOP write occurs, the TRDY flag is cleared. While t he TRDY bit is clear, the data is still in the TXDATA register, so writes to the TXDATA register with TRDY clear will overwrite existing TXDATA. When the TXDATA is trans- ferred to the shift register, the TRDY bit is set again. Reads of the TXDATA register will always return the last byte written. TXDATA contents are undefined after a reset. Note: The correct sequence to transmit is to write first the TXDATA register (if datum is needed) and then the TXOP one. Only using the DMA, the correct sequence of writ- ing operations is first the TXOP register and then the TXDATA one (if needed). TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) JBLPD RECEIVE DATA REGISTER (RXDATA) R242- Read only Register Page: 23 Reset Value: xxxx xxxx (xxh) The RXDATA register is an 8-bit read only register in which the data received from VPWI is stored. VPWI data is transferred from the input VPW de- coder to a serial shift register unless it is inhibited by sleep mode, filter mode or an error condition (IBD, IFD, CRCE, RBRK) during a frame. When the shift register is full, this data is transferred to the RXDATA register, and the RDRF flag gets set. All received data bytes are transferred to RXDATA including CRC bytes. A read of the RXDATA reg- ister will clear the RDRF flag. Note that care must be taken when reading RXDA- TA subsequent to an RDRF flag. Multiple reads of RXDATA after an RDRF should only be attempted if the user can be sure that another RDRF will not occur by the time the read takes place. RXDATA content is undefined after a reset. JBLPD TRANSMIT OPCODE REGISTER (TXOP) R243 - Read/Write Register Page: 23 Reset Value: 0000 0000 (00h) TXOP is an 8-bit read/write register which contains the instructions required by the JBLPD to transmit a byte. A write to the TXOP triggers the state ma- chine to initialize an attempt to serially transmit a byte out on the VPWO pin. An opcode which trig- gers a message byte or IFR type 3 to be sent will transfer the TXDATA register contents to the transmit serial shift register. An opcode which trig- gers a message byte or IFR type 3 to be sent with a CRC appended will transfer the TXDATA regis- ter contents to the transmit serial shift register and subsequently the computed CRC byte. An opcode which triggers an IFR type 1 or 2 to be sent will transfer the PADDR register contents to the trans- mit serial shift register. If a TXOP opcode is written which is invalid for the bus conditions at the time (e.g. 12 byte frame or IFR3ing an IFR2), then no transmit attempt is tried and the TRA bit in the ER- ROR register is set. Transmission of a string of data bytes requires multiple TXDATA/TXOP write sequences. Each write combination shoul d be accomplished while the TRDY flag is set. However, writes to the TXOP when TRDY is not set will be accepted by the state machine, but it may override the previous data and opcode. Under normal message transmission conditions the MSG opcode is written. If the last data byte of a string is to be sent, then the MSG+CRC opcode will be written. An IFRx op code is written if a re- sponse byte or bytes to a received message (i.e. bytes received in RXDATA with RDT=0) is wanted to transmit. The Message Length Count bits (MLC[3:0]) may be used to require that the IFR be enabled only if the correct number of message bytes has been received. NOTE: The correct sequence to transmit is to write first the TXDATA register and then the TXOP one. Only using the DMA, the correct sequence of writ- ing operations is first the TXOP register and then the TXDATA one (if needed). RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 MLC3 MLC2 MLC1 MLC0 - OP2 OP1 OP0

Bit 7:4 = MLC[3:0] Message Length Count. (TRA) bit in the ERROR register. ing a MSG or MSG+CRC opcode write. Bit 2:0 = OP[2:0] Transmit Opcode Select Bits. Table 58. Opcode definitions the body of a message out the VPWO pin. no message byte will be sent on the next frame. first byte of the next frame.

000 No operation or

001 Send Break Symbol SBRK

010 Message Byte MSG

011 Message Byte then ap-

100 In-Frame Response Type

1 IFR1

101 In-Frame Response Type

2 IFR2

110 In-Frame Response Type

3 IFR3

111 IFR Type 3 then append

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) MSG+CRC, Message byte then append CRC op- code. The ‘Message byte with CRC’ opcode is set when the user program wants to transmit a single byte message followed by a CRC byte, or transmit the final byte of a message string followed by a CRC byte. A single byte message is basically an SOF symbol followed by a single data byte retrieved from TX- DATA register followed by the computed CRC byte followed by an EOD symbol. If the J1850 bus is in idle condition when the opcode is written, an SOF symbol is immediately transmitted out the VPWO pin. It then transmits the byte contained in the TXDATA register, then the computed CRC byte is transmitted. VPWO is then set to a passive state. If the J1850 bus is not idle and the J1850 transmitter has not been locked out by loss of arbi- tration, then the TXDATA byte is transferred to the serial output shift register for transmission immedi- ately on completion of any previously transmitted data. After completion of the TXDATA byte the computed CRC byte is transferred out the VPWO pin and then the VPWO pin is set passive to time an EOD symbol. Special Conditions for MSG+CRC Transmit: – 1) A MSG+CRC opcode cannot be queued on top of an executing IFR3 opcode. If so, then TRA is set, and TDUF will get set because the transmit state machine will be expecting more data, then the inverted CRC is appended to this frame. Also, no message byte will be sent on the next frame. – 2) If NFL=0, a MSG+CRC can only be queued if Received Byte Count for this frame <=10 other- wise the TRA will get set, and TDUF will get set because the state machine will be expecting more data, so the transmit machine will send the inverted CRC after the byte which is pres- ently transmitting. Also, no message byte will be sent on the next frame. Caution should be taken when TRA gets set in these cases because the TDUF error sequence may engage before the user program has a chance to rewrite the TXOP register with the cor- rect opcode. If a TDUF error occurs, a subsequent MSG+CRC write to the TXOP register will be used as the first byte of the next frame. IFR1, In-Frame Response Type 1 opcode. The In-frame Response Type 1 (IFR 1) opcode is written if the user program wants to transmit a physical address byte (contained in the PADDR register) in response to a message that is currently being received. The user program decides to set up an IFR1 upon receiving a certain portion of the data byte string of an incoming message. No write of the TXDATA register is required. The IFR1 gets its data byte from the PADDR register. The JBLPD block will enable the transmission of the IFR1 on these conditions: – 1) The CRC check is valid (otherwise the CRCE is set) – 2) The received message length is valid if ena- bled (otherwise the TRA is set) – 3) A valid EOD minimum symbol is received (oth- erwise the IFD may eventually get set due to byte synchronization errors) – 4) If NFL = 0 & Received Byte Count for this frame <=11 (otherwise TRA is set) – 5) If not presently executing an MSG, IFR3, op- code (otherwise TRA is set, and TDUF will get set because the transmit state machine will be expecting more data, so the inverted CRC will be appended to this frame) – 6) If not presently executing an IFR1, IFR2, or IFR3+CRC opcode otherwise TRA is set (but no TDUF) – 7) If not presently receiving an IFR portion of a frame, otherwise TRA is set. The IFR1 byte is then attempted according to the procedure described in section “Transmitting a type 1 IFR”. Note that if an IFR1 opcode is written, a queued MSG or MSG+CRC is overridden by the IFR1.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) IFR2, In-Frame Response Type 2 opcode. The In-frame Response Type 2 (IFR2) opcode is set if the user program wants to transmit a physical address byte (contained in the PADDR register) in response to a message that is currently being re- ceived. The user program decides to set up an IFR2 upon receiving a certain portion of the data byte string of an incoming message. No write of the TXDATA register is required. The IFR gets its data byte from the PADDR register. The JBLPD block will enable the transmission of the IFR2 on these conditions: – 1) The CRC check is valid (otherwise the CRCE is set) – 2) The received message length is valid if ena- bled (otherwise the TRA is set) – 3) A valid EOD minimum symbol is received (oth- erwise the IFD may eventually get set due to byte synchronization errors) – 4) If NFL = 0 & Received Byte Count for this frame <=11 (otherwise TRA is set) – 5) If not presently executing an MSG, IFR3, op- code (otherwise TRA is set, and TDUF will get set because the transmi t state machine will be expecting more data, so the inverted CRC will be appended to this frame) – 6) If not presently executing an IFR1, IFR2, or IFR3+CRC opcodes, otherwise TRA is set (but no TDUF) – 7) If not presently receiving an IFR portion of a frame, otherwise TRA is set. The IFR byte is then attempted according to the procedure described in section “Transmitting a type 2 IFR”. Note that if an IFR opcode is written, a queued MSG or MSG+CRC is overridden by the IFR2. IFR3, In-Frame Response Type 3 opcode. The In-Frame Response Type 3 (IFR3) opcode is set if the user program wants to initiate to transmit or continue to transmit a string of data bytes in re- sponse to a message that is currently being re- ceived. The IFR3 uses the contents of the TXDATA regis- ter for data. The user program decides to set up an IFR3 upon receiving a certain portion of the data byte string of an incoming message. A previous write of the TXDATA register should have oc- curred. The JBLPD block will enable the transmission of the first byte of an IFR3 string on these conditions: – 1) The CRC check is valid (otherwise the CRCE is set) – 2) The received message length is valid if ena- bled (otherwise the TRA is set) – 3) A valid EOD minimum symbol is received (oth- erwise the IFD may eventually get set due to byte synchronization errors) – 4) If NFL = 0 & Received Byte Count for this frame <=9 (otherwise TRA is set and inverted CRC is transmitted due to TDUF) – 5) If not presently executing an MSG opcode (otherwise TRA is set, and TDUF will get set be- cause the transmit state machine will be expect- ing more data and the inverted CRC will be appended to this frame) – 6) If not presently executing an IFR1, IFR2, or IFR3+CRC opcode, otherwise TRA is set (but no TDUF) – 7) If not presently receiving an IFR portion of a frame, otherwise TRA is set. The IFR3 byte string is then attempted according to the procedure described in section “Transmit- ting a type 3 IFR”. Note that if an IFR3 opcode is written, a queued MSG or MSG+CRC is overrid- den by the IFR3. The next byte(s) in the IFR3 data string shall also be written with the IFR3 opcode except for the last byte in the string which shall be written with the IFR3+CRC opcode. Each IFR3 data byte trans- mission is accomplishe d with a TXDATA/TXOP write sequence. The succeeding IFR3 transmit re- quests will be enabled on conditions 4 and 5 listed above.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) IFR3+CRC, In-Frame Response Type 3 then ap- pend CRC opcode. The In-frame Response Type 3 then append CRC opcode (IFR3+CRC) is set if the user program wants to either initiate to transmit a single data byte IFR3 followed by a CRC, or transmit the last data byte of an IFR3 string followed by the CRC byte in response to a message that is currently be- ing received. The IFR3+CRC opcode transmits the contents of the TXDATA register followed by the computed CRC byte. The user program decides to set up an IFR3 upon receiving a certain portion of the data byte string of an incoming message. A previous write of the TXDATA register should have oc- curred. The J1850 block will enable the transmission of the first byte of an IFR3 string on these conditions: – 1) The CRC check is valid (otherwise the CRCE is set) – 2) The received message length is valid if ena- bled (otherwise the TRA is set) – 3) A valid EOD minimum symbol is received (oth- erwise the IFD may eventually get set due to byte synchronization errors) – 4) If NFL = 0 & Received Byte Count for this frame <=10 (otherwise TRA is set and inverted CRC is transmitted) – 5) If not presently executing an MSG opcode (otherwise TRA is set, and TDUF will get set be- cause the transmit state machine will be expect- ing more data and the inverted CRC will be appended to this frame) – 6) If not presently executing an IFR1, IFR2 or IFR3+CRC opcodes, otherwise TRA is set (but no TDUF) – 7) If not presently receiving an IFR portion of a frame, otherwise TRA is set. The IFR3 byte is attempted according to the pro- cedure described in section “Transmitting a type 3 IFR”. The CRC byte is transmitted out on comple- tion of the transmit of the IFR3 byte. If this opcode sets up the last byte in an IFR3 data string, then the TXDATA register contents shall be transmitted out immediately upon completion of the previous IFR3 data byte followed by the trans- mit of the CRC byte. In this case the IFR3+CRC is enabled on conditions 4 and 5 listed above. Note that if an IFR3+CRC opcode is written, a queued MSG or MSG+CRC is overridden by the IFR3+CRC. SBRK, Send Break Symbol. The SBRK opcode is written to transmit a nominal break (BRK) symbol out the VPWO pin. A Break symbol can be initiated at any time. Once the SBRK opcode is written a BRK symbol of the nom- inal Tv5 duration will be transmitted out the VPWO pin immediately. To terminate the transmission of an in-progress break symbol the JE bit should be set to a logic zero. An SBRK command is non- maskable, it will override any present transmit op- eration, and it does not wait for the present trans- mit to complete. Note that in the 4X mode a SBRK will send a break charac ter for the nominal Tv5 time times four (4 x Tv5) so that all nodes on the bus will recognize the br eak. A CANCEL opcode does not override a SBRK command. CANCEL, No Operation or Cancel Pending Trans- mit. The Cancel opcode is used by the user program to tell the J1850 transmitter that a previously queued opcode should not be transmitted. The Cancel op- code will set the TRDY bit. If the JBLPD peripheral is presently not transmitting, the Cancel command effectively cancels a pending MSGx or IFRx op- code if one was queued, or it does nothing if no opcode was queued. If the JBLPD peripheral is presently transmitting, then a queued MSGx or IFRx opcode is aborted and the TDUF circuit may take affect.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) JBLPD SYSTEM FREQUENCY SELECTION REGISTER (CLKSEL) R244- Read/Write Register Page: 23 Reset Value: 0000 0000 (00h) Bit 7 = 4X Diagnostic Four Times Mode. This bit is set when the J1850 clock rate is chosen four times faster than the standard requests, to force the BREAK symbol ( nominally 300 µs long) and the Transmitter Timeout Time (nominally 1 ms) at their nominal durations. When the user want to use a 4 times faster J1850 clock rate, the new prescaler factor should be stored in the FREQ[5:0] bits and the 4X bit must be set with the same instructio n. In the same way, to exit from the mode, FREQ[5:0] and 4X bits must be placed at the previous value with the same in- struction. 0: Diagnostic Four Times Mode disabled 1: Diagnostic Four Times Mode enabled Note: Setting this bit, the prescaler factor is not au- tomatically divided by four. The user must adapt the value stored in FREQ[5:0] bits by software. Note: The customer should take care using this mode when the MCU internal frequency is less than 4MHz. Bit 6 = Reserved. Bit 5:0 = FREQ[5:0] Internal Frequency Selectors. These 6 bits must be programmed depending on the internal frequency of the device. The formula that must be used is the following one: MCU Int. Freq.= 1MHz * (FREQ[5:0] + 1). Note: To obtain a correct operation of the periph- eral, the internal frequency of the MCU (INTCLK) must be an integer multiple of 1MHz and the cor- rect value must be written in the register. So an in- ternal frequency less than 1MHz is not allowed. Note: If the MCU internal clock frequency is lower than 1MHz, the peripheral is not able to work cor- rectly. If a frequency lower than 1MHz is used, the user program must disable the peripheral. Note: When the clock prescaler factor or the MCU internal frequency is changed, the peripheral could lose the synchronization with the J1850 bus. JBLPD CONTROL REGISTER (CONTROL) R245- Read/Write Register Page: 23 Reset Value: 0100 0000 (40h) The CONTROL register is an eight bit read/write register which contains JBLPD control information. Reads of this register return the last written data. Bit 7 = JE JBLPD Enable. The JBLPD block enable bit (JE) enables and dis- ables the transmitter and receiver to the VPWO and VPWI pins respectively. When the JBLPD pe- ripheral is disabled the VPWO pin is in its passive state and information coming in the VPWI pin is ig- nored. When the JBLPD block is enabled, the transmitter and receiver function normally. Note that queued transmits are aborted when JE is cleared. JE is cleared on reset, by software and setting the JDIS bit. 0: The peripheral is disabled 1: The peripheral is enabled Note: It is not possible to reset the JDIS bit and to set the JE bit with the same instruction. The cor- rect sequence is to first reset the JDIS bit and then set the JE bit with another instruction. 4X - FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 JE JDIS NFL JDLY4 JDLY3 JDLY2 JDLY1 JDLY0

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 6 = JDIS Peripheral clock frozen. When this bit is set by software, the peripheral is stopped and the bus is not decoded anymore. A reset of the bit restarts the internal state machines as after a MCU reset. The JDIS bit is set on MCU reset. 0: The peripheral clock is running 1: The peripheral clock is stopped Note: When the JDIS bit is set, the STATUS reg- ister, the ERROR register, the IMR register and the TEOBP and REOBP bits of the PRLR register are forced into their reset value. Note: It is not possible to reset the JDIS bit and to set the JE bit with the same instruction. The cor- rect sequence is to first reset the JDIS bit and then set the JE bit with another instruction. Bit 5 = NFL No Frame Length Check The NFL bit is used to enable/disable the J1850 requirement of 12 bytes maximum per frame limit. The SAE J1850 standard st ates that a maximum of 12 bytes (including CRCs and IFRs) can be on the J1850 between a start of frame symbol (SOF) and an end of frame symbol (EOF). If this condi- tion is violated, then the JBLPD peripheral gets an Invalid Frame Detect (IFD) and the sleep mode ensues until a valid EOFM is detected. If the valid frame check is disabled (NFL=1), then no limits are imposed on the number of data bytes which can be sent or received on the bus between an SOF and an EOF. The default upon reset is for the frame checking to be enabled. The NFL bit is cleared on reset 0: Twelve bytes frame length check enabled 1: Twelve bytes frame length check disabled Bit 4:0 = JDLY[4:0] JBLPD Transceiver External Loop Delay Selector. These five bits are used to select the nominal ex- ternal loop time delay which normally occurs when the peripheral is connected and transmitting in a J1850 bus system. The external loop delay is de- fined as the time between when the VPWO is set to a certain level to when the VPWI recognizes the corresponding (inverted) edge on its input. Refer to “Transmit Opcode Queuing” section and the SAE-J1850 standard for information on how the external loop delay is used in timing transmitted symbols. The allowed values are integer values between 0 µs and 31 µs. JBLPD PHYSICAL ADDRESS REGISTER (PADDR) R246- Read/Write Register Page: 23 Reset Value: xxxx xxxx (xxh) The PADDR is an eight bit read/write register which contains the physical address of the JBLPD peripheral. During initialization the user program will write the PADDR register with its physical ad- dress. The Physical Address is used during in- frame response types 1 and 2 to acknowledge the receipt of a message. The JBLPD peripheral will transmit the contents of the PADDR register for type 1 or 2 IFRs as defined by the TXOP register. This register is undefined on reset. ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) JBLPD ERROR REGISTER (ERROR) R247- Read only Register Page: 23 Reset Value: 0000 0000 (00h) ERROR is an eight bit read only register indicating error conditions that may arise on the VPWO and VPWI pins. A read of the ERROR register clears all bits (except for TTO and possibly the RBRK bit) which were set at the time of the read. The register is cleared after the MCU reset, while the CON- TROL.JE bit is reset, or while the CONTROL.JDIS bit is set. All error conditions that can be read in the ERROR register need to have redundant ERROR indicator flags because: – With JE set, the TDUF, RDOF, TRA, CRCE, IFD, & IBD bits in the ERROR register can only be cleared by reading the register. – The TTO bit can only be cleared by clearing the JE bit. – The RBRK bit can only be cleared by reading the ERROR register after the break condition has disappeared. Error condition indicator flags associated with the error condition are cleared when the error condi- tion ends. Since error conditions may alter the ac- tions of the transmitter and receiver, the error con- dition indicators must remain set throughout the error condition. All error conditions, including the RBRK condition, are events that get set during a particular clock cycle of the prescaled clock of the peripheral. The IFD, IBD, RBRK, and CRCE error conditions are then cleared when a valid EOF symbol is detected from the VPWI pin. The TRA error condition is a singular event that sets the cor- responding ERROR register bit, but this error itself causes no other actions. Bit 7 = TTO Transmitter Timeout Flag The TTO bit is set when the VPWO pin has been in a logic one (or active) state for longer than 1 ms. This flag is the output of a diagnostic circuit based on the prescaled system clock input. If the 4X bit is not set, the TTO will trip if the VPWO is constantly active for 1000 prescaled clock cycles. If the 4X bit is set, then the TTO will timeout at 4000 prescaled clock cycles. When the TTO flag is set then the di- agnostic circuit will disable the VPWO signal, and disable the JBLPD peripheral. The user program must then clear the JE bit to remove the TTO error. It can then retry the block by setting the JE bit again. The TTO bit can be used to determine if the exter- nal J1850 bus is shorted low. Since the transmitter looks for proper edges returned at the VPWI pin for its timing, a lack of edges seen at VPWI when trying to transmit (assuming the RBRK does not get set) would indicate a constant low condition. The user program can take appropriate actions to test the J1850 bus circ uit when a TTO occurs. Note that a transmit attempt must occur to detect a bus shorted low condition. The TTO bit is cleared while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set. TTO is cleared on reset. 0: VPWO line at 1 for less than 1 ms 1: VPWO line at 1 for longer than 1 ms Bit 6 = TDUF Transmitter Data Underflow. The TDUF will be set to a logic one if the transmit- ter expects more information to be transmitted, but a TXOP write has not occurred in time (by the end of transmission of the last bit). The transmitter knows to expect more information from the user program when transmitting messag- es or type 3 IFRs only. If an opcode is written to TXOP that does not include appending a CRC byte, then the JBLPD peripheral assumes more data is to be written. When the JBLPD peripheral has shifted out the data byte it must have the next data byte in time to place it directly next to it. If the user program does not place new data in the TX- DATA register and write the TXOP register with a proper opcode, then the CRC byte which is being kept tabulated by the transmitter is logically invert- ed and transmitted out the VPWO pin. This will en- sure that listeners will de tect this message as an error. In this case the TDUF bit is set to a logic one. TDUF is cleared by reading the ERROR register with TDUF set. TDUF is also cleared on reset, while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set. 0: No transmitter data underflow condition oc- curred 1: Transmitter data underflow condition occurred TTO TDUF RDOF TRA RBRK CRCE IFD IBD

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 5 = RDOF Receiver Data Overflow The RDOF gets set to a logic one if the data in the RXDATA register has not been read and new data is ready to be transferred to the RXDATA register. The old RXDATA information is lost since it is overwritten with new data. RDOF is cleared by reading the ERROR register with RDOF set, while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set, or on reset. 0: No receiver data overflow condition occurred 1: Receiver data overflow condition occurred Bit 4 = TRA Transmit Request Aborted The TRA gets set to a logic one if a transmit op- code is aborted by the JBLPD state machine. Many conditions may cause a TRA. They are ex- plained in the transmit opcode section. If the TRA bit gets set after a TXOP write, then a transmit is not attempted, and the TRDY bit is not cleared. If a TRA error condition occurs, then the requested transmit is aborted, and the JBLPD peripheral takes appropriate measures as described under the TXOP register section. TRA is cleared on reset, while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set. 0: No transmission request aborted 1: Transmission request aborted Bit 3 = RBRK Received Break Symbol Flag The RBRK gets set to a logic one if a valid break (BRK) symbol is detected from the filtered VPWI pin. A Break received from the J1850 bus will can- cel queued transmits of all types. The RBRK bit re- mains set as long as the break character is detect- ed from the VPWI. Reads of the ERROR register will not clear the RBRK bit as long as a break char- acter is being received. Once the break character is gone, a final read of the ERROR register clears this bit. An RBRK error occurs once for a frame if it is re- ceived during a frame. Afterwards, the receiver is disabled from receiving information (other than the break) until an EOFM symbol is received. RBRK bit is cleared on reset, while the CON- TROL.JE bit is reset or while the CONTROL.JDIS bit is set. The RBRK bit can be used to detect J1850 bus shorted high conditions. If RBRK is read as a logic high multiple times before an EOFM occurs, then a possible bus shorted high condition exists. The user program can take appropriate measures to test the bus if this condition occurs. Note that this bit does not necessarily clear when ERROR is read. 0: No valid Break symbol received 1: Valid Break symbol received Bit 2 = CRCE Cyclic Redundancy Check Error The receiver section always keeps a running tab of the CRC of all data bytes received from the VPWl since the last EOD symbol. The CRC check is per- formed when a valid EOD symbol is received both after a message string (subsequent to an SOF symbol) and after an IFR3 string (subsequent to an NB0 symbol). If the received CRC check fails, then the CRCE bit is set to a logic one. CRC errors are inhibited if the JBLPD peripheral is in the “sleep or filter and NOT presently transmitting” mode. A CRC error occurs once for a frame. After- wards, the receiver is disabled until an EOFM symbol is received and queued transmits for the present frame are cancelled (but the TRA bit is not set). CRCE is cleared when ERROR is read. It is also cleared while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set, or on reset. 0: No CRC error detected 1: CRC error detected Bit 1 = IFD Invalid Frame Detect The IFD bit gets set when the following conditions are detected from the filtered VPWI pin: – An SOF symbol is received after an EOD mini- mum, but before an EOF minimum. – An SOF symbol is received when expecting data bits. – If NFL = 0 and a message frame greater than 12 bytes (i.e. 12 bytes plus one bit) has been re- ceived in one frame. – An EOD minimum time has elapsed when data bits are expected. – A logic 0 or 1 symbol is received (active for Tv1 or Tv2) when an SOF was expected. – The second EODM symbol received in a frame is NOT followed directly by an EOFM symbol. IFD errors are inhibited if the JBLPD peripheral is in the “sleep or filter and NOT presently transmit- ting” mode. An IFD error occurs once for a frame. Afterwards, the receiver is disabled until an EOFM symbol is received, and queued transmits for the present frame are cancelled (but the TRA bit is not set). IFD is cleared when ERROR is read. It is also cleared while the CONTROL.JE bit is reset or while the CONTROL.JDIS bit is set or on reset. 0: No invalid frame detected 1: Invalid frame detected

Bit 0 = IBD Invalid Bit Detect. until a valid EOF symbol is received. ting” mode. An IBD error occurs once for a frame. Bit 7:3 = V[7:3] Interrupt Vector Base Address. User programmable interrupt vector bits. Table 59. Interrupt Sources cannot be suspended by an ERROR or TLA event. Refer to the description of DMASUSP bit. Table 60. Internal Interrupt and DMA Priorities Table 61. Internal Interrupt and DMA Priorities

00 E R R O R , T L A

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 4 = SLP Receiver Sleep Mode. The SLP bit is written to one when the user pro- gram does not want to receive any data from the JBLPD VPWI pin until an EOFM symbol occurs. This mode is usually set when a message is re- ceived that the user does not require - including messages that the JBLPD is transmitting. If the JBLPD is not transmitting and is in Sleep mode, no data is transferred to the RXDATA regis- ter, the RDRF flag does not get set, and errors as- sociated with received data (RDOF, CRCE, IFD, IBD) do not get set. Also, the EODM flag will not get set. If the JBLPD peripheral is transmitting and is in sleep mode, no data is transferred to the RXDATA register, the RDRF flag does not get set and the RDOF error flag is inhibited. The CRCE, IFD, and IBD flags, however, will NOT be inhibited while transmitting in sleep mode. The SLP bit cannot be written to zero by the user program. The SLP bit is set on reset or TTO get- ting set, and it will stay set upon JE getting set until an EOFM symbol is received. The SLP gets cleared on reception of an EOF or a Break symbol. SLP is se t while CONTROL.JE is reset and while CONTROL.JDIS is set. 0: The JBLPD is not in Sleep Mode 1: The JBLPD is in Sleep Mode Bit 3:2 = Reserved. Bit 1 = REOP Receiver DMA End Of Block Pend- ing. This bit is set after a receiver DMA cycle to mark the end of a block of data. An interrupt request is performed if the RDRF_M bit of the IMR register is set. REOBP should be rese t by software in order to avoid undesired interrupt routines, especially in initialisation routine (after reset) and after entering the End Of Block interrupt routine. Writing “0” in this bit will cancel the interrupt re- quest. This bit is reset when the CONTROL.JDIS bit is set at least for 6 MCU clock cycles (3 NOPs). Note: When the REOBP flag is set, the RXD_M bit is reset by hardware. Note: REOBP can only be written to “0”. Bit 0 = TEOP Transmitter DMA End Of Block Pending. This bit is set after a transmitter DMA cycle to mark the end of a block of data. An interrupt request is performed if the TRDY_M bit of the IMR register is set. TEOBP should be reset by software in order to avoid undesired interrupt routines, especially in in- itialisation routine (after reset) and after entering the End Of Block interrupt routine. Writing “0” in this bit will cancel the interrupt re- quest. This bit is reset when the CONTROL.JDIS bit is set at least for 6 MCU clock cycles (3 NOPs). Note: When the TEOBP flag is set, the TXD_M bit is reset by hardware. Note: TEOBP can only be written to “0”. JBLPD INTERRUPT MASK REGISTER (IMR) R250 - Read/Write Register Page: 23 Reset Value: 0000 0000 (00h) To enable an interrupt source to produce an inter- rupt request, the related mask bit must be set. When these bits are reset, the related Interrupt Pending bit can not generate an interrupt. Note: This register is forced to its reset value if the CONTROL.JDIS bit is set at least for 6 clock cy- cles (3 NOPs). If the JDIS bit is set for a shorter time, the bits could be reset or not reset. Bit 7 = ERR_M Error Interrupt Mask bit. This bit enables the “error” interrupt source to gen- erate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: Error interrupt source masked 1: Error interrupt source un-masked Bit 6 = TRDY_M Transmit Ready Interrupt Mask bit. This bit enables the “transmit ready” interrupt source to generate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: TRDY interrupt source masked 1: TRDY interrupt source un-masked ERR_ M TRDY_ M RDRF_ M TLA_ M RXD_ M EODM_ M EOFM_ M TXD_ M

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 5 = RDRF_M Receive Data Register Full Inter- rupt Mask bit. This bit enables the “receive data register full” in- terrupt source to generate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: RDRF interrupt source masked 1: RDRF interrupt source un-masked Bit 4 = TLA_M Transmitter Lost Arbitration Inter- rupt Mask bit. This bit enables the “transmitter lost arbitration” in- terrupt source to generate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: TLA interrupt source masked 1: TLA interrupt source un-masked Bit 3 = RXD_M Receiver DMA Mask bit. If this bit is “0” no receiver DMA request will be generated, and the RDRF bit, in the Status Regis- ter (STATUS), can request an interrupt. If RXD_M bit is set to “1” then the RDRF bit can request a DMA transfer. RXD_M is reset by hardware when the transaction counter value decrements to zero, that is when a Receiver End Of Block condition oc- curs (REOBP flag set). This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: Receiver DMA disabled 1: Receiver DMA enabled Bit 2 = EODM_M End of Data Minimum Interrupt Mask bit. This bit enables the “end of data minimum” inter- rupt source to generate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: EODM interrupt source mask 1: EODM interrupt source un-masked Bit 1 = EOFM_M End of Frame Minimum Interrupt Mask bit. This bit enables the “end of frame minimum” inter- rupt source to generate an interrupt request. This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: EOFM interrupt source masked 1: EOFM interrupt source un-masked Bit 0 = TXD_M Transmitter DMA Mask bit. If this bit is “0” no transmitter DMA request will be generated, and the TRDY bit, in the Status Regis- ter (STATUS), can request an interrupt. If TXD_M bit is set to “1” then the TRDY bit can request a DMA transfer. TXD_M is reset by hardware when the transaction counter value decrements to zero, that is when a Transmitter End Of Block condition occurs (TEOBP flag set). This bit is reset if the CONTROL.JDIS bit is set at least for 6 clock cycles (3 NOPs). 0: Transmitter DMA disabled 1: Transmitter DMA enabled JBLPD OPTIONS AND REGISTER GROUPS SELECTION REGISTER (OPTIONS) R251- Read/Write Register Page: 23 Reset Value: 0000 0000 (00h) Bit 7 = INPOL VPWI Input Polarity Selector. This bit allows the selectio n of the polarity of the RX signal coming from the transceivers. Depend- ing on the specific transceiver, the RX signal is in- verted or not inverted respect the VPWO and the J1850 bus line. 0: VPWI input is inverted by the transceiver with respect to the J1850 line. 1: VPWI input is not inverted by the transceiver with respect to the J1850 line. Bit 6 = NBSYMS NB Symbol Form Selector. This bit allows the selection of the form of the Nor- malization Bits (NB0/NB1). 0: NB0 active long symbol (Tv2), NB1 active short symbol (Tv1) 1: NB0 active short symbol (Tv1), NB1 active long symbol (Tv2) INPOL NBSYMS DMASUSP LOOPB RSEL3 RSEL2 RSEL1 RSEL0

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Bit 5 = DMASUSP DMA Suspended Selector. If this bit is “0”, JBLPD DMA has higher priority with respect to the Interrupts of the peripheral. DMA is performed even if an interrupt request is already scheduled or if the relative interrupt rou- tine is in execution. If the bit is “1”, while the ERROR or TLA flag of the STATUS register are set, the DMA transfers are suspended. As soon as the flags are reset, the DMA transfers can be performed. 0: DMA not suspended 1: DMA suspended Note: This bit has effect only on the priorities of the JBLPD peripheral. Bit 4 = LOOPB Local Loopback Selector. This bit allows the Local Loopback mode. When this mode is enabled (LOOPB=1), the VPWO out- put of the peripheral is sent to the VPWI input with- out inversions whereas the VPWO output line of the MCU is placed in the passive state. Moreover the VPWI input of the MCU is ignored by the pe- ripheral. (Refer to Figure 138). 0: Local Loopback disabled 1: Local Loopback enabled Note: When the LOOPB bit is set, also the INPOL bit must be set to obtain the correct management of the polarity. Bit 3:0 = RSEL[3:0] Registers Group Selection bits. These four bits are used to select one of the 9 groups of registers, each one composed of four registers that are stacked at the addresses from R252 (FCh) to R255 (FFh) of this register page (23). Unless the wanted registers group is already selected, to address a specific registers group, these bits must be correctly written. This feature allows that 36 registers (4 DMA regis- ters - RDADR, RDCPR, TDAPR, TDCPR - and 32 Message Filtering Registers - FREG[0:31]) are mapped using only 4 registers (here called Current Registers - CREG[3:0]). Since the Message Filtering Registers (FREG[0:31]) are seldom read or written, it is sug- gested to always reset the RSEL[3:0] bits after ac- cessing the FREG[0:31] registers. In this way the DMA registers are the current registers.

Table 62. Stacked registers map

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.7.2 Stacked Registers

See the description of the OPTIONS register to obtain more information on the map of the regis- ters of this section. JBLPD RECEIVER DMA ADDRESS POINTER REGISTER (RDAPR) R252 - RSEL[3:0]=0000b Register Page: 23 Reset Value: xxxx xxxx (xxh) To select this register, the RSEL[3:0] bits of the OPTIONS register must be reset Bit 7:1 = RA[7:1] Receiver DMA Address Pointer. RDAPR contains the address of the pointer (in the Register File) of the Receiver DMA data source when the DMA between the peripheral and the Memory Space is selected. Otherwise, when the DMA between the peripheral and Register File is selected, this register has no meaning. See Section 10.9.6.2 for more details on the use of this register. Bit 0 = PS Memory Segment Pointer Selector. This bit is set and cleared by software. It is only meaningful if RDCPR.RF/MEM = 1. 0: The ISR register is used to extend the address of data received by DMA (see MMU chapter) 1: The DMASR register is used to extend the ad- dress of data received by DMA (see MMU chap- ter) JBLPD RECEIVER DMA TRANSACTION COUNTER REGISTER (RDCPR) R253 - RSEL[3:0]=0000b Register Page: 23 Reset Value: xxxx xxxx (xxh) To select this register, the RSEL[3:0] bits of the OPTIONS register must be reset Bit 7:1 = RC[7:1] Receiver DMA Counter Pointer. RDCPR contains the address of the pointer (in the Register File) of the DM A receiver transaction counter when the DMA between Peripheral and Memory Space is selected. Otherwise, if the DMA between Peripheral and Register File is selected, this register points to a pair of registers that are used as DMA Address register and DMA Transac- tion Counter. more details on the use of this register. Bit 0 = RF/MEM Receiver Register File/Memory Selector. If this bit is set to “1”, then the Register File will be selected as Destination, otherwise the Memory space will be used. 0: Receiver DMA with Memory space 1: Receiver DMA with Register File JBLPD TRANSMITTER DMA ADDRESS POINT- ER REGISTER (TDAPR) R254 - RSEL[3:0]=0000b Register Page: 23 Reset Value: xxxx xxxx (xxh) To select this register, the RSEL[3:0] bits of the OPTIONS register must be reset Bit 7:1 = TA[7:1] Transmitter DMA Address Point- er. TDAPR contains the address of the pointer (in the Register File) of the Transmitter DMA data source when the DMA between the Memory Space and the peripheral is selected. Otherwise, when the DMA between Register File and the peripheral is selected, this register has no meaning. See Section 10.9.6.2 for more details on the use of this register. Bit 0 = PS Memory Segment Pointer Selector. This bit is set and cleared by software. It is only meaningful if TDCPR.RF/MEM = 1. 0: The ISR register is used to extend the address of data transmitted by DMA (see MMU chapter) 1: The DMASR register is used to extend the ad- dress of data transmitted by DMA (see MMU chapter) RA7 RA6 RA5 RA4 RA3 RA2 RA1 PS RC7 RC6 RC5 RC4 RC3 RC2 RC1 RF/MEM TA7 TA6 TA5 TA4 TA3 TA2 TA1 PS

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) JBLPD TRANSMITTER DMA TRANSACTION COUNTER REGISTER (TDCPR) R255 - RSEL[3:0]=0000b Register Page: 23 Reset Value: xxxx xxxx (xxh) To select this register, the RSEL[3:0] bits of the OPTIONS register must be reset Bit 7:1 = TC[7:1] Transmitter DMA Counter Point- er. RDCPR contains the address of the pointer (in the Register File) of the DM A transmitter transaction counter when the DMA between Memory Space and peripheral is selected. Otherwise, if the DMA between Register File and peripheral is selected, this register points to a pair of registers that are used as DMA Address register and DMA Transac- tion Counter. more details on the use of this register. Bit 0 = RF/MEM Transmitter Register File/Memory Selector. If this bit is set to “1”, then the Register File will be selected as Destinatio n, otherwise the Memory space will be used. 0: Transmitter DMA with Memory space 1: Transmitter DMA with Register File JBLPD MESSAGE FILTE RING REGISTERS (FREG[0:31]) R252/R253/R254/R255 - RSEL[3]=1 Register Page: 23 Reset Value: xxxx xxxx (xxh) TC7 TC6 TC5 TC4 TC3 TC2 TC1 RF/MEM Register 70 FREG0 F_07 F_06 F_05 F_04 F_03 F_02 F_01 F_00 FREG1 F_0F F_0E F_0D F_0C F_0B F_0A F_09 F_08 FREG2 F_17 F_16 F_15 F_14 F_13 F_12 F_11 F_10 FREG3 F_1F F_1E F_1D F_1C F_1B F_1A F_19 F_18 FREG4 F_27 F_26 F_25 F_24 F_23 F_22 F_21 F_20 FREG5 F_2F F_2E F_2D F_2C F_2B F_2A F_29 F_28 FREG6 F_37 F_36 F_35 F_34 F_33 F_32 F_31 F_30 FREG7 F_3F F_3E F_3D F_3C F_3B F_3A F_39 F_38 FREG8 F_47 F_46 F_45 F_44 F_43 F_42 F_41 F_40 FREG9 F_4F F_4E F_4D F_4C F_4B F_4A F_49 F_48 FREG10 F_57 F_56 F_55 F_54 F_53 F_52 F_51 F_50 FREG11 F_5F F_5E F_5D F_5C F_5B F_5A F_59 F_58 FREG12 F_67 F_66 F_65 F_64 F_63 F_62 F_61 F_60 FREG13 F_6F F_6E F_6D F_6C F_6B F_6A F_69 F_68 FREG14 F_77 F_76 F_75 F_74 F_73 F_72 F_71 F_70 FREG15 F_7F F_7E F_7D F_7C F_7B F_7A F_79 F_78 FREG16 F_87 F_86 F_85 F_84 F_83 F_82 F_81 F_80 FREG17 F_8F F_8E F_8D F_8C F_8B F_8A F_89 F_88 FREG18 F_97 F_96 F_95 F_94 F_93 F_92 F_91 F_90 FREG19 F_9F F_9E F_9D F_9C F_9B F_9A F_99 F_98 FREG20 F_A7 F_A6 F_A5 F_A4 F_A3 F_A2 F_A1 F_A0 FREG21 F_AF F_AE F_AD F_AC F_AB F_AA F_A9 F_A8 FREG22 F_B7 F_B6 F_B5 F_B4 F_B3 F_B2 F_B1 F_B0 FREG23 F_BF F_BE F_BD F_BC F_BB F_BA F_B9 F_B8 FREG24 F_C7 F_C6 F_C5 F_C4 F_C3 F_C2 F_C1 F_C0 FREG25 F_CF F_CE F_CD F_CC F_CB F_CA F_C9 F_C8 FREG26 F_D7 F_D6 F_D5 F_D4 F_D3 F_D2 F_D1 F_D0 FREG27 F_DF F_DE F_DD F_DC F_DB F_DA F_D9 F_D8 FREG28 F_E7 F_E6 F_E5 F_E4 F_E3 F_E2 F_E1 F_E0 FREG29 F_EF F_EE F_ED F_EC F_EB F_EA F_E9 F_E8 FREG30 F_F7 F_F6 F_F5 F_F4 F_F3 F_F2 F_F1 F_F0 FREG31 F_FF F_FE F_FD F_FC F_FB F_FA F_F9 F_F8

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) These registers are structured in eight groups of four registers. The user can gain access to these registers programming the RSEL[2:0] bits of the OPTIONS register while the RSEL[3] bit of the same register must be placed at 1. In this way the user can select the group where the registers that he/she wants to use are placed. See the descrip- tion of OPTIONS register for the correspondence between registers and the values of RSEL[2:0] bits (See Table 62). From the functional point of view, the FREG[0]- FREG[31] registers can be seen as an array of 256 bits involved in the J1850 received message filtering system. The first byte received in a frame (following a valid received SOF character) is an Identifier (I.D.) byte. It is used by the JBLPD peripheral as the address of the 256 bits array. If the bit of the array correspondent to the I.D. byte is set, then the byte is transferred to the RXDATA register and the RDRF flag is set. Also, every other data byte received in this frame is transferred to the RXDATA register unless the JBLPD peripheral is put into sleep mode setting the SLP bit. If the bit of the array correspondent to the I.D. byte is clear, then the transfer of this byte as well as any byte for the balance of this frame is inhibited, and the RDRF bit remains cleared. The bit 0 of the FREG[0] register (FREG[0].0 - marked as F_00 in the previous table) corre- sponds to the I.D. byte equal to 00h while the bit 7 of the FREG[31] register (FREG[31].7 - marked as F_FF in the previous table) corresponds to the I.D. byte equal to FFh. Note: The FREG registers are undefined upon re- set. Because of this, it is strongly recommended that the contents of these registers has to be de- fined before JE is set for the first time after reset. Otherwise, unpredictable results may occur.

J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) Register Address 7 0 STATUS reset value F0h ERR TRDY RDRF TLA RDT EODM EOFM IDLE TXDATA reset value F1h TXD7 x TXD6 x TXD5 x TXD4 x TXD3 x TXD2 x TXD1 x TXD0 x RXDATA reset value F2h RXD7 x RXD6 x RXD5 x RXD4 x RXD3 x RXD2 x RXD1 x RXD0 x TXOP reset value F3h MLC3 MLC2 MLC1 MLC0 OP2 OP1 OP0 CLKSEL reset value F4h 4X FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 CONTROL reset value F5h JE JDIS NFL JDLY4 JDLY3 JDLY2 JDLY1 JDLY0 PADDR reset value F6h ADR7 x ADR6 x ADR5 x ADR4 x ADR3 x ADR2 x ADR1 x ADR0 x ERROR reset value F7h TTO TDUF RDOF TRA RBRK CRCE IFD IBD IVR reset value F8h V7 x x x x x EV2 x EV1 x PRLR reset value F9h PRL2 PRL1 PRL0 SLP REOBP TEOBP IMR reset value FAh ERR_M TRDY_M RDRF_M TLA_M RXD_M EODM_M EOFM_M TXD_M OPTIONS reset value FBh INPOL NBSYMS DMASUSP LOOPB RSEL3 RSEL2 RSEL1 RSEL0 CREG0 reset value FCh b7 x x x x x x x x CREG1 reset value FDh b7 x x x x x x x x CREG2 reset value FEh b7 x x x x x x x x CREG3 reset value FFh b7 x x x x x x x x

10.10 CONTROLLER AREA NETWORK (bxCAN)

10.10.1 Introduction

CAN Time Triggered Communication option.

10.10.2 Main Features

10.10.3 General Description

handle each type of message. message reception have to be reduced. riod without losing messages. terface to the CAN controller. lected via a page select register. Figure 142. CAN Network Topology

tifiers (29-bit) are fully supported by hardware. managed completely by hardware. Figure 143. CAN Block Diagram

Figure 144. bxCAN Operating Modes

10.10.4 Operating Modes

sumption and an internal pull-up is active on RX1.

10.10.4.1 Initialization Mode

once the INAK bit has been cleared by hardware. of the configuration registers.

10.10.4.2 Normal Mode

activities and start message transfer. must be configured before entering Normal Mode.

10.10.4.3 Low Power Mode (Sleep)

bxCAN will not update the status bits. hardware, INAK stays cleared. occurs, in order to exit from sleep mode. bit has been cleared by hardware.

10.10.4.4 Test Mode

10.10.4.5 Silent Mode

the SILM bit in the CDGR register. bits (Acknowledge Bits, Error Frames). Figure 145. bxCAN in Silent Mode

10.10.4.6 Loop Back Mode

10.10.4.7 Loop Back combined with Silent

Figure 146. bxCAN in Combined Mode

10.10.5 Functional Description

10.10.5.1 Transmission Handling

the corresponding TXRQ bit in the MCSR register. TXOK bits in the MCSR and CTSR registers. transmission error detection. mailbox number will be scheduled first. ly restart the message transmission. ter by the TXOK, ALST and TERR bits.

Figure 147. Transmit Mailbox States

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.5.2 Time Triggered Communication

In this mode, the internal counter of the CAN hard- ware is activated and used to generate the Time Stamp value stored in the MTSRH and MTSRL registers. The internal counter is captured on the sample point of the Start Of Frame bit in both re- ception and transmission.

10.10.5.3 Reception Handling

For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox. Valid Message A received message is considered as valid when it has been received correctly according to the CAN protocol (no error until the last but one bit of the EOF field) and It passed through the identifier fil- tering successfully, see Section 10.10.5.4 Identifi- er Filtering.

Figure 148. Receive FIFO states

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) FIFO Management Starting from the empty state, the first valid mes- sage received is stored in the FIFO which be- comes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR regis- ter to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CRFR register. The FIFO be- comes empty again. If a new valid message has been received in the meantime, the FIFO stays in pending_1 state and the new message is availa- ble in the output mailbox. If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message. Otherwise the next valid message re- ceived will cause a loss of message. Refer also to Section 10.10.5.5 Message Storage Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message recep- tion will lead to an overrun and a message will be lost. The hardware signals the overrun condition by setting the FOVR bit in the CRFR register. Which message is lost depends on the configura- tion of the FIFO: – If the FIFO lock function is disabled (RFLM bit in the CMCR register cleared) the last message stored in the FIFO will be overwritten by the new incoming message. In this case the latest mes- sages will be always available to the application. – If the FIFO lock function is enabled (RFLM bit in the CMCR register set) the most recent message will be discarded and the software will have the three oldest messages in the FIFO available. Reception Related Interrupts Once a message has been stored in the FIFO, the FMP[1:0] bits are updated and an interrupt request is generated if the FMPIE bit in the CIER register is set. When the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CRFR register is set and an interrupt is generated if the FFIE bit in the CIER register is set. On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in the CIER register is set.

10.10.5.4 Identifier Filtering

In the CAN protocol the identifier of a message is not associated with the address of a node but re- lated to the content of the message. Consequently a transmitter broadcasts its message to all receiv- ers. On message reception a receiver node de- cides - depending on the identifier value - whether the software needs the message or not. If the mes- sage is needed, it is copied into the RAM. If not, the message must be discarded without interven- tion by the software. To fulfil this requiremen t, the bxCAN Controller provides eight configurable and scalable filter- banks (0-7) to the application, in order to receive only the messages the software needs. This hard- ware filtering saves CP U resources which would be otherwise needed to perform filtering by soft- ware. Each filter bank consists of eight 8-bit regis- ters, CFxR[0:7]. Scalable Width To optimize and adapt the filters to the application needs, each filter bank can be scaled independ- ently. Depending on the filter scale a filter bank provides: – One 32-bit filter for the STDID[10:0], IDE, EX- TID[17:0] and RTR bits. – Two 16-bit filters for the STDID[10:0], RTR and IDE bits. – Four 8-bit filters for the STDID[10:3] bits. The other bits are considered as don’t care. – One 16-bit filter and two 8-bit filters for filtering the same set of bits as the 16 and 8-bit filters de- scribed above. Refer to Figure 149. Furthermore, the filters can be configured in mask mode or in identifier list mode. Mask mode In mask mode the identifier registers are associat- ed with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. Identifier List mode In identifier list mode, the mask registers are used as identifier registers. Thus instead of defin- ing an identifier and a mask, two identifiers are specified, doubling the number of single identifi- ers. All bits of the incoming identifier must match the bits specified in the filter registers.

Figure 149. Filter Bank Scale Configuration - Register Organisation

1 These bits are located in the CFCR register

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) Filter Bank Scale and Mode Configuration The filter banks are configured by means of the corresponding CFCRx register. To configure a fil- ter bank it must be deactivated by clearing the FACT bit in the CFCR register. The filter scale is configured by means of the FSC[1:0] bits in the corresponding CFCR register, refer to Figure 149. The identifier list or identifier mask mode for the corresponding Mask/Identifier registers is config- ured by means of the FMCLx and FMCHx bits in the CFMR register. The FMCLx bit defines the mode for the two least significant bytes, and the FMCHx bit the mode for the two most significant bytes of filter bank x. Examples: – If filter bank 1 is configured as two 16-bit filters, then the FMCL1 bit defines the mode of the CF1R2 and CF1R3 registers and the FMCH1 bit defines the mode of the CF1R6 and CF1R7 reg- isters. – If filter bank 2 is configured as four 8-bit filters, then the FMCL2 bit defines the mode of the CF2R1 and CF2R3 registers and the FMCH2 bit defines the mode of the CF2R5 and CF2R7 reg- isters. Note: In 32-bit configuration, the FMCLx and FM- CHx bits must have the same value to ensure that the four Mask/Identifier registers are in the same mode. To filter a group of identifiers, configure the Mask/ Identifier registers in mask mode. To select single identifiers, configure the Mask/ Identifier registers in identifier list mode. Filters not used by the application should be left deactivated. Filter Match Index Once a message has been received in the FIFO it is available to the application. Typically application data are copied into RAM locations. To copy the data to the right location the application has to identify the data by means of the identifier. To avoid this and to ease the access to the RAM loca- tions, the CAN controller provides a Filter Match Index. This index is stored in the mailbox together with the message according to the filter priority rules. Thus each received message has its associated filter match index. The Filter Match index can be used in two ways: – Compare the Filter Match index with a list of ex- pected values. – Use the Filter Match Index as an index on an ar- ray to access the data destination location. For non-masked filters, the software no longer has to compare the identifier. If the filter is masked the software reduces the comparison to the masked bits only. Filter Priority Rules Depending on the filter combination it may occur that an identifier passes successfully through sev- eral filters. In this case the filter match value stored in the receive mailbox is chosen according to the following rules: – A filter in identifier list mode prevails on an filter in mask mode. – A filter with full identifier coverage prevails over filters covering part of the identifier, e.g. 16-bit fil- ters prevail over 8-bit filters. – Filters configured in the same mode and with identical coverage are prioritized by filter number and register number. The lower the number the higher the priority.

Figure 150. Filtering Mechanism - example content and MFMI 2 is stored in the FIFO.

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.5.5 Message Storage

The interface between the software and the hard- ware for the CAN messages is implemented by means of mailboxes. A mailbox contains all infor- mation related to a message; identifier, data, con- trol, status and time stamp information. Transmit Mailbox The software sets up the message to be transmit- ted in an empty transmit mailbox. The status of the transmission is indicated by hardware in the MCSR register. Transmit Mailbox Mapping Receive Mailbox When a message has been received, it is available to the software in the FIFO output mailbox. Once the software has handled the message (e.g. read it) the software must release the FIFO output mail- box by means of the RFOM bit in the CRFR regis- ter to make the next incoming message available. The filter match index is stored in the MFMI regis- ter. The 16-bit time stamp value is stored in the MTSR[0:1] registers. Receive Mailbox Mapping Offset to Transmit Mailbox base ad- dress (bytes) Register Name 0M C S R

1 MDLC

2 MIDR0

3 MIDR1

4 MIDR2

5 MIDR3

10 MDAR4

11 MDAR5

12 MDAR6

13 MDAR7

14 MTSR0

15 MTSR1

dress (bytes) Register Name 0M F M I 1M D L C

6 MDAR0

7 MDAR1

8 MDAR2

9 MDAR3

Figure 151. . CAN Error State Diagram

10.10.5.6 Error Management

longer able to transmit and receive messages. ter and to leave initialization mode.

10.10.5.7 Bit Timing

synchronizing on the following edges. between 1 and 4 time quanta. that the sample point is delayed. RJW so that the transmit point is moved earlier. fer to the ISO 11898 standard. Figure 152. Bit Timing TS1[3:0] and TS2[2:0] are defined in the CBTR1 Register.

Figure 153. CAN Frames

3 Transmission

active else 6 recessive bits.

10.10.6 Interrupts

Four interrupt vectors are dedicated to bxCAN. Figure 154. Event flags and Interrupt Generation

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) – The transmit interrupt can be generated by the following events: – Transmit mailbox 0 becomes empty, RQCP0 bit in the CTSR register set. – Transmit mailbox 1 becomes empty, RQCP1 bit in the CTSR register set. – Transmit mailbox 2 becomes empty, RQCP2 bit in the CTSR register set. – The FIFO 0 interrupt can be generated by the following events: – Reception of a new message, FMP bits in the CRFR0 register incremented. – FIFO0 full condition, FULL bit in the CRFR0 register set. – FIFO0 overrun condition, FOVR bit in the CRFR0 register set. – The FIFO 1 interrupt can be generated by the following events: – Reception of a new message, FMP bits in the CRFR1 register incremented. – FIFO1 full condition, FULL bit in the CRFR1 register set. – FIFO1 overrun condition, FOVR bit in the CRFR1 register set. – The error and status change interrupt can be generated by the following events: – Error condition, for more details on error con- ditions please refer to the CAN Error Status register (CESR). – Wake-up condition, SOF monitored on the CAN Rx signal.

10.10.7 Register Access Protection

Erroneous access to certain configuration regis- ters can cause the hardware to temporarily disturb the whole CAN network. Therefore the following registers can be modified by software only while the hardware is in initialization mode: CBTR0, CBTR1, CFCR0, CFCR1, CFMR and CDGR registers. Although the transmission of incorrect data will not cause problems at the CA N network level, it can severely disturb the application. A transmit mail- box can be only modified by software while it is in empty state, refer to Figure 147.Transmit Mailbox States The filters must be deactivated before their value can be modified by software. The modification of the filter configuration (scale or mode) can be done by software only in initialization mode.

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.8 Register Description

10.10.8.1 Control and Status Registers

CAN MASTER CONTROL REGISTER (CMCR) Reset Value: 0000 0010 (02h) Bit 7 = TTCM Time Triggered Communication Mode - Read/Set/Clear 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 10.10.5.2 Time Triggered Communication Mode. Bit 6 = ABOM Automatic Bus-Off Management - Read/Set/Clear This bit controls the behaviour of the CAN hard- ware on leaving the Bus-Off state. 0: The Bus-Off state is left on software request, once 128 x 11 recessive bits have been moni- tored and the software has first set and cleared the INRQ bit of the CMCR register. 1: The Bus-Off state is left automatically by hard- ware once 128 x 11 recessive bits have been monitored. For detailed information on the Bus-Off state please refer to Section 10.10.5.6 Error Manage- ment. Bit 5 = AWUM Automatic Wake-Up Mode - Read/Set/Clear This bit controls the behaviour of the CAN hard- ware on message reception during sleep mode. 0: The sleep mode is left on software request by clearing the SLEEP bit of the CMCR register. 1: The sleep mode is left automatically by hard- ware on CAN message detection. The SLEEP bit of the CMCR register and the SLAK bit of the CMSR register are cleared by hardware. Bit 4 = NART No Automatic Retransmission - Read/Set/Clear 0: The CAN hardware will automatically retransmit the message until it has been successfully transmitted according to the CAN standard. 1: A message will be transmitted only once, inde- pendently of the transmission result (successful, error or arbitration lost). Bit 3 = RFLM Receive FIFO Locked Mode - Read/Set/Clear 0: Receive FIFO not locked on overrun. Once a re- ceive FIFO is full the next incoming message will overwrite the previous one. 1: Receive FIFO locked against overrun. Once a receive FIFO is full the next incoming message will be discarded. Bit 2 = TXFP Transmit FIFO Priority - Read/Set/Clear This bit controls the transmission order when sev- eral mailboxes are pending at the same time. 0: Priority driven by the identifier of the message 1: Priority driven by the request order (chronologi- cally) Bit 1 = SLEEP Sleep Mode Request - Read/Set/Clear This bit is set by software to request the CAN hard- ware to enter the sleep mode. Sleep mode will be entered as soon as the current CAN activity (trans- mission or reception of a CAN frame) has been completed. This bit is cleared by software to exit sleep mode. This bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the CAN Rx signal. Bit 0 = INRQ Initialization Request - Read/Set/Clear The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synch ronized and ready for transmission and reception. Hardware signals this event by clearing the INAK bit if the CMSR regis- ter. Software sets this bit to request the CAN hardware to enter initialization mode. Once software has set the INRQ bit, the CAN ha rdware waits until the current CAN activity (transmission or reception) is completed before entering the initialization mode. Hardware signals this event by setting the INAK bit in the CMSR register. TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) CAN MASTER STATUS REGISTER (CMSR) Reset Value: 0000 0010 (02h) Note: To clear a bit of this register the software must write this bit with a one. Bit 7:4 = Reserved. Forced to 0 by hardware. Bit 5 = REC Receive - Read The CAN hardware is currently receiver. Bit 4 = TRAN Transmit - Read The CAN hardware is currently transmitter. Bit 3 = WKUI Wake-Up Interrupt - Read/Clear This bit is set by hardware to signal that a SOF bit has been detected while the CAN hardware was in sleep mode. Setting this bit generates a status change interrupt if the WKUIE bit in the CIER reg- ister is set. This bit is cleared by software. Bit 2 = ERRI Error Interrupt - Read/Clear This bit is set by hardware when a bit of the CESR has been set on error detection and the corre- sponding interrupt in the CEIER is enabled. Set- ting this bit generates a status change interrupt if the ERRIE bit in the CIER register is set. This bit is cleared by software. Bit 1 = SLAK Sleep Acknowledge - Read This bit is set by hardware and indicates to the software that the CAN ha rdware is now in sleep mode. This bit acknowledges the sleep mode re- quest from the software (set SLEEP bit in CMCR register). This bit is cleared by hardware when the CAN hardware has left sleep mode. Sleep mode is left when the SLEEP bit in the CMCR register is cleared. Please refer to the AWUM bit of the CMCR register description for detailed information for clearing SLEEP bit. Bit 0 = INAK Initialization Acknowledge - Read This bit is set by hardware and indicates to the software that the CAN har dware is now in initiali- zation mode. This bit acknowledges the initializa- tion request from the software (set INRQ bit in CMCR register). This bit is cleared by hardware when the CAN hardware has left the initialization mode and is now synchronized on the CAN bus. To be syn- chronized the hardware has to monitor a se- quence of 11 consecutiv e recessive bits on the CAN RX signal. CAN TRANSMIT STATUS REGISTER (CTSR) Read / Write Reset Value: 0000 0000 (00h) Note: To clear a bit of this register the software must write this bit with a one. Bit 7 = Reserved. Forced to 0 by hardware. Bit 6 = TXOK2 Transmission OK for mailbox 2 - Read This bit is set by hardware when the transmission request on mailbox 2 has been completed suc- cessfully. Please refer to Figure 147. This bit is cleared by hardware when mailbox 2 is requested for transmission or when the software clears the RQCP2 bit. Bit 5 = TXOK1 Transmission OK for mailbox 1 - Read This bit is set by hardware when the transmission request on mailbox 1 has been completed suc- cessfully. Please refer to Figure 147 This bit is cleared by hardware when mailbox 1 is requested for transmission or when the software clears the RQCP1 bit. 0 0 REC TRAN WKUI ERRI SLAK INAK

0 TXOK2 TXOK1 TXOK0 0

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) Bit 4 = TXOK0 Transmission OK for mailbox 0 - Read This bit is set by hardware when the transmission request on mailbox 0 has been completed suc- cessfully. Please refer to Figure 147. This bit is cleared by hardware when mailbox 0 is requested for transmission or when the software clears the RQCP0 bit. Bit 3 = Reserved. Forced to 0 by hardware. Bit 2 = RQCP2 Request Completed for Mailbox 2 - Read/Clear This bit is set by hardware to signal that the last re- quest for mailbox 2 has been completed. The re- quest could be a transmit or an abort request. This bit is cleared by software. Bit 1 = RQCP1 Request Completed for Mailbox 1 - Read/Clear This bit is set by hardware to signal that the last re- quest for mailbox 1 has been completed. The re- quest could be a transmit or an abort request. This bit is cleared by software. Bit 0 = RQCP0 Request Completed for Mailbox 0 - Read/Clear This bit is set by hardware to signal that the last re- quest for mailbox 0 has been completed. The re- quest could be a transmit or an abort request. This bit is cleared by software. CAN TRANSMIT PRIORITY REGISTER (CTPR) All bits of this register are read only. Reset Value: 0000 0000 (00h) Bit 7 = LOW2 Lowest Priority Flag for Mailbox 2 - Read This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1 - Read This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0 - Read This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority. Note: These bits are set to zero when only one mailbox is pending. Bit 4 = TME2 Transmit Mailbox 2 Empty - Read This bit is set by hardware when no transmit re- quest is pending for mailbox 2. Bit 3 = TME1 Transmit Mailbox 1 Empty - Read This bit is set by hardware when no transmit re- quest is pending for mailbox 1. Bit 2 = TME0 Transmit Mailbox 0 Empty - Read This bit is set by hardware when no transmit re- quest is pending for mailbox 0. Bit 1:0 = CODE[1:0] Mailbox Code - Read In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. In case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority. LOW2 LOW1 LOW0 TME2 TME1 TME0 CODE1 CODE0

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) CAN RECEIVE FIFO REGISTERS (CRFRx) Read / Write Reset Value: 0000 0000 (00h) Note: To clear a bit in this register, software must write a “1” to the bit. Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = RFOM Release FIFO Output Mailbox - Read/Set Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no ef- fect. If at least two messages are pending in the FIFO, the software has to release the output mail- box to access the next message. Cleared by hardware when the output mailbox has been released. Bit 4 = FOVR FIFO Overrun - Read/Clear This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. Bit 3 = FULL FIFO Full - Read/Clear Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 = Reserved. Forced to 0 by hardware. Bit 1:0 = FMP[1:0] FIFO Message Pending - Read These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mail- box by setting the RFOM bit. CAN INTERRUPT ENABLE REGISTER (CIER) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 7 = WKUIE Wake-Up Interrupt Enable 0: No interrupt when WKUI is set. 1: Interrupt generated when WKUI bit is set. Bit 6 = FOVIE1 FIFO Overrun Interrupt Enable 0: No interrupt when FOVR is set. 1: Interrupt generation when FOVR is set. Bit 5 = FFIE1 FIFO Full Interrupt Enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 4 = FMPIE1 FIFO Message Pending Interrupt Enable 0: No interrupt on FMP[1:0] bits transition from 00b to 01b. 1: Interrupt generated on FMP[1:0] bits transition from 00b to 01b. Bit 3 = FOVIE0 FIFO Overrun Interrupt Enable 0: No interrupt when FOVR bit is set. 1: Interrupt generated when FOVR bit is set. Bit 2 = FFIE0 FIFO Full Interrupt Enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 1 = FMPIE0 FIFO Message Pending Interrupt Enable 0: No interrupt on FMP[1:0] bits transition from 00b to 01b. 1: Interrupt generated on FMP[1:0] bits transition from 00b to 01b. Bit 0 = TMEIE Transmit Mailbox Empty Interrupt Enable 0: No interrupt when RQCPx bit is set. 1: Interrupt generated when RQCPx bit is set. Note: refer to Standard Interrupts Section. 0 0 RFOM FOVR FULL 0 FMP1 FMP0 WKUIE FOVIE1 FFIE1 FMPIE1 FOVIE0 FFIE0 FMPIE0 TMEIE

Bit 7 = Reserved. Forced to 0 by hardware. sion) without error, this field will be cleared to ‘0’. Table 63. LEC Error Types Bit 3 = Reserved. Forced to 0 by hardware. Transmit Error Counter greater than 127). Transmit Error Counter greater than 96. condition is pending in the CESR. condition is pending in the CESR. Bit 6:5 = Reserved. Forced to 0 by hardware. LEC[2:0] is set by hardware on error detection. LEC[2:0] is set by hardware on error detection. Bit 3 = Reserved. Forced to 0 by hardware. 0: ERRI bit will not be set when BOFF is set. 1: ERRI bit will be set when BOFF is set. 0: ERRI bit will not be set when EPVF is set. 1: ERRI bit will be set when EPVF is set. 0: ERRI bit will not be set when EWGF is set. 1: ERRI bit will be set when EWGF is set. Note: refer to Standard Interrupts Section.

0 LEC2 LEC1 LEC0 0 BOFF EPVF EWGF

1 Stuff Error

3 Acknowledgment Error

4 Bit recessive Error

5 Bit dominant Error

6 CRC Error

7 Set by software

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) TRANSMIT ERROR COUNTER REG. (TECR) Read Only Reset Value: 00h TEC[7:0] is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol. RECEIVE ERROR COUNTER REG. (RECR) Page: 00h — Read Only Reset Value: 00h REC[7:0] is the Receive Error Counter implement- ing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN stand- ard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. CAN DIAGNOSIS REGISTER (CDGR) All bits of this register are set and clear by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 3 = RX CAN Rx Signal - Read Monitors the actual value of the CAN_RX Pin. Bit 2 = SAMP Last Sample Point - Read The value of the last sample point. Bit 1 = SILM Silent Mode - Read/Set/Clear 0: Normal operation 1: Silent Mode Bit 0 = LBKM Loop Back Mode - Read/Set/Clear 0: Loop Back Mode disabled 1: Loop Back Mode enabled TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0 0 0 0 RX SAMP SILM LBKM

when the CAN hardware is in configuration mode. or shorten a bit to perform the resynchronization. These bits define the length of a time quantum. Section 10.10.5.7 Bit Timing. Bit 7 = Reserved. Forced to 0 by hardware. Section 10.10.5.7 Bit Timing. Bit 7:3 = Reserved. Forced to 0 by hardware. Table 64. Filter Page Selection

0 TS22 TS21 TS20 TS13 TS12 TS11 TS10

0 Acceptance Filter 0:1

1 Acceptance Filter 2:3

2 Acceptance Filter 4:5

3 Acceptance Filter 6:7

4 Filter Configuration

5 Filter Configuration

6 Filter Configuration

7 Filter Configuration

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.8.2 Mailbox Registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 10.10.5.5 Message Storage for detailed register mapping. Transmit and receive mailboxes have the same registers except: – MCSR register in a transmit mailbox is replaced by MFMI register in a receive mailbox. – A receive mailbox is always write protected. – A transmit mailbox is write enable only while empty, corresponding TME bit in the CTPR reg- ister set. MAILBOX CONTROL STATUS REGISTER (MCSR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = TERR Transmission Error - Read/Clear This bit is updated by hardware after each trans- mission attempt. 0: The previous transmission was successful 1: The previous transmission failed due to an error Bit 4 = ALST Arbitration Lost - Read/Clear This bit is updated by hardware after each trans- mission attempt. 0: The previous transmission was successful 1: The previous transmission failed due to an arbi- tration lost Bit 3 = TXOK Transmission OK - Read/Clear The hardware updates this bit after each transmis- sion attempt. 0: The previous transmission failed 1: The previous transmission was successful Note: This bit has the same value as the corre- sponding TXOKx bit in the CTSR register. Bit 2 = RQCP Request Completed - Read/Clear Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request. Note: This bit has the same value as the corre- sponding RQCPx bit of the CTSR register. Clearing this bit clears all the status bits (TX- OK, ALST and TERR) in the MCSR register and the RQCP and TXOK bits in the CTSR register. Bit 1 = ABRQ Abort Request for Mailbox - Read/Set Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bit 0 = TXRQ Transmit Mailbox Request - Read/Set Set by software to request the transmission for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Note: This register is implemented only in transmit mailboxes. In receive mailboxes, the MFMI regis- ter is mapped at this location. 0 0 TERR ALST TXOK RQCP ABRQ TXRQ

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) MAILBOX FILTER MATCH INDEX (MFMI) This register is read only. Reset Value: 0000 0000 (00h) Bit 7:0 = FMI[7:0] Filter Match Index This register contains the index of the filter the message stored in the mailbox passed through. For more details on identifi er filtering please refer to Section 10.10.5.4 - Filter Match Index para- graph. Note: This register is implemented only in receive mailboxes. In transmit mailboxes, the MCSR reg- ister is mapped at this location. MAILBOX IDENTIFIER REGISTERS (MIDR[3:0]) Read / Write Reset Value: xxxx xxxx (xxh) MIDR0 Bit 7 = Reserved. Forced to 0 by hardware. Bit 6 = IDE Extended Identifier This bit defines the identifier type of message in the mailbox. 0: Standard identifier. 1: Extended identifier. Bit 5 = RTR Remote Transmission Request 0: Data frame 1: Remote frame Bit 4:0 = STID[10:6] Standard Identifier 5 most significant bits of the standard part of the identifier. MIDR1 Bit 7:2 = STID[5:0] Standard Identifier 6 least significant bits of the standard part of the identifier. Bit 1:0 = EXID[17:16] Extended Identifier 2 most significant bits of the extended part of the identifier. MIDR2 Bit 7:0 = EXID[15:8] Extended Identifier Bit 15 to 8 of the extended part of the identifier. MIDR3 Bit 7:1 = EXID[6:0] Extended Identifier 6 least significant bits of the extended part of the identifier. FMI7 FMI6 FMI5 FMI4 FMI3 FMI2 FMI1 FMI0

0 IDE RTR STID10 STID9 STID8 STID7 STID6

STID5 STID4 STID3 STID2 STID1 STID0 EXID17 EXID16 EXID15 EXID14 EXID13 EXID12 EXID11 EXID10 EXID9 EXID8 EXID7 EXID6 EXID5 EXID4 EXID3 EXID2 EXID1 EXID0

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) MAILBOX DATA LENGTH CONTROL REGIS- TER (MDLC) All bits of this register is write protected when the mailbox is not in empty state. Read / Write Reset Value: xxxx xxxx (xxh) Bit 7 = TGT Transmit Global Time This bit is active only when the hardware is in the Time Trigger Communication mode, TTCM bit of the CCR register is set. 0: MTSRH and MTSRL registers are not sent. 1: MTSRH and MTSRL registers are sent in the last two data bytes of the message. 6:4 = Reserved. Forced to 0 by hardware. Bit 3:0 = DLC[3:0] Data Length Code This field defines the number of data bytes a data frame contains or a remote frame request. MAILBOX DATA REGISTERS (MDAR[7:0]) All bits of this register are write protected when the mailbox is not in empty state. Read / Write Reset Value: xxxx xxxx (xxh) Bit 7:0 = DATA[7:0] Data A data byte of the message. A message can con- tain from 0 to 8 data bytes. MAILBOX TIME STAMP LOW REGISTER (MTSLR) Read / Write Reset Value: xxxx xxxx (xxh) Bit 7:0 = TIME[7:0] Message Time Stamp Low This fields contains the low byte of the 16-bit timer value captured at the SOF detection. MAILBOX TIME STAMP HIGH REGISTER (MTSHR) Read / Write Reset Value: xxxx xxxx (xxh) Bit 7:0 = TIME[15:8] Message Time Stamp High This field contains the high byte of the 16-bit timer value captured at the SOF detection. TGT 0 0 0 DLC3 DLC2 DLC1 DLC0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 TIME7 TIME6 TIME5 TIME4 TIME3 TIME2 TIME1 TIME0 TIME15 TIME14 TIME13 TIME12 TIME11 TIME10 TIME9 TIME8

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.8.3 CAN Filter Registers

CAN FILTER CONFIGURATION REG.0 (CFCR0) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Note: To modify the FFAx and FSCx bits, the bx- CAN must be in INIT mode. Bit 7 = FFA1 Filter FIFO Assignment for Filter 1 The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 6:5 = FSC1[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 4 = FACT1 Filter Active The software sets this bit to activate Filter 1. To modify the Filter 1 registers (CF1R[7:0]), the FACT1 bit must be cleared. 0: Filter 1 is not active 1: Filter 1 is active Bit 3 = FFA0 Filter FIFO Assignment for Filter 0 The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 2:1 = FSC0[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 0 = FACT0 Filter Active The software sets this bit to activate Filter 0. To modify the Filter 0 registers (CF0R[0:7]), the FACT0 bit must be cleared. 0: Filter 0 is not active 1: Filter 0 is active CAN FILTER CONFIGURATION REG.1 (CFCR1) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 7 = FFA3 Filter FIFO Assignment for Filter 3 The message passing throug h this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 6:5 = FSC3[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 4 = FACT3 Filter Active The software sets this bit to activate filter 3. To modify the Filter 3 registers (CF3R[0:7]) the FACT3 bit must be cleared. 0: Filter 3 is not active 1: Filter 3 is active Bit 3 = FFA2 Filter FIFO Assignment for Filter 2 The message passing throug h this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 2:1 = FSC2[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 0 = FACT2 Filter Active The software sets this bit to activate Filter 2. To modify the Filter 2 registers (CF2R[0:7]), the FACT2 bit must be cleared. 0: Filter 2 is not active 1: Filter 2 is active FFA1 FSC11 FSC10 FACT1 FFA0 FSC01 FSC00 FACT0 FFA3 FSC31 FSC30 FACT3 FFA2 FSC21 FSC20 FACT2

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) CAN FILTER CONFIGURATION REG.2 (CFCR2) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Note: To modify FFAx and FSCx bits bxCAN must be in INIT mode. Bit 7 = FFA5 Filter FIFO Assignment for Filter 5 The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 6:5 = FSC5[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 4 = FACT5 Filter Active The software sets this bit to activate Filter 5. To modify the filter 5 registers (CF5R[7:0]), the FACT5 bit must be cleared. 0: Filter 5 is not active 1: Filter 5 is active Bit 3 = FFA4 Filter FIFO Assignment for Filter 4 The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 2:1 = FSC4[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 0 = FACT4 Filter Active The software sets this bit to activate filter 4. To modify the Filter 4 registers (CF4R[7:0]), the FACT4 bit must be cleared). 0: Filter 4 is not active 1: Filter 4 is active CAN FILTER CONFIGURATION REG.3 (CFCR3) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 7 = FFA7 Filter FIFO Assignment for Filter 7 The message passing throug h this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 6:5 = FSC7[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 4 = FACT7 Filter Active The software sets this bit to activate Filter 7. To modify the Filter 7 registers (CF7R[7:0]), the FACT7 bit must be cleared. 0: Filter 7 is not active. 1: Filter 7 is active. Bit 3 = FFA6 Filter FIFO Assignment for Filter 6 This bit allows the softwa re to define whether the message passing through this filter will be as- signed to the receive FIFO0 or FIFO1. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Bit 2:1 = FSC6[1:0] Filter Scale Configuration These bits define the scale configuration of Filter Bit 0 = FACT6 Filter Active The software sets this bit to activate Filter 6. To modify the Filter 6 registers (CF6R[7:0]), the FACT6 bit must be cleared. 0: Filter 6 is not active 1: Filter 6 is active FFA5 FSC51 FSC50 FACT5 FFA4 FSC41 FSC40 FACT4 FFA7 FSC71 FSC70 FACT7 FFA6 FSC61 FSC60 FACT6

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) CAN FILTER MODE REG.1 (CFMR1) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Note: Please refer to Figure 149.Filter Bank Scale Configuration - Register Organisation Bit 7 = FMH7 Filter Mode High Mode of the high registers of Filter 7. 0: High registers are in mask mode. 1: High registers are in identifier list mode. Bit 6 = FML7 Filter Mode Low Mode of the low registers of Filter 7. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 5 = FMH6 Filter Mode High Mode of the high registers of Filter 6. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 4 = FML6 Filter Mode Low Mode of the low registers of Filter 6. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 3 = FMH5 Filter Mode High Mode of the high registers of filter 5. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 2 = FML5 Filter Mode Low Mode of the low registers of Filter 5. 0: Low registers are in mask mode 1: Low registers are in identifier list mode. Bit 1 = FMH4 Filter Mode High Mode of the high registers of filter 4. 0: High registers are in mask mode. 1: High registers are in identifier list mode. Bit 0 = FML4 Filter Mode Low Mode of the low registers of filter 4. 0: Low registers are in mask mode. 1: Low registers are in identifier list mode. CAN FILTER MODE REG.0 (CFMR0) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 7 = FMH3 Filter Mode High Mode of the high registers of Filter 3. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 6 = FML3 Filter Mode Low Mode of the low registers of Filter 3. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 5 = FMH2 Filter Mode High Mode of the high registers of Filter 2. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 4 = FML2 Filter Mode Low Mode of the low registers of Filter 2. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 3 = FMH1 Filter Mode High Mode of the high registers of Filter 1. 0: High registers are in mask mode 1: High registers are in identifier list mode FMH7 FML7 FMH6 FML6 FMH5 FML5 FMH4 FML4 FMH3 FML3 FMH2 FML2 FMH1 FML1 FMH0 FML0

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) Bit 2 = FML1 Filter Mode Low Mode of the low registers of filter 1. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 1 = FMH0 Filter Mode High Mode of the high registers of filter 0. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 0 = FML0 Filter Mode Low Mode of the low registers of filter 0. 0: Low registers are in mask mode 1: Low registers are in identifier list mode FILTER x REGISTER[7:0] (CFxR[7:0]) Read / Write Reset Value: xxxx xxxx (xxh) In all configurations: Bit 7:0 = FB[7:0] Filter Bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: Don’t care, the bit is not used for the comparison 1: Must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. Note: Each filter x is composed of 8 registers, CFxR[7:0]. Depending on the scale and mode configuration of the filter the function of each reg- ister can differ. For the filter mapping, functions description and mask registers association, refer to Section 10.10.5.4Identifier Filtering. A Mask/Identifier register in mask mode has the same bit mapping as in identifier list mode. Note: To modify these registers, the correspond- ing FACT bit in the CFCR register must be cleared. F B 7F B 6F B 5F B 4F B 3F B 2F B 1F B 0

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.8.4 Page Mapping for CAN 0 / CAN 1

PAGE 50 / 38 PAGE 51 / 39 PAGE 52 / 40 PAGE 54/0 42/0 PAGE 54/1 42/1 Receive FIFO 1 Tx Mailbox 0 Tx Mailbox 1 Acceptance Filter 0:1 Acceptance Filter 2:3 MIDR0 MIDR1 MIDR2 MIDR3 MDAR0 MDAR1 MDAR2 MDAR3 MDAR4 MDAR5 MDAR6 MDAR7 MCSR MDLC MTSLR MTSHR MIDR0 MIDR1 MIDR2 MIDR3 MDAR0 MDAR1 MDAR2 MDAR3 MDAR4 MDAR5 MDAR6 MDAR7 MCSR MDLC MTSLR MTSHR MIDR0 MIDR1 MIDR2 MIDR3 MDAR0 MDAR1 MDAR2 MDAR3 MDAR4 MDAR5 MDAR6 MDAR7 PAGE 54/4 42/4 Filter Configuration CFMR0 CFMR1 Reserved Reserved CFCR0 CFCR1 CFCR2 CFCR3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CF0R0 CF0R1 CF0R2 CF0R3 CF0R4 CF0R5 CF0R6 CF0R7 CF1R0 CF1R1 CF1R2 CF1R3 CF1R4 CF1R5 CF1R6 CF1R7 CF2R0 CF2R1 CF2R2 CF2R3 CF2R4 CF2R5 CF2R6 CF2R7 CF3R0 CF3R1 CF3R2 CF3R3 CF3R4 CF3R5 CF3R6 CF3R7 CMCR CMSR Reserved CFPSR PAGE 48 / 36 Control/Status CTSR CTPR CRFR0 CRFR1 CIER CESR CEIER TEC REC CDGR CBTR0 CBTR1 MFMI MDLC MTSLR MTSHR PAGE 49 / 37 Receive FIFO 0 MIDR0 MIDR1 MIDR2 MIDR3 MDAR0 MDAR1 MDAR2 MDAR3 MDAR4 MDAR5 MDAR6 MDAR7 PAGE 53 / 41 Tx Mailbox 2 MCSR MDLC MTSLR MTSHR MIDR0 MIDR1 MIDR2 MIDR3 MDAR0 MDAR1 MDAR2 MDAR3 MDAR4 MDAR5 MDAR6 MDAR7 PAGE 54/2 42/2 Acceptance Filter 4:5 CF4R0 CF4R1 CF4R2 CF4R3 CF4R4 CF4R5 CF4R6 CF4R7 CF5R0 CF5R1 CF5R2 CF5R3 CF5R4 CF5R5 CF5R6 CF5R7 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d) Page Mapping for CAN0 /CAN1 (Cont’d) PAGE 54/3 42/3 Acceptance Filter 6:7 CF6R0 CF6R1 CF6R2 CF6R3 CF6R4 CF6R5 CF6R6 CF6R7 CF7R0 CF7R1 CF7R2 CF7R3 CF7R4 CF7R5 CF7R6 CF7R7 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255

Table 65. bxCAN Control & Status Page - Register Map and Reset Values

Table 66. bxCAN Mailbox Pages - Register Map and Reset Values Table 67. bxCAN Filter Configuration Page - Register Map and Reset Values

CONTROLLER AREA NETWORK (bxCAN) CONTROLLER AREA NETWORK (Cont’d)

10.10.9 IMPORTANT NOTES ON CAN

Refer to Section 13.4 on page 413 and Section 13.6 on page 414.

10.11.1 Main Characteristics

10.11.2 Introduction

cessive approximation converter. PR[2:0] bits of the CLR2 register (R253-page 63)). log channel to be converted. CC[3:0] bits in the CLR1 register (R252-page 63). Figure 155. ADC Block Diagram

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) ANALOG TO DIGITAL CONVERTER (Cont’d) Single and continuous conversion modes are available. These two modes may be triggered by an external signal or, inte rnally, by the Multifunc- tion Timer MFT0. A Power-Down programmable bit allows the ADC to be set in low-power idle mode. The reference voltage AV DD can be switched off when the ADC is in power down mode. The ADC Interrupt Unit provides two maskable channels (Analog Watchdog and End of Conver- sion) with hardware fixed priority, and up to 7 pro- grammable priority levels. Conversion Time The maximum CKAD frequency allowable for the analog part is 4 MHz. This is provided by a pro- grammable prescaler that divides the ST9 system clock (INTCLK) and a divider by 2. The user must program the PR[2:0] bits in Control Logic Register 2 (CLR2, R253 - Page 63) to select the right pres- caler dividing factor to obtain the correct clock fre- quency for the analog part. Table 69 shows the possible prescaling values and the related sam- pling and conversion times. Generally, the formu- las for the sampling and conversion times are: T Sample = (TINTCLK x 2) x (PR[2:0] x 8) TConv = (TINTCLK x 2) x (PR[2:0] x 28) The user may need to increase the conversion time if a resistor is added to the input pin, for in- stance, as an overvoltage protection. In this case, the ADC needs a longer sampling time to work correctly. CAUTION: ADC INPUT PIN CONFIGURATION The input Analog channel is selected by using the I/O pin Alternate Function setting (PxC2, PxC1, PxC0 = 1,1,1) as described in the I/O ports sec- tion. The I/O configuration of the port connected to the ADC converter is modified in order to prevent the analog voltage present on the I/O pin from causing high power dissipation across the input buffer. Analog channels should be maintained in Alternate Function configuration for this reason.

10.11.3 Functional Description

10.11.3.1 Operating Modes

Two operating modes are available: Continuous Mode and Single Mode. To enter one of these modes it is necessary to program the CONT bit of the Control Logic Register2 (CLR2, R253- page63). The Continuous Mode is selected when CONT is set, while Single Mode is selected when CONT is reset. Both modes operate in AUTOSCAN configuration, allowing sequential conversion of the input chan- nels. The number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into Control Reg- ister 1 (SC[3:0] bits). As each conversion is com- pleted, the channel number is automatically incre- mented, up to channel 15. For example, if SC[3:0] are set to 0011, the conv ersion will proceed from channel 3 to channel 15, whereas, if SC[3:0] are set to 1111, only channel 15 will be converted. When the ST bit of Control Logic Register 2 is set, either by software or by hardware (by an internal or external synchronisation trigger signal), the an- alog inputs are sequentially converted (from the first selected channel up to channel 15) and the re- sults are stored in the relevant pair of Data Regis- ters. In Single Mode (CONT = “0”), the ST bit is reset by hardware following conversion of channel 15; an End of Conversion (ECV) interrupt request is is- sued and the ADC waits for a new start event. In Continuous Mode (CONT = “1”), a continuous conversion flow is initiated by the start event. When conversion of channel 15 is complete, conversion of channel 's' is initiated (where 's' is specified by the setting of the SC[3:0] bits); this will continue until the ST bit is reset by software. In all cases, an ECV interrupt is issued each time channel 15 conversion ends. When channel 'i' is converted ('s' <'i' <15), the re- lated pair of Data Regi sters is reloaded with the new conversion result and the previous value is lost. The End of Conversion (ECV) interrupt serv- ice routine can be used to save the current values before a new conversion sequence (so as to cre- ate signal sample tables in the Register File or in Memory).

10.11.3.2 Triggering and Synchronisation

In both modes, conversion may be triggered by in- ternal or external conditions; externally this may be tied to EXTRG, as an Alternate Function input on an I/O port pin, and internally, it may be tied to INTRG, generated by a Multifunction Timer pe- ripheral. Both external and internal events can be separately masked by programming the EXTG/ INTG bits of the Control Logic Register (CLR). The events are internally ORed, thus avoiding potential hardware conflicts. However, the correct proce- dure is to enable only one alternate synchronisa- tion condition at any time.

ger pulses after the first are ignored. sion is still in progress, it will be ignored. even if the CLR2.POW is reset.

10.11.3.3 Analog Watchdog

to see the possible choices for this feature.

10.11.3.4 Power Down Mode

tion of the converter circuitry. Figure 156. Analog Watchdog Function Figure 157. ADC Trigger Source

Figure 158. Application Example: Analog Watchdog used in Motor Speed Control

10.11.4 Interrupts

service routines are stored. of Conversion request, which is held pending. will cause an interrupt request to be generated.

70 Lower

70 Upper

10-BIT ANALOG TO DIGITAL CONVERTER (ADC)

10.11.5 Register Description

DATA REGISTERS (DiHR/DiLR) The conversion results for the 16 available chan- nels are loaded into the 32 Data Registers (two for each channel) following conversion of the corre- sponding analog input. CHANNEL 0 DATA HIGH REGISTER (D0HR) R240 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D0.[9:2]: Channel 0 9:2 bit Data CHANNEL 0 DATA LOW REGISTER (D0LR) R241 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:6 = D0.[1:0]: Channel 0 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 1 DATA HIGH REGISTER (D1HR) R242 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D1.[9:2]: Channel 1 9:2 bit Data CHANNEL 1 DATA LOW REGISTER (D1LR) R243 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D1.[1:0]: Channel 1 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 2 DATA HIGH REGISTER (D2HR) R244 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D2.[9:2]: Channel 2 9:2 bit Data CHANNEL 2 DATA LOW REGISTER (D2LR) R245 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D2.[1:0]: Channel 2 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 3 DATA HIGH REGISTER (D3HR) R246 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D3.[9:2]: Channel 3 9:2 bit Data CHANNEL 3 DATA LOW REGISTER (D3LR) R247 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D3.[1:0]: Channel 3 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. D 0 . 1 D 0 . 0 000000 D 1 . 1 D 1 . 0 000000 D 2 . 1 D 2 . 0 000000 D 3 . 1 D 3 . 0 000000

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CHANNEL 4 DATA HIGH REGISTER (D4HR) R248 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D4.[9:2]: Channel 4 9:2 bit Data CHANNEL 4 DATA LOW REGISTER (D4LR) R249 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:6 = D4.[1:0]: Channel 4 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 5 DATA HIGH REGISTER (D5HR) R250 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D5.[9:2]: Channel 5 9:2 bit Data CHANNEL 5 DATA LOW REGISTER (D5LR) R251 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D1.[1:0]: Channel 5 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 6 DATA HIGH REGISTER (D6HR) R252 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D6.[9:2]: Channel 6 9:2 bit Data CHANNEL 6 DATA LOW REGISTER (D6LR) R253 - Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D6.[1:0]: Channel 6 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 7 DATA HIGH REGISTER (D7HR) R254 - Read/Write Register Page: 61 Reset Value: undefined Bits 7:0 = D7.[9:2]: Channel 7 9:2 bit Data CHANNEL 7 DATA LOW REGISTER (D7LR) R255- Read/Write Register Page: 61 Reset Value: xx00 0000 Bits 7:0 = D7.[1:0]: Channel 7 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. D 4 . 1 D 4 . 0 000000 D 5 . 1 D 5 . 0 000000 D 6 . 1 D 6 . 0 000000 D 7 . 1 D 7 . 0 000000

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CHANNEL 8 DATA HIGH REGISTER (D8HR) R240 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D8.[9:2]: Channel 8 9:2 bit Data CHANNEL 8 DATA LOW REGISTER (D8LR) R241 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:6 = D8.[1:0]: Channel 8 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 9 DATA HIGH REGISTER (D9HR) R242 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D9.[9:2]: Channel 9 9:2 bit Data CHANNEL 9 DATA LOW REGISTER (D9LR) R243 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D9.[1:0]: Channel 9 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 10 DATA HIGH REGISTER (D10HR) R244 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D10.[9:2]: Channel 10 9:2 bit Data CHANNEL 10 DATA LOW REGISTER (D10LR) R245 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D10.[1:0]: Channel 10 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 11 DATA HIGH REGISTER (D11HR) R246 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D11.[9:2]: Channel 11 9:2 bit Data CHANNEL 11 DATA LOW REGISTER (D11LR) R247 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D11.[1:0]: Channel 11 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. D 8 . 1 D 8 . 0 000000 D 9 . 1 D 9 . 0 000000 D10.1 D10.0 0 0 0 0 0 0 D11.1 D11.0 0 0 0 0 0 0

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CHANNEL 12 DATA HIGH REGISTER (D12HR) R248 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D12.[9:2]: Channel 12 9:2 bit Data CHANNEL 12 DATA LOW REGISTER (D12LR) R249 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:6 = D12.[1:0]: Channel 12 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 13 DATA HIGH REGISTER (D13HR) R250 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D13.[9:2]: Channel 13 9:2 bit Data CHANNEL 13 DATA LOW REGISTER (D13LR) R251 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D13.[1:0]: Channel 13 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 14 DATA HIGH REGISTER (D14HR) R252 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D14.[9:2]: Channel 14 9:2 bit Data CHANNEL 14 DATA LOW REGISTER (D14LR) R253 - Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D14.[1:0]: Channel 14 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL 15 DATA HIGH REGISTER (D15HR) R254 - Read/Write Register Page: 62 Reset Value: undefined Bits 7:0 = D15.[9:2]: Channel 15 9:2 bit Data CHANNEL 15 DATA LOW REGISTER (D15LR) R255- Read/Write Register Page: 62 Reset Value: xx00 0000 Bits 7:0 = D15.[1:0]: Channel 15 1:0 bit Data Bits 5:0 = Reserved, forced by hardware to 0. Note: If only 8-bit accuracy is required, each Data High Register can be used to get the conversion result, ignoring the corresponding DxLR register content. D12.1 D12.0 0 0 0 0 0 0 D13.1 D13.0 0 0 0 0 0 0 D14.1 D14.0 0 0 0 0 0 0 D15.1 D15.0 0 0 0 0 0 0

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) COMPARE RESULT REGISTER (CRR) R243 - Read/Write Register Page: 63 Reset Value: 0000 xxxx (0xh) Two adjacent channels (identified as A and B) can be selected through CLR1 register programming (bits CC[3:0]); a level window for the converted an- alog input can be defined on these channels. Bits 7 = CBU: Compare Register Ch. B Upper Threshold Set when converted data on channel B is greater than the threshold value set in UTBHR/UTBLR registers. Bits 6 = CAU: Compare Register Ch. A Upper Threshold Set when converted data on channel A is greater than the threshold value set in UTAHR/UTALR registers. Bits 5 = CBL: Compare Register Ch. B Lower Threshold Set when converted data on channel B is less than the threshold value set in LTBHR/LTBLR regis- ters. Bits 4 = CAL: Compare Register Ch. A Lower Threshold Set when converted data on channel A is less than the threshold value set in LTAHR/LTALR regis- ters. Bits 3:0 = Don’t care LOWER THRESHOLD REGISTERS (LTiHR/ LTiLR) The two pairs of Lower Threshold High/Low regis- ters are used to store the user programmable low- er threshold 10-bit values, to be compared with the current conversion results, thus setting the lower window limit. CHANNEL A LOWER THRESHOLD HIGH REGISTER (LTAHR) R244 - Read Register Page: 63 Reset Value: undefined Bits 7:0 = LTA.[9:2]: Channel A [9:2] bit Lower Threshold CHANNEL A LOWER THRESHOLD LOW REGISTER (LTALR) R245 - Read/Write Register Page: 63 Reset Value: xx00 0000 Bits 7:6 = LTA.[1:0]: Channel A [1:0] bit Lower Threshold Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL B LOWER THRESHOLD HIGH REG- ISTER (LTBHR) R246 - Read/Write Register Page: 63 Reset Value: undefined Bits 7:0 = LTB.[9:2]: Channel B [9:2] bit Lower Threshold CBU CAU CBL CAL x x x x L T A . 1 L T A . 0 000000

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CHANNEL B LOWER THRESHOLD LOW REGISTER (LTBLR) R247 - Read/Write Register Page: 63 Reset Value: xx00 0000 Bits 7:6 = LTB.[1:0]: Channel B [1:0] bit Lower Threshold Bits 5:0 = Reserved, forced by hardware to 0. UPPER THRESHOLD REGISTERS (UTiHR/ UTiLR) The two pairs of Upper Threshold High/Low Reg- isters are used to store the user programmable up- per threshold 10-bit values, to be compared with the current conversion results, thus setting the up- per window limit. CHANNEL A UPPER THRESHOLD HIGH REG- ISTER (UTAR) R248 - Read/Write Register Page: 63 Reset Value: undefined Bits 7:0 = UTA.[9:2]: Channel 6 [9:2] bit Upper Threshold value CHANNEL A UPPER THRESHOLD LOW REGISTER (UTALR) R249 - Read/Write Register Page: 63 Reset Value: xx00 0000 Bits 7:6 = UTA.[1:0]: Channel A [1:0] bit Upper Threshold Bits 5:0 = Reserved, forced by hardware to 0. CHANNEL B UPPER THRESHOLD HIGH REG- ISTER (UTBHR) R250 - Read/Write Register Page: 63 Reset Value: undefined Bits 7:0 = UTB.[9:2]: Channel B [9:2] bit Upper Threshold CHANNEL B UPPER THRESHOLD LOW REGISTER (UTBLR) R251 - Read/Write Register Page: 63 Reset Value: xx00 0000 Bits 7:6 = UTB.[1:0]: Channel B [1:0] bit Lower Threshold Bits 5:0 = Reserved, forced by hardware to 0. L T B . 1 L T B . 0 000000 U T A . 1 U T A . 0 000000 U T B . 1 U T B . 0 000000

conversion is re-started from the SC[3:0] channel. Table 68. Compare Channels definition Table 69. Prescaler programming

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) Bit 4 = EXTG: External Trigger Enable. This bit is set and cleared by software. 0: External trigger disabled. 1: External trigger enabled. Allows a conversion sequence to be started on the subsequent edge of the external signal applied to the EXTRG pin (when enabled as an Alternate Function). Bit 3 = INTG: Internal Trigger Enable. This bit is set and cleared by software. 0: Internal trigger disabled. 1: Internal trigger enabled. Allows a conversion se- quence to be started, synchronized by an inter- nal signal (On-chip Event signal) from a Multi- function Timer peripheral. Both External and Internal Trigger inputs are inter- nally ORed, thus avoiding Hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. Note: The effect of either synchronization mode is to set the START/STOP bit, which is reset by hard- ware when in SINGLE mode, at the end of each sequence of conversions. Requirements: The External Synchronisation In- put must receive a low level pulse wider than an INTCLK period and, for both External and On-Chip Event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. Bit 2 = POW: Power Up/Power Down. This bit is set and cleared by software. 0: Power down mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: Power up mode: the ADC converter logic and analog circuitry is enabled. Bit 1 = CONT: Continuous/Single. 0: Single Mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the ST bit is set by soft- ware. 1: Continuous Mode: the first sequence of conver- sions is started, either by software (by setting the ST bit), or by hardware (on an internal or ex- ternal trigger, depending on the setting of the INTG and EXTG bits); a continuous conversion sequence is then initiated. Bit 0 = ST: Start/Stop. 0: Stop conversion. When the ADC converter is running in Single Mode, this bit is hardware re- set at the end of a sequence of conversions. 1: Start a sequence of conversions. Note: If a write access to this register occurs, the conversion is re-started from the SC[3:0] channel. INTERRUPT CONTROL REGISTER (AD_ICR) The Interrupt Control Register contains the three priority level bits, the two source flags, and their bit mask: INTERRUPT CONTROL REGISTER (AD_ICR) R254 - Read/Write Register Page: 63 Reset Value: 0000 0111 (07h) Bit 7 = ECV: End of Conversion. This bit is automatically set by hardware after a group of conversions is completed. It must be re- set by the user, before returning from the Interrupt Service Routine. Setting this bit by software will cause a software interrupt request to be generat- ed. 0: No End of Conversion event occurred 1: An End of Conversion event occurred Bit 6 = AWD: Analog Watchdog. This is automatically set by hardware whenever ei- ther of the two monitored analog inputs exceeds a threshold. The threshold values are stored in reg- isters R244/R245 and R248/R249 for channel A, and in registers R246/R247 and R250/R251 for channel B respectively. The Compare Result Reg- ister (CRR) keeps track of the analog inputs ex- ceeding the thresholds. The AWD bit must be reset by the user, before re- turning from the Interrupt Service Routine. Setting this bit by software will ca use a software interrupt request to be generated. 0: No Analog Watchdog event occurred 1: An Analog Watchdog event occurred ECV AWD ECI AWDI X PL2 PL1 PL0

10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) Bit 5 = ECI: End of Conversion Interrupt Enable. This bit masks the End of Conversion interrupt re- quest. 0: Mask End of Conversion interrupts 1: Enable End of Conversion interrupts Bit 4 = AWDI: Analog Watchdog Interrupt Enable. This bit masks or enables the Analog Watchdog interrupt request. 0: Mask Analog Watchdog interrupts 1: Enable Analog Watchdog interrupts Bit 3 = Reserved. Bits 2:0 = PL[2:0]: ADC Interrupt Priority Level. These three bits are used to select the Interrupt priority level for the ADC. INTERRUPT VECTOR REGISTER (AD_IVR) R255 - Read/Write Register Page: 63 Reset Value: xxxx xx10 (x2h) Bits 7:2 = V[7:2]: ADC Interrupt Vector. This vector should be programmed by the user to point to the first memory location in the Interrupt Vector table containing the starting addresses of the ADC interrupt service routines. Bit 1 = W1: Word Select. This bit is set and cleared by hardware, according to the ADC interrupt source. 0: Interrupt source is the Analog Watchdog, point- ing to the lower word of the ADC interrupt serv- ice block (defined by V[7:2]). 1:Interrupt source is the End of Conversion inter- rupt, thus pointing to the upper word. Note: When two requests occur simultaneously, the Analog Watchdog Request has priority over the End of Conversion request, which is held pending. Bit 0 = Reserved, forced by hardware to 0. V7 V6 V5 V4 V3 V2 W1 0

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS

11 ELECTRICAL CHARACTERISTICS

This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V IN and VO be higher than V SS and lower than V DD. Reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (V DD or VSS). Power Considerations . The average chip-junc- tion temperature, T J, in Celsius can be obtained from: TJ =T A + PD x RthJA Where: T A = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD = P INT + PPORT. PINT =I DD x VDD (chip internal power). PPORT =Port power dissipation (determined by the user) ABSOLUTE MAXIMUM RATINGS Notes: Stresses above those listed as “absolute maximum ratings“ may cause permanent damage to the device. This is a stress rating onl y and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to VSS = 0 V. Note 1: Pin injection current occurs when the voltage on any pin exceeds the specified range. Note 2: Value guaranteed by design. THERMAL CHARACTERISTICS Symbol Parameter Value Unit VDD Supply Voltage – 0.3 to 6.5 V AVDD ADC Reference Voltage V SS to VDD + 0.3 V AVSS ADC Ground V SS VIN Input Voltage (all pins except pure open drain I/O pins) – 0.3 to V DD + 0.3 V VINOD Input Voltage (pure open drain I/O pins) – 0.3 to 6.5 V VAIN Analog Input Voltage (ADC inputs) -0.3 to AV DD + 0.3 V TSTG Storage Temperature – 55 to +150 °C ⎥IIO⎥ Load Current 10 (2) mA ⎥IINJ⎥ Pin Injection Current - Digital and Analog Inputs (1) 10 (2) mA ⎥ITINJ⎥ Absolute sum of all Pin Injection Current in the device 100 (2) mA Symbol Package Value Unit RthJA LQFP64 PQFP100 LQFP100 °C/W

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS Note: (1) > 1MHz when ADC or JBLPD is used, 2.6MHz when I²C is used Symbol Parameter Min Max Unit TA Ambient temperature range

6 Suffix Version -40 85

°CB Suffix Version -40 105 C Suffix Version -40 125 VDD Operating Supply Voltage 4.5 5.5 V AVDD ADC Reference Voltage 0 V DD + 0.2 V fINTCLK Internal Clock Frequency 0 (1) 24 MHz C33 Stabilization capacitor between V REG and VSS 300 nF

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS (VDD = 5 V ± 10%, TA = –40° C to +125° C, unless otherwise specified) Symbol Parameter Comment Value UnitMin Typ (1) Max VIH Input High Level TTL 2.0 (2) V CMOS 0.7 x V DD (2) V Input High Level Standard Schmitt Trigger 0.6 x VDD (2) V Input High Level High Hyst. Schmitt Trigger P4[7:6]-P6[5:4] 0.7 x VDD (2) V VIL Input Low Level P4.2-P4.5-P5.3 TTL 0.8 (2) V CMOS 0.3 x V DD (2) V Input Low Level Standard Schmitt Trigger 0.2 x VDD (2) V Input Low Level High Hyst.Schmitt Trigger P4[7:6]-P6[5:4] 0.25 x VDD (2) V VI Input Voltage Range Pure Open Drain P2[3:2]-P4[7:6] -0.3 6.0 V Input Voltage Range All other pins -0.3 V DD + 0.3 V VHYS Input Hysteresis Standard Schmitt Trigger 250 mV Input Hysteresis High Hyst. Schmitt Trigger P4[7:6]-P6[5:4] VOH Output High Level P6[5:4] Push Pull mode IOH= – 8mA EMR1.BSZ bit = 1 (3) VDD – 0.8 V Output High Level P5[7:0]-P6[3:0]- AS-DS-RW Push Pull mode I OH= – 2mA VDD – 0.8 V

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS Note: (1) Unless otherwise stated, typical data are based on T A= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production. (2) Value guaranteed by characterisation. (3) For a description of the EMR1 Register - BSZ bit refer to the External Memory Interface Chapter. (4) Value guaranteed by Design. (5) Not tested in production, guaranteed by product characterisation. An overload condition occurs when the input voltage on an y pin ex- ceeds the specified voltage range. (6) Indicative values extracted from design simulation, 20% to 80% on 50pF load, EMR1.BSZ bit =0. VOL Output Low Level P4[7:6]-P6[5:4] Push Pull or Open Drain mode, I OL=8mA, EMR1.BSZ bit = 1 (3) 0.4 V Output Low Level All pins except OSCOUT Push Pull or Open Drain mode, IOL=2mA 0.4 V IWPU Weak Pull-up Current Bidirectional Weak Pull-up mode V IN = 0V 50 100 300 µA Weak Pull-up Current P6[5:4]-AS-DS-RW Bidirectional Weak Pull-up mode V IN = 0V 100 220 450 µA ILKIO I/O Pin Input Leakage Input or Tri-State mode, 0V < VIN < VDD – 1 1 µA ILKIOD I/O Pin Open Drain Input Leakage Input or Tri-State mode, 0V < VIN < VDD – 1 1 µA |ILKADC| ADC Conv.Input leakage current on ro- bust pins VIN<VSS, | IIN |< 400µA on robust analog pin 6 µA ADC Conv.Input leakage current V SS≤VIN≤VDD 1 µA IIO Load current P4[7:6]-P6[5:4] EMR1.BSZ bit = 1 (3) 8(4) mAP4[7:6]-P6[5:4] EMR1.BSZ bit = 0 (3) 2 (4) All other pins except OSCOUT 2 (4) ⎥IOV⎥ Overload Current (5) 5 (4) mA SRR Slew Rate Rise (6) 20 30 ns SRF Slew Rate Fall (6) 20 30 ns Symbol Parameter Comment Value UnitMin Typ (1) Max

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS (VDD = 5 V ± 10%, TA = –40° C to +125° C for Max values and 25°C for Typ values, unless otherwise specified) Note: All I/O Ports are configured in bidirectional weak pull-up mode with no DC load, unless otherwise specified, external clock is driven by a square wave. (1) Unless otherwise stated, typical data are based on VDD= 5V. They are only reported for design guide lines not tested in production. (2) Current consumption to be added to IDDRUN when the FLASH memory is accessed. (3) Value guaranteed by product characterization, not tested in production. (4) Current consumption to be added to IDDLPWFI when the FLASH memory is in stand-by mode. (5) The I/Os draw a transient current from V DD when an input takes a voltage level in between V SS and VDD. This current is 0 for VIN<0.3V or VIN>VDD-0.3V, it typically reaches its maximum value when VIN is approximatively at VDD/2. Symbol Parameter Conditions INTCLK Typ (1) Max Unit IDDRUN Run Mode Current CPU running with code execution from RAM memory, all peripherals in reset state, clock input (OSCIN) driven by external square wave. f INTCLK in [MHz].

24 MHz 45 60 mA

2.5 + 1.8xfINTCLK/MHz mA ∆IDD1 FLASH/E3 TM Supply Current (Read) (2) -2 m A ∆IDD2 FLASH/E3 TM Supply Current (Write/Erase) (2) -1 2 m A Typical application Run Mode Current CPU running with code execution from FLASH memory, all peripher- als running in a typical configura- tion, clock input (OSCIN) driven by a 4-MHz crystal = I DDRUN + ∆IDD1 + IDD Peripherals (Timers, CAN, etc)

24 MHz 50 mA

24 MHz 14 22 mA

f INTCLK in [MHz]. any frequency 0.9xfINTCLK/MHz(3) mA ∆IDD3 FLASH/E3 TM Supply Current (Stand-by) (4) -2 0 µA IDDLPR Main Voltage Regu- lator Power Consumption -3 0 0 µA I DDOSC Crystal Oscillator Power Consump- tion 200 µA I DDLPWFI Low Power WFI Mode Current FLASH/E3 TM in Stand-by Mode, Main Voltage Regulator ON, IDDL- PR + IDDOSC + IDD (Standard Timer in real time clock mode) 4MHz / 32 550 1000 µA IDDRTC RTC Mode Current FLASH/E3 TM in Power-Down Mode, Main Voltage Regulator OFF, Standard Timer in Real Time Clock mode 4MHz / 32 250 µA I DDHALT HALT Mode Cur- rent(3) -5 2 5 µA IDDSTOP STOP Mode Cur- rent (3) All I/O ports are configured in out- put push-pull mode with no DC load see Figure 159 (3) µA IDDTR Input Transient IDD Current (5) -3 0 0 µA

Figure 159. Stop Mode Current

formed, leading to the worst case. Figure 160. Evolution of Worst Case E3 Page Update Time

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. Functional EMS (Electro Magnetic Susceptibil- ity) Based on a simple application running on the product, the product is stressed by two electro magnetic events until a failure occurs. ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4- 4 standard. A device reset allows normal operations to be re- sumed. Designing hardened software to avoid noise problems EMC characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the manage- ment of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the RE- SET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be ap- plied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be improved to pre- vent unrecoverable errors occurring (see applica- tion note AN1015). Electro Magnetic Interference (EMI) Based on a simple application running on the product, the product is monitored in terms of emis- sion. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Notes: 1. Data based on characterization results, not tested in production. Symbol Parameter Conditions Level Unit VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=4MHz conforms to IEC 1000-4-2 >1.5 kV VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a func- tional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-4 >1.5 kV Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] Unit 4/10MHz SEMI Peak level VDD=5V, TA=+25°C, PQFP100 14x20 package conforming to SAE J 1752/3 0.1MHz to 30MHz 13 dBµV30MHz to 130MHz 25 130MHz to 1GHz 24 SAE EMI Level 3.5 -

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EMC CHARACTERISTICS (Cont’d) Absolute Maximum Rati ngs (Electrical Sensi- tivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181. Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test con- forms to the JESD22-A114A/A115A standard. Absolute Maximum Ratings Notes: 1. Data based on characterization results, not tested in production. Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. ■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1 000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standar d. B Class strictly covers all the JEDEC criteria (international standard). Symbol Ratings Conditions Maximum value 1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA=+25°C 2000 V VESD(MM) Electro-static discharge voltage (Machine Model) TA=+25°C 200 Symbol Parameter Conditions Class 1) LU Static latch-up class TA=+25°C TA=+85°C TA=+125°C A A A DLU Dynamic latch-up class V DD=5.5V, fOSC=4MHz, TA=+25°C A

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EXTERNAL INTERRUPT TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. The value in the right hand two columns shows the timing minimum and maximum for an internal clock at 24MHz (INTCLK). Measurement points are VIH for positive pulses and VIL for negative pulses. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 7is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. EXTERNAL INTERRUPT TIMING WAKE-UP MANAGEMENT TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. The value in the right hand two columns show the timing minimum and maximum for an internal clock at 24MHz (INTCLK). The given data are related to Wake-up Management Unit used in External Interrupt mode. Measurement points are V IH for positive pulses and VIL for negative pulses. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. WAKE-UP MANAGEMENT TIMING N° Symbol Parameter Value UnitFormula Min

1 TwINTLR Low Level Minimum Pu lse Width in Rising Edge Mode ≥Tck+10 50 ns

2 TwINTHR High Level Minimum Pu lse Width in Rising Edge Mode ≥Tck+10 50 ns

3 TwINTHF High Level Minimum Pulse Width in Falling Edge Mode ≥Tck+10 50 ns

4 TwINTLF Low Level Minimum Puls e Width in Falling Edge Mode ≥Tck+10 50 ns

N° Symbol Parameter Value UnitFormula Min

1 TwWKPLR Low Level Minimum Pulse Width in Rising Edge Mode ≥Tck+10 50 ns

2 TwWKPHR High Level Minimum Pulse Width in Rising Edge Mode ≥Tck+10 50 ns

3 TwWKPHF High Level Minimum Pulse Width in Falling Edge Mode ≥Tck+10 50 ns

4 TwWKPLF Low Level Minimum Pulse Width in Falling Edge Mode ≥Tck+10 50 ns

Rising Edge Detection Falling Edge Detection INTn n = 0-7 n = 0-15 Rising Edge Detection Falling Edge Detection WKUPn

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS RCCU CHARACTERISTICS (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: (1) Unless otherwise stated, typical data are based on T A= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production. (2) Value guaranteed by design. RCCU TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, fINTCLK = 24 MHz, unless otherwise specified) Note: (1) Unless otherwise stated, typical data are based on T A= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production. (2) To be valid, a RESET pulse must exceed tNFR. All reset glitches with a duration shorter than tFRS will be filtered (3) Depending on the delay between rising edge of RESET pin and the first rising edge of CLOCK1, the value can differ from the typical value for +/- 1 CLOCK1 cycle. Legend: Tosc = Crystal Oscilllator Clock (CLOCK1) period. BOOTROM TIMING TABLE Note: (1) Unless otherwise stated, typical data are based on T A= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production (2) Refer to AN1528 for more details on BOOTROM code. Symbol Parameter Comment Value UnitMin Typ (1) Max VIHRS RESET Input High Level Input Threshold 0.75 x V DD V VILRS RESET Input Low Level Input Threshold 0.25 x V DD V VIRS Input Voltage Range – 0.3 V DD + 0.3 V VHYRS RESET Input Hysteresis 1 (2) V ILKRS RESET Pin Input Leakage 0V < V IN < VDD – 1 1 µA Symbol Parameter Comment Value UnitMin Typ (1) Max tFRS RESET Input Filtered Pulse(2) 50 ns tNFR RESET Input Non Filtered Pulse(2) 20 µs tRSPH (3) RESET Phase duration 20400 T osc tSTR STOP Restart duration DIV2 = 0 DIV2 = 1 10200

20400 Tosc

Symbol Parameter Conditions Typ Value (1) Unit tBRE BOOTROM Execution Duration (see Figure 65 on page 137) (2) fOSC = 4MHz 33 ms

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS PLL CHARACTERISTICS (VDD = 5 V ± 10%, TA = –40° C to +125° C, fINTCLK = 24 MHz, unless otherwise specified) Note: (1) Unless otherwise stated, typical data are based on T A= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production. (2) Value guaranteed by design. Legend: Tosc = Crystal Oscilllator Clock (CLOCK1) period. Symbol Parameter Value UnitMin Typ (1) Max FXTL Crystal Reference Frequency 3 5 MHz FVCO VCO Operating Frequency 6 24 MHz TPLK Lock-in Time 350 (2) 1000 (2) Tosc PLL Jitter 0 1200 (2) ps PLL Jitter Impact on applicative 500kHz signal (CAN, SCI, TIMERS) 0.2 (2) % FPLLFREE PLL free running mode Frequency 10 (2) 50 250 (2) kHz

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS OSCILLATOR CHARACTERISTICS (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: (1) Unless otherwise stated, typical data are based on T A= 25° C and VDD= 5V. They are only reported for design guide lines not tested in production. (2) Value guaranteed by design. Symbol Parameter Comment Value UnitMin Typ (1) Max fOSC Crystal Frequency Fundamental mode crystal or ex- ternal clock applied to OSCOUT 35 M H z gm Oscillator Transconductance 1.2 (2) 1.5 (2) mA/V VIHCK Clock Input High Level External Clock 2 (2) VDD + 0.3 V VILCK Clock Input Low Level External Clock -0.3 0.4 (2) V TSTUP Oscillator Start-up Time 5 (2) ms ILOAD 100 µA RPOL 90 128 180 k Ω VOSC Oscillation Level 600 (2) mV

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING TABLE (MC=1) (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 0 to 50pF Notes: The expressions in the “Formula” column show how to calculate the typical parameter value depending on the CPU clock period and the number of inserted wait cycles. The values in the Min column give the parameter values for a CPU clock at 12MHz and two wait states for T1 and T2. For certain versions of the ST92F150, the external bus has high-drive capabilities. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; = 2*OSCIN period when OSCIN is divided by 2; = OSCIN period / PLL factor when the PLL is enabled TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width) TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width) P = clock prescaling value (=PRS; division factor = 1+P) Wa = wait cycles on ALE; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT) Wd = wait cycles on OEN and WEN ; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT) N° Symbol Parameter Value (see note) UnitFormula Min Max

1 TsA (ALE) Address Set-up Time before ALE ↓ Tck*Wa+TckH - 48 160 ns

2 ThALE (A) Address Hold Time after ALE ↓ TckL - 31 10 ns

3 TwALE ALE High Pulse Width Tck*Wa+TckH - 58 150 ns

4 TdAz (OEN) Address Float (P0) to OEN

↓ 00 n s

5 TdOEN(Az) P0 driven after OEN ↑ TckL - 13 29 ns

6T w O E N O E N Low Pulse Width Tck*Wd+TckH - 36 172 ns 7T w W E N W E N Low Pulse Width Tck*Wd+TckH - 36 172 ns

8 TdOEN (DR) OEN ↓ to Data Valid Delay Tck*Wd+TckH - 44 164 ns

9 ThDR (OEN) Data hold time after OEN ↑ 00 n s

10 ThOEN(A) Address (A21:A8) hold time after OEN ↑ 00 n s

11 ThWEN(A) Address (A21:A8) hold time after WEN ↑ 00 n s

12 TvA(OEN) Address (A21:A0) valid to OEN ↑ Tck (Wd+Wa+1.5) - 76 382 ns 13 TvA(WEN) Address (A21:A0) valid to WEN ↑ Tck (Wd+Wa+1.5) - 44 414 ns

14 TsD (WEN) Data Set-up time before WEN ↑ Tck*Wd+TckH - 158 50 ns

15 ThWEN(DW) Data Hold Time after WEN ↑ TckL - 37 5 ns

16 TdALE (WEN) ALE ↑ to WEN ↑ Delay Tck (Wd+Wa+1.5) - 54 404 ns 17 TdALE (OEN) ALE ↑ to OEN ↑ Delay Tck (Wd+Wa+1.5) - 50 408 ns

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING A21 - A8 Note : OEN stays high for the whole write cycle and WEN stays high for the whole read cycle. 14 15 CPUCLK PORT9/1 PORT0 PORT0 ALE OEN (READ) WEN (WRITE) (WRITE) A7-A0 D7-D0 INA7-A0(READ) D7-D0 OUT

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS WATCHDOG TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, Push-pull output configuration, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and maximum prescaler value and minimum and maximum counter value. Measurement points are V OH or VIH for positive pulses and VOL or VIL for negative pulses. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. Psc = Watchdog Prescaler Register content (WDTPR): from 0 to 255 Cnt = Watchdog Couter Registers content (WDTRH,WDTRL): from 0 to 65535 TWDIN = Watchdog Input signal period (WDIN), TWDIN ≥ 8 x Tck WATCHDOG TIMING N° Symbol Parameter Value UnitFormula Min Max

1 TwWDOL WDOUT Low Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167

2.8 ns s (Psc+1) x (Cnt+1) x TWDIN 333 ns

2 TwWDOH WDOUT High Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167

2.8 ns s (Psc+1) x (Cnt+1) x TWDIN 333 ns

3 TwWDIL WDIN High Pulse Width ≥ 4 x Tck 167 ns

4 TwWDIH WDIN Low Pulse Width ≥ 4 x Tck 167 ns

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS STANDARD TIMER TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, Push-pull output configuration, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and maximum prescaler value and minimum and maximum counter value. Measurement points are V OH or VIH for positive pulses and VOL or VIL for negative pulses. (1) On this product STIN is not available as Alternate Function but it is internally connected to a precise clock source directly derived from the crystal oscillator. Refer to RCCU chapter for details about clock distribution. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. Psc = Standard Timer Prescaler Register content (STP): from 0 to 255 Cnt = Standard Timer Counter Registers content (STH,STL): from 0 to 65535 T STIN = Standard Timer Input signal period (STIN) , TSTIN ≥ 8 x Tck STANDARD TIMER TIMING N° Symbol Parameter Value UnitFormula Min Max

1 TwSTOL STOUT Low Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167

2.8 ns s (Psc+1) x (Cnt+1) x TSTIN (1) (1) ns

2 TwSTOH STOUT High Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167

2.8 ns s (Psc+1) x (Cnt+1) x TSTIN (1) (1) ns

3 TwSTIL STIN High Pulse Width ≥ 4 x Tck (1) (1) ns

4 TwSTIH STIN Low Pulse Width ≥ 4 x Tck (1) (1) ns

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS EXTENDED FUNCTION TIMER EXTERNAL TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, and minimu m prescaler factor (=2). Measurement points are V IH for positive pulses and VIL for negative pulses. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. Prsc = Precsaler factor defined by Extended Function Timer Clock Control bits (CC1,CC0) on control register CR2 (values: 2,4,8). EXTENDED FUNCTION TIMER EXTERNAL TIMING N° Symbol Parameter Value UnitFormula Min 1T w PEWL External Clock low pulse width (EXTCLK) ≥ 2 x Tck + 10 52 ns 2T w PEWH External Clock high pulse width (EXTCLK) ≥ 2 x Tck + 10 52 ns 3T w PIWL Input Capture low pulse width (ICAPx) ≥ 2 x Tck + 10 52 ns 4T w PIWH Input Capture high pulse width (ICAPx) ≥ 2 x Tck + 10 52 ns 5T w ECKD Distance between two active edges on EXTCLK ≥ 4 x Tck + 10 177 ns 6T w EICD Distance between two active edges on ICAPx ≥ 2 x Tck x Prsc +10 177 ns 1 2 EXTCLK ICAPA ICAPB

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS MULTIFUNCTION TIMER EXTERNAL TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz. (1) n = 1 if the input is rising OR falling edge sensitive n = 3 if the input is rising AND falling edge sensitive (2) In Autodiscrimination mode Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. MULTIFUNCTION TIMER EXTERNAL TIMING N° Symbol Parameter Value Unit NoteFormula Min Max 1T w CTW External clock/trigger pulse width n x Tck n x 42 - ns (1) 2T w CTD External clock/trigger pulse distance n x Tck n x 42 - ns (1) 3T w AED Distance between two active edges 3 x Tck 125 - ns 4T w GW Gate pulse width 6 x Tck 250 - ns 5T w LBA Distance between TINB pulse edge and the fol- lowing TINA pulse edge Tck 42 - ns (2) 6T w LAB Distance between TINA pulse edge and the fol- lowing TINB pulse edge 0- n s (2) 7T w AD Distance between two TxINA pulses 0 - ns (2) 8T w OWD Minimum output pulse width/distance 3 x Tck 125 - ns

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS SCI-M TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. Note 1: Values guaranteed by product characterization, not tested in production. SCI TIMING N° Symbol Parameter Condition Value (1) UnitMin Max FRxCKIN Frequency of RxCKIN 1x mode f INTCLK / 8 MHz 16x mode f INTCLK / 4 MHz TwRxCKIN RxCKIN shortest pulse 1x mode 4 x Tck s 16x mode 2 x Tck s FTxCKIN Frequency of TxCKIN 1x mode f INTCLK / 8 MHz 16x mode f INTCLK / 4 MHz TwTxCKIN TxCKIN shortest pulse 1x mode 4 x Tck s 16x mode 2 x Tck s 1T s DS DS (Data Stable) before rising edge of RxCKIN 1x mode reception with RxCKIN Tck / 2 ns 2T d D1 TxCKIN to Data out delay Time 1x mode transmission with external clock CLoad < 50pF 2.5 x Tck ns 3T d D2 CLKOUT to Data out delay Time 1x mode transmission with CLKOUT 350 ns

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS SPI TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: Measurement points are VOL, VOH, VIL and VIH in the SPI Timing Diagram. (1) Values guaranteed by design. Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. N° Symbol Parameter Condition Value (1) Unit Min Max fSPI SPI frequency Master Slave fINTCLK / 128 fINTCLK / 4 fINTCLK / 2 MHz 1t SPI SPI clock period Master Slave 4 x Tck 2 x Tck ns 2t Lead Enable lead time Slave 40 ns 3t Lag Enable lag time Slave 40 ns 4t SPI_H Clock (SCK) high time Master Slave 90 ns 5t SPI_L Clock (SCK) low time Master Slave 90 ns 6t SU Data set-up time Master Slave 40 ns 7t H Data hold time (inputs) Master Slave 40 ns 8t A Access time (time to data active from high impedance state) Slave 0 120 ns 9t Dis Disable time (hold time to high im- pedance state) 240 ns 10 t V Data valid Master (before capture edge) Slave (after enable edge) Tck / 4 120 ns ns 11 t Hold Data hold time (outputs) Master (before capture edge) Slave (after enable edge) Tck / 4 ns ns 12 t Rise Rise time (20% VDD to 70% VDD, CL = 200pF) Outputs: SCK,MOSI,MISO Inputs: SCK,MOSI,MISO,SS 100 100 ns µs 13 t Fall Fall time (70% VDD to 20% VDD, CL = 200pF) Outputs: SCK,MOSI,MISO Inputs: SCK,MOSI,MISO,SS 100 100 ns µs

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS SPI Master Timing Diagram CPHA=0, CPOL=0 SPI Master Timing Diagram CPHA=0, CPOL=1 SPI Master Timing Diagram CPHA=1, CPOL=0 SPI Master Timing Diagram CPHA=1, CPOL=1 6 7 10 11 1213 SS (INPUT) SCK (OUTPUT) MISO MOSI (INPUT) (OUTPUT) D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN VR000109 6 7 10 11 1213 SS (INPUT) SCK (OUTPUT) MISO MOSI (INPUT) (OUTPUT) VR000110 D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN 6 7 10 11 1213 SS (INPUT) SCK (OUTPUT) MISO MOSI (INPUT) (OUTPUT) VR000107 D7-IN D6-IN D0-IN D7-OUT D6-OUT D0-OUT 6 7 10 11 12 13 SS (INPUT) SCK (OUTPUT) MISO MOSI (INPUT) (OUTPUT) VR000108 D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS SPI Slave Timing Diagram CPHA=0, CPOL=0 SPI Slave Timing Diagram CPHA=0, CPOL=1 SPI Slave Timing Diagram CPHA=1, CPOL=0 SPI Slave Timing Diagram CPHA=1, CPOL=1 6 7 10 11 1213 SS (INPUT) SCK MISO MOSI (INPUT) (OUTPUT) (INPUT) 8 9 HIGH-Z VR000113 D7-IN D6-IN D0-IN D7-OUT D6-OUT D0-OUT 6 7 10 11 12 13 SS (INPUT) SCK MISO MOSI (INPUT) (OUTPUT) 5 4 (INPUT) 8 9 HIGH-Z VR000114 D7-IN D6-IN D0-IN D7-OUT D6-OUT D0-OUT 6 7 10 11 1213 SS (INPUT) SCK MISO MOSI (INPUT) (OUTPUT) (INPUT) 2 3 8 9 HIGH-Z VR000111 D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN 6 7 10 11 12 13 SS (INPUT) SCK MISO MOSI (INPUT) (OUTPUT) 5 4 (INPUT) 2 3 8 9 HIGH-Z D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN VR000112

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS I2C/DDC-BUS TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: (1) Value guaranteed by design. (2) The ST9 device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the fall- ing edge of SCL (3) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal Legend: Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2; 2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2; Crystal Oscillator Clock period x PLL factor when the PLL is enabled. Cb = total capacitance of one bus line in pF FREQ[2:0] = Frequency bits value of I 2C Own Address Register 2 (I2COAR2) I2C TIMING Symbol Parameter Formula Protocol Specifications UnitStandard I2C Fast I 2C Min Max Min Max fINTCLK Internal Frequency (Slave Mode) 2.5 2.5 MHz fSCL SCL clock frequency 0 100 0 400 kHz TBUF Bus free time between a STOP and START condition 4.7 1.3 µs THIGH SCL clock high period 4.0 0.6 µs TLOW SCL clock low period Standard Mode Fast Mode 4.7 1.3 µs THD:STA Hold time START condition. After this period, the first clock pulse is generated TLOW + Tck 4.0 0.6 µs TSU:STA Set-up time for a repeated START condi- tion TLOW + THIGH – THD:STA 4.7 0.6 µs THD:DAT Data hold time FREQ[2:0] = 000 FREQ[2:0] = 001 FREQ[2:0] = 010 FREQ[2:0] = 011 3 x Tck 4 x Tck 4 x Tck 10 x Tck TSU:DAT Data set-up time (Without SCL stretching) TLOW – THD:DAT 250(1) 100 (1) nsData set-up time (With SCL stretch- ing) FREQ[2:0] = 000 FREQ[2:0] = 001 FREQ[2:0] = 010 FREQ[2:0] = 011 7 x Tck 15 x Tck 15 x Tck 31 x Tck T R Rise time of both SDA and SCL signals 1000 (1) 20+0.1Cb (1) ns TF Fall time of both SDA and SCL signals 300 (1) 20+0.1Cb (1) ns TSU:STO Set-up time for STOP condition TLOW + THIGH – THD:STA 4.0(1) 0.6 (1) ns Cb Capacitive load for each bus line 400 400 pF t BUF t LOW P S t HD:STA t HD:DAT t R t HIGH t F t SU:DAT t SU:STA Sr t HD:STA t SP t SU:STO P SDA SCL

required I2C SCL line frequency. Table 70. SCL Frequency Table The above variations depend on the accuracy of the external components used.

ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS J1850 BYTE LEVEL PROTOCOL DECODER TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +125°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: (1) Values obtained with internal frequency at 24 MHz (INTCLK), with CLKSEL Register set to 23. (2) In Transmission Mode, symbol durations are compliant to nominal values defined by the J1850 Protocol Specifications. (3) All values are reported with a precision of ±1 µs. J1850 PROTOCOL TIMING Symbol Parameter Value Unit NoteReceive Mode Transmission Mode Min Max Nominal TF Symbols Filtered 0 ≤ 7- µs (1)(2) TIB Invalid Bit Detected > 7 ≤ 34 - µs (1)(2) TP0 Passive Data Bit “0” > 34 ≤ 96 64 µs (1)(2)(3) TA0 Active Data Bit “0” > 96 ≤ 163 128 µs (1)(2)(3) TP1 Passive Data Bit “1” > 96 ≤ 163 128 µs (1)(2)(3) TA1 Active Data Bit “1” > 34 ≤ 96 64 µs (1)(2)(3) TNBS Short Normalization Bit > 34 ≤ 96 64 µs (1)(2)(3) TNBL Long Normalization Bit > 96 ≤ 163 128 µs (1)(2)(3) TSOF Start Of Frame Symbol > 163 ≤ 239 200 µs (1)(2)(3) TEOD End Of Data Symbol > 163 ≤ 239 200 µs (1)(2)(3) TEOF End Of Frame Symbol > 239 - 280 µs (1)(2)(3) TBRK Break Symbol > 239 - 300 µs (1)(2)(3) TIDLE Idle Symbol > 280 - 300 µs (1)(2)(3) T NBST A1T P0 T EODT SOF VPWO T IDLE T EOF T EOD VPWO T IDLE T EOF SOF “0” SHORT “0” LONG “1” LONG “1” SHORT EOD NB SHORT EOF / IDLE SOF “0” SHORT “0” LONG “1” LONG “1” SHORT EOD NB LONG EOF / IDLE T A0 T P1 T A1T P0T SOF T A0 T P1 T NBL

Subject to general operating conditions for VDD, fOSC, and TA, unless otherwise specified. Figure 161. Typical Application with ADC

1. Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. These values are given only as design

guidelines and are not tested.

1. VAIN may exceed AVSS or AVDD. However the conversion result in these cases will be 0000h or FFC0h respectively.
2. Any external serial impedance will downgrade the ADC accuracy (especially for resistance greater than 10 kΩ). Data

based on characterization results, not tested in production.

1. Value guaranteed by design.

1. Typical data is based on TA=25°C, Vdd=5V
2. Monotonicity and No Missing Codes are guaranteed by design.
3. Refer to Figure 162. for the definition of these parameters.

Figure 162. ADC Accuracy Characteristics between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

12 GENERAL INFORMATION

12.1 ORDERING INFORMATION

Figure 163. Device Types

12.2 VERSION-SPECIFIC SALES CONDITIONS

appropriate product for his application.

Table 71. Supported part numbers

12.3 PACKAGE MECHANICAL DATA

Figure 164. 64-Pin Low Profile Quad Flat Package Figure 165. 100-Pin Low Profile Quad Flat Package

Figure 166. 100-Pin Plastic Quad Flat Package

12.4 DEVELOPMENT TOOLS

kernel software and gang programmers. Table 72. STMicroelectronics Development Tools Note 1: The I²C 1 and the general purpose I/Os P3.0, P6.6 and P6.7 cannot be emulated by this emulator. ations on the F4 and F5 Flash sectors are not emulated.

12.4.1 Socket and Emulator Adapter Information

ed list of sockets in Table 73. www.cabgmbh.com for LQFP64). Table 73. Suggested List of Socket Types

13 KNOWN LIMITATIONS

Table 74. List of limitations

13.1 FLASH ERASE SUSPEND LIMITATIONS

13.1.1 Description

1. Program all addresses to 0 on selected sectors

13.1.2 Workaround

tion and an erase error is still detected.

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.2 FLASH CORRUPTION WHEN EXITING STOP MODE

Under very specific conditions, the first read per- formed in flash memory by the core when exiting stop mode may be corrupted. Impact on application As this first read is an opcode, this corruption may lead to an unpredictable behavior of the applica- tion. Workaround In ST92F124/F150/F250 datasheet, there is a warning in the WUCTRL register description: “In order to avoid to execute register write instruc- tions after a correct STOP bit setting sequence and before entering the STOP mode, it is manda- tory to execute 3 NOP instructions after the STOP bit setting sequence.” The workaround is to replace these 3 NOPs by the following assembly code: RRx is an unused register in the register file. Implementation In a C language software, implement the following code. Declare a dummy variable in the register file (for example in RR0 16-bit register) And replace the actual STOP bit setting sequence (specified in datasheet): nop ldw RRx,0 #pragma register_file Dummy_16bit_data 0 volatile unsigned int Dummy_16bit_data; spp(WU_PG); WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; WU_CTLR = WUm_wuit | WUm_id1s; WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; asm("nop"); asm("nop"); asm("nop");

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) By: Compiled code (with –O2 optimization option) and hexa is: spp(WU_PG); WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; WU_CTLR = WUm_wuit | WUm_id1s; WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; asm(“nop”); Dummy_16bit_data = 0; C language Assembly Hexa Comment WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; ld @WU_CTLR, #7 F5 F9 07 WU_CTLR = WUm_wuit | WUm_id1s; ld @WU_CTLR, #3 F5 F9 03 WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop; ld @WU_CTLR, #7 F5 F9 07 The CORE executes the following NOP and prefetch the 2 following bytes (BF and 00) NOP nop FF Dummy_16bit_data = 0; ldw RR0,#0 BF 00 00 00 The two first bytes fetch in flash after wake up are 00 00 RR0 is always filled with

00 RR0 is not used in the

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.3 I2C LIMITATIONS

13.3.1 Start condition ignored in multimaster mode

In multimaster configurations, if the ST9 I2C re- ceives a START condition from another I2C master after the START bit is set in the I2CCR reg- ister and before the START condition is generated by the ST9 I2C, it may ignore the START condition from the other I2C master. In this case, the ST9 master will receive a NACK from the other device. Workaround On reception of the NACK, ST9 can send a re-start and Slave address to re-initiate communication.

13.3.2 Missing BUS error in master transmitter

BERR will not be set if an error is detected during the first or second pulse of each 9-bit transaction. Single Master Mode: If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfe r will continue however the BUSY flag will be reset. Multimaster Mode: Normally the BERR bit would be set whenever un- authorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first or second pulse of a 9-bit transaction. Workaround Single Master Mode: Slave devices should issue a NACK when they re- ceive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmission. Multimaster Mode: It is possible to work around the problem by polling the BUSY bit during I2C master mode transmis- sion. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. Limitations Description Mode Section 13.3.1 Start condition ignored Mustimaster mode Section 13.3.2 Missing bus error Master transmitter mode Section 13.3.3 AF bit (acknowledge failure flag) T ransmitter mode (Master and Slave) Section 13.3.4 BUSY bit Mustimaster mode Section 13.3.5 ARLO (arbitration lost) Multimaster mode Section 13.3.6 BUSY flag All

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.3.3 AF bit (acknowledge failure flag) in

transmitter mode (slave and master) The AF bit is cleared by reading the I2CSR2 reg- ister. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Workaround Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.

13.3.4 BUSY flag in multimaster mode

The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. Workaround Check that the I2C is not busy before enabling the I2C Multimaster cell.

13.3.5 ARLO (arbitration lost) flag in

In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Ac- knowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Workaround None

13.3.6 BUSY flag gets cleared when BUS error

BUSY bit gets cleared when the BUS error occurs but the bus is actually BUSY (SCL line shows CLK pulses). Contradictory, M/SL bit is unaffected on BUS error Workaround If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re- synchronize communication, get the transmission acknowledged and the bus released for further communication

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.4 SCI-A AND CAN INTERRUPTS

SCI-A interrupt (I0 channel) and CAN interrupts (channels E0, E1, F0, F1, G0, G1, H0, H1) do not respond when the CPUCLK is prescaled (MODER register). Workaround Avoid using CPU prescaler when SCI-A and/or CAN interrupts are used in the application.

13.5 SCI-A MUTE MODE

13.5.1 Mute Mode Description

The SCI can be put in Mute mode waiting for an Idle line detection or an Address Mark detection, and discarding all other byte transmissions. This is done by setting the RWU (Receiver wake-up) bit in the SCICR2 register (R244, page 26). This bit can be reset either by software, to leave the Mute mode, or by hardware when a wake up condition has been reached. A received data is indicated by the RDRF (Read Data Ready Flag) bit in the SCISR register (R240, page 26). This status bit is evaluated at the end of the stop bit. If the RWU bit is in the set state at the end of the stop bit, the data is not loaded in the data register and the RDRF bit is not set. On the contrary, if the RWU bit is in the reset state at the end of the stop bit the data is loaded in the data register and the RDRF bit is set.

13.5.2 Limitation Description

The SCICR2 also contains the following configura- tion bits: Interrupt Enable, Transmitter Enable, Re- ceiver Enable and Send Break. When the value of one of these bits is modified by software, the SCICR2 register is read, its value is modified and reloaded in the SCICR2 register. If the SCI-A is in Mute mode during the read opera- tion (RWU=1) and if an address mark event occurs (resetting the RWU bit) before the write operation, the RWU bit is set before the end of the stop bit. In this case, the RDRF bit is not set, the data is not received and no flag indicates the lost of the data. Figure 1. Mute Mode Mechanism on address mark Consequence The address byte is lost and the SCI-A is again in Mute mode.

13.5.3 Workaround

If you need to disable the SCI-A interrupt while it is in Mute mode, use the global interrupt mask in the dedicated interrupt controller, refer to Section 5.7 “Standard Interrupts” in the datasheet. Do not change the TE, RE and SBK bits in the SCICR2 register while the SCI-A is in Mute mode. data Start Address Stop Data Line RWU RDRF data Data Line RWU RDRF ld r0,SCICR2 and r0,0x80 ld SCICR2, r0 Corrupted Mute mode mechanism Mute mode mechanism int Start Address Stop under an SCICR2 access

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING

Under certain conditions, FIFO corruption can occur in the following cases: WHEN a bxCAN RX FIFO already holds 2 mes- sages (i.e. FMP==2) AND the application releases the same FIFO (with the instruction CANx_CTRL_CRFRy |= CRF_rfom; x=0 for the CAN_0 cell x=1 for the CAN_1 cell y=0 for the Receive FIFO 0 y=1 for the Receive FIFO 1 ) WHILE the bxCAN requests the transfer of a new receive message into the FIFO (this lasts one CPU cycle) THEN the internal FIFO pointer is not updated BUT the FMP bits are updated correctly Impact on Application: As the FIFO pointer is not updated correctly, this causes the last message received to be over- written by any incoming message. This means one message is lost as shown in the example in Figure

2 The bxCAN will not recover normal operation

until a device reset occurs. Figure 2. FIFO Corruption

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Workaround 1 The workaround is to replace any occurrence of by: x=0 for the CAN_0 cell x=1 for the CAN_1 cell y=0 for the Receive FIFO 0 y=1 for the Receive FIFO 1 Explanation of Workaround 1 First, we need to make sure no interrupt can occur between the test and the release of the FIFO to avoid any added delay. The workaround checks if the first 2 FIFO levels are already full (FMP = 2) as the problem happens only in this case. If FMP ≠2 we release the FIFO immediately, if FMP=2, we monitor the reception status of the cell. The reception status is available in the CMSR reg- ister bit 5 (REC bit). Note: The REC bit was called RX in olders ver- sions of the datasheet. If the cell is not receiving, then REC bit in CMSR is at 0, the software can release the FIFO immedi- ately: there is no risk. If the cell is receiving, it is important to make sure the release of the mail box will not happen at the time when the received message is loaded into the FIFO. We could simply wait for the end of the reception, but this could take a long time (200µs for a 100-bit frame at 500kHz), so we also monitor the Rx pin of the microcontroller to minimize the time the appli- cation may wait in the while loop. We know the critical window is located at the end of the frame, 6+ CAN bit times after the acknowl- edge bit (exactly six full bit times plus the time from the beginning of the bit to the sample point). Those bits represent the acknowledge delimiter + the end of frame slot. We know also that those 6+ bits are in recessive state on the bus, therefore if the CAN Rx pin of the device is at ‘0’, (reflecting a CAN dominant state on the bus), this is early enough to be sure we can release the FIFO before the critical time slot. Therefore, if the device hardware pin Rx is at 0 and there is a reception on going, its message will be transferred to the FIFO only 6+ CAN bit times later at the earliest (if the dominant bit is the ac- knowledge) or later if the dominant bit is part of the message. spp (CANx_CTRL_PG); CANx_CTRL_CRFRy |= CRFR_rfom; spp(CANx_CTRL_PG); if ((CANx_CTRL_CRFRy & 0x03) == 0x02) while (( CANx_CTRL_CMSRy & 0x20) && (CANx_CTRL_CDGRy & 0x08)); CANx_CTRL_CRFRy |= CRFR_rfom;

Figure 3. Workaround 1 in Assembler

52 CPU cycles (48 for the 6 bit times + 4 for the

to evaluate how frequently this delay occurs. level interrupts are being serviced.

Figure 4. Critical Window Timing Diagram Figure 5. Reception of a Sequence of Frames Table 75. While Loop Timing higher and if the CAN baud rate is below 1MBaud. quence is present on in the CAN frame. CPU and the sampling time is 16/fCPU. which reduces the Rx pin sampling time.

24 MHz No dominant bit missed

16 MHz 1 MBaud

8 MHz > 500 kHz

4 MHz > 250 kHz

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d)

13.7 MFT DMA MASK BIT RESET WHEN MFT0

DMA PRIORITY LEVEL IS SET TO 0 Introduction The MultiFunction Timer is a 16-bit timer with Input Capture and Output Compare modes. In Input Capture mode, the timer value is saved when an external event occurs. In Output Compare mode, the timer changes an I/O pin level when it reaches the Compare Register value. In these two modes the event (Input Capture or Output Compare) may generate an interrupt or re- quest a Direct Memory Access. – In interrupt Input Capture mode (or Output Com- pare mode), the interrupt routine saves the coun- ter in the RAM or the Register File (or updates the compare register from a location in RAM or in the Register File). – In DMA mode these transfers are done automat- ically. The choice between Interrupt or DMA modes is defined by the CP0D and CM0D bits (bit 6 and bit 3 in the IDMR register, R255 page 10/8). CP0D : Capture 0 DMA Mask. Capture on REG0R DMA is enabled when CP0D = 1. CM0D: Compare 0 DMA Mask. Compare on CMP0R DMA is enabled when CM0D = 1. In DMA mode a DMA counter register and a DMA address register define the location and the size of the memory block (RAM or Reg. File) involved in these transfers. Each DMA transfer decreases the counter value. When the counter reaches 0, an EndOfBlock event occurs on the DMA controller. This event is detected by the MFT which resets the CP0D or the CM0D bit. Limitation Description The MFT1 resets its DMA Mask bit even if the End-of-Block signal is dedicated to the MFT0. This limitation occurs if the following conditions are fulfilled: – a MFT DMA request (for instance MFT1) occurs while another peripheral DMA request is being serviced (for instance MFT0), – the MFT0 DMA request corresponds to an End- of-Block – the MFT0 DMA priority level is set to 0. This limitation is due to wrong End-of-Block event management by the MFT, it does not impact the SCI and the I2C but they can be involved in the limitation if: – First peripheral requests a DMA transfer with End-of-Block event, – Other peripherals request a DMA transfer with a higher priority level between the same two DMA arbitrations. As a consequence, the MFT1 DMA request is not serviced and a DMA transfer is lost. This is also true for a Top Level Interrupt (higher priority than DMA).

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Arbitra- MFT0 MFT1 End-Of Output Com- pare DMA Request DMA Transfer DMA Transfer End-of-Block Interrupt Routine DMA Request The next Output Compare event generates an interrupt and not a DMA request. Interrupt Request Output Compare -Block tion CM0D reset CM0D reset (1) (1) The MFT1 CM0D bit should not be reset by the End-of- Block signal unless its DMA request is being serviced.

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Impact On Apllication 1. The MFT1 wins the next DMA Arbitration, the DMA request is serviced. The MFT0 interrupt routine is executed before the next Input Capture or Output Compare event. It detects that a wrong Mask Bit Reset has occurred on the MFT1 and re-enables the DMA Mask. => There is no application impact. 2. The MFT1 does not win the next DMA Arbitra- tion, the DMA request is not serviced. The MFT1 will not request the DMA again as its DMA Mask bit is reset. => A DMA transfer is lost. The MFT0 interrupt routine is executed be- fore the next Input Capture or Output Com- pare event. It detects that a wrong Mask Bit Reset has occurred on the MFT1 and re-ena- bles the DMA Mask. => An Input Capture value is lost or a Com- pare value is used twice. 3. The MFT1 wins the next DMA Arbitration, the DMA request is serviced. The MFT0 interrupt routine is not executed before the next MFT1 Input Capture or Output Compare event. This new event generates an Interrupt. The interrupt routine must check that the DMA counter is equal to 0. If it is not equal to 0, the DMA counter and address must not be changed, but the DMA Mask must be set. => An Input Capture value or a Comparison value must be handled by the interrupt rou- tine. If this failure recovery management can be executed fast enough within the interrupt rou- tine, there is no impact on the application. Otherwise the counter will reach the new compare value before it has been loaded in the Compare Register or a new input capture event will occur before the previous value has been saved. 4. The MFT1 does not win the next DMA Arbi- tration, the DMA request is not serviced. The MFT1 will not request the DMA again as its DMA Mask bit is reset. => A DMA transfer is lost. The MFT0 interrupt routine is not executed before the next MFT1 Input Capture or Output Compare event. This new event generates an Interrupt. The interrupt routine must check that the DMA counter is equal to 0. If it is not equal to 0, the DMA counter and address must not be changed, but the DMA Mask must be set. => An Input Capture value or a Comparison value must be handled by the interrupt rou- tine. If this failure recovery management can be executed fast enough within the interrupt rou- tine, only one transfer is lost. Otherwise the counter will reach the new compare value before it has been loaded in the Compare Register or a new input capture event will occur before the previous value has been saved. Workaround If it is not possible to limit the DMA to one MFT only (no DMA with another MFT, SCI-M or I2C), the following failure recovery management must be included in the MFT, SCI-M, I2C Interrupt rou- tines (if the DMA is used). 1. Following an End-of-Block event (DMA coun- ter equal to 0): Check the other MFT DMA counter (both MFTs if this is the SCI-M or the I2C interrupt routine). If the counter does not equal 0 and the DMA mask is reset, reset the interrupt flag bit, set the DMA Mask bit. 2. Following an Input Capture or an Output Compare event (DMA counter does not equal 0): Execute the transfer by software, modify the DMA counter and address, reset the interrupt flag bit, set the DMA Mask bit.

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Here is an example of a patch for the MFT1 using DMA in ouput compare mode, inserted at the be- ginning of the MFT0 interrupt routine: spp #8 ;Set to page 8 (mft1) tm T_IDMR,#0x08 ;test mft0 OCMP dma mask bit jxnz MFT0_it_routine cpw DMA_CNT1,#0 ;If the DMA count is not at zero the block did not complete jxeq MFT0_it_routine and T_FLAGR,#11011111b ;Clear dma compare interrupt request or T_IDMR,#0x08 ;Re-enable the com- pare 0 dma MFT0_it_routine: ;MFT0 interrupt rou- tine code In addition, the peripheral DMA priorities must be organized so that the MFT DMA priorities are the highest. This way the impact is limited: DMA re- quests with the wrong Mask Bit Reset are serv- iced. Workaround Limitation If the counter event period is too short, the failure recovery in the interrupt routines will not work.

13.8 EMULATION CHIP LIMITATIONS

present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.

13.8.1 RESET BEHAVIOUR FOR BI-

Table 76. Reset Behaviour Table Shaded areas represent erroneous operations.

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) During reset, the risk of power consumption in the input stage due to floating inputs is avoided by a design feature. However, if the application requires pull-ups during reset (for instance, in order to send known logic values to external devices), external pull-ups must be provided. When the I/O port outputs a zero, there will be some additional power con- sumption as these external pull-ups are not switched off. These ports behave in the same way following an external, watchdog or software reset.

13.8.2 High Drive I/Os when BSZ=1

If the BSZ bit in the EMR1 register (bit 1 of R245, page 21) is set so as to use high-drive output buffers for P4[7:6] and P6[5:4], all I/O ports as well as AS , DS and RW will also use high-drive output buffers. Impact On Application P0[7:0], AS , DS and RW have the same V OH pa- rameter value as P6[5:4]. P0[7:0]-P2[3:2], AS , DS and RW have the same VOL and IIO parameter values as the P4[7:6] and P6[5:4]. These I/Os using high-drive output buffers will generate more noise than those using the standard low-noise output buffers.

13.8.3 ADC PARASITIC DIODE

A parasitic diode is present between an ADC input and AVDD. As described in the datasheet, the user has the possibility to switch off AVDD when he switches off the ADC to save power consumption. However, if AVDD is connected to ground and a voltage is present on the Input Port, an increase in power consumption can occur. The Input Port affected by this diode is the one pointed to by the analog multiplexer of the ADC, if the port is set up as AF analog input. When the ADC is stopped, the multiple xer points to the first input to be converted in a scan (i.e. the channel pointed to by the SC[3:0] bits). Workaround In order to avoid this problem, the I/O connected to the ADC has to be set up in any mode except AF analog input (i.e. any combination of PxC2.. PxC0 except 111). 1. Deprogram analog input mode from the I/O port which is pointed to by the SC[3:0] bits (start conversion channel, b7..b4 of CLR1). For example the I/O can be reprogrammed as an open drain output, with the data at 1. The high impedance of the output stage then avoids a conflict with the external voltage source. In order to avoid potential power con- sumption in the input buffer of this I/O, depending on the external voltage applied to the pin, it is wise to set the 'start conversion channel' to a channel which carries levels below 800 mV or above (V DD -8 0 0m V ) . Another possibility is to modify the SC[3:0] bits so that they point to an I/O Port which is not used as an analog input. 2. Next, switch off the A/D Converter. The current in AV DD will be zero, whatever the logic levels on the analog inputs, and whatever the voltage level applied to AV DD (between 0 and VDD). 13.8.4 ADC ACCURACY VS. NEGATIVE INJECTION CURRENT If a negative current is injected to an input pin (i.e. input signal voltage below -0.3V), a part of this cur- rent will be drawn from the adjacent I/Os. The fol- lowing curve quantifies this current:

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Figure 8. Impact of negative current injection on adjacent pin resulting in a conversion error.

13.8.5 I2CECCR REGISTER LIMITATION

13.8.6 I2C BEHAVIOUR DISTURBED DURING

If a DMA transfer occurs on SCI-M, MFT or J1850 during I2C transmission or reception, I2C periph- eral may be disturbed. In transmission mode, additional bytes can be ob- served on I2C lines (SDA and SCL). In reception mode, additional bytes can be seen in the I2CDR register. Workaround Avoid using DMA transfer while I2C peripheral is running.

13.8.7 MFT DMA MASK BIT RESET

The limitation described in Section 13.7 on page 419 applies whatever the MFT0 DMA priority level.

13.8.8 DMA DATA CORRUPTED BY MFT INPUT

If the MFT requests a DMA transfer following an input capture event and while a DMA transfer is currently ongoing to or from another peripheral (SCI-M, I2C, or second MFT), the DMA data is cor- rupted (overwritten by the captured data). Workaround Avoid using the MFT Input Capture function in DMA mode while another peripheral is in DMA mode. 100 150 200 250 300 350 0 5 10 15 20 25 30 Current injection (mA) Current drawn from adjacent pin (uA, absolute value)

ST92F124/F150/F250 - KNOWN LIMITATIONS

13.8.9 SCI-A wrong break duration

A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if M=0 - 22 bits instead of 11 bits if M=1. In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than ex- pected. Occurrence The occurrence of the problem is random and pro- portional to the baudrate. With a transmit fre- quency of 19200 baud (f CPU =8MHz and SCIBRR=0xC9), the wrong break duration occur- rence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, soft- ware can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the applica- tion is not doing anything between the idle and the break. This can be ensured by temporarily disa- bling interrupts. The exact sequence is: - Disable interrupts - Reset and Set TE (IDLE request) - Set and Reset SBK (Break Request) - Re-enable interrupts LIN mode (if available) If the LINE bit in the SCICR3 is set and the M bit in the SCICR1 register is reset, the SCI-A is in LIN master mode. A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: - 24 bits instead of 13 bits

ST92F124/F150/F250 - KNOWN LIMITATIONS KNOWN LIMITATIONS (Cont’d) Occurrence The occurrence of the problem is random and pro- portional to the baudrate. With a transmit fre- quency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration occur- rence is around 1%. Analysis The LIN protocol specifies a minimum of 13 bits for the break duration, but there is no maximum value. Nevertheless, the maximum length of the header is specified as (14+10+10+1)x1.4=49 bits. This is composed of: - the synch break field (14 bits), - the synch field (10 bits), - the identifier field (10 bits). Every LIN frame starts with a break character. Adding an idle character increases the length of each header by 10 bits. When the problem oc- curs, the header length is increased by 11 bits and becomes ((14+11)+10+10+1)=45 bits. To conclude, the problem is not always critical for LIN communication if the software keeps the time between the sync field and the ID smaller than 4 bits, i.e. 208us at 19200 baud. The workaround is the same as for SCI mode but considering the low probability of occurrence (1%), it may be better to keep the break generation se- quence as it is.

13.8.10 LIN MASTER MODE NOT AVAILABLE

LIN Synch Breaks (13 low bits) generation is not possible on SCI-A. LINE bit has no effect on break length.

13.8.11 LIMITATIONS ON LQFP64 DEVICES

13.8.11.1 AIN[7:0] NOT AVAILABLE ON

ADC Channels from AIN0 to AIN7 are not present on LQFP64 devices.

13.8.11.2 EFT0 AND EFT1 NOT AVAILABLE ON

Extended Function Timers are not present on LQFP64 devices.

14 REVISION HISTORY

Table 77. Revision History Changed Table 73 on page 407. 19-Nov-2004 4 Changed Table 69 on page 372. and changed according to modifications made to Table 3 on page 24.