Power Management

PQ25619RTWR

Texas Instruments

BQ25619 I2C Controlled 1-Cell 1.5-A Battery Charger with 20-mA Termination and 1-A Boost Operation

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION VBUS SW BTST SYS BAT I2C Bus TS USB QON REGN ICHG Host Host Control Optional Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. BQ25619 SLUSDF8 – JUNE 2019 BQ25619I2CControlled1-Cell1.5-ABatteryChargerwith20-mATerminationand1-A BoostOperation

1 Features

1• High-efficiency, 1.5-MHz, synchronous switch- mode buck charger – 92% Charge efficiency at 2 A from 5-V input – Pulse Frequency Modulation (PFM) mode for light load operations

Supports USB On-The-Go (OTG) – Boost converter with up to 1-A output – 92% Boost efficiency at 1-A output – Soft-start up to 500-µF capacitive load – PFM Mode for light load operations
Single Input to support USB input and high voltage adapters – Support 3.9-V to 13.5-V input voltage range with 22-V absolute maximum input voltage (VBUS) rating – Programmable input current limit (IINDPM) with I2C (100-mA to 3.2-A, 100-mA/step) to support USB 2.0, USB 3.0 standards and high voltage adaptors – Maximum power tracking by input voltage limit (VINDPM) up to 5.4 V – VINDPM Threshold automatically tracks battery voltage
Narrow VDC (NVDC) PowerPath management – Instant-on works with no battery or deeply discharged battery – Ideal diode operation in battery supplement mode
Flexible I2C configuration and autonomous charging for optimal system performance
High integration includes all MOSFETs, current sensing and loop compensation
Low Rdson 19.5-mΩ BATFET to minimize the charging loss and extend battery life – BATFET Control to support ship mode, wake up and full system reset
10-µA Low battery leakage current with system voltage standby
7-µA Low battery leakage current in ship mode
High accuracy battery charging profile – ±0.5% Charge voltage regulation – ±5% at Charge current regulation – ±7.5% at Input current regulation – Remote battery sensing for fast charge – 20-mA Termination current – Programmable top-off timer for full battery charging

2 Applications

Wearable, watches, fitness accessories
Earphone charging cases

3 Description

The BQ25619 is a highly-integrated 1.5-A switch- mode battery charge management and system PowerPath management device for single cell Li-Ion and Li-polymer battery. The low impedance PowerPath optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) BQ25619 WQFN (24) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application

12.3 Receiving Notification of Documentation Updates 51

13 Mechanical, Packaging, and Orderable

4 Revision History

June 2019 * Advance Information Initial release.

5 Description (continued)

The BQ25619 is a highly-integrated 1.5-A switch-mode battery charge management and system PowerPath management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high input voltage support for a wide range of applications including wearables, earphone charging case. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. Its input voltage and current regulation, and battery remote sensing deliver maximum charging power to battery. The solution is highly integrated with input reverse-blocking FET (RBFET, Q1), high- side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also integrates the bootstrap diode for the high-side gate drive for simplified system design. The I2C serial interface with charging and system settings makes the device a truly flexible solution. The device supports a wide range of input sources, including standard USB host port, USB charging port, and USB compliant high voltage adapter. It is compliant with USB 2.0 and USB 3.0 power spec with input current and voltage regulation. The device takes the result from detection circuit in the system, such as USB PHY device. The device also meets USB On-the-Go (OTG) operation power rating specification by supplying 5 V with current limit up to 1 A. The PowerPath management regulates the system slightly above battery voltage but does not drop below 3.5-V minimum system voltage (programmable). With this feature, the system maintains operation even when the battery is completely depleted or removed. When the input current limit or voltage limit is reached, the PowerPath management automatically reduces the charge current. As the system load continues to increase, the battery start to discharge the battery until the system power requirement is met. This supplement mode prevents overloading the input source. The device initiates and completes a charging cycle without software control. It senses the battery voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit and the battery voltage is higher than recharge threshold. If the fully charged battery falls below the recharge threshold, the charger automatically starts another charging cycle. The charger provides various safety features for battery charging and system operations, including battery negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and over-current protections. The thermal regulation reduces charge current when the junction temperature exceeds 110°C. The status register reports the charging status and any fault conditions. Other safety features include battery temperature sensing for charge and boost mode, thermal regulation and thermal shutdown and input UVLO and over-voltage protection. With I2C, the VBUS_GD bit indicates if a good power source is present, and the INT output Immediately notifies host when fault occurs. The device also provides QON pin for BATFET enable and reset control to exit low power ship mode or full system reset function. The device is available in 24-pin, 4 mm × 4 mm x 0.75 mm thin WQFN package.

ADVANCE□INFORMATION BQ25619 23 22 21 20 19 7 8 9 10 11 12 VAC PSEL PMID_GOOD STAT SCL SDA /INT NC /CE BATSNS TS /QON BAT BAT SYS SYS PGND PGND VBUS PMID REGN BTST SW SW BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

6 Pin Configuration and Functions

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. BAT P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely to the BAT pin.14 BATSNS 10 AIO Battery voltage sensing pin for charge voltage regulation. in order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery voltage through BAT pin. BTST 21 P PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST. CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled. GND P Ground INT 7 DO Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault. PMID 23 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Given the total input capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND. PMID_GOOD 3 DO Open drain active high PMID good indicator. Connect to the pull up rail through 10-kΩ resistor. HIGH indicates PMID voltage is below 5.2 V and the current in Q1 is below 110% of input current limit. This signal can be used to drive external p-channel OVPFET to disconnect the PMID from ear phone under charging when input voltage is too high or input current is too high. PSEL 2 DI Power source selection input. High indicates 500-mA input current limit. Low indicates 2.4-A input current limit. Once the device gets into host mode, the host can program different input current limit to IINDPM register.

ADVANCE□INFORMATION BQ25619 www.ti.com SLUSDF8 – JUNE 2019 Product Folder Links: BQ25619 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. QON 12 DI BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on BATFET to exit ship mode. When BATFET is not in ship mode, a logic low of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplug or not through I2C bit BATFET_RST_WVBUS. The pin contains an internal pull-up to maintain default high logic. REGN 22 P PWM low side driver positive supply output. internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. SCL 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. SDA 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor. STAT 4 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status. Charge in progress: LOW Charge complete or charger in SLEEP mode: HIGH Charge suspend (fault response): Blink at 1 Hz SW P Switching node connecting to output inductor. Internally SW is connected to the source of the n- channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.20 SYS P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 20 µF closely to the SYS pin.16 TS 11 AI Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge and OTG suspend when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor. VAC 1 AI Input voltage sensing. This pin must be tied to VBUS. VBUS 24 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to IC. Thermal Pad — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.

ADVANCE□INFORMATION BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage VAC (converter not switching) –2 30 V VBUS (converter not switching) –2 22 V PMID (converter not switching) –0.3 22 V SW –0.3 16 V BAT, SYS (converter not switching) –0.3 7 V BTST –0.3 22 V Voltage BATSNS (converter not switching) –0.3 7 V Voltage PSEL, STAT, SCL, SDA, INT, PMID_GOOD, CE, TS, QON –0.3 7 V Output Sink Current SDA, STAT, INT, PMID_GOOD 6 mA TJ Junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±250

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VVBUS Input voltage 3.9 13.5 V VBAT Battery voltage 4.52 V IVBUS Input current 3.2 A ISW Output current (SW) 3.2 A IBAT Fast charging current 1.5 A TA Ambient temperature –40 85 °C TJ Junction temperature –40 110 °C L Inductance 1 µH CVBUS VBUS capacitance 1 µF CPMID PMID capacitance 10 µF CSYS SYS capacitance 10 µF CBAT BAT capacitance 10 µF CREGN REGN capacitance 4.7 µF CBTST BTST capacitance 47 nF

ADVANCE□INFORMATION BQ25619 www.ti.com SLUSDF8 – JUNE 2019 Product Folder Links: BQ25619 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) BQ25619 UNITRTW (WQFN)

24 Pins

RθJA Junction-to-ambient thermal resistance (JEDEC(1)) 31.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27 °C/W RθJB Junction-to-board thermal resistance 9.2 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 9.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.8 °C/W

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENTS IQ_BAT Quiescent battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5V, VBUS floating or VBUS = 0V - 5V, SCL, SDA = 0V or 1.8V, TJ < 85 °C, BATFET enabled (OVPFET_DIS=0)

10 TBD µA

ISD_BAT Shipmode battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5V, VBUS floating or VBUS = 0V - 5V, SCL, SDA = 0V or 1.8V, TJ < 85 °C, BATFET disabled (OVPFET_DIS=1)

7 TBD µA

IQ_VBUS Quiescent input current (VBUS) in converter switching Charge disabled, converter switching, ISYS = 0A 3 mA ISD_VBUS Quiescent input current in HIZ VAC/VBUS = 5V, High-Z mode, no battery 37 50 µA VAC/VBUS = 12V, High-Z mode, no battery 68 90 µA IQ_OTG Quiescent battery current (BATSNS, BAT, SYS, SW) in OTG VBAT = 4.5V, VBUS = 5V, OTG mode enabled, converter switching, IVBUS = 0A 2.4 mA VBUS / VBAT SUPPLY VVBUS_O P VBUS operating range 3.9 13.5 V VVBUS_UV LOZ VBUS rising for active I2C, no battery VBUS rising 3.3 3.7 V VVBUS_UV LO VBUS falling to turnoff I2C, no battery VBUS falling 3 3.3 V VVBUS_PR ESENT VBUS to enable REGN VBUS rising 3.65 3.9 V VVBUS_PR ESENTZ VBUS to disable REGN VBUS falling 3.15 3.4 V VSLEEP Enter Sleep mode threshold VBUS falling, VBUS - VBAT, VBAT = 4V 15 60 110 mV VSLEEPZ Exit Sleep mode threshold VBUS rising, VBUS - VBAT, VBAT = 4V 115 220 340 mV VACOV VAC overvoltage rising threshold to turn of switching VAC rising, OVP[1:0]=00 5.42 5.7 5.99 V VAC rising, OVP[1:0]=01 6.099 6.42 6.741 V VAC rising, OVP[1:0]=10 10.45 11 11.55 V VAC rising, OVP[1:0]=11 13.5 14.2 14.85 V VAC overvoltage falling threshold to resume switching VAC falling, OVP[1:0]=00 5.31 5.59 5.87 V VAC falling, OVP[1:0]=01 5.98 6.3 6.61 V VAC falling, OVP[1:0]=10 10.24 10.78 11.32 V VAC falling, OVP[1:0]=11 13.1 13.9 14.6 V

ADVANCE□INFORMATION BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBAT_UVL OZ BAT voltage for active I2C, no VBUS VBAT rising 2.5 V VBAT_DPL Z BAT depletion rising threshold to turnon BATFET VBAT rising 2.35 2.8 V VBAT_DPL BAT depletion falling threshold to turnoff BATFET VBAT falling 2.18 2.62 V VPOORSR C Bad adapter detection threshold VBUS falling 3.75 3.9 4.0 V POWER-PATH MANAGEMENT VSYS_MIN Typical minimum system regulation voltage VBAT=3.2V < SYS_MIN = 3.5V, ISYS = 0A 3.5 3.65 V VSYS_OVP System overvoltage threshold VREG = 4.35V, Charge disabled, ISYS = 0A 4.7 V RON_QBL K (Q1) Blocking FET on-resistance TJ = 25°C 45 TBD mΩ TJ = -40°C - 125°C 45 TBD mΩ RON_QHS (Q2) High-side switching FET on-resistance TJ = 25°C 62 TBD mΩ TJ = -40°C - 125°C 62 TBD mΩ RON_QLS (Q3) Low-side switching FET on-resistance TJ = 25°C 71 TBD mΩ TJ = -40°C - 125°C 71 TBD mΩ VBATFET_ FWD BATFET forward voltage in supplement mode BAT discharge current 10mA, converter running 30 mV BATTERY CHARGER VREG_RA NGE Typical charge voltage regulation range 3.5 4.52 V VREG_STE P Typical charge voltage step 4.3V < VREG < 4.52V 10 mV VREG_AC C Charge voltage accuracy VREG = 4.1V, TJ = –40°C - 85°C 4.0795 4.1 4.1205 V VREG = 4.2V, TJ = –40°C - 85°C 4.179 4.2 4.221 V VREG = 4.35V, TJ = –40°C - 85°C 4.32825 4.35 4.37175 V VREG = 4.45V, TJ = –40°C - 85°C 4.427 4.45 4.48 V ICHG_RAN GE Typical charge current regulation range 0 1.5 A ICHG_STE P Typical charge current regulation step 20 mA ICHG_ACC Fast charge current regulation accuracy ICHG = 0.24A, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 0.2112 0.24 0.2688 A ICHG = 0.72A, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 0.6768 0.72 0.7632 A ICHG = 1.50A, VBAT = 3.1V or 3.8V, TJ IPRECHG_ RANGE Typical pre-charge current range 20 260 mA IPRECHG_ STEP Typical pre-charge current step 20 mA IPRECHG_ ACC Precharge current accuracy VBAT = 2.6V, IPRECHG = 20mA 28 40 52 mA VBAT = 2.6V, IPRECHG = 120mA 84 120 156 mA ITERM_RA NGE Typical termination current range 60 780 mA ITERM_ST EP Typical termination current step 60 mA

ADVANCE□INFORMATION BQ25619 www.ti.com SLUSDF8 – JUNE 2019 Product Folder Links: BQ25619 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ITERM_AC C Termination current accuracy ITERM=60mA, ICHG>260mA, VREG=4.35V, TJ = –40°C - 85°C (char, all codes) 42 60 78 mA ITERM=20mA, ICHG<260mA, VREG=4.35V, TJ = –40°C - 85°C (char, all codes) 10 20 30 mA VBAT_SHO RTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.15 2.25 2.35 V VBAT_SHO RT Battery short voltage falling threshold to stop pre-charge VBAT falling 1.85 2 2.15 V IBAT_SHO RT Battery short trickle charging current VBAT < VBAT_SHORTZ 70 90 110 mA VBATLOW V Battery LOWV rising threshold to start fast-charge VBAT rising 3 3.12 3.24 V Battery LOWV falling threshold to stop fast-charge VBAT falling 2.7 2.8 2.9 V VRECHG Battery recharge threshold VRECHG=0, VBAT falling 90 120 150 mV VRECHG=1, VBAT falling 200 230 265 mV IBAT_LOA D Battery discharge load current 30 mA ISYS_LOA D System discharge load current 30 mA RON_QBA T (Q4) Battery FET on-resistance TJ = 25°C 19.5 23.4 mΩ TJ = -40°C - 125°C 19.5 29.25 mΩ RBATSNS BATP Input Resistance EN_HIZ = 1 1 MΩ BATTERY OVER-VOLTAGE PROTECTION VBAT_OVP Battery overvoltage rising threshold VBAT rising, as percentage of VREG 103 104 105 % Battery overvoltage falling threshold VBAT falling, as percentage of VREG 101 102 103 % INPUT VOLTAGE / CURRENT REGULATION VINDPM_R ANGE Typical input voltage regulation range 3.9 5.4 V VINDPM_S TEP Typical input voltage regulation step 100 mV VINDPM_A CC Typical input voltage regulation accuracy 4.365 4.5 4.635 % VINDPM_T RACK VINDPM threshold to track battery voltage VBAT = 4.35V, VDPM_BAT_TRACK = VBAT+200mV 4.4135 4.55 4.6865 V IINDPM_RA NGE Typical input current regulation range 0.1 3.2 A IINDPM_ST EP Typical input current regulation step 100 mA IINDPM_AC C Input current regulation accuracy IINDPM = 500mA 450 462.5 500 mA IINDPM_AC C Input current regulation accuracy IINDPM = 900mA 750 832.5 900 mA IINDPM_AC C Input current regulation accuracy IINDPM = 1500mA 1300 1387.5 1500 mA THERMAL REGULATION AND THERMAL SHUTDOWN TREG Junction temperature regulation accuracy TREG = 90°C 90 °C TREG = 110°C 110 °C TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C

ADVANCE□INFORMATION BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Thermal Shutdown Falling threshold Temperature Decreasing 130 °C JEITA THERMISTOR COMPARATOR (CHARGE MODE) VT1_RISE TS pin voltage rising threshold, Charge suspended above this voltage. As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 % VT1_FALL TS pin voltage falling threshold. Charge re-enabled to 20% of ICHG and VREG below this voltage. As Percentage to REGN 71.5 72 72.5 % VT2_RISE TS pin voltage rising threshold, Charge back to 20% of ICHG and VREG above this voltage. As Percentage to REGN, JEITA_T2=5°C w/ 103AT 70.25 70.75 71.25 % As Percentage to REGN, JEITA_T2=10°C w/ 103AT 67.75 68.25 68.75 % As Percentage to REGN, JEITA_T2=15°C w/ 103AT 64.75 65.25 65.75 % As Percentage to REGN, JEITA_T2=20°C w/ 103AT 61.75 62.25 62.75 % VT2_FALL TS pin voltage falling threshold. Charge back to ICHG and VREG below this voltage. As Percentage to REGN, JEITA_T2=5°C w/ 103AT 68.7 69.2 69.7 % As Percentage to REGN, JEITA_T2=10°C w/ 103AT 66.45 66.95 67.45 % As Percentage to REGN, JEITA_T2=15°C w/ 103AT 63.7 64.2 64.7 % As Percentage to REGN, JEITA_T2=20°C w/ 103AT 60.7 61.2 61.7 % VT3_FALL TS pin voltage falling threshold. Charge to ICHG and 4.1V below this voltage. As Percentage to REGN, JEITA_T3=40°C w/ 103AT 47.75 48.25 48.75 % As Percentage to REGN, JEITA_T3=45°C w/ 103AT 44.25 44.75 45.25 % As Percentage to REGN, JEITA_T3=50°C w/ 103AT 40.2 40.7 41.2 % As Percentage to REGN, JEITA_T3=55°C w/ 103AT 37.2 37.7 38.2 % VT3_RISE TS pin voltage rising threshold. Charge back to ICHG and VREG above this voltage. As Percentage to REGN, JEITA_T3=40°C w/ 103AT 48.8 49.3 49.8 % As Percentage to REGN, JEITA_T3=45°C w/ 103AT 45.3 45.8 46.3 % As Percentage to REGN, JEITA_T3=50°C w/ 103AT 41.3 41.8 42.3 % As Percentage to REGN, JEITA_T3=55°C w/ 103AT 38.5 39 39.5 % VT5_FALL TS pin voltage falling threshold, charge suspended below this voltage. As Percentage to REGN (60°C w/ 103AT) 33.7 34.2 35.1 % VT5_RISE TS pin voltage rising threshold. Charge back to ICHG and 4.1V above this voltage. As Percentage to REGN 35 35.5 36 % COLD / HOT THERMISTOR COMPARATOR (OTG MODE) VBCOLD_ RISE TS pin voltage rising threshold, OTG is suspended above this voltage. As Percentage to REGN (–20°C w/ 103AT) 79.5 80 80.5 % VBCOLD_F ALL TS pin voltage falling threshold 71.5 72 72.5 % VBHOT_RI SE TS pin voltage threshold. OTG is suspended below this voltage. As Percentage to REGN, (65°C w/ 103AT) 30.2 31.2 32.2 % VBHOT_FA LL TS pin voltage rising threshold As Percentage to REGN, JEITA_T3=55°C w/103AT 38.5 39 39.5 %

ADVANCE□INFORMATION BQ25619 www.ti.com SLUSDF8 – JUNE 2019 Product Folder Links: BQ25619 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING CONVERTER FSW PWM switching frequency Oscillator frequency 1.32 1.5 1.68 MHz DMAX Maximum PWM Duty Cycle GBD 97 % CONVERTER PROTECTION ILSOCP LSFET cycle by cycle current limit 5.2 8 A ILSZCP LSFET under current falling threshold 100 160 mA IHSOCP HSFET cycle by cycle current limit 5.2 8 A IHSZCP HSFET under current falling threshold 100 160 mA IBLK_OCP BLKFET over-current threshold As percentage of IINDPM setting 115 % IBLK_UCP BLKFET under-current threshold From sync mode to non-sync mode 100 mA OTG MODE CONVERTER VOTG_BAT Battery voltage exiting OTG mode BAT falling 2.4 2.5 2.6 V VOTG_RA NGE Typical OTG mode voltage regulation range 4.6 5.15 V VOTG_AC C OTG mode voltage regulation accuracy IVBUS = 0A, OTG_VLIM = 5V 4.6 5 5.15 V IOTG_OCP _Q4 OTG mode battery discharge current clamp on Q4 5 6 VOTG_OV P OTG mode overvoltage threshold on PMID 5.45 5.6 5.75 V REGN LDO VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.58 4.7 4.8 V VVBUS = 9V, IREGN = 20mA 5.6 6 6.65 V IREGN REGN LDO current limit VVBUS = 5V, VREGN = 3.8V 50 mA I2C INTERFACE (SCL, SDA) VIH Input high threshold level, SDA and SCL Pull up rail 1.8V 1.3 V VIL Input low threshold level Pull up rail 1.8V 0.4 V VOL Output low threshold level Sink current = 5mA 0.4 V IBIAS High-level leakage current Pull up rail 1.8V 1 mA LOGIC INPUT PIN VIH Input high threshold level (/CE, PSEL) 1.3 V VIL Input low threshold level (/CE, PSEL) 0.4 V IIN_BIAS High-level leakage current (/CE, PSEL) Pull up rail 1.8V 1 mA LOGIC OUTPUT PIN VOL Output low threshold level (/INT, STAT, PMID_GOOD) Sink current = 5mA 0.4 V IOUT_BIAS High-level leakage current (/INT, STAT, PMID_GOOD) Pull up rail 1.8V 1 mA

7.6 Timing Requirements

tVBUS_OV VBUS OVP Reaction-time 130 ns tPOORSRC Bad adapter detection duration 30 ms tPOORSRC_ RETRY Bad adapter detection retry wait time 2 s BATTERY CHARGER

ADVANCE□INFORMATION BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Timing Requirements (continued) MIN NOM MAX UNIT tTERM_DGL Deglitch time for charge termination 30 ms tRECHG_DG L Deglitch time for recharge threshold 30 ms tBAT_OVP_D GL Deglitch time for battery overvoltage to disable charge 1 µs tTOP_OFF Typical top-off timer accuracy 24 30 36 min tSAFETY Charge safety timer accuracy, CHG_TIMER = 20hr 18 20 24 hr tSAFETY Charge safety timer accuracy, CHG_TIMER = 10hr 9 10 12 hr QON Timing tSHIPMODE QON low time to turn on BATFET and exit shipmode 0.9 1.3 s tQON_RST QON low time before BATFET full system reset 8 12 s tBATFET_RS T BATFET off time during full system reset 250 400 ms tBATFET_DL Y Delay time before BATFET turn off in ship mode 10 15 s I2C INTERFACE fSCL SCL clock frequency 1000 kHZ DIGITAL CLOCK AND WATCHDOG fLPDIG Digital low-power clock (EN_HIZ = 1) 18 30 45 kHz fDIG Digital power clock (EN_HIZ = 0) 1.35 1.5 1.65 MHz tLP_WDT Watchdog Reset time (EN_HIZ = 1, WATCHDOG = 160s) 100 160 s tWDT Watchdog Reset time (EN_HIZ = 0, WATCHDOG = 160s) 136 160 s

8 Detailed Description

8.1 Overview

The BQ25619 device is a highly integrated 1.5-A switch-mode battery charger for single cell Li-Ion and Li- polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.

ADVANCE□INFORMATION TS Battery Sensing Thermistor I2C Interface USB Adapter FBO PGND REGN RBFET (Q1) VBUS LSFET (Q3) HSFET (Q2) SW BATFET (Q4) SYS BAT ICHG VBUS_OVP_BOOST /QON Q1 Gate Control REGN PMID Q3_OCP_BOOST Q2_UCP_BOOST IQ3 IQ2 VVBUS VOTG_OVP VOTG_HSZCP VOTG_BAT ILSFET_UCP IQ3 104% × V BAT_REG BAT UCP BATOVP CONVERTER Control ICHG_REG VBAT_REG BAT VSYSMIN IINDPM IC TJ TREG VINDPM SYS REGN LDOEN_HIZ UVLO SLEEP ACOV+ VVBUS_UVLOZ VBAT + VSLEEP VVAC_OV BTST REFRESH Q2_OCP VBTST_REFRESH VBTST - VSW IHSFET_OCP IQ2 EN_CHARGE EN_BOOST EN_HIZ Q4 Gate Control VQON /CESDASCL Input Source Detection REF DAC ICHG_REG VBAT_REG STAT PMID_GOOD INT PSEL CHARGE CONTROL STATE MACHINE Converter Control State Machine BATLOWV SUSPEND RECHRG TERMINATION BATSHORT TSHUT BAD_SRC BAT_GD TSHUT IC TJ BAT VBATLOWV BAT IBADSRC IDC VBATGD BAT ITERM ICHG BAT VSHORT VREG -VRECHG ICHG BQ25619 VVBUS IIN IIN VVBUS VVBUS VVBUS BATSNS SNS SNS SNS SNS SNS EN_REGN Copyright © 2019, Texas Instruments Incorporated BQ25619 SLUSDF8 –JUNE 2019 www.ti.com Product Folder Links: BQ25619 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

8.3.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately. As the device has I2C, when BATFET turns off due to over-current, the device sets BATFET_DIS bit to indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET Enable (Exit Ship Mode) is applied to re-enable BATFET.

8.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up sequence from input source is as listed: 1. Power Up REGN LDO 2. Poor Source Qualification 3. Input Source Type Detection is based on PSEL to set default input current limit (IINDPM threshold). 4. Input Voltage Limit Threshold Setting (VINDPM threshold) 5. Power Up Converter

8.3.3.1 Power Up REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. It also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the below conditions are valid:

VVBUS>VVBUS_UVLOZ
In buck mode, , VVBUS>VBAT + VSLEEPZ
In boost mode, VVBUS<VBAT + VSLEEP.
After 220-ms delay is completed During high impedance mode when EN_HIZ bit is 1, REGN LDO turns off. The battery powers up the system.

8.3.3.2 Poor Source Qualification

After REGN LDO powers up, the device starts to check current capability of the input source. The first step is poor source detection.

VBUS voltage above VPOORSRC when pulling IBADSRC (typical 30 mA) With I2C, once the input source passes poor source detection, the status register bit VBUS_GD is set to 1 and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

8.3.3.3 Input Source Type Detection (IINDPM Threshold)

After poor source detection, the device runs input source detection through PSEL pin. The PSEL pin sets input current limit 0.5 A (HIGH) or 2.4 A (LOW) in the register. After input source type detection is completed, PMID_GOOD pin is asserted to HIGH and PG_STAT bit goes to 1.

Input Current Limit (IINDPM) register is updated from detection result
VBUS_STAT bit is updated to indicate USB or other input source
PG_STAT bit is updated to indicate good adapter plugs in

The host can over-write IINDPM register to change the input current limit if needed.

8.3.3.3.1 PSEL Pins Sets Input Current Limit

update the IINDPM register. When the device is in default mode, PSEL value updates IINDPM in real time. Table 1. Input Current Limit Setting from PSEL

8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

offset voltage in VINDPM_BAT_TRACK[1:0].

8.3.3.5 Power Up Converter in Buck Mode

off. Otherwise, BATFET stays on to charge the battery. VBAT_SHORTZ V, the device input current limit is the value set by IINDPM register. voltage, charge current and temperature, simplifying output filter design. operation in buck configuration.

8.3.3.6 HIZ Mode with Adapter Present

with Q1 RBFET, REGN LDO and the bias circuits off.

8.3.4 Boost Mode Operation From Battery

Register setting: BATFET_DIS = 0, CHG_COFNIG = 0 and OTG_CONFIG = 1
BAT above VOTG_BAT set by Min_VBAT_SEL bit,

VBUS less than BAT+VSLEEP (in sleep mode) before converter starts
Voltage at TS (thermistor) pin is within acceptable range (VBHOT_RISE < VTS < VBCOLD_RISE)

During boost mode, the status register VBUS_STAT bits is set to 111. operation in boost configuration. and power the accessories connected to PMID.

8.3.5 PowerPath Management

8.3.5.1 Narrow VDC Architecture

battery is the VDS of BATFET. 1 when the system is in minimum system voltage regulation. Figure 1. System Voltage vs Battery Voltage

8.3.5.2 Dynamic Power Management

current limit and the input voltage rises above the input voltage limit.

Figure 2. DPM Response

8.3.5.3 Supplement Mode

regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. supplement mode when the battery is below battery depletion threshold. Figure 3. BAFET V-I Curve

8.3.6 Battery Charging Management

mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

8.3.6.1 Autonomous Charging Cycle

Table 2. The host configures the power path and charging parameters by writing to the corresponding registers Table 2. Charging Parameter Default Setting

Converter starts
Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
No thermistor fault on TS. (TS pin can be ignored by setting TS_IGNORE bit to 1)
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0) The charger device automatically terminates the charging cycle when the charging current is below termination threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle. The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.

8.3.6.2 Battery Charging Profile

and regulates current and voltage accordingly. current charge time to delivery maximum power to battery. BATSNS can be disabled through BATSNS_DIS bit. Table 3. Charging Current Setting

2.2 V to 3 V IPRECHG 40 mA 01

Figure 4. Battery Charging Profile

8.3.6.3 Charging Termination

again to engage Supplement Mode. less than the termination value. In this case, termination is temporarily disabled. is asserted to the host. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination. Due to the termination current accuracy, the actual termination current may be higher than the termination target. termination status. STAT pin stays HIGH during top-off timer counting cycle. as when top-off timer expires.

8.3.6.4 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

8.3.6.4.1 JEITA Guideline Compliance During Charging Mode

Figure 5. JEITA Profile Equation 1 through describe updates to the resistor bias network.

RTHCOLD = 27.28 KΩ (0°C)
RTHHOT = 3.02 KΩ (60°C)
RT1 = 5.3 KΩ
RT2 = 31.4 KΩ

8.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode

returns within thresholds, the boost mode is recovered and NTC_FAULT is cleared.

8.3.6.5 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours (10/20 hours) when the battery is higher than VBATLOWV threshold. When safety timer expires, STAT pin is blinking at 1 Hz to report a fault. The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer (both fast charge and pre-charge) can be disabled through I2C by setting EN_TIMER bit During IINDPM/VINDPM regulation, or thermal regulation, or JEITA cool/warm when fast charge current is reduced,the safety timer counts at half clock rate, because the actual charge current is likely below the setting. For example, if the charger is in input current regulation (IINDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 10 hours, the safety timer will expire in 20 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit. During faults such as BAT_FAULT, NTC_FAULT leading to charging suspend, safety timer is suspended as well. Once the fault goes away, timer resumes. If user stops the current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).

8.3.7 Ship Mode and QON Pin

8.3.7.1 BATFET Disable Mode (Enter Ship Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device turns off BATFET so that the system voltage is floating to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tBATFET_DLY as configured by BATFET_DLY bit. To set the device into ship mode with adapter present, the host has to first set BATFET_RST_VBUS to 1 and then BATFET_DIS to 1. The charger will turn off BATFET (no charging, no supplement) while the adapter is still attached. When adapter is removed, the charger will enter ship mode.

8.3.7.2 BATFET Enable (Exit Ship Mode)

When the BATFET is disabled (in ship mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET to restore system power: 1. Plug in adapter 2. Clear BATFET_DIS bit 3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0) 4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit ship mode. EN_HIZ bit is set to 1 (regardless of adapter present or not). Host has to set EN_HIZ bit to 0 before OTG mode enable. Once adapter plugs in, EN_HIZ will be cleared.

8.3.7.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged–in. When BATFET_RST_EN=1 and BATFET_DIS=0, BATFET full system reset function is enabled. By changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a power-on-reset. After the reset is complete, device is in POR state, and all the registers are in POR default settings. The QON pin supports push-button interface to reset system power without host by changing the state of BATFET. When the QON pin is driven to logic low for tQON_RST, BATFET reset process starts. The BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0. BATFET full system reset functions either with or without adapter present. If BATFET_RST_WVBUS=1, the system reset function starts after tQON_RST when QON pin is pushed to LOW. Once the reset process starts, the device first get into HIZ mode to turn off the converter, and then power cycle BATFET. If BATFET_RST_WVBUS=0, the system reset function doesn't start till tQON_RST after QON pin is pushed to LOW and adapter is removed. After BATFET full system reset is complete, the device will power up again if EN_HIZ is not set to 1 before the system reset.

Figure 6. QON Timing

8.3.8 Status Outputs (STAT, INT, PMID_GOOD)

8.3.8.1 Power Good Indicator ( PG_STAT Bit)

VBUS above VVBUS_UVLO
VBUS above battery (not in sleep)
VBUS below VACOV threshold
VBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Completed input Source Type Detection

8.3.8.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. Table 4. STAT Pin State

8.3.8.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system on the device operation. The following events will generate 256-μs INT pulse.

Good input source detected – VBUS above battery (not in sleep) – VBUS below VACOV threshold – VBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Input removed
USB/adapter source identified during Input Source Type Detection.
Charge Complete
Any FAULT event in REG09
VINDPM / IINDPM event detected (maskable)
Top off timer starts and expires REG09[7:0] and REG0A[6:4] report charger operation faults and status change to the host. When a fault/status change occurs, the charger device sends out INT and keeps the state in REG09[7:0]/REG0A[6:4] until the host reads the registers. Before the host reads REG09[7:0]/REG0A[6:4] and all the ones are cleared, the charger device would not send any INT upon new fault/status change. To read the current status, the host has to read REG09/REG0A two times consecutively. The first read reports the pre-existing register status and the second read reports the current register status.

8.3.8.4 PMID Voltage Indicator (PMID_GOOD)

In BQ25619, the accessory devices is connected on PMID pin to get power from either adapter through Q1 or battery through boost mode. In boost mode, the device regulates PMID voltage around 5 V as a stable power supply to the accessory devices. However, when adapter plugs in, its voltage could be as high as 13.5 V. During the fault condition in the accessory device, its current could exceed the rating of the adapter. PMID_GOOD goes from HIGH to LOW when one of the following conditions is valid:

Q1 turns off when adapter is present.
PMID voltage exceeds 5.6 V (VOTG_OVP)
Q1 current exceeds 115% of the IINDPM threshold. (IBLK_OCP)
PMID voltage falls below VPOORSRC.
During OTG mode, when BATFET over current (IOTG_OCP_Q4) is detected. Once PMID_GOOD is asserted, host may take actions to disconnect the accessories from the PMID. The device will keep charging the battery if all the charge enable conditions are valid.

8.3.9 Protections

8.3.9.1 Voltage and Current Monitoring in Buck Mode

8.3.9.1.1 Input Over-Voltage Protection (ACOV)

The input voltage is sensed via the VAC pin and the ACDRV pin is used to control the external FET gate for bits. ACOV event will immediately stop converter switching whether in buck or boost mode. The device will automatically resume normal operation once the input voltage drops back below the OVP threshold. During input over-voltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host.

8.3.9.1.2 System Over-Voltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. SYSOVP threshold is about 300 mV above system regulation voltage. Upon SYSOVP, converter stops switching immediately to clamp the overshoot. The charger provides 30- mA discharge current to bring down the system voltage.

8.3.9.2 Voltage and Current Monitoring in Boost Mode

8.3.9.2.1 VBUS Soft Start

When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.

8.3.9.2.2 Boost Mode Over-Voltage Protection

When the PMID voltage rises above regulation target and exceeds VOTG_OVP, the device stops switching immediately and the device exits OTG mode OTG_CONFIG bit is set to 0. During boost over-voltage, the fault register bit BOOST_FAULT is set tot 1 to indicate fault in boost operation. An INT is asserted to the host.

8.3.9.2.3 PMID Over-Current Protection

The BQ25619 closely monitors the battery discharge current through BATFET (Q4) to ensure safe boost mode operation. During over-current condition when output current exceeds IOTG_OCP_Q4, the device stops converter in 100 µs. When over-current condition is detected, the fault register bit BOOST_FAULT is set high to indicate fault in boost operation. An INT is asserted to the host. If the over-current condition is removed, the boost converter returns to normal operation.

8.3.9.3 Thermal Regulation and Thermal Shutdown

8.3.9.3.1 Thermal Protection in Buck Mode

Besides the battery temperature monitor on TS pin, the device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high. Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface temperature exceeds TSHUT 150ºC. The BATFET and converter is enabled to recover when IC temperature is 130ºC. The fault register CHRG_FAULT is set to 1 during thermal shutdown and an INT is asserted to the host.

8.3.9.3.2 Thermal Protection in Boost Mode

Besides the battery temperature monitor on TS pin, The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC junction temperature exceeds TSHUT 150ºC, the boost mode is disabled by setting OTG_CONFIG bit low . When IC junction temperature is below 145ºC, the host can re-enable OTG mode.

8.3.9.4 Battery Protection

8.3.9.4.1 Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately stops switching. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.

8.3.9.4.2 Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL_FALL, the BATFET will latch off to protect battery from over discharge. To recover from over-discharge latch-off, an input source plug-in is required at VAC/VBUS.

8.3.9.4.3 System Over-Current Protection

IOTG_OCP_Q4 sets battery discharge current limit. Once IBAT>IOTG_OCP_Q4, charger will latch off Q4 and put the device into ship mode. All methods to exit ship mode are valid to bring the part out of Q4 latch off.

8.3.10 Serial Interface

addressed is considered a slave. 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). are HIGH. The SDA and SCL pins are open drain.

8.3.10.1 Data Validity

Figure 7. Bit Transfer on the I2C Bus

8.3.10.2 START and STOP Conditions

bus is considered busy after the START condition, and free after the STOP condition. Figure 8. TS START and STOP conditions

8.3.10.3 Byte Format

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Figure 9. Data Transfer on the I2C Bus

8.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.10.5 Slave Address and Data Direction Bit

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). Figure 10. Complete Data Transfer

8.3.10.6 Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state. Figure 11. Single Write Figure 12. Single Read

8.3.10.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0C.

Figure 13. Multi-Write Figure 14. Multi-Read

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode

registers are in the default settings. bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.

Figure 15. Watchdog Timer Flow Chart

8.5 Register Maps

Table 5. I2C Registers access types in this section. Table 6. I2C Access Type Codes

8.5.1 Input Current Limit Register (Address = 00h) [reset = 0Bh]

Figure 16. REG00 Register Table 7. REG00 Field Descriptions

7 EN_HIZ 0 R/W by REG_RST

6 TS_IGNORE 0 R/W by REG_RST

0 – Include TS pin into charge and OTG enable conditions. and OTG. NTC_FAULT bits are 000 to report normal status.

5 BATSNS_DIS 0 R/W by REG_RST

Select either BATSNS pin or BAT pin to regulate battery voltage. 1 – Disable BATSNS. Use BAT pin in battery CV regulation.

4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input current limit setting (maximum limit, not

input source detection is completed.

3 IINDPM[3] 0 R/W by REG_RST 800 mA

2 IINDPM[2] 1 R/W by REG_RST 400 mA

1 IINDPM[1] 1 R/W by REG_RST 200 mA

0 IINDPM[0] 1 R/W by REG_RST 100 mA

8.5.2 Charger Control 0 Register (Address = 01h) [reset = 1Ah]

Figure 17. REG01 Register Table 8. REG01 Field Descriptions

7 PFM _DIS 0 R/W by REG_RST

6 WD_RST 0 R/W by REG_RST

5 OTG_CONFIG 0 R/W by REG_RST

and CHG_CONFIG bit both to 1.

4 CHG_CONFIG 1 R/W by REG_RST

pin is pulled low, CHG_CONFIG bit is 1 and charge current is not zero. 3 SYS_MIN[2] 1 R/W by REG_RST System minimum voltage setting.

2 SYS_MIN[1] 0 R/W by REG_RST

1 SYS_MIN[0] 1 R/W by REG_RST

0 MIN_VBAT_SEL 0 R/W by REG_RST

Minimum battery voltage when exiting OTG boost mode.

8.5.3 Charge Current Limit Register (Address = 02h) [reset = 91h]

Figure 18. REG02 Register Table 9. REG02 Field Descriptions

7 Reserved

6 Q1_FULLON 0 R/W by REG_RST

is over 700 mA, Q1 is always fully on.

5 ICHG[5] 0 R/W by REG_RST

4 ICHG[4] 1 R/W by REG_RST

3 ICHG[3] 0 R/W by REG_RST

2 ICHG[2] 0 R/W by REG_RST

1 ICHG[1] 0 R/W by REG_RST

0 ICHG[0] 1 R/W by REG_RST

8.5.4 Precharge and Termination Current Limit Register (Address = 03h) [reset = 12h]

Figure 19. REG03 Register Table 10. REG03 Field Descriptions

7 IPRECHG[3] 0 R/W by REG_RST

6 IPRECHG[2] 0 R/W by REG_RST

5 IPRECHG[1] 0 R/W by REG_RST

4 IPRECHG[0] 1 R/W by REG_RST

3 ITERM[3] 0 R/W by REG_RST

2 ITERM[2] 0 R/W by REG_RST

1 ITERM[1] 1 R/W by REG_RST

0 ITERM[0] 0 R/W by REG_RST

8.5.5 Battery Voltage Limit Register (Address = 04h) [reset = 40h]

Figure 20. REG04 Register Table 11. REG04 Field Descriptions

7 VBATREG[4] 0 R/W by REG_RST

6 VBATREG[3] 1 R/W by REG_RST

5 VBATREG[2] 0 R/W by REG_RST

4 VBATREG[1] 0 R/W by REG_RST

3 VBATREG[0] 0 R/W by REG_RST

2 TOPOFF_TIMER[1] 0 R/W by REG_RST

1 TOPOFF_TIMER[0] 0 R/W by REG_RST

0 VRECHG 0 R/W

Battery recharge threshold setting.

8.5.6 Charger Control 1 Register (Address = 05h) [reset = 5Ch]

Figure 21. REG05 Register Table 12. REG05 Field Descriptions

7 EN_TERM 1 R/W by REG_RST

Battery charging termination enable.

6 Reserved 0 R/W by REG_RST

5 WATCHDOG[1] 0 R/W by REG_RST

4 WATCHDOG[0] 1 R/W by REG_RST

3 EN_TIMER 1 R/W by REG_RST

charge and pre-charge timers. Precharge timer is 2 hours.

2 CHG_TIMER 1 R/W by REG_RST

Battery fast charging safety timer setting.

1 TREG 1 R/W by REG_RST

0 JEITA_VSET (45C-60C) 0 R/W by REG_RST

8.5.7 Charger Control 2 Register (Address = 06h) [reset = E6h]

Figure 22. REG06 Register Table 13. REG06 Field Descriptions 7 OVP[1] 1 R/W by REG_RST VAC OVP threshold during buck mode and boost mode.

6 OVP[0] 1 R/W by REG_RST

5 BOOSTV[1] 1 R/W by REG_RST Boost regulation voltage setting

4 BOOSTV[0] 0 R/W by REG_RST

3 VINDPM[3] 0 R/W by REG_RST 800 mV VINDPM threshold setting

2 VINDPM[2] 1 R/W by REG_RST 400 mV

1 VINDPM[1] 1 R/W by REG_RST 200 mV

0 VINDPM[0] 0 R/W by REG_RST 100 mV

8.5.8 Charger Control 3 Register (Address = 07h) [reset = 4Ch]

Figure 23. REG07 Register Table 14. REG07 Field Descriptions

7 IINDET_EN 0 R/W by REG_RST

1 – Force input current limit detection when VBUS is present.

6 TMR2X_EN 1 R/W by REG_RST

0 – Disable. Safety timer duration is set by REG05[2].

5 BATFET_DIS 0 R/W by REG_RST

BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.

4 BATFET_RST_WVBUS 0 R/W by REG_RST

Start BATFET full system reset with or without adapter present. 1 – Start BATFET full system reset when adapter is present on VBUS.

3 BATFET_DLY 1 R/W by REG_RST

0 – Turn off BATFET immediately when BATFET_DIS bit is set.

2 BATFET_RST_EN 1 R/W by REG_RST

system reset is based on the setting of BATFET_RST_WVBUS bit. register value and VBAT + VINDPM_BAT_TRACK.

0 VINDPM_BAT_TRACK[0] 0 R/W by REG_RST

8.5.9 Charger Status 0 Register (Address = 08h)

Figure 24. REG08 Table 15. REG08 Field Descriptions

7 VBUS_STAT[2] x R NA VBUS Status register

6 VBUS_STAT[1] x R NA

5 VBUS_STAT[0] x R NA

4 CHRG_STAT[1] x R NA Charging status:

3 CHRG_STAT[0] x R NA

2 PG_STAT x R NA

1 THERM_STAT x R NA 0 – Not in thermal regulation

0 VSYS_STAT x R NA 0 – Not in VSYSMin regulation (BAT > VSYSMin)

8.5.10 Charger Status 1 Register (Address = 09h)

Figure 25. REG09 Register Table 16. REG09 Field Descriptions

7 WATCHDOG_FAULT 1 R NA 0 – Normal, device is in host mode,

1 – Watchdog timer expiration, device is in default mode.

6 BOOST_FAULT x R NA

5 CHRG_FAULT[1] x R NA 00 – Normal,

4 CHRG_FAULT[0] x R NA

3 BAT_FAULT x R NA 0 – Normal,

2 NTC_FAULT[2] x R NA TS fault in buck mode

1 NTC_FAULT[1] x R NA

0 NTC_FAULT[0] x R NA

8.5.11 Charger Status 2 Register (Address = 0Ah)

Figure 26. REG0A Register Table 17. REG0A Field Descriptions

7 VBUS_GD x R NA 0 – VBUS does not pass poor source detection

6 VINDPM_STAT x R NA 0 – Not in VINDPM

5 IINDPM_STAT x R NA 0 – Not in IINDPM

4 BATSNS_STAT x R NA

3 TOPOFF_ACTIVE x R NA 0 – Top off timer not counting.

2 ACOV_STAT x R NA 0 – Not in ACOV

1 VINDPM_INT_ MASK 0 R/W by REG_RST

0 IINDPM_INT_ MASK 0 R/W by REG_RST

8.5.12 Part Information Register (Address = 0Bh)

Figure 27. REG0B Register Table 18. REG0B Field Descriptions

7 REG_RST 0 R/W NA

returns to 0 after register reset is completed.

6 Reserved 0 R NA

5 Reserved 1 R NA

4 Reserved 0 R NA

3 Reserved 1 R NA

2 Reserved 1 R NA 1

1 Reserved 0 R NA

0 Reserved 0 R NA

8.5.13 Charger Control 4 Register (Address = 0Ch) [reset = 75h]

Figure 28. REG0C Table 19. REG0C Field Descriptions

7 JEITA_COOL_ISET [1] 0 R/W by REG_RST

percentage of ICHG in REG02[5:0].

6 JEITA_COOL_ISET [0] 1 R/W by REG_RST

5 JEITA_WARM_ISET [1] 1 R/W by REG_RST

as percentage of ICHG in REG02[5:0].

4 JEITA_WARM_ISET [0] 1 R/W by REG_RST

3 JEITA_VT2 [1] 0 R/W by REG_RST

1 JEITA_VT3 [1] 0 R/W by REG_RST

9 Application and Implementation

information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

A typical application consists of the device configured as an I2C controlled PowerPath management device and a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The device also integrates a bootstrap diode for the high-side gate drive.

9.2 Typical Application

Figure 29. BQ25619 Application Diagram with Optional PMOS

9.2.1 Design Requirements

Table 20. Design Parameters

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

frequency (fS) and the inductance (L). inductor size and efficiency for a practical design.

9.2.2.2 Input Capacitor

to 50% and can be estimated using Equation 4. preferred for 15-V input voltage. Capacitance of 22 μF is suggested for typical of 3-A charging current.

9.2.2.3 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current. Equation 5 shows the output capacitor RMS current ICOUT calculation.

ADVANCE□INFORMATION BQ25619 www.ti.com SLUSDF8 – JUNE 2019 Product Folder Links: BQ25619 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated The charger device has internal loop compensation optimized for >20-μF ceramic output capacitance. The preferred ceramic capacitor is 10-V rating, X7R or X5R.

10 Power Supply Recommendations

in order to provide an output voltage on SYS, the battery charger device requires a power supply between 3.9 V and 13.5 V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the charger to provide maximum output power to SYS.

11 Layout

11.1 Layout Guidelines

Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper

trace connection or GND plane.

Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC

ground with a short copper trace connection or GND plane.

Route analog ground separately from power ground. Connect analog ground and connect power ground

connection point. Or using a 0-Ω resistor to tie analog ground to power ground.

Use single ground connection to tie charger power ground to charger analog ground. Just beneath the

device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
Ensure that the number and sizes of vias allow enough copper for a given current path.

Application Report and QFN and SON PCB Attachment Application Report.

11.2 Layout Example

Figure 30. High Frequency Current Path

Figure 31. Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following: BQ25619 BMS025 Evaluation Module EVM User's Guide

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 4-Jul-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PQ25619RTWR ACTIVE WQFN RTW 24 3000 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated

Product Information

PQ25619RTWR specifications and overview.

Summary

BQ25619 I2C Controlled 1-Cell 1.5-A Battery Charger with 20-mA Termination and 1-A Boost Operation

Description

BQ25619 I2C Controlled 1-Cell 1.5-A Battery Charger with 20-mA Termination and 1-A Boost Operation

Source title PQ25619RTWR Datasheet(PDF) - Texas Instruments

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