PPSM82916VCER

TPSM82916_V01 TI | Alldatasheet

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Technical content

TPSM8291x 3V to 17V, 4.5A/6A, Low Noise and Low Ripple Buck Module With Integrated Ferrite Bead Filter Compensation

1 Features

• Low output 1/f noise < 20µVRMS (100Hz to 100kHz)
• Low output voltage ripple < 10µVRMS after ferrite bead
• High PSRR of > 65dB (up to 100kHz)
• 2.2MHz, 1.4MHz, or 1.0MHz fixed frequency peak current mode control
• Synchronizable with external clock (optional)
• Integrated loop compensation supports ferrite bead for second stage L-C filter with 30dB attenuation (optional)
• Spread spectrum modulation (optional)
• 3.0V to 17V input voltage range
• 0.8V to 5.5V output voltage range
• 25mΩ/7mΩ RDSon
• Output voltage accuracy of ±1% over temperature
• Precise enable input allows – User-defined undervoltage lockout – Exact sequencing
• Adjustable soft start
• Power-good output
• Output discharge (optional)
• –40°C to 125°C junction temperature range
• 4.0mm × 4.7mm × 3.0mm QFN
• Create a custom design using the TPSM8291x with the WEBENCH® Power Designer

2 Applications

• Telecom infrastructure
• Test and measurement
• Aerospace and defense (radar, avionics)
• Medical

3 Description

The TPSM8291x devices are a family of high- efficiency, low noise, and low ripple current mode synchronous buck modules. The devices are designed for noise sensitive applications that normally use an LDO for post regulation such as high-speed ADCs, clock and jitter cleaner, serializer, de-serializer, and radar applications. To reduce the output voltage ripple, the device loop compensation is designed to operate with an optional second-stage ferrite bead L-C filter. Low- frequency noise levels, similar to a low-noise LDO, are further achieved by filtering the internal voltage reference with a capacitor connected to the NR/SS pin. Combined, these features allow for an output voltage ripple below 10µVRMS. The device operates at a fixed switching frequency of 2.2MHz, 1.4MHz, or 1MHz , and can be synchronized to an external clock. An optional spread spectrum modulation scheme spreads the DC/DC switching frequency over a wider span, which lowers the mixing spurs. Device Information DEVICE NAME OUTPUT CURRENT PACKAGE(1) PACKAGE SIZE(2) TPSM82916 6A VCE (QFN- FCMOD, 16) 4.7mm × 4.0mm TPSM82914(3) 4.5A (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Product Preview information (not Advance Information). F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 4 . 5  V R M S C N R S S = 4 7 0 n F , 2 9 . 7  V R M S C N R S S = 2 . 2  F , 3 0 . 2  V R M S Output Noise Versus Frequency VoVin 3V to 17V VIN EN/SYNC VO 2 × 10µF Cin Cout 6 × 22µF FB S-CONF NR/SS VOUT 470 nF Cnr/ss Cf 1 × 22µF Lf Ferrite Bead 4.87k 2.43k PSNS PGND PG Typical Application ADVANCE INFORMATION TPSM82916 SLVSH49 – OCTOBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. 16-Pin VCE QFN-FCMOD Package (Top View) GND GND GND SW VIN BOOT PSNS NR/SS FB VIN EN S-CONF PG VO VIN VOUT Figure 4-2. 16-Pin VCE QFN-FCMOD Package (Bottom View) www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSM82916 ADVANCE INFORMATION

Table 4-1. Pin Functions PIN TYPE (1) DESCRIPTION NO. NAME 1, 13,

15 PGND — Power ground connection

2, 12,

16 VIN I Power supply input voltage pin

3 BOOT

(NC) I Supply for the internal high-side MOSFET gate driver. This pin is internally connected to a capacitor. Do not connect anything to this pin.

4 PSNS — Power sense ground, connect directly to GND plane

5 NR/SS O A capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.

6 FB O Feedback pin of the device

7 VOUT O VOUT pin. Connect to the recommend output capacitance. 8 VO I Output voltage sense pin. This pin must be connected directly after the first inductor. 9 PG O Open-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. This pin requires a pullup resistor to output a logic high. This pin can be left open or tied to GND if not used.

11 EN/SYNC I

Enable/Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device. This pin has an internal pulldown resistor of typically 500kΩ when the device is disabled. Apply a clock to this pin to synchronize the device

14 SW (NC) O

Switch pin of the power stage. This pin is internally connected to the SW of the converter and the inductor. Make these pads as small as possible under the device, and do not connect anything but a test node to the pad if desired. (1) I = input, O = output TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage(2) VIN, EN/SYNC, PG, S-CONF –0.3 18 V SW (DC) –0.3 VIN + 0.3 V SW (AC, less than 10ns)(3) –2.5 21 V BOOT –0.3 VIN + 6 BOOT to SW –0.3 6 VO, FB, NR/SS –0.3 6 V VSNS- –0.3 0.3 V Sink Current PG 10 mA TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to the network ground terminal. (3) While switching.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 3.0 17 V VOUT Output voltage 0.8 5.5 V CIN Effective input capacitance 5 10 µF COUT Effective output capacitance 80 120 200 µF Lf Effective filter inductance 0 10 50 nH Cf Effective filter capacitance 20 40 160 µF COUT + Cf Effective total output capacitance, including first and second L-C filter 80 400 µF IOUT Output current for TPSM82914 0 4.5 A IOUT Output current for TPSM82916 0 6 A TJ (1) Junction temperature –40 125 °C (1) Operating lifetime is derated at junction temperatures above 125°C. www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM82916 ADVANCE INFORMATION

5.4 Thermal Information

THERMAL METRIC(1) TPSM8291x UNITVCE 16-pin QFN-FCMOD JEDEC 51-7 PCB TPSM8291xEVM RθJA Junction-to-ambient thermal resistance TBD 25.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance TBD n/a (2) °C/W RθJB Junction-to-board thermal resistance TBD n/a (2) °C/W ΨJT Junction-to-top characterization parameter TBD TBD °C/W YJB Junction-to-board characterization parameter TBD TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) Not applicable to an EVM.

5.5 Electrical Characteristics

Over recommended input voltage range, TJ= –40℃ to 125℃. Typical values are at Vin = 12V and TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current EN = High, no load, device switching, fsw = 1MHz 5 mA ISD Shutdown current EN = GND, TJ = –40°C to 125°C 0.3 70 µA VUVLO Undervoltage lockout VIN rising, TJ = –40°C to 125°C 2.85 2.92 3.0 V VHYS Undervoltage lockout hysteresis 200 mV TJSD Thermal shutdown threshold TJ rising 170 °C Thermal shutdown hysteresis TJ falling 20 °C CONTROL and INTERFACE VH_EN High-level input-threshold voltage at EN/ SYNC 0.97 1.01 1.04 V VL_EN Low-level input-threshold voltage at EN/ SYNC 0.87 0.9 0.93 V VH_SYNC High-level input-threshold clock signal on EN/SYNC EN/SYNC = clock 1.1 V VL_SYNC Low-level input-threshold clock signal on EN/SYNC EN/SYNC = clock 0.4 V IEN,LKG Input leakage current into EN/SYNC EN/SYNC = GND or VIN, –40℃ ≤ TJ ≤ 125℃ 5 160 nA RPD Pulldown resistor on EN/SYNC EN/SYNC = Low 330 500 kΩ tdelay Enable delay time Time from EN/SYNC high to device starts switching, RS-CONF = 80.6kΩ 1 ms INR/SS NR/SS source current 67.5 75 82.5 µA RS-CONF S-CONF resistor step range accuracy RS-CONF tolerance for all settings according to S-CONF Table –4 +4 % VPG Power-good threshold VFB rising, referenced to VFB nominal 93 95 98 % VPG Power-good threshold VFB falling, referenced to VFB nominal 88 90 93 % VPG,OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V IPG,LKG Input leakage current into PG pin VPG = 5 V; –40℃ ≤ TJ ≤ 125℃ 5 500 nA tPG,DLY Power-good delay time VFB falling 8 µs OUTPUT ton Minimum on-time VIN ≥ 5V, Iout = 1A 35 ns toff Minimum off-time VIN ≥ 5V, Iout = 1A 50 ns TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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5.5 Electrical Characteristics (continued)

Over recommended input voltage range, TJ= –40℃ to 125℃. Typical values are at Vin = 12V and TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback regulation accuracy –40℃ ≤ TJ ≤ 125℃ 0.792 0.8 0.808 V IFB,LKG Input leakage current into FB VFB = 0.8V, –40℃ ≤ TJ ≤ 125℃ 1 70 nA IVO,LKG Input leakage current into VO VVO = 1.2V, –40℃ ≤ TJ ≤ 125℃ 0.01 30 µA PSRR Power supply rejection ratio VIN = 12V, 1.2VOUT, 1A, CNR/SS = 470nF, fsw = 1MHz, CFF = open, COUT = 4 × 22µF, f ≤ 100 kHz 65 dB PSRR Power supply rejection ratio VIN = 5V, 1.2VOUT, 1A, CNR/SS = 470nF, fsw = 2.2MHz, CFF = open, COUT = 4 × 22µF, f ≤ 100 kHz 70 dB VNRMS Output voltage RMS noise VIN = 12V, BW = 100Hz to 100kHz, CNR/ SS = 470nF, fSW = 1MHz, VOUT = 1.2V, CFF = open, COUT = 4 × 22µF 24.4 µVRMS VNRMS Output voltage RMS noise VIN = 5V, BW = 100Hz to 100kHz, CNR/ SS = 470nF, fSW = 2.2MHz, VOUT = 1.2V, CFF = open, COUT = 4 × 22µF 16.5 µVRMS Vopp Output ripple voltage at fSW VIN = 12V, fSW = 1MHz, VOUT = 1.2V, COUT = 4 × 22µF, Lf = 10nH, Cf = 22µF 36 µVRMS RDIS Output discharge resistance EN/SYNC = GND, VOUT = 1.2V, VIN ≥ 5V. 3.5 Ω RDIS Output discharge resistance EN/SYNC = GND, VOUT = 5V, VIN ≥ 5V. 16 Ω fSW Switching frequency 2.2MHz setting 1.98 2.2 2.42 MHz fSW Switching frequency 1.4MHz setting 1.26 1.4 1.54 MHz fSW Switching frequency 1MHz setting 0.9 1 1.18 MHz DSYNC Synchronization duty cycle 45 55 % tsync_elay Synchronization phase delay Phase delay from EN/SYNC rising edge to SW rising edge 90 ns ISWpeak Peak switch current limit TPSM82914 6.0 7.0 8.0 A ISWvalley Valley switch current limit TPSM82914 6.8 A ISWpeak Peak switch current limit TPSM82916 8.0 8.5 9.0 A ISWvalley Valley switch current limit TPSM82916 8.3 A Inegvalley Negative valley current limit –2.9 –2 A RDS(ON) High-side FET on-resistance VIN ≥ 5V 25 mΩ Low-side FET on-resistance VIN ≥ 5V 6.5 mΩ www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM82916 ADVANCE INFORMATION

5.6 Typical Characteristics

IN = 12V, VOUT = 1.2V, TA = 25°C, BOM = Table 7-1, (unless otherwise noted) 1  s / d i v V OUT (1 mV/div) 12V to 1.2V, 2A 1μH, 1MHz First L-C Only Figure 5-1. VOUT Ripple After the First L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 4 0 8 0 1 2 0 1 6 0 2 0 0 2 4 0 2 8 0 3 2 0 3 6 0 4 0 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 1.2V, 2A 1μH, 2MHz First L-C Only BW = 10kHz Figure 5-2. VOUT Ripple FFT After the First L-C Filter 1  s / d i v V OUT (1 mV/div) 12V to 1.2V, 2A 1μH, 1MHz First and second L-C Figure 5-3. VOUT Ripple After the Second L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 1 0 1 2 1 4 1 6 1 8 2 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 1.2V, 2A 1μH, 1MHz First and second L-C BW = 10kHz Figure 5-4. VOUT Ripple FFT After the Second L-C Filter 1  s / d i v V OUT (1 mV/div) 12V to 1.8V, 2A 1μH, 1.4MHz First L-C Only Figure 5-5. VOUT Ripple After the First L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 4 0 8 0 1 2 0 1 6 0 2 0 0 2 4 0 2 8 0 3 2 0 3 6 0 4 0 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 1.8V, 2A 1μH, 1.4MHz First L-C Only BW = 10kHz Figure 5-6. VOUT Ripple FFT After the First L-C Filter TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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5.6 Typical Characteristics (continued)

IN = 12V, VOUT = 1.2V, TA = 25°C, BOM = Table 7-1, (unless otherwise noted) 1  s / d i v V OUT (1 mV/div) 12V to 1.8V, 2A 1μH, 1.4MHz First and second L-C Figure 5-7. VOUT Ripple After the Second L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 1 0 1 2 1 4 1 6 1 8 2 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 1.8V, 2A 1μH, 1.4MHz First and second L-C BW = 10kHz Figure 5-8. VOUT Ripple FFT After the Second L-C Filter 4 0 0 n s / d i v V OUT (1 mV/div) 12V to 3.3V, 2A 1μH, 2.2MHz First L-C Only Figure 5-9. VOUT Ripple After the First L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 4 0 8 0 1 2 0 1 6 0 2 0 0 2 4 0 2 8 0 3 2 0 3 6 0 4 0 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 3.3V, 2A 1μH, 2.2MHz First L-C Only BW = 10kHz Figure 5-10. VOUT Ripple FFT After the First L-C Filter 4 0 0 n s / d i v V OUT (1 mV/div) 12V to 3.3V, 2A 1μH, 2.2MHz First and second L-C Figure 5-11. VOUT Ripple After the Second L-C Filter F r e q u e n c y ( H z ) V OUT Ripple (V RMS 0 x 1 0 2 x 1 0 4 x 1 0 6 x 1 0 8 x 1 0 1 x 1 0 1 0 1 2 1 4 1 6 1 8 2 0 S p r e a d S p e c t r u m M o d u l a t i o n O F F 12V to 3.3V, 2A 1μH, 2.2MHz First and second L-C BW = 10kHz Figure 5-12. VOUT Ripple FFT After the Second L-C Filter www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM82916 ADVANCE INFORMATION

IN = 12V, VOUT = 1.2V, TA = 25°C, BOM = Table 7-1, (unless otherwise noted) F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 4 4  V R M S C N R S S = 4 7 0 n F , 2 6 . 0  V R M S C N R S S = 2 . 2  F , 2 7 . 0  V R M S 12V to 1.2V 1μH, 1MHz First L-C Only NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-13. Output Noise Density vs Frequency F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 4 . 5  V R M S C N R S S = 4 7 0 n F , 2 9 . 7  V R M S C N R S S = 2 . 2  F , 3 0 . 2  V R M S 12V to 1.2V 1μH, 1MHz After ferrite bead filter NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-14. Output Noise Density vs Frequency F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 0  V R M S C N R S S = 4 7 0 n F , 2 0 . 6  V R M S C N R S S = 2 . 2  F , 2 0 . 0  V R M S 12V to 1.8V 1μH, 1.4MHz First L-C Only NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-15. Output Noise Density vs Frequency F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 9 . 8  V R M S C N R S S = 4 7 0 n F , 2 2 . 7  V R M S C N R S S = 2 . 2  F , 2 2 . 5  V R M S 12V to 1.8V 1μH, 1.4MHz After ferrite bead filter NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-16. Output Noise Density vs Frequency F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 4 . 1  V R M S C N R S S = 4 7 0 n F , 1 5 . 6  V R M S C N R S S = 2 . 2  F , 1 5 . 3  V R M S 12V to 3.3V 1μH, 2.2MHz First L-C Only NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-17. Output Noise Density vs Frequency F r e q u e n c y ( H z ) Noise Density (V/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 C N R S S = o p e n , 1 5 9  V R M S C N R S S = 4 7 0 n F , 1 5 . 9  V R M S C N R S S = 2 . 2  F , 1 5 . 9  V R M S 12V to 3.3V 1μH, 2.2MHz After ferrite bead filter NR/SS = Open, 470nF, 2.2μF, BW = 100Hz to 100kHz Figure 5-18. Output Noise Density vs Frequency TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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6 Detailed Description

6.1 Overview

The TPSM8291x low-noise, low-ripple, synchronous buck module is a fixed frequency current modemodule. The module has a filtered internal reference to achieve a low-noise output similar to low noise LDOs. The module achieves lower output voltage ripple by using a switching frequency of either 2.2MHz, 1.4MHz, or 1MHz and a larger inductance. The output voltage ripple can be further reduced by adding a small second stage L-C filter to the output. This can be a ferrite bead or a small inductor, followed by an output capacitor. Internal compensation maintains stability with an external filter inductor up to 50nH. To avoid voltage drops across this second stage filter, the device regulates the output voltage after the filter. The TPSM8291x family supports an optional spread spectrum modulation. When powering ADCs, for example, spread spectrum modulation reduces the mixing spurs. Switching frequency, spread spectrum modulation, and output discharge are set using the S-CONF pin.

6.2 Functional Block Diagram

0.8V Rf PSNS 1.0V Low Side Current Sense S-CONF ADC Start-up readout S-CONF Register Selection MODE MODE MODE MUX Spread Spectrum Modulation MODE Clock Detector Softstart GM GM Amplifier RPD EN/SYNC VIN VIN RDIS BOOT

1 MHz,

1.4 MHz, or

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6.3 Feature Description

6.3.1 Smart Config (S-CONF)

This S-CONF pin configures the device based on the resistor value. This pin is read after EN/SYNC goes high. The device configuration cannot be changed during operation. The S-CONF value is re-read if EN is pulled below 200mV or if VIN falls below UVLO. Table 6-1 shows the configuration options of switching frequency, spread spectrum modulation, output discharge, and synchronization. To make sure the internal circuit detects the resistor value correctly, minimize the distance between the resistor and the S-CONF pin and do not place any capacitors on the S-CONF pin. Table 6-1. S-CONF Device Configuration Modes S-CONF SWITCHING FREQUENCY SPREAD SPECTRUM OUTPUT DISCHARGE SYNC VIN 2.2MHz OFF OFF No GND 1MHz OFF OFF No 4.87kΩ 1.4MHz OFF OFF No 6.04kΩ 1.4MHz OFF OFF 1.2MHz to 1.6MHz 7.5kΩ 2.2MHz OFF OFF 1.9MHz to 2.42MHz 9.31 kΩ 1MHz OFF OFF 0.9MHz to 1.2MHz 11.5kΩ 1MHz Random OFF No 14.3kΩ 1.4MHz Random OFF No 18.2kΩ 2.2MHz Random OFF No 22.1kΩ 1MHz OFF ON No 27.4kΩ 1.4MHz OFF ON No 34kΩ 2.2MHz OFF ON No 42.2kΩ 1MHz OFF ON 0.9MHz to 1.2MHz 52.3kΩ 1.4MHz OFF ON 1.2MHz to 1.6MHz 64.9kΩ 2.2MHz OFF ON 1.9MHz to 2.42MHz 80.6kΩ 1MHz Random ON No 100kΩ 1.4MHz Random ON No 124kΩ 2.2MHz Random ON No TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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6.3.2 Device Enable (EN/SYNC)

The device is enabled by pulling the EN/SYNC pin high, and has an accurate rising threshold voltage of typically 1.01V. After the device is enabled, the operation mode is set by the configuration of the S-CONF pin. This action occurs during the device start-up delay time tdelay. After tdelay expires, the internal soft-start circuitry ramps up the output voltage over the soft-start time set by the CNR/SS capacitor. The start-up delay time tdelay varies depending on the selected S-CONF value. The start-up delay time is shortest with smaller S-CONF resistors. The EN/SYNC pin has an active pulldown resistor R PD. This resistor prevents an uncontrolled start-up of the device, in case the EN/SYNC pin cannot be driven to a low level. The pulldown resistor is disconnected after start-up. With EN set to a low level, the device enters shutdown and the pulldown resistor is activated again.

6.3.3 Device Synchronization (EN/SYNC)

The EN/SYNC pin is also used for device synchronization. After a clock signal is applied to this pin, the device is enabled and reads the configuration of the S-CONF pin. The external clock frequency must be within the clock synchronization frequency range set by the S-CONF pin. When the clock signal changes from a clock to a static high, then the device switches from external clock to internal clock. To shutdown the device when using an external clock, EN/SYNC must go low for at least 10µs. The clock signal can be a logic signal with a logic level as specified in the electrical table, and can be applied directly to the EN/SYNC pin. External logic, such as an AND gate, can be used to combine separate enable and clock inputs, as shown in Figure 6-1. Figure 6-1. Synchronization With Separate Enable Signal (Optional)

6.3.4 Spread Spectrum Modulation

Using the S-CONF pin enables or disables spread spectrum modulation. The DC/DC module generates an output voltage ripple at the switching frequency. When powering ADCs or an analog front-end (AFE), the switching frequency generates high frequency mixing spurs as well as a low frequency spur in the output frequency spectrum. Using the optional second stage L-C filter reduces the ripple of the module and spurs by up to 30dB. The device has an integrated random spread spectrum modulation (SSM) scheme, selected by the resistor connected to the S-CONF pin according to Table 6-1. Selecting random modulation to spread the switching frequency over a larger frequency range is possible. The modulation spread is +/– 10% of the device switching frequency. This SSM provides high attenuation when the receiver bandwidth is ≤ the modulation frequency, typically the case for systems using Fast Fourier Transforms (FFT) post processing as in high speed ADC applications. For applications sensitive to noise at the modulation frequency, random SSM is used. Using a random spread spectrum modulation also reduces the spurs in the output spectrum as shown in Figure 5-2. The randomized modulation uses a Fibonacci Linear-Feedback Shift Register (LFSR) so that every tone is generated once during the pseudo-random generation period. The frequency spreading is shown in Figure 6-2. www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM82916 ADVANCE INFORMATION

(single tone) fSW Unmodulated (single tone)Spectral envelope of triangular modulation (+/- 10% fSW) Spectral envelope of random modulation (+/- 10% fSW) Increased noise floor with random modulation Amplitude (dB) Figure 6-2. Spread Spectrum Modulation

6.3.5 Output Discharge

Output discharge is enabled or disabled, depending on the S-CONF setting. With output discharge enabled, the output voltage is pulled low by a discharge resistor RDIS of typically 7Ω. The output discharge function is enabled during thermal shutdown, UVLO, or when EN/SYNC is pulled low.

6.3.6 Undervoltage Lockout (UVLO)

To avoid misoperation of the device at low input voltages, the device is enabled after the input voltage is above the undervoltage lockout threshold. The device is disabled after the input voltage falls below the undervoltage threshold.

6.3.7 Power-Good Output

The device has a power-good output. The PG pin goes high impedance after the FB pin voltage is above 95% of the nominal voltage, and is driven low after the voltage falls below typically 90% of the nominal voltage. Table 6-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 10mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 18V. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other modules. If not used, the PG pin can be left floating or connected to GND. PG has a deglitch time of typically 8μs before going low. Table 6-2. Power-Good Pin Logic DEVICE STATE PG LOGIC STATUS HIGH IMPEDANCE LOW Enabled (EN/SYNC = High) VFB ≥ VPG √ VFB < VPG after tPG √ Shutdown (EN/SYNC = Low) √ UVLO 0.7V < VIN < VUVLO √ Thermal shutdown TJ > TJSD √ Power supply removal VIN < 0.7V √

6.3.8 Noise Reduction and Soft-Start Capacitor (NR/SS)

A capacitor connected to this pin reduces the low frequency noise of the module and sets the soft-start time. The larger the capacitor, the lower the noise and the longer the start-up time of the module. A 470nF capacitor is typically connected to this pin for a start-up time of 5ms, although longer and shorter start-up times can be used. During soft start with a light load, the device skips switching pulses as needed to not discharge the output voltage. The device can start into a prebiased output voltage. TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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The device achieves low noise by adding an R-C filter to the reference voltage, as shown in Section 6.2. During start-up, the NR/SS capacitor is charged with a constant current of 75µA (typical) to 0.8V. Larger NR/SS capacitors provide for lower low frequency noise. The maximum NR/SS cap is 3.3µF for a start-up time of 35ms. The minimum start-up time is set internally to 0.7ms, which occurs when there is a small NR/SS capacitor or no NR/SS capacitor.

6.3.9 Current Limit and Short-Circuit Protection

The device is protected against short circuits and overcurrent. The switch current limit prevents the device from high inductor current and from drawing excessive current from the input voltage rail. Excessive current can occur with a shorted, saturated inductor or a heavy load, shorted output circuit condition. If the inductor current reaches the threshold ISWpeak, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down the inductor current. The high-side MOSFET is turned on again only when the low-side current is below the low-side sourcing current limit ISWvalley. Due to internal propagation delay, the actual current can exceed the static current limit, especially if the input voltage is high and very small inductances are used. The dynamic current limit is calculated as follows in Equation 1: I PE AK t y p = I SW p eak + V L L × t PD (1) where

• ISWpeak is the static current limit, specified in Electrical Characteristics.
• L is the inductance, 1 uH internal.
• VL is the voltage across the inductor (VIN – VOUT).
• tPD is the internal propagation delay, typically 50ns. The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off. In this scenario, both MOSFETs are off until the start of the next cycle.

6.3.10 Thermal Shutdown

The device goes into thermal shutdown after the junction temperature exceeds typically 170°C with a 20°C hysteresis.

6.4 Device Functional Modes

6.4.1 Fixed Frequency Pulse Width Modulation

To minimize output voltage ripple, the device operates in fixed frequency PWM operation down to no load. The switching frequency of 1MHz, 1.4MHz, or 2.2MHz is selected using the S-CONF pin.

6.4.2 Low Duty Cycle Operation

For high input voltages or low output voltages, the 70ns minimum on-time limits the maximum input to output voltage difference and the switching frequency selected. When the minimum on-time is reached, the output voltage rises above the regulation point. Refer to Table 7-2 for detailed design recommendations.

6.4.3 High Duty Cycle Operation (100% Duty Cycle)

The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on. The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, is calculated as: V I N mi n = V OU T m i n + I OU T × R DS O N + R L (2) where

• VOUT(min) is the minimum output voltage the load can accept. www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM82916 ADVANCE INFORMATION

• IOUT is the output current.
• RDS(ON) is the RDS(ON) of the high-side MOSFET.
• RL is the DC resistance of the inductor used. To maintain fixed frequency switching, the device requires a minimum off-time of 50ns (typical), 60ns (maximum). If this limit is reached during a switching pulse, the device skips switching pulses to maintain output voltage regulation. If the input voltage decreases further, the device enters 100% mode.

6.4.4 Second Stage L-C Filter Compensation (Optional)

Most low-noise and low-ripple applications use a ferrite bead and bypass capacitor before the load. Using a second L-C filter is especially useful for low-noise and low-ripple applications with constant load current such as ADCs, DACs, and Jitter Cleaner. The second stage L-C filter is optional, and the device can be used without this filter. Without the filter, the device has a low output voltage noise of typically 16.9 μVRMS with an output voltage ripple of 280 μVRMS shown in Figure 5-10. The second stage L-C filter attenuates the output voltage ripple by another approximately 30dB shown in Figure 5-12 . To improve load regulation, the device can remote sense the output voltage after the second stage L-C filter and is internally compensated for the additional double pole generated by the L-C filter. To keep the second stage L-C filter as small as possible, the internal compensation is optimized for a 10nH to 50nH inductance. A small ferrite bead or even a PCB trace provides sufficient inductance for output voltage TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The TPSM8291x family of devices are designed for low noise and low output voltage ripple.

7.2 Typical Applications

1.2V / 6A Vin 12V VIN EN/SYNC VO 2 × 10µF Cin Cout 6 × 22µF FB S-CONF NR/SS VOUT 470 nF Cnr/ss Cf 1 × 22µF Lf Ferrite Bead 4.87k 2.43k PSNS PGND PG Figure 7-1. Typical Schematic Table 7-1 shows the list of recommended components for most applications. Table 7-1. List of Components REFERENCE PART NUMBER DESCRIPTION MANUFACTURER TPS8291x TPS8291x Low noise and low ripple buck module Texas Instruments CIN C2012X7S1E106K125AC Ceramic capacitors: 2 × 10µF ±10% 25V Ceramic Capacitor X7S 0805 TDK COUT C2012X7S1A226M125AC Ceramic capacitors: 6 × 22µF, 10V, ±20%, X7S, 0805 TDK Lf BLE32SN120SN1L Ferrite Bead MuRata Cf C2012X7S1A226M125AC Ceramic capacitor: 1 × 22µF, 10V, ±20%, X7S, 0805 TDK CNR/SS, CFF Ceramic capacitor Standard R1, R2, R3, R4 Resistor Standard www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM82916 ADVANCE INFORMATION

7.2.1 Design Requirements

The external components have to fulfill the needs of the application, but also meet the stability criteria of the control loop of the device. The device is designed to work within a range of external components, and can be optimized for efficiency, output ripple, component count, or lowest 1/f noise. Typical applications that have input voltages of ≤ 6V a 2.2MHz switching frequency. Applications that have input voltages > 6V can be optimized for efficiency using a 1MHz or 1.4MHz switching frequency depending on the output voltage. For the application cases that are not found in the following table, there are two methods to design the TPSM8291x circuit. Section 7.2.2.1 uses WEBENCH to design the circuit automatically or the calculations in Section 7.2.2.2 can be used instead. Table 7-2. Typical Single L-C Filter Design Recommendations DESIGN GOAL VIN VOUT FSW INDUCTOR OUTPUT CAPACITORS (2) Typical 12V(1) ≤ 1.4V(1) 1MHz 1µH 6 × 22µF, 10V, 0805 Typical 12V 1.4V < VOUT ≤ 2.2V 1.4MHz 1µH 6 × 22µF, 10V, 0805 Typical 12V > 2.2V 2.2MHz 1µH 8 × 22µF, 10V, 0805 Typical 5V ≤ 3.3V 2.2MHz 1µH 6 × 22µF, 10V, 0805 Typical 5V > 3.3V 2.2MHz 1µH 8 × 22µF, 10V, 0805 (1) The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70ns. This limit is especially (2) For output capacitor part numbers, see Table 7-4. The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20 μVRMS noise typically. A second stage filter is added to provide additional attenuation of the output ripple voltage. The output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to the following table for second stage L-C filter recommendations based on the output voltage. Table 7-3. Second Stage L-C (Ferrite Bead) Filter Design Recommendations VOUT (V) FERRITE BEAD IMPEDANCE (AT 100MHZ)(2) OUTPUT CAPACITORS (1) ≤ 2.2V 8 to 20Ω 1 × 22µF, 10V, 0805 > 2.2V 8 to 20Ω 2 × 22µF, 10V, 0805 (1) For output capacitor part numbers, see Table 7-4. (2) For second stage L-C filter part numbers, see Table 7-5.

7.2.2 Detailed Design Procedure

If the specific design is not found in Table 7-2, TI recommends WEBENCH to generate the design. Alternatively, follow the manual design procedure in Section 7.2.2.2.

7.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM8291x device with the WEBENCH Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost. 3. Open the advanced tab to optimize for output voltage ripple. 4. After in a TPSM8291x design, you can enable the second stage L-C filter and change other settings from the drop-down on the left. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

7.2.2.2 External Component Selection

7.2.2.2.1 Switching Frequency Selection

The switching frequency can be chosen to optimize efficiency (lower) or ripple noise (higher). Using the higher 1.4MHz or 2.2MHz setting increases the gain of the feedback loop and can result in lower output noise. However, additional considerations for minimum on-time and duty cycle must also be considered. First, calculate the duty cycle using Equation 3. Higher efficiency results in a shorter on-time, so a conservative approach is to use a higher efficiency than expected in the application. D = V O U T V I N × η (3) where:

• η = estimated efficiency (use the value from the efficiency curves or 0.9 as an conservative assumption) Then, calculate the on-time with 1MHz, 1.4MHz, and 2.2MHz using Equation 4. The on-time must always remain above the minimum on-time of 70ns. Use the maximum input voltage and maximum efficiency to determine the minimum duty cycle, Dmin. Use the maximum switching frequency for fSW. T ON = D m i n f SW _ mi n (4) then
• If tON_min minimum < 70ns with 2.2MHz, use 1.4MHz.
• If tON_min minimum < 70ns with 1.4MHz, use 1MHz
• If tON_min minimum < 70ns with 1MHz, reduce the maximum input voltage.
• If tON_min minimum ≥ 70ns, use a lower frequency for highest efficiency, or the highest frequency for the lowest noise and ripple.

7.2.2.2.2 Output Capacitor Selection

The effective output capacitance can range from 80 μF (minimum) up to 400 μF (maximum) for a single L-C system design. When using a second L-C filter, the first L-C filter must have output capacitance between 80μF and 160 μF, the second stage L-C filter (if used) must have at least 20 μF of capacitance, and the total capacitance for both L-C filters must be less than 400 μF. Load transient testing and measuring the bode plot are good ways to verify stability. Note For designs requiring cold temperature (< –10°C) operation, TI recommends to use a minimum effective output capacitance of 120μF for a single L-C system design or within the first L-C filter when using a second L-C filter design. TI recommends ceramic capacitors (X5R or X7R). Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitor carefully in combination with considering the package size and voltage rating. The ESR and ESL of the output capacitor are also important considerations in selecting the output capacitors for low noise applications. Smaller package sizes typically have lower ESL and ESR. TI recommends 0805 or smaller packages, as long as the packages provide the required capacitance and voltage rating for stable operation. Table 7-4 lists recommended output capacitors. Table 7-4. Recommended Output Capacitors CAPACITOR TYPE CAPACITOR VALUE MANUFACTURER VOLTAGE (V) PACKAGE Bulk Capacitor 22μF, X7S TDK C2012X7S1A226M125AC 10 0805 www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM82916 ADVANCE INFORMATION

Table 7-4. Recommended Output Capacitors (continued) CAPACITOR TYPE CAPACITOR VALUE MANUFACTURER VOLTAGE (V) PACKAGE Bulk Capacitor 47μF, X7R Murata GRM32ER71A476ME15L 10 1210

7.2.2.2.3 Ferrite Bead Selection for Second L-C Filter

Using a ferrite bead for the second stage L-C filter minimizes the external component count because most of the noise sensitive circuits use a RF bead for high frequency attenuation as a default component at the inputs. Make sure to select a ferrite bead with sufficiently high inductance at full load, and with low DC resistance (below 10mΩ) to keep the module efficiency as high as possible. The ferrite bead inductance decreases with increased load current. Therefore, the ferrite bead must have a current rating much higher than the desired load current. The recommendation is to choose a ferrite bead with an impedance of 8 Ω to 20Ω at 100MHz. Ferrite beads can be used in parallel if higher current is needed, however this can halve the inductance and filtering. Refer to Table 7-5 for possible ferrite beads. Table 7-5. Recommended Ferrite Beads PART NUMBER MANUFACTURER SIZE IMPEDANCE AT 100MHZ INDUCTANCE AT 100MHz (CALCULATED) DC RESISTANCE CURRENT RATING BLE18PS080SN1 MuRata 0603 8.5Ω 13.5 nH 4mΩ 5A BLE32SN120SN1L MuRata 1210 12Ω 18 nH 0.78mΩ 20A 74279221100 Wurth Elektronik 1206 10Ω 15.9 nH 3mΩ 10.5A 7427922808 Wurth Electronik 0603 8Ω 12.7 nH 5mΩ 9.5A The internal compensation has been designed to be stable with up to 50nH of inductance in the second stage filter. To achieve low ripple, the second L-C filter requires only 5nH to 10nH inductance. The inductance can be estimated from the ferrite bead impedance specification at 100MHz, with the assumption that the inductance is similar at the selected module switching frequency of 1MHz, 1.4MHz, or 2.2MHz, and can be verified through tools available on some manufacturer websites. Use Equation 5 to calculate the inductance of a ferrite bead: L = Ζ 2π × f (5) where

• Z is the impedance of the ferrite bead in ohms at the specified frequency (usually 100MHz).
• f is the specified frequency (usually 100MHz).

7.2.2.2.4 Input Capacitor Selection

For the best output and input voltage filtering, TI recommends X5R or X7R ceramic capacitors. The input bulk capacitor minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device. TI recommends a 10 μF or larger input capacitor. Having two in parallel further improves the input voltage ripple filtering, minimizing noise coupling into adjacent circuits. The voltage rating of the cap must also be taken into consideration, and must provide the required 5 μF minimum effective capacitance after DC bias derating. In addition to the bulk input cap, a smaller cap must be placed directly from the VIN pin to the PGND pin to minimize input loop parasitic inductance, thereby minimizing the high frequency noise of the device. The input cap placement affects the output noise, so care needs to be taken in placing both the bulk cap and bypass caps as shown in Section 7.4.2. Table 7-6 lists recommended input capacitors. Table 7-6. Recommended Input Capacitors INPUT CAP TYPE CAPACITOR VALUE MANUFACTURER VOLTAGE RATING (V) PACKAGE SIZE Bulk Cap 10μF, X7S TDK C2012X7S1E106K125AC 25 0805 TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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Table 7-6. Recommended Input Capacitors (continued) INPUT CAP TYPE CAPACITOR VALUE MANUFACTURER VOLTAGE RATING (V) PACKAGE SIZE Bypass Cap 2.2nF, X7R Murata GRM155R71E222KA01D 25 0402

7.2.2.2.5 Setting the Output Voltage

Choose resistors R1 and R2 to set the output voltage within a range of 0.8V to 5.5V, according to Equation 6. To keep the feedback network robust from noise, and to reduce the self-generated noise of resistors, set R2 equal to or lower than 5kΩ. Lower values of FB resistors achieve better noise immunity, and lower light load efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter analog design journal. R 1 = R 2 × V OU T V F B − 1 = R 2 × V OU T

0.8 V − 1 (6)

VOUT (V) R1 R2 0.9 604Ω 4.87kΩ 1.0 1.21kΩ 4.87kΩ 1.2 2.43kΩ 4.87kΩ 1.8 6.04kΩ 4.87kΩ 2.5 10.4kΩ 4.87kΩ 3.3 15.2kΩ 4.87kΩ 5 25.5kΩ 4.87kΩ A feedforward capacitor (C FF) is not required for proper operation, but can further improve output noise. However, care must be taken in choosing the C FF because the power-good (PG) function can not be valid with a large C FF during start-up, and can cause spurious triggering of the PG pin during a large load transient. Refer to the Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application report for a discussion of the pros and cons of using a feedforward capacitor.

7.2.2.2.6 NR/SS Capacitor Selection

As described in Section 6.3.8, the NR/SS cap affects both the total noise and the soft-start time. The recommended value for a 5ms soft-start time and good noise performance is 470nF. The maximum NR/SS cap is 3.3μF for a start-up time of 35ms. Values greater than 1μF have minimal improvement in noise performance. Use Equation 7 and Equation 8 to calculate the soft-start time based on desired soft-start time or the chosen capacitor value. t s s s = C NRS S × 0.8 V I N RSS (7) C NRS S F = I N RSS × t SS

0.8 V (8)

7.3 Power Supply Recommendations

The power supply to the TPSM8291x must have a current rating according to the supply voltage, output voltage, and output current of the TPSM8291x.

7.4 Layout

7.4.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching frequencies. Therefore, the PCB layout of the TPSM8291x demands careful attention to make sure of best performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter analog www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM82916 ADVANCE INFORMATION

design journal for a detailed discussion of general best practices. Specific recommendations for the device are listed below.

• Place the input capacitor or capacitors as close as possible to the VIN and PGND pins of the device. This placement is the most critical component placement. Route the input capacitors directly to the VIN and PGND pins avoiding vias.
• Place the output capacitor ground close to the PGND pin and route directly avoiding vias. Minimize the length of the connection from the inductor to the output capacitor.
• Connect the VO pin directly to the first output capacitor, COUT.
• Connect sensitive traces, such as the connections to the NR/SS, VO, and FB pins with short traces and be routed away from any noise source, such as the SW pin.
• Connect the PSNS pin directly to the system GND plane with a via.
• Place the second L-C filter, Lf and Cf, near the load to reduce any radiated coupling around the second L-C filter
• Avoid placing the ferrite bead in the keep out region as shown in Figure 7-3
• Place the FB resistors, R1 and R2, close to the FB pin and route the VOUT connection from R1 to the load as a remote sense trace. If a second L-C filter is used, this connection must be made after Lf.
• See the recommended layout implemented on the EVM and shown in the EVM user's guide, TPS62916EVM Evaluation Module, as well as in Figure 7-3.

7.4.2 Layout Example

Figure 7-2. Recommended Layout for Single L-C Filter Note The red dot indicates where the feedback sense must be placed for the best DC regulation. For a single L-C configuration, the feedback sense is placed near the VOUT capacitors. For a second L-C filter design, the feedback sense is placed near the load after the VOUT_FILT capacitors. TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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Figure 7-3. Recommended Layout for Design with Second L-C Filter Note The ferrite bead can be placed closer to the device as long as the ferrite bead is not placed between the inductor and output capacitors. Placing the ferrite bead further away avoids capacitive and electromagnetic coupling to the output of the ferrite bead. If the ferrite bead is placed in the keep out area, the filtering effect of the ferrite bead is greatly reduced. If the ferrite bead is routed through a via to the back side of the board, make sure adequate ground plane between the layers if the ferrite bead are in this area. www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM82916 ADVANCE INFORMATION

8 Device and Documentation Support

8.1 Device Support

8.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

8.1.2 Development Support

8.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM8291x device with the WEBENCH Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost. 3. Open the advanced tab to optimize for output voltage ripple. 4. After in a TPSM8291x design, you can enable the second stage L-C filter and change other settings from the drop-down on the left. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application report
• Texas Instruments, TPS62916EVM Evaluation Module EVM user's guide
• Texas Instruments, Five Steps to a Great PCB Layout for a Step-Down Converter analog design journal
• Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter analog design journal

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2024 * Initial Release

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM82916 ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE C 4.13.9 4.84.6 3.12.8 12X 0.550.45 1.7780.052.2250.05 2.2250.05 2X 0.65.000 PKG 02X 0.65 1.1250.05 1.1250.0510.05 10.05 0.80.050.80.05 1.1250.05 1.1250.05 (0.095)0.010.00 0.9750.855 (0.125) TYP QFN-FCMOD - 3.1 mm max heightVCE0016APLASTIC SMALL OUTLINE - NO LEAD 4230263/B 06/2024 0.08C 1516 PIN 1 INDEX AREA DESIGNATED LASERMARKING AREATEXT HEIGHT TO BE150 um MINIMUM SEATING PLANE PIN 1 ID(45X 0.125)1 6 8 1314 0.1CAB0.05C SEE DETAIL A SCALE 3.000 A45.000 DETAIL ATYPICAL AB TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP 0.07 MAXALL AROUND0.07 MINALL AROUND .000 PKG 0 .000 PKG 0 3X ()2.55 4X ()2.225()1.778 ()1.85 ()1.85 ()1.125 ()1.125 2X ()0.65 2X ()0.65 ()1.125 ()1.125 ()0.04 ()1.09 (0.3) (0.6) (2) (1.6) 3X ()1.9 3X ()2.002 2X ()0.875 2X ()0.875 ()0.55 ()0.55 (0.2) TYPVIA 6X (0.2) QFN-FCMOD - 3.1 mm max heightVCE0016APLASTIC SMALL OUTLINE - NO LEAD LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X SEE SOLDER MASKDETAILS1 6 8 METAL EDGESOLDER MASKOPENINGEXPOSED METAL METAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DEFINEDSOLDER MASK DETAILS www.ti.com TPSM82916 SLVSH49 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM82916 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 ()0.04 ()1.09(0.57) (0.3)(1.8) (1.47) ()1.85 ()0.65 ()0.65 ()1.85 ()1.035 ()1.035 ()1.015 ()1.0156X (0.2) QFN-FCMOD - 3.1 mm max heightVCE0016APLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLEBASED ON 0.100 MM THICK STENCILSCALE: 20X PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGEPADS: 7 & 14: 85%PAD 15: 87 %PAD 16: 90% 6 8 TPSM82916 SLVSH49 – OCTOBER 2024 www.ti.com

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www.ti.com 18-Nov-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPSM82916VCER ACTIVE QFN-FCMOD VCE 16 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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