PPS7A2118PQWDSGRQ1

TPS7A21-Q1_V02 TI | Alldatasheet

Document overview

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Technical content

TPS7A21-Q1 Automotive, 500mA, Low-Noise, Low-IQ, High-PSRR LDO

1 Features

• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C – Junction temperature: –40°C to +150°C
• Very low IQ: 6.5μA
• Input voltage range: 2.0V to 6.0V
• Output voltage range: 0.8V to 5.5V (50mV steps)
• High PSRR: 91dB at 1kHz
• Low output voltage noise: 7.7μVRMS
• Low dropout: – 265mV (maximum) at 500mA (2.5V VOUT)
• Smart EN pulldown
• Output voltage tolerance: ±1% at 1mA IOUT
• Supports a wide range of ceramic capacitors: – 1µF to 200µF
• Package: – 3mm × 3mm wettable flank VSON – 2mm × 2mm wettable flank WSON (Advance Information) – 2mm × 2mm WSON (Advance Information)

2 Applications

• DAS cameras and radar
• Automotive infotainment
• Telematics systems
• Navigation systems Simplified Schematic

3 Description

The TPS7A21-Q1 is a small, low-dropout (LDO) linear voltage regulator that sources 500mA of output current. The device provides low noise, high PSRR, and excellent load and line transient performance to meet the requirements of RF and other sensitive analog circuits in automotive applications. Innovative design techniques result in low-noise performance without the addition of an external noise bypass capacitor. The TPS7A21-Q1 low quiescent current is a good choice for low-power systems. The 2.0V to 6.0V input voltage range and 0.8V to 5.5V output voltage range support a variety of system requirements. The maximum output voltage tolerance is 1.5%, –2.25% over load, line, and temperature variations. An internal soft-start circuit helps control inrush current, thus minimizing the input voltage drop during start-up. The LDO is stable with small ceramic capacitors, allowing for a small overall solution size. A smart enable input circuit with an internally controlled pulldown resistor keeps the LDO disabled even when the EN pin is unconnected. This circuit also helps eliminate external components that are otherwise required to pull down the EN input.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TPS7A21-Q1 DRB (Wettable flank VSON, 8) 3mm × 3mm DSG (Wettable flank WSON, 8)(3) 2mm × 2mm DSG (WSON, 8)(3) 2mm × 2mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Advance Information (not Production Data). TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

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4 Pin Configuration and Functions

1 OUT 8 IN

2 NC 7 NC

3 NC 6 NC

4 GND 5 EN

Figure 4-1. DRB Package, 8-Pin Fixed VSON (Top View) IN IN NC EN OUT OUT NC GND Thermal Pad Not to scale Figure 4-2. DSG Package (DSG0008B, Advance Information), 8-Pin Fixed WSON (Top View) NC NC OUT OUT GND EN IN IN Thermal Pad Not to scale Figure 4-3. DSG Package (DSG0008A, Advance Information), 8-Pin Fixed WSON C Version (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME DRB DSG0008B DSG0008A (C Version) EN 5 5 2 I Enable pin. Drive EN greater than VEN(HI) to turn on the regulator. Drive EN less than VEN(LO) to put the low-dropout regulator (LDO) into shutdown mode. GND 4 4 1 — Ground pin. IN 8 7, 8 3, 4 I Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table and the Input and Output Capacitor Requirements section. Place the input capacitor as close to the output of the device as possible. NC 2, 3, 6, 7 3, 6 7, 8 — No internal connection. Ground this pin for better thermal performance. OUT 1 1, 2 5, 6 O Regulated output voltage pin. Connect a low-equivalent series resistance (ESR) capacitor to this pin. For best transient response, use the nominal recommended value or larger capacitor from OUT to GND. An internal pulldown resistor prevents a charge from remaining on OUT when the regulator is in shutdown mode (VEN < VEN (LOW)). Thermal Pad The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance. (1) I = input, O = output, NC = no connect. www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS7A21-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (3) MIN MAX UNIT VIN Input voltage –0.3 6.5 V VOUT Output voltage –0.3 Lesser of VIN + 0.3, or 6.5 V VEN Enable input voltage –0.3 6.5 V Maximum output current(3) Internally limited A TJ Operating junction temperature -40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltages are with respect to the GND pin. (3) Internal thermal shutdown circuitry helps protect the device from permanent damage.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over the operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT VIN Input supply voltage 2.0 6.0 V VEN Enable input voltage 0 6.0 V VOUT Nominal output voltage range 0.8 5.5 V IOUT Output current 0 500 mA CIN Input capacitor(2) 1 µF COUT Output capacitor(3) 1 200 µF ESR Output capacitor effective series resistance 100 mΩ TJ Operating junction temperature –40 150 °C (1) All voltages are with respect to the GND pin. (2) An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47μF minimum is recommended to counteract the effect of source resistance and inductance, which in some cases causes symptoms of system- level instability such as ringing or oscillation, especially in the presence of load transients. (3) Effective output capacitance of 0.4μF minimum and 200μF maximum over all temperature and voltage conditions is required for stability with ESR values as high as 100mΩ. If the ESR is reduced to 20mΩ or lower, stable operation is achieved with effective output capacitance as low as 0.3μF. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) TPS7A21-Q1 UNITDRB (VSON) DSG (WSON)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 58.9 77.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 76.3 109.0 °C/W RθJB Junction-to-board thermal resistance 31.8 44.5 °C/W ψJT Junction-to-top characterization parameter 6.3 7.2 °C/W ψJB Junction-to-board characterization parameter 31.8 44.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 13.3 17.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics and An empirical analysis of the impact of board layout on LDO thermal performance application notes.

5.5 Electrical Characteristics

specified over operating temperature range (TJ = –40℃ to +150℃), VIN = VOUT(NOM) + 0.3V or 2V, whichever is greater, VEN = 1.0V, IOUT = 1mA, CIN = 1µF, COUT = 1µF (unless otherwise noted); all typical values are at TJ = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔVOUT Output voltage tolerance VIN = (VOUT(NOM) + 0.3V) to 6.0V, IOUT = 1mA to 500mA, VOUT ≥ 3.3V –2.25 1.5 VIN = (VOUT(NOM) + 0.3 V) to 6.0V, IOUT = 1mA to 500mA, 2.8V ≤ VOUT < 3.3V –2.5 1.5 VIN = (VOUT(NOM) + 0.3V) to 6.0V, IOUT = 1mA VOUT ≥ 2.8V –1 1 VIN = (VOUT(NOM) + 0.3V) to 6.0V, IOUT = 1mA to 500mA, VOUT < 2.8V –70 50 mV VIN = (VOUT(NOM) + 0.3V) to 6.0V, IOUT = 1mA VOUT < 2.8V –50 50 ΔVOUT Line regulation VIN = (VOUT(NOM) + 0.3V) to 6.0V, IOUT = 1mA 0.03 %/V ΔVOUT Load regulation IOUT = 1mA to 500mA 0.003 %/mA IGND Quiescent current VEN = VIN, VIN = 6.0V, IOUT = 0mA TJ = 25°C 6.5 9 µA TJ = –40°C to 85°C 11 TJ = –40°C to 125°C 15 TJ = –40°C to 150°C 18 VEN = VIN, VIN = 6.0V, IOUT = 500mA 2300 3500 ISHTDWN Shutdown current VEN = 0V (disabled), VIN = 6.0V, TJ = 25°C 0.15 1 µA VEN = 0V (disabled), VIN = 6.0V, TJ = –40°C to 150°C 10 IQ(DO) Quiescent current in dropout VIN ≤ VOUT(NOM), IOUT = 0mA 7 15 µA VDO Dropout voltage IOUT = 500mA, VOUT = 95% × VOUT(NOM) 0.8V ≤ VOUT < 1.0V (1) 825 mV 1.0V ≤ VOUT < 1.2V (1) 605 1.2V ≤ VOUT < 1.5V (1) 470 1.5V ≤ VOUT < 2.5V 355 2.5V ≤ VOUT ≤ 5.5V 265 ICL Output current limit VOUT = 0.9 × VOUT(NOM) 650 1060 1500 mA ISC Short-circuit current limit VOUT = 0 V 325 mA www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS7A21-Q1

5.5 Electrical Characteristics (continued)

specified over operating temperature range (TJ = –40℃ to +150℃), VIN = VOUT(NOM) + 0.3V or 2V, whichever is greater, VEN = 1.0V, IOUT = 1mA, CIN = 1µF, COUT = 1µF (unless otherwise noted); all typical values are at TJ = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Power-supply rejection ratio IOUT = 20mA, VIN = VOUT + 1.0 V f = 100Hz 90 dB f = 1kHz 91 f = 10kHz 71 f = 100kHz 61 f = 1MHz 50 IOUT = 500mA, VIN = VOUT + 1.0 V f = 100Hz 65 f = 1kHz 85 f = 10kHz 79 f = 100kHz 44 f = 1MHz 50 VN Output noise voltage BW = 10Hz to 100kHz, VOUT = 2.8V IOUT = 500mA 7.7 µVRMS IOUT = 1mA 10 RPULLDOWN Output automatic discharge pulldown resistance VIN = 2V, VEN < VIL (output disabled) 150 Ω TSD Thermal shutdown rising TJ rising 165 Thermal shutdown falling TJ falling 140 VEN(LOW) Low input threshold VIN = 2.0V to 6.0V, VEN falling until the output is disabled 0.3 V VEN(HI) High input threshold VIN = 2.0V to 6.0V, VEN rising until the output is enabled 0.9 V VUVLO UVLO threshold VIN rising 1.11 1.32 1.63 V VIN falling 1.05 1.27 1.57 VUVLO(HYST) UVLO hysteresis 50 mV IEN EN pin leakage current VEN = 6.0V and VIN = 6.0V 100 250 nA REN(PULL- DOWN) Smart enable pulldown resistor 440 kΩ tON Turnon time From VEN > VIH to VOUT = 95% of VOUT(NOM) 120 200 280 µs (1) Dropout voltages for VOUT values below or very near the UVLO threshold are not measured directly. Values shown are verified by simulation. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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5.6 Typical Characteristics

at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) VEN = 1V Figure 5-1. Output Voltage Accuracy vs IOUT VEN = 1V Figure 5-2. Output Voltage Accuracy vs IOUT VEN = 1V Figure 5-3. Output Voltage Accuracy vs VIN VEN = 1V Figure 5-4. Line Regulation vs VIN Output Current (mA) Change in Output Voltage (mV) 0 50 100 150 200 250 300 350 400 450 500 Load TJ -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C VEN = 1V Figure 5-5. Load Regulation vs IOUT Output Current (mA) Dropout Voltage (mV) 0 50 100 150 200 250 300 350 400 450 500 100 110 120 130 140 150 160 TJ -55°C -40°C 0°C 25°C 85°C 125°C 150°C VEN = 1V Figure 5-6. Dropout Voltage vs IOUT www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS7A21-Q1

5.6 Typical Characteristics (continued)

at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) Output Current (mA) Dropout Voltage (mV) TJ -55°C -40°C 0°C 25°C 85°C 125°C 150°C VEN = 1V Figure 5-7. Dropout Voltage vs IOUT VEN = VIN Figure 5-8. IQ vs VIN VEN = 1V Figure 5-9. IQ vs VIN VEN = 1V Figure 5-10. IGND vs IOUT VEN = 1V Figure 5-11. IGND vs IOUT Input Voltage (V) Quiescent Current in Shutdown (nA) -10 TJ VEN = 0V, IOUT = 0mA Figure 5-12. Shutdown Current vs VIN TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) Input Voltage (V) Quiescent Current in Shutdown (nA) 500 1000 1500 2000 2500 3000 TJ 85°C 125°C 150°C VEN = 0V, IOUT = 0mA Figure 5-13. Shutdown Current vs VIN Output Current (mA) Output Voltage (V) 0 200 400 600 800 1000 1200 1400 0.5 1.5 2.5 3.5 4.5 TJ -55°C -40°C 0°C 25°C 85°C 125°C 150°C VEN = 1V Figure 5-14. Foldback Current Limit Figure 5-15. Enable Logic Threshold vs Temperature VEN - VIN (V) Enable Pin Leakage Current (nA) 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 TJ -55°C -40°C 0°C 25°C 85°C 125°C 150°C VEN = 6V, IOUT = 0mA Figure 5-16. Enable Pin Leakage Current vs VEN – VIN VEN = 0.3V Figure 5-17. Smart Enable Pulldown Resistor vs Temperature and VIN VEN = 0.3V Figure 5-18. Output Pulldown Resistance vs Temperature and VIN www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS7A21-Q1

at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) VEN = 1V Figure 5-19. VIN UVLO Threshold vs Temperature VIN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 500mA Figure 5-20. Start-Up With VEN Before VIN VIN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 0mA Figure 5-21. Start-Up With VEN After VIN VIN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 500mA Figure 5-22. Start-Up With VEN After VIN VIN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 500mA Figure 5-23. Start-Up With VEN = VIN VIN = 4.3V, VEN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 0mA, COUT = 1μF Figure 5-24. Start-Up Inrush Current TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) VIN = 4.3V, VEN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 0mA, COUT = 10μF Figure 5-25. Start-Up Inrush Current VEN = VEN(HI) to VOUT = 95% of VOUT(NOM), IOUT = 0mA Figure 5-26. Start-Up Turn-On Time vs Temperature Time (µs) AC-Coupled Output Voltage (mV) Input Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 6 VOUT VIN VEN = VIN, tr = tf = 5μs, IOUT = 500mA Figure 5-27. Line Transient From 3.6V to 4.6V Time (µs) AC-Coupled Output Voltage (mV) Input Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 6 VOUT VIN VEN = VIN, tr = tf = 5μs, IOUT = 1mA Figure 5-28. Line Transient From 3.6V to 4.6V VEN = VIN, tr = tf = 1μs Figure 5-29. Load Transient From 1mA to 500mA VEN = VIN, tr = tf = 200ns Figure 5-30. Load Transient From 1mA to 500mA www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS7A21-Q1

at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) VEN = VIN, tr = tf = 1μs Figure 5-31. Load Transient From 0mA to 500mA VEN = VIN, tr = tf = 200ns Figure 5-32. Load Transient From 0mA to 500mA VEN = VIN Figure 5-33. PSRR vs Frequency and IOUT VEN = VIN, IOUT = 20mA Figure 5-34. PSRR vs Frequency and VIN VEN = VIN, IOUT = 500mA Figure 5-35. PSRR vs Frequency and VIN VEN = VIN, IOUT = 20mA Figure 5-36. PSRR vs Frequency and COUT TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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at VIN = 3.6V, VOUT = 3.3V, IOUT = 1mA, CIN = 1µF, COUT = 1µF, and TA = 25°C (unless otherwise noted) VEN = VIN, IOUT = 500mA Figure 5-37. PSRR vs Frequency and COUT Frequency (Hz) Output Voltage Noise (VHz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 10 100 1k 10k 100k 1M 10M VIN 3.6 V, RMS Noise = 6.73 VRMS 4.75 V, RMS Noise = 6.70 VRMS 6.0 V, RMS Noise = 6.65 VRMS VEN = VIN, IOUT = 20mA Figure 5-38. Noise vs Frequency and VIN Frequency (Hz) Output Voltage Noise (VHz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 5 5 10 100 1k 10k 100k 1M 10M VIN 3.6 V, RMS Noise = 6.90 VRMS 4.75 V, RMS Noise = 7.32 VRMS 6.0 V, RMS Noise = 11.54 VRMS VEN = VIN, IOUT = 500mA Figure 5-39. Noise vs Frequency and VIN VEN = VIN Figure 5-40. Noise vs Frequency and IOUT Frequency (Hz) Output voltage Noise (VHz) 0.001 0.002 0.003 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 10 100 1k 10k 100k 1M 10M COUT 0.47 µF, RMS Noise = 6.63 VRMS 1.0 µF, RMS Noise = 6.71 VRMS 10 µF, RMS Noise = 7.20 VRMS 200 uF, RMS Noise = 7.69 VRMS VEN = VIN, IOUT = 20mA Figure 5-41. Noise vs Frequency and COUT Frequency (Hz) Output voltage Noise (VHz) 0.001 0.002 0.003 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 10 100 1k 10k 100k 1M 10M COUT 0.47 µF, RMS Noise = 6.84 VRMS 1.0 µF, RMS Noise = 6.96 VRMS 10 µF, RMS Noise = 7.16 VRMS 200 uF, RMS Noise = 8.74 VRMS VEN = VIN, IOUT = 500mA Figure 5-42. Noise vs Frequency and COUT www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS7A21-Q1

6 Detailed Description

6.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the TPS7A21-Q1 provides low noise, high PSRR, low quiescent current, and excellent line and load transient response. The TPS7A21-Q1 achieves excellent noise performance without the need for a separate noise filter capacitor. The TPS7A21-Q1 is designed to operate properly with a single 1µF input capacitor and a single 1µF ceramic output capacitor. Make sure the effective output capacitance is at least 0.4µF across all operating voltage and temperature conditions.

6.2 Functional Block Diagram

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6.3 Feature Description

6.3.1 Smart Enable (EN)

The enable pin (EN) is active high. The output is enabled when the voltage applied to EN is greater than V EN(HI) and disabled when the applied voltage is less than V EN(LOW). If external control of the output voltage is not needed, connect EN to IN. This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven above V EN(HI), the output is enabled and the smart enable internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the R EN(PULLDOWN) is connected and pulls the enable pin low to disable the output. In addition to reducing quiescent current, the smart pulldown helps make sure that the logic level is correct even when EN is driven from a source that has limited current drive capability. The REN(PULLDOWN) value is listed in the Electrical Characteristics table.

6.3.2 Low Output Noise

Any internal noise at the TPS7A21-Q1 reference voltage is reduced by a first-order, low-pass RC filter before being passed to the output buffer stage. The low-pass RC filter has a –3dB cutoff frequency of approximately 0.1Hz. During start-up, the filter resistor is bypassed to reduce output rise time. The filter begins normal operation after the output voltage reaches the nominal value.

6.3.3 Active Discharge

The regulator has an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that connects a pulldown resistor between the output and ground pins when the device is disabled to actively discharge the output voltage. Make sure the voltage on IN is high enough to turn on the pulldown MOSFET. When V IN is too low to provide sufficient V GS on the pulldown MOSFET, the pulldown circuit is not active. The active discharge circuit is activated by the enable pin, or by the voltage on IN falling below the undervoltage lockout (UVLO) threshold. Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply collapses. Reverse current potentially flows from the output to the input. This reverse current flow potentially causes damage to the device. Limit any such transient reverse current to no more than 5% of the device rated current.

6.3.4 Dropout Voltage

Dropout voltage (VDO) is defined as the input voltage minus the output voltage (V IN – VOUT) at the rated output current (IRATED), when the pass transistor is fully on. I RATED is the maximum I OUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the value required to support output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (R DS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. Equation 1 calculates the RDS(ON) of the device. R =DS(ON) VDO IRA TED (1)

6.3.5 Foldback Current Limit

The TPS7A21-Q1 has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the output voltage above V FOLDBACK, the brick-wall scheme limits the output current to the current limit (I CL). When the output voltage drops below V FOLDBACK, a foldback current limit activates that scales back the current when the output voltage approaches GND. When the output is shorted, the www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS7A21-Q1

device supplies a typical current called the short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the regulator begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(V IN – VOUT) × ICL]. When the output is shorted and the output voltage is less than V FOLDBACK, the pass transistor dissipates power [(V IN – V OUT) × I SC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition persists, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. Figure 6-1 shows a diagram of the foldback current limit. VOUT(NOM) 0 V 0 mA VOUT VFOLDBACK ICLISC IRATED IOUT Brickwall Foldback Figure 6-1. Foldback Current Limit

6.3.6 Undervoltage Lockout

An independent undervoltage lockout (UVLO) circuit monitors the input voltage, allowing a controlled and consistent turn on and turn off of the output voltage. If the input voltage drops during load transients (when the device output is enabled), the UVLO has built-in hysteresis to prevent unwanted turn off.

6.3.7 Thermal Overload Protection (TSD)

Thermal shutdown disables the output when the junction temperature T J rises to the shutdown temperature threshold TSD. The thermal shutdown circuit hysteresis requires the temperature to fall to a lower temperature before turning on again. The thermal time constant of the semiconductor die is fairly short. Thus, the device cycles on and off when thermal shutdown is reached until power dissipation is reduced. High power dissipation occurs during start up from large V IN – V OUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the regulator to exceed operational specifications. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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Although the thermal shutdown circuitry is designed to protect against temporary thermal overload conditions, this circuitry is not intended to replace proper thermal design. Continuously running the regulator into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

6.4 Device Functional Modes

6.4.1 Device Functional Mode Comparison

Table 6-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 6-1. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VEN IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN ≥ VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN ≥ VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VEN ≤ VEN(LOW) Not applicable TJ ≥ TSD(shutdown)

6.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold

6.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, V IN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (V OUT(NOM) + V DO), the output voltage overshoots for a short period of time while the device pulls the pass transistor back into the linear region. For output currents less than approximately 200mA, the slope of the dropout voltage curve is lower than for higher currents. This slope helps maintain better performance when the LDO is in dropout.

6.4.4 Disabled

Shit down the output of the device by forcing the enable pin voltage to less than V EN(LOW)). When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS7A21-Q1

7 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for many types of applications and are recommended, but use good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Consult the manufacturer data sheet to verify performance. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value.

7.1.2 Input and Output Capacitor Requirements

Although the LDO is stable without an input capacitor, good design practice is to connect a capacitor from IN to GND, with a value at least equal to the nominal value specified in the Recommended Operating Conditions table. The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the source resistance and inductance are sufficiently high, the overall system is susceptible to instability (including ringing and sustained oscillation) and other performance degradation if there is insufficient capacitance between IN and GND. A capacitor with a value greater than the minimum is necessary if there are large fast-rise-time load or line transients or if the LDO is located more than a few centimeters from the input power source. An output capacitor of an appropriate value helps provide stability and improve dynamic performance. Use an output capacitor within the range specified in the Recommended Operating Conditions table.

7.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 7-1 are broken down as follows. Regions A, E, and H are where the output voltage is in a steady state. tAt tDt tEttCt tGt tHt FB Figure 7-1. Load Transient Waveform TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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During transitions from a light load to a heavy load, the:

• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B)
• Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage regulation (region C) During transitions from a heavy load to a light load, the:
• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F)
• Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor.

7.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum operational voltage range, and makes sure that the device shuts down when the input supply collapses. Figure 7-2 shows the UVLO circuit response to various input voltage events. The diagram is separated into the following parts:

• Region A: The device does not start until the input reaches the UVLO rising threshold.
• Region B: Normal operation, regulating device.
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output falls out of regulation but the device remains enabled.
• Region D: Normal operation, regulating device.
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0V. The output falls because of the load and active discharge circuit. C tAt VIN VOUT UVLO Rising Threshold UVLO Hysteresis tBt tDt tEt tFt tGt Figure 7-2. Typical UVLO Operation

7.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. Make sure the PCB area around the regulator is as free as possible of other heat-generating devices that cause added thermal stresses. As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 2 to approximate PD: www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS7A21-Q1

PD = (VIN – VOUT) × IOUT (2) Power dissipation is minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A21-Q1 allows for maximum efficiency across a wide range of output voltages. The main heat conduction path for the device is through the thermal pad on the package. As such, solder the thermal pad to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane. The maximum allowable junction temperature (T J) determines the maximum power dissipation for the device. According to Equation 3, power dissipation and junction temperature are most often related by the junction-to- ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) (3) Equation 4 rearranges Equation 3 for output current. IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4) Unfortunately, this thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The R θJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, R θJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.

7.1.6 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi ( Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics ( ΨJT and ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table. ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD (5) where:

• PD is the power dissipated as explained in the Power Dissipation (PD) section
• TT is the temperature at the center-top of the device package
• TB is the PCB surface temperature measured 1mm from the device package and centered on the package edge

7.1.7 Recommended Area For Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator is given in Figure 7-3 and is separated into the following parts:

• Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level. See the Dropout Operation section for more details.
• The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification.
• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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– The shape of the slope is depicted in the third region of Figure 7-3. The slope is nonlinear because the maximum-rated junction temperature of the LDO is controlled by the power dissipation across the LDO. Thus, when VIN – VOUT increases the output current decreases.

• The rated input voltage range governs both the minimum and maximum of VIN – VOUT. Figure 7-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a RθJA, as given in the Thermal Information table. Rated output current Output current limited by dropout Output current limited by thermals Limited by minimum VIN Limited by maximum VIN VIN ± VOUT (V) Output Current (A) Figure 7-3. Region Description of Continuous Operation Regime

7.2 Typical Application

Figure 7-4 shows the typical application circuit for the TPS7A21-Q1. If necessary for some applications, increase the input and output capacitances above the 1µF minimum value. Figure 7-4. TPS7A21-Q1 Typical Application www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS7A21-Q1

7.2.1 Design Requirements

Table 7-1 summarizes the design requirements for the typical application circuit. Table 7-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 3.6V to 4.2V Output voltage 3.3V Output current 350mA Maximum ambient temperature 125°C

7.2.2 Detailed Design Procedure

For this design example, the 3.3V output version (TPS7A2133PQWDRBRQ1) is selected. A nominal 3.6V input supply is assumed. Use a minimum 1.0 μF input capacitor to minimize the effect of resistance and inductance between the source and the LDO input. Use a minimum 1.0 μF output capacitor for stability and good load transient response. The dropout voltage (V DO) is less than 150mV maximum at a 3.3V output voltage and 500mA output current, so there are no dropout issues with an input voltage of 3.6V and a maximum output current of 350mA.

7.2.2.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source (the junctions of the device) to the ultimate heat sink of the ambient environment. Thus, power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. Equation 6 calculates the maximum allowable power dissipation for the device in a given package: PD-MAX = ((TJ-MAX – TA) / RθJA) (6) Equation 7 represents the actual power being dissipated in the device: PD = (VIN – VOUT) × IOUT (7) These two equations establish the relationship between the maximum power dissipation allowed resulting from thermal consideration, the voltage drop across the device, and the continuous current capability of the device. Use these two equations to determine the optimum operating conditions for the device in the application. In applications where lower power dissipation (P D) or excellent package thermal resistance (R θJA) is present, increase the maximum ambient temperature (TA-MAX). In applications where high power dissipation or poor package thermal resistance is present, derate the maximum ambient temperature (T A-MAX) if necessary. As given by Equation 8 , T A-MAX is dependent on the maximum operating junction temperature (T J-MAX-OP = 150°C), the maximum allowable power dissipation in the device package in the application (P D-MAX), and the junction-to ambient thermal resistance of the device or package in the application (RθJA): TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (8) Alternately, if T A-MAX is unable to be derated, do not reduce the P D value. This reduction is accomplished by reducing VIN in the VIN–VOUT term as long as the minimum V IN is met, or by reducing the IOUT term, or by some combination of the two. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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7.2.3 Application Curves

VIN = 0V to 4.3V, slew rate = 1V/μs, IOUT = 1mA Figure 7-5. Start-Up With VEN After VIN VEN = VIN, IOUT = 500mA Figure 7-6. PSRR vs Frequency and VIN

7.3 Power Supply Recommendations

This LDO is designed to operate from an input supply voltage range of 2.0V to 5.5V. Make sure the input supply is well regulated and free of spurious noise. To make sure that the TPS7A21-Q1 output voltage is well regulated and dynamic performance is optimum, set the input supply to be at least V OUT + 0.3V. A minimum capacitor value of 1µF is required to be within 1cm of the IN pin.

7.4 Layout

7.4.1 Layout Guidelines

The dynamic performance of the TPS7A21-Q1 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs potentially degrade the PSRR, noise, or transient performance of the TPS7A21- Q1. Best performance is achieved by placing C IN and COUT on the same side of the PCB as the TPS7A21-Q1, and as close to the package as practical. Route the ground connections for C IN and COUT back to the TPS7A21-Q1 ground pin using as wide and short a copper trace as practical. Avoid connections using long trace lengths, narrow trace widths, or connections through vias. These connections add parasitic inductances and resistance that results in inferior performance, especially during transient conditions. www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS7A21-Q1

7.4.2 Layout Example

Figure 7-7. Typical DRB Layout TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Device Nomenclature

PRODUCT(1) (2) VOUT TPS7A21xx(x)(C)PQ(W)yyyzQ1 xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8V; 125 = 1.25V). C (when present) indicates an alternate pin configuration. P indicates an active output discharge feature. All variants of the TPS7A21 actively discharge the output when the device is disabled. Q indicates that this device is a Grade-1 device in accordance with the AEC-Q100 standard. W (when present) indicates the package has wettable flanks. yyy is the package designator. z is the package quantity. R is for a 3,000 piece reel. Q1 indicates that this is an automotive grade (AEC-Q100) device. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. (2) Output voltages from 0.8V to 5.5V in 50mV increments are available. Contact the factory for details and availability.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, QFN/SON PCB Attachment application report

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS7A21-Q1

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2023) to Revision B (February 2024) Page Changes from Revision * (December 2022) to Revision A (August 2023) Page

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS7A21-Q1 SBVS437B – DECEMBER 2022 – REVISED FEBRUARY 2024 www.ti.com

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www.ti.com 17-Feb-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples P7A2110PQWDRBRQ1 ACTIVE SON DRB 8 5000 TBD Call TI Call TI -40 to 125 Samples P7A2118PQWDRBRQ1 ACTIVE SON DRB 8 5000 TBD Call TI Call TI -40 to 125 Samples P7A2128PQWDRBRQ1 ACTIVE SON DRB 8 5000 TBD Call TI Call TI -40 to 125 Samples P7A2133PQWDRBRQ1 ACTIVE SON DRB 8 5000 TBD Call TI Call TI -40 to 125 Samples P7A2150PQWDRBRQ1 ACTIVE SON DRB 8 5000 TBD Call TI Call TI -40 to 125 Samples PPS7A2118PQWDSGRQ1 ACTIVE WSON DSG 8 5000 TBD Call TI Call TI -40 to 125 Samples TPS7A2110PQWDRBRQ1 ACTIVE SON DRB 8 5000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A2110P Samples TPS7A2118PQWDRBRQ1 ACTIVE SON DRB 8 5000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A2118P Samples TPS7A2128PQWDRBRQ1 ACTIVE SON DRB 8 5000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A2128P Samples TPS7A2133PQWDRBRQ1 ACTIVE SON DRB 8 5000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A2133P Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

www.ti.com 17-Feb-2024 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS7A21-Q1 :

• Catalog : TPS7A21 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A2110PQWDRBRQ1 SON DRB 8 5000 367.0 367.0 35.0 TPS7A2118PQWDRBRQ1 SON DRB 8 5000 367.0 367.0 35.0 TPS7A2128PQWDRBRQ1 SON DRB 8 5000 367.0 367.0 35.0 TPS7A2133PQWDRBRQ1 SON DRB 8 5000 367.0 367.0 35.0 Pack Materials-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225036/A 06/2019 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRB0008J A 0.08 C

0.1 C A B

0.05 C B SYMM SYMM PIN 1 INDEX AREA 3.1 2.9 3.1 2.9

1 MAX

0.05 0.00 SEATING PLANE C SECTION A-A TYPICAL (0.13)

0.1 MIN

1.75 1.55 (0.2) TYP (0.19) 8X 0.36 0.26 2.5 2.3 6X 0.65 1.95 8X 0.5 0.3 PIN 1 ID (OPTIONAL)

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

0.07 MAX

0.07 MIN

(1.65) (2.4) (2.8) (0.95) (0.575) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP (Ø 0.2) VIA TYP

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (1.51) (1.06) (2.8) (0.63) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP METAL TYP

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDSG 8 PLASTIC SMALL OUTLINE - NO LEAD2 x 2, 0.5 mm pitch 4224783/A

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