TPS746-Q1_V03 TI | Alldatasheet
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RPG* PG *Pull-up resistor not required for push-pull option FB GND Cff TPS746-Q1 EN IN OUT VIN VOUT CIN COUT RPG* PG *Pull-up resistor not required for push-pull option GND Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS746-Q1 SBVS358A –JUNE 2018–REVISED OCTOBER 2019 TPS746-Q11-ALDOWithPower-GoodinSmallWettableFlankWSONPackages
1 Features
1• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
- Device operating junction temperature range: –40°C to +150°C
- Package: – 2-mm × 2-mm wettable flank WSON – 3-mm × 3-mm wettable flank WSON (preview)
- Input voltage range: 1.5 V to 6.0 V
- Output voltage range: – Fixed option: 0.65 V to 5.0 V – Adjustable option: 0.55 V to 5.5 V
- High PSRR: 38 dB at 100 kHz
- Output accuracy: ±0.85% typical, ±1.5% maximum
- Power-good output options: – Open-drain or push-pull
- Ultra-low dropout: – 265 mV (max) at 1 A (3.3 VOUT)
- Stable with a 1-µF or larger capacitor
- Low IQ: 25 µA (typical)
- Active output discharge
- Low thermal resistance: – DRV (6-pin WSON), RθJA = 80.3°C/W – DRB (8-pin WSON), RθJA = 62.0°C/W (preview)
2 Applications
- Automotive head units
- Front and rear cameras
- Automotive cluster displays
- Telematics control units
- Medium, short range radar
3 Description
The TPS746-Q1 is a 1-A ultra-low-dropout regulator (LDO) with power-good functionality. This device is available in a small 6-pin, 2-mm × 2-mm and a small 8-pin, 3-mm × 3-mm WSON package with wettable flanks to facilitate optical inspection. The TPS746-Q1 consumes low quiescent current and provides fast line and load transient performance. The TPS746-Q1 is a flexible device for post- regulation by supporting an input voltage range from 1.5 V to 6.0 V and an externally adjustable output range of 0.55 V to 5.5 V. The device also features fixed output voltages for powering common voltage rails. The TPS746-Q1 has a power-good (PG) output that monitors the voltage at the feedback pin to indicate the status of the output voltage. The EN input and PG output can be used for sequencing multiple power supplies in the system. The TPS746-Q1 is stable with small ceramic output capacitors, allowing for a small overall solution size. A precision band-gap and error amplifier provides high accuracy of ±0.85% (max) at 25°C and ±1.5% (max) over temperature. This device includes integrated thermal shutdown, current limit, and undervoltage lockout (UVLO) features. The TPS746- Q1 has an internal foldback current limit that helps reduce the thermal dissipation during short-circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS746-Q1 Wettable flank WSON (6) 2.00 mm × 2.00 mm Wettable flank WSON (8)(2) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package. Typical Application: Fixed Voltage Version Typical Application: Adjustable Voltage Version
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11.3 Receiving Notification of Documentation Updates 30
12 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (June 2019) to Revision A Page
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5 Pin Configuration and Functions
(Fixed) DRV (Adjust) DRB (Fixed) DRB (Adjust) EN 4 4 5 5 Input Enable pin. Drive EN greater than VEN(HI) to turn on the regulator. Drive EN less than VEN(LO) to put the low-dropout regulator (LDO) into shutdown mode. FB — 2 — 3 — This pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. GND 3 3 4 4 — Ground pin. IN 6 6 8 8 Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible. NC 2 — 2, 3, 7 2, 7 — No internal connection. Ground this pin for better thermal performance. OUT 1 1 1 1 Output Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to the output of the device as possible.
SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME DRV (Fixed) DRV (Adjust) DRB (Fixed) DRB (Adjust) PG 5 5 6 6 Output Power-good output. Available in open-drain and push-pull topologies. A pullup resistor is required for the open-drain version. For the open-drain version, if the power-good functionality is not being used, ground this pin or leave floating. For the push-pull version, if the power-good functionality is not being used, leave this pin floating. Thermal Pad — The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6.5 V Enable, VEN –0.3 6.5 Feedback, VFB –0.3 2.0 Power-good, VPG –0.3 6.5 Output, VOUT –0.3 VIN + 0.3(2) Current Output, IOUT Internally limited Power-good, IPG ±10 mA Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 VCharged-device model (CDM), per AEC Q100-011, corner pins ±750 Charged-device model (CDM), per AEC Q100-011, other pins ±500 (1) Minimum derated capacitance of 0.47 µF is required for stability
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 1.5 6.0 V VOUT Output voltage Adjustable version 0.55 5.5 V Fixed version 0.65 5.0 IOUT Output current 0 1 A CIN Input capacitor 1 µF COUT Output capacitor(1) 1 220 µF CFF Feed-forward capacitor 10 nF VEN Enable voltage 0 6.0 V fEN Enable toggle frequency 10 kHz VPG PG voltage 0 6.0 V TJ Junction temperature –40 150 °C
www.ti.com SBVS358A –JUNE 2018–REVISED OCTOBER 2019 Product Folder Links: TPS746-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Preview package.
6.4 Thermal Information
THERMAL METRIC(1) TPS746-Q1 UNITDRV (WSON) DRB (WSON)(2)
6 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 80.3 62.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.7 73.1 °C/W RθJB Junction-to-board thermal resistance 44.8 35.1 °C/W ψJT Junction-to-top characterization parameter 6.1 6.3 °C/W ψJB Junction-to-board characterization parameter 45.0 35.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 20.8 18.2 °C/W (1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included. (2) VIN = 1.5V for VOUT < 1.0 V (3) Dropout is not tested for nominal output voltages below 0.65 V since the input voltage may be below UVLO.
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback voltage 0.55 V Output accuracy(1) Line regulation VOUT(NOM) + 0.5 V(2) ≤ VIN ≤ 6.0 V 2 7.5 mV Load regulation 0.1 mA ≤ IOUT ≤ 1 A, VIN ≥ 2.0 V 0.030 V/A IGND Ground current IOUT = 0 mA TJ = 25°C 25 32 µA -40°C ≤ TJ ≤ 150°C 25 36 ISHDN Shutdown current VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V -40°C ≤ TJ ≤ 125°C 0.1 1 µA IFB Feedback pin current Adjustable only 0.01 0.1 µA ICL Output current limit VOUT(NOM) < 1 V, VOUT = VOUT(NOM) - 0.2 V, VIN = 2.0 V 1.22 1.5 1.83 A VOUT(NOM) ≥ 1 V, VOUT = VOUT(NOM) × 0.85, VIN = VOUT(NOM) + 1.0 V ISC Short-circuit current limit VOUT = 0 V VOUT(NOM) < 1 V, VIN = 2.0 V 680 850 mA VOUT(NOM) ≥ 1 V, VIN = VOUT(NOM) + 1.0 V VDO Dropout voltage IOUT = 1 A, VOUT = 0.95 x VOUT(NOM) 0.65 V ≤ VOUT < 0.8 V(3) 895 1090 mV 0.8 V ≤ VOUT < 0.9 V 765 960 0.9 V ≤ VOUT < 1.0 V 700 890 1.0 V ≤ VOUT < 1.2 V 600 790 1.2 V ≤ VOUT < 1.5 V 465 625 1.5 V ≤ VOUT < 1.8 V 335 480 1.8 V ≤ VOUT < 2.5 V 265 400 2.5 V ≤ VOUT < 3.3 V 195 310 3.3 V ≤ VOUT < 5.5 V 160 265 PSRR Power-supply rejection ratio VOUT = 1.8 V, VIN = 2.8 V, IOUT = 1 A, COUT = 2.2 µF f = 1 kHz 53 dBf = 100 kHz 38 f = 1 MHz 30 VN Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 0.9 V, VIN = 1.9 V 53 µVRMS VUVLO Undervoltage lockout VIN rising 1.21 1.33 1.47 V VIN falling 1.17 1.29 1.42
SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) Push-pull version only. The push-pull option is supported only for VOUT ≥ 1.0 V. (5) Open-drain version only. VUVLO,HYST Undervoltage lockout hysteresis VIN hysteresis 40 mV tSTR Startup time From EN low-to-high transition to VOUT = VOUT(NOM) x 95% 500 650 µs VHI EN pin high voltage (enabled) 1.0 V VLO EN pin low voltage (disabled) 0.3 V IEN Enable pin current VIN = VEN = 6.0 V 10 nA RPULLDOWN Pulldown resistance VIN = 6.0 V 95 Ω PGHTH PG high threshold VOUT increasing 89 92 96 %VOUT PGLTH PG low threshold VOUT decreasing 86 90 93 %VOUT PGHYST PG hysteresis 2 %VOUT VOL(PG) PG pin low-level output voltage VOUT ≥ 1.5 V, ISINK = 1 mA 300 mV VOUT ≥ 2.75 V, ISINK = 2 mA VOH(PG) PG pin high-level output voltage(4) VOUT ≥ 1.0 V, ISOURCE = 0.04 mA 0.8 × VOUT V VOUT ≥ 1.4 V, ISOURCE = 0.2 mA VOUT ≥ 2.5 V, ISOURCE = 0.5 mA VOUT ≥ 4.5 V, ISOURCE = 1.0 mA Ilkg(PG) PG pin leakage current(5) VOUT > PGHTH, VPG = 6.0 V 7 50 nA TSD Thermal shutdown Shutdown, temperature increasing 170 Reset, temperature decreasing 155 (1) Output overdrive = 10%. (2) See the Device Nomenclature table for more information on available PG timings.
6.6 Timing Requirements
PG delay time rising, time from 92% VOUT to 20% of PG(1) 135 165 178 µs 'B' version(2) 4.5 5 5.5 ms tPGDL PG delay time falling, time from 90% VOUT to 80% of PG(1) 1.5 7 10 µs
6.7 Typical Characteristics
Figure 1. 3.3-V Line Regulation vs VIN Figure 2. 0.55-V Line Regulation vs VIN Figure 3. 5.5-V Line Regulation vs VIN Figure 4. 3.3-V Dropout Voltage vs IOUT Figure 5. 0.55-V Dropout Voltage vs IOUT Figure 6. 5.5-V Dropout Voltage vs IOUT
7 Detailed Description
7.1 Overview
dropout voltage, make this device ideal for portable consumer applications. for this device is –40°C to +150°C.
7.2 Functional Block Diagrams
Figure 45. Adjustable Version With Open-Drain Power-Good Figure 46. Adjustable Version With Push-Pull Power-Good
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS746-Q1 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN).
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. The TPS746-Q1 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the pulldown resistor (RPULLDOWN). Equation 1 calculates the time constant: τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL) (1)
7.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short- circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table. For this device, VFOLDBACK = 0.4 V × VOUT(NOM). The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brickwall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application report.
Figure 49 shows a diagram of the foldback current limit. Figure 49. Foldback Current Limit
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
operation. See the Electrical Characteristics table for parameter values. Table 1. Device Functional Mode Comparison
7.4.2 Normal Operation
- The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
- The output current is less than the current limit (IOUT < ICL)
- The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
- The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold
7.4.3 Dropout Operation
transients in dropout can result in large output-voltage deviations. while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
discharge circuit from the output to ground.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
Figure 50. Adjustable Operation
8.1.2 Input and Output Capacitor Selection
performance, the maximum recommended output capacitance is 220 µF. inches from the input power source.
8.1.3 Dropout Voltage
response degrade as (VIN – VOUT) approaches dropout operation.
8.1.4 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up. range. Use an enable signal to avoid this condition. Figure 51. Startup Into Dropout slow enough to reduce the overshoot.
Figure 52. Line Transients From Dropout
8.1.5 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
- Degradation caused by electromigration
- Excessive heat dissipation
- Potential for a latch-up condition Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V:
- If the device has a large COUT and the input supply collapses with little or no load current
- The output is biased when the input supply is not established
- The output is biased above the input supply
If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 53 shows one approach of protecting the device. Figure 53. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.6 Power Dissipation (PD)
other heat-generating devices that cause added thermal stress. and load conditions. Equation 4 calculates power dissipation (PD). minimum input voltage required for correct output regulation. array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Application Information (continued)
8.1.7 Power-Good Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages and pulls the PG pin close to GND. When the output voltage exceeds PGHTH, the PG pin becomes high impedance. The open-drain output requires a pullup resistor. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Additionally, the open-drain output can be tied to other open-drain outputs to implement AND logic. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. The push-pull power-good output option does not require the pullup resistor and instead has a high logic signal that correlates with the output voltage of the device. The push- pull option is supported only for VOUT ≥ 1.0 V. Do not tie the push-pull output to other logic outputs. When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO startup and the power-good output match, which can be done by adding a capacitor in parallel with the power-good pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low- Dropout Regulator application report. The state of PG is only valid when the device operates above the minimum input voltage of the device and power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.
8.1.8 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
8.1.9 Start-Up Sequencing
If VEN is greater than VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being turned on with a floating input pin.
8.2 Typical Application
Figure 58. TPS746-Q1 Typical Application
8.2.1 Design Requirements
Use the parameters listed in Table 2 for typical linear regulator applications. Table 2. Design Parameters
8.2.2 Detailed Design Procedure
Input and Output Capacitor Selection section for details. the Adjustable Device Feedback Resistors section for details.
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO. Equation 6 to calculate the current through the input.
- VOUT(t) is the instantaneous output voltage of the turn-on ramp
- dVOUT(t) / dt is the slope of the VOUT ramp
- RLOAD is the resistive load impedance (6)
8.2.2.2 Thermal Dissipation
shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).
Calculate the maximum ambient temperature as Equation 9 shows if the (TJ(MAX)) value does not exceed 125°C. Equation 10 calculates the maximum ambient temperature with a value of 109.85°C.
8.2.3 Application Curve
Figure 59. PSRR vs Frequency and ILOAD
9 Power Supply Recommendations
noise performance. Connect a low output impedance power supply directly to the IN pin of the TPS746-Q1.
10 Layout
10.1 Layout Guidelines
- Place input and output capacitors as close to the device as possible.
- Use copper planes for device connections in order to optimize thermal performance.
- Place thermal vias around the device to distribute heat.
- Place a tented thermal via directly beneath the thermal pad of the DRV or DRB package. An untented via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.
10.2 Layout Examples
Figure 60. Layout Example for the DRV Package Figure 61. Layout Example for the DRB package
device product folder on www.ti.com. (2) Output voltages from 0.65 V to 5.0 V in 50-mV increments are available. Contact the factory for details and availability.
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature(1)(2) the output when the device is disabled. v indicates the topology of the power-good output and the timing associated with the power-good delay.
- If unused, indicates an open-drain power-good output with a 150-µs delay.
- If B, indicates an open-drain, power-good output with a 5-ms delay.
- If C, indicates a push-pull, power-good output with a 150-µs delay. Q indicates that this device is a Grade-1 device in accordance with the AEC-Q100 standard. W indicates the package has wettable flanks. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces). Q1 indicates that this device is an automotive grade (AEC-Q100) device.
11.2 Documentation Support
11.2.1 Related Documentation
- Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report
- Texas Instruments, An Empirical Analysis of the Impact of Board Layout on LDO Thermal Performance application report
11.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.7 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C 6X 0.35 0.25 1.6 0.1 6X 0.35 0.25 1.3 0.9 0.1 4X 0.65
0.8 MAX
0.05 0.00
0.1 MIN
B 2.1 1.9 A 2.1 1.9 (0.2) TYP (0.05) WSON - 0.8 mm max heightDRV0006C PLASTIC SMALL OUTLINE - NO LEAD 4223939/A 09/2017 PIN 1 INDEX AREA SEATING PLANE 0.08 C (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 5.500 A-A 40.000 SECTION A-A TYPICAL TPS746-Q1 SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
4X (0.65) (1.9) 6X (0.3) 6X (0.5) (R0.05) TYP (1.1) (1.6) (0.9) ( 0.2) TYP VIA WSON - 0.8 mm max heightDRV0006C PLASTIC SMALL OUTLINE - NO LEAD 4223939/A 09/2017 SYMM 3 4 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL TPS746-Q1 www.ti.com SBVS358A –JUNE 2018–REVISED OCTOBER 2019 Product Folder Links: TPS746-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN 6X (0.3) 6X (0.5) 4X (0.65) (1.9) (R0.05) TYP (0.9) (0.7) (0.45) WSON - 0.8 mm max heightDRV0006C PLASTIC SMALL OUTLINE - NO LEAD 4223939/A 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7: 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X SYMM 3 4 SYMM METAL TPS746-Q1 SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225036/A 06/2019 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRB0008J A 0.08 C 0.05 C B SYMM SYMM PIN 1 INDEX AREA 3.1 2.9 3.1 2.9
1 MAX
0.05 0.00 SEATING PLANE C SECTION A-A TYPICAL (0.13) 1.75 1.55 (0.2) TYP (0.19) 8X 0.36 0.26 2.5 2.3 6X 0.65 1.95 8X 0.5 0.3 PIN 1 ID (OPTIONAL) TPS746-Q1 www.ti.com SBVS358A –JUNE 2018–REVISED OCTOBER 2019 Product Folder Links: TPS746-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED (1.65) (2.4) (2.8) (0.95) (0.575) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP (Ø 0.2) VIA TYP TPS746-Q1 SBVS358A –JUNE 2018–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS746-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (1.51) (1.06) (2.8) (0.63) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP METAL TYP TPS746-Q1 www.ti.com SBVS358A –JUNE 2018–REVISED OCTOBER 2019 Product Folder Links: TPS746-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
www.ti.com 18-Aug-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS74601PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 125 PPS74610PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 PPS74611PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 PPS74612PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 PPS74618PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 PPS74633PQWDRBRQ1 ACTIVE SON DRB 8 3000 TBD Call TI Call TI -40 to 150 TPS74601PBQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 1S46 TPS74601PCQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 1OZ6 TPS74601PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74601PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1OW6 TPS74607PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74610PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74610PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SG6 TPS74611PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74611PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SH6 TPS746125PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74612PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74612PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SI6 TPS74615PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74615PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SJ6 TPS74617PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125
www.ti.com 18-Aug-2020 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS74618PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74618PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SK6 TPS74625PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74625PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SL6 TPS74628PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74628PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SM6 TPS74629PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74629PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1SN6 TPS74630PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74633PCQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 1P16 TPS74633PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TPS74633PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 1OX6 TPS74650PQWDRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 18-Aug-2020 Addendum-Page 3 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS746-Q1 :
- Catalog: TPS746 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS74601PBQWDRVRQ TPS74601PCQWDRVRQ TPS74633PCQWDRVRQ PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2019 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74601PBQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74601PCQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74601PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74610PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74611PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74612PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74615PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74618PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74625PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74628PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74629PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74633PCQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TPS74633PQWDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2019 Pack Materials-Page 2
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F
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