PPS74512PQWDRVRQ1

TPS745-Q1_V01 TI1 | Alldatasheet

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ADVANCE□INFORMATION TPS745-Q1 EN IN OUT VIN VOUT C IN C OUT R PG * PG *Pull-up resistor not required for push-pull option Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS745-Q1 SBVS355 – JUNE 2019 TPS745-Q1500-mALDOWithPower-GoodinaSmallWettableFlankWSONPackage

1 Features

1• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA

• Device junction temperature: –40°C to 150°C
• Package: – 2-mm × 2-mm wettable flank WSON
• Input voltage range: 1.5 V to 6.0 V
• Output voltage range: – Fixed option: 0.65 V to 5.0 V – Adjustable option: 0.55 V to 5.5 V
• High PSRR: 45 dB at 100 kHz
• Output accuracy: 1% typical, 2% maximum
• Power-good output options: – Open-drain and push-pull
• Ultra-low dropout: – 225 mV (max) at 500 mA (3.3 VOUT)
• Stable with a 1-µF or larger capacitor
• Low IQ: 25 µA (typical)
• Active output discharge

2 Applications

• Head units
• Clusters
• Telematics
• Radar
• Camera modules
• General post-regulation (for example, 5 V to 3.3 V)

3 Description

The TPS745-Q1 is a 500-mA ultra-low-dropout regulator (LDO) with power-good functionality. This device is available in a small 6-pin, 2-mm × 2-mm WSON package with wettable flanks to facilitate optical inspection. The TPS745-Q1 consumes low quiescent current and provides fast line and load transient performance. The TPS745-Q1 is a flexible device for post- regulation by supporting an input voltage range from 1.5 V to 6.0 V and an externally adjustable output range of 0.65 V to 5.5 V. The device also features fixed output voltages for powering common voltage rails. The TPS745-Q1 has a power-good (PG) output that monitors the voltage at the feedback pin to indicate the status of the output voltage. The EN input and PG output can be used for sequencing multiple power sources in the system. The TPS745-Q1 is stable with small ceramic output capacitors, allowing for a small overall solution size. A precision band-gap and error amplifier provides high accuracy of 1% (max) at 25°C and 2% (max) over temperature. This device includes integrated thermal shutdown, current limit, and undervoltage lockout (UVLO) features. The TPS745-Q1 has an internal foldback current limit that helps reduce the thermal dissipation during short-circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS745-Q1 Wettable flank WSON (6) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application

ADVANCE□INFORMATION TPS745-Q1 SBVS355 – JUNE 2019 www.ti.com Product Folder Links: TPS745-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

11.3 Receiving Notification of Documentation Updates 24

12 Mechanical, Packaging, and Orderable

4 Revision History

June 2019 * Initial release.

ADVANCE□INFORMATION 1OUT 2NC 3GND 4 EN 5 PG 6 IN Not to scale Thermal Pad 1OUT 2FB 3GND 4 EN 5 PG 6 IN Not to scale Thermal Pad TPS745-Q1 www.ti.com SBVS355 – JUNE 2019 Product Folder Links: TPS745-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

EN 4 4 Input Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to put the low-dropout regulator (LDO) into shutdown mode. FB — 2 — This pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. GND 3 3 — Ground pin. IN 6 6 Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible. NC 2 — — No internal connection. Ground this pin for better thermal performance. OUT 1 1 Output Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible. PG 5 5 Output Power-good output. Available in open-drain and push-pull topologies. For the open-drain version, if the power-good functionality is not being used, ground this pin or leave floating. For the push-pull version, if the power- good functionality is not being used, leave this pin floating. Thermal Pad — The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance.

ADVANCE□INFORMATION TPS745-Q1 SBVS355 – JUNE 2019 www.ti.com Product Folder Links: TPS745-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VIN + 0.3 V or 6.5 V, whichever is smaller.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6.5 V Enable, VEN –0.3 6.5 Feedback, VFB –0.3 2 Power-good, VPG –0.3 6.5 Output, VOUT –0.3 VIN + 0.3(2) Current Output, IOUT Internally Limited Power-good, IPG ±10 mA Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) TBD V Charged-device model (CDM), per AEC Q100-011 TBD (1) Maximum enable toggle frequency must be below 10 kHz.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CIN Input capacitor 1 µF COUT Output capacitor 1 220 µF VIN Input voltage 1.5 6.0 V VOUT Output voltage Adjustable only 0.55 5.5 V Fixed only 0.65 5.0 IOUT Output current 0 500 mA VEN Enable voltage(1) 0 6 V VPG PG voltage 0 6 V TJ Junction operating temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS745-Q1 UNITDRV (WSON)

6 PINS

RθJA Junction-to-ambient thermal resistance 80.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.7 °C/W RθJB Junction-to-board thermal resistance 44.8 °C/W ψJT Junction-to-top characterization parameter 6.1 °C/W ψJB Junction-to-board characterization parameter 45.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 20.8 °C/W

ADVANCE□INFORMATION TPS745-Q1 www.ti.com SBVS355 – JUNE 2019 Product Folder Links: TPS745-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

6.5 Electrical Characteristics

at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 1.5 6.0 V VOUT Output voltage Adjustable only 0.55 5.5 V Fixed only 0.65 5.0 VFB Feedback voltage 0.542 0.55 0.558 V Output accuracy

0.6 V ≤ VOUT < 1 V –25 25 mV

(ΔVOUT)ΔVIN/VOU T Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.0 V 2 10 mV ΔVOUT/ΔIOUT Load regulation 0.1 mA ≤ IOUT ≤ 500 mA 0.050 V/A IGND Ground current TJ = 25°C , IOUT = 0 mA 25 41 µA IOUT = 0 mA 45 ISHDN Shutdown current VEN ≤ 0.4 V, 1.4 V ≤ VIN ≤ 6.0 V, TJ = 25°C 0.1 1 µA IFB Feedback pin current (adjustable only) 0.01 0.1 µA ICL Output current limit VIN = VOUT + VDO(MAX) + 0.1 V VOUT = VOUT – 0.2 V, VOUT ≤ 1 V 530 720 865 mA VOUT = 0.9 × VOUT, 1.0 V < VOUT ≤ 5.5 V 530 720 865 ISC Short-circuit current limit VOUT = 0 V 990 mA VDO Dropout voltage IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM) 0.6 V ≤ VOUT < 0.8 V 850 mV 0.8 V ≤ VOUT < 1.0 V 675 1.0 V ≤ VOUT < 1.2 V 505 1.2 V ≤ VOUT < 1.5 V 340 1.5 V ≤ VOUT < 1.8 V 285 1.8 V ≤ VOUT < 2.5 V 235 2.5 V ≤ VOUT < 3.3 V 225 3.3 V ≤ VOUT < 5.5 V 50 PSRR Power-supply rejection ratio f = 1 kHz 45 dBf = 100 kHz 30 f = 1 MHz 30 VN Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 0.6 V 53 µVRMS VUVLO,r Undervoltage lockout VIN rising 1.21 1.33 1.47 V VUVLO,f Undervoltage lockout VIN falling 1.17 1.29 1.42 V VUVLO,HYST Undervoltage lockout hysteresis VIN hysteresis 40 mV tSTR Startup time From EN low-to-high transition to VOUT = VOUT × 95% 500 µs VHI EN pin high voltage (enabled) 1.0 V VLO EN pin low voltage (enabled) 0.3 V IEN Enable pin current VIN = EN = 6.0 V 10 nA RPULLDOWN Pulldown resistance VIN = 6.0 V 95 Ω PGHTH PG high threshold VOUT increasing 89 94 95 %VOUT PGLTH PG low threshold VOUT decreasing 87 92 93 %VOUT VOL(PG) PG pin low-level output voltage VIN ≥ 1.5 V, ISINK = 1 mA 300 mV VIN ≥ 2.75 V, ISINK = 2 mA 300

ADVANCE□INFORMATION TPS745-Q1 SBVS355 – JUNE 2019 www.ti.com Product Folder Links: TPS745-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The push-pull option is supported only for VOUT ≥ 1.0 V. VOH(PG) PG pin high-level output voltage (only for push-pull version) VOUT ≥ 1.0 V(1), ISINK = 0.04 mA 0.8 × VOUT V VOUT ≥ 1.4 V, ISource = 0.2 mA 0.8 × VOUT VOUT ≥ 2.5 V, ISource = 0.5 mA 0.8 × VOUT VOUT ≥ 4.5 V, ISource = 1.0 mA 0.8 × VOUT Ilkg(PG) PG pin leakage current VOUT > PGHTH, VPG = 6.0 V 300 nA TSD Thermal shutdown Shutdown, temperature increasing 170 Reset, temperature decreasing 155 (1) Output overdrive = 10%

6.6 Timing Requirements

PARAMETER MIN NOM MAX UNIT tPGDH PG delay time (rising) from 92% VOUT to 20% of PG(1) 135 165 178 µs 'B' version 5 ms tPGDL PG delay time (falling) from 90% VOUT to 80% of PG(1) 1.5 7 10 µs

6.7 Typical Characteristics

Figure 1. Output Voltage vs Ambient Temperature Figure 2. Output Voltage vs Ambient Temperature Figure 3. Output Voltage vs Ambient Temperature Figure 4. Temperature Drift Histogram (–40°C to +25°C) Figure 5. Temperature Drift Histogram (25°C to 150°C) Figure 6. 3.3-V Line Regulation vs VIN

7 Detailed Description

7.1 Overview

dropout voltage, make this device ideal for automotive applications. for this device is –40°C to 150°C.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 TPS745-Q1 Comparison

Table 1 lists the three different power-good (PG) options for the TPS745-Q1. Table 1. TPS745-Q1 Comparison Table

7.3.2 Undervoltage Lockout (UVLO)

VIN is less than VUVLO, the output is connected to ground with a 95-Ω pulldown resistor.

7.3.3 Shutdown

7.3.4 Foldback Current Limit

circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table. For this device, VFOLDBACK = 0.4 V × VOUT(NOM). more information on current limits, see the Know Your Limits application report. Figure 42 shows a diagram of the foldback current limit. Figure 42. Foldback Current Limit

7.3.5 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 175°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation, protecting the regulator from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions.

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

operation. See the Electrical Characteristics table for parameter values. Table 2. Device Functional Mode Comparison

7.4.2 Normal Operation

• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold

7.4.3 Dropout Operation

transients in dropout can result in large output-voltage deviations. while the device pulls the pass transistor back into the linear region.

ADVANCE□INFORMATION TPS745-Q1 www.ti.com SBVS355 – JUNE 2019 Product Folder Links: TPS745-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

The TPS745-Q1 needs an output capacitance of 1 µF or larger for stability. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. When choosing a capacitor for a specific application be sure to look at the DC bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the maximum recommended output capacitance is 100 µF. Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the input power source.

8.1.2 Dropout Voltage

response degrade as (VIN – VOUT) approaches dropout operation.

8.1.3 Exiting Dropout

Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up. range. Use an enable signal to avoid this condition. Figure 43. Startup Into Dropout slow enough to reduce the overshoot.

Figure 44. Line Transients From Dropout

8.1.4 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply

If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 45 shows one approach of protecting the device. Figure 45. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.5 Power Dissipation (PD)

other heat-generating devices that cause added thermal stress. and load conditions. Equation 2 calculates power dissipation (PD). minimum input voltage required for correct output regulation. array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

Figure 46. TPS745-Q1 (WSON) RθJA vs Board Layout

8.1.6 Power-Good Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. in a valid logic signal for the receiving device. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. Dropout Regulator application report. pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.

8.1.7 Feed-Forward Capacitor (CFF)

the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

8.1.8 Startup sequencing

turn on with a floating input pin.

8.2 Typical Application

Figure 47. TPS745-Q1 Typical Application

8.2.1 Design Requirements

Table 3. Design Parameters

8.2.2 Detailed Design Procedure

Input and Output Capacitor Selection section for details. Figure 47 illustrates the output voltage of the ; set the output voltage using the resistor divider.

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO. Equation 4 to calculate the current through the input.

• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance (4)

8.2.2.2 Thermal Dissipation

shows and add the ambient temperature (TA) to calculate the junction temperature (TJ). Calculate the maximum ambient temperature as Equation 7 shows if the (TJ(MAX)) value does not exceed 150°C. Equation 8 calculates the maximum ambient temperature with a value of 113.86°C.

9 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TPS745-Q1.

10 Layout

10.1 Layout Guidelines

• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections, in order to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DRV package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.

10.2 Layout Example

Figure 48. Layout Example for the DRV Package

device product folder on www.ti.com. (2) Output voltages from 0.6 V to 5.0 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 4. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). the output when the device is disabled. v indicates the topology of the power-good output and the timing associated with the power-good delay.

• If unused, indicates an open-drain power-good output with a 150-µs delay.
• If B, indicates a open-drain power-good output with a 5-ms delay.
• If C, indicates a push-pull power-good output with a 150-µs delay. Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard. W indicates the package has wettable flanks. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). Q1 indicates that this device is an automotive grade (AEC-Q100) device.

11.2 Documentation Support

11.2.1 Related Documentation

• Texas Instruments, An empirical analysis of the impact of board layout on LDO thermal performance application report
• Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report

11.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

ADVANCE□INFORMATION TPS745-Q1 www.ti.com SBVS355 – JUNE 2019 Product Folder Links: TPS745-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Sep-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS74501PCQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 P1ZF PPS74501PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PS26 PPS74511PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PS76 PPS74512PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PS86 PPS74518PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PSA6 PPS74525PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PSC6 PPS74528PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PSD6 PPS74533PCQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 P1ZE PPS74533PQWDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 PSF6 TPS74501PBQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74501PCQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74501PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS745105PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74510PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74511PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74512PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74515PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74518PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74522PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74525PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74528PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74529PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74533PCQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125

www.ti.com 10-Sep-2019 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS74533PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TPS74550PQWDRVRQ1 PREVIEW WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS745-Q1 :

• Catalog: TPS745

www.ti.com 10-Sep-2019 Addendum-Page 3 NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F

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