Power Management

PPS62903QRYTRQ1

Texas Instruments

TPS62903-Q1 3-V to 18-V, 3-A, Automotive Low IQ Buck Converter with +165째C TJ MAY 2022

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TPS62903-Q1 3-V to 18-V, 3-A, Automotive Low IQ Buck Converter with +165°C TJ

1 Features

AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA – Level 2 device HBM ESD classification – Level C4B CDM ESD classification
Functional Safety-Capable – Documentation available to aid functional safety system design
Extended TJ range: up to 165°C
High efficiency DCS-Control topology – RDS(ON): 62-mΩ high side, 22-mΩ low side – Seamless PWM/PFM transition – Internal compensation
4-µA low IQ (typical)
Up to 3-A continuous output current
±1% feedback voltage accuracy across temp
Configurable output voltage options: – 0.6-V to 5.5-V VFB external divider – VSET internal divider
16 options between 0.4 V and 5.5 V
Flexibility through the MODE/S-CONF pin – 2.5-MHz or 1.0-MHz switching frequency – Forced PWM or auto PFM (power save mode) with dynamic mode change option – Output discharge on and off
No external bootstrap capacitor required
Overcurrent and overtemperature protection
100% duty cycle mode
Precise enable input
Adjustable soft start and tracking
Power-good output
Optimized pinout for single-layer routing
Wettable 2.2-mm × 2.0-mm VQFN package with 0.5-mm pitch
Create a custom design with the TPS62903-Q1 using the WEBENCH® Power Designer

2 Applications

ADAS
Body electronics and lighting
Infotainment and cluster
Hybrid, electric, and powertrain systems

3 Description

The TPS62903-Q1 is a highly efficient, small, and flexible synchronous step-down DC-DC converter that is easy to use. A selectable switching frequency of 2.5 MHz or 1.0 MHz allows the use of small inductors and provides fast transient response. The device supports high V OUT accuracy of ± 1% with the DCS-Control topology. The wide 3-V to 18-V input voltage range supports a variety of nominal inputs, like 12-V supply rails, single-cell or multi-cell Li-Ion, and 5-V or 3.3-V rails. The TPS62903-Q1 can automatically enter power save mode (if auto PFM or PWM is selected) at light loads to maintain high efficiency. Additionally, to provide high efficiency at very small loads, the device has a low typical quiescent current of 4 µA. AEE, if enabled, provides high efficiency across V IN, VOUT, and load current. The device includes a MODE/ Smart-CONF input to set the internal and external divider, switching frequency, output voltage discharge, and automatic power save mode or forced PWM operation. The device is available in small 9-pin VQFN package measuring 2.20 mm × 2.00 mm with 0.5-mm pitch with wettable flank. Device Information Part Number Package(1) Body Size (NOM) TPS62903-Q1 Wettable flank VQFN-HR 2.20 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VIN 3V t17V EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x-Q1 L1 VOUT 0.6V t5.5V GNDR3C3 F F Simplified Schematic IOUT (A) Efficiency (%) 100 VIN=3V VIN=5V VIN=8V VIN=10V VIN=12V VIN=15V Efficiency Versus Output Current (1.2 VO at 2.5 MHz, 1 μH, Auto PFM or PWM) ADVANCE INFORMATION TPS62903-Q1 SLVSG65 – MAY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

9.2 Typical Application with Adjustable Output Voltage.. 18 12.3 Receiving Notification of Documentation Updates..30

13 Mechanical, Packaging, and Orderable

4 Revision History

May 2022 * Advance Information TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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5 Device Comparison Table

Device Number Output Current Input Voltage Operating Temperature Range Switching Frequency PWM Mode VO Adjust TPS62903-Q1 0 A–3 A

3 V–18 V –40°C to 165°C Selectable 1-MHz or

2.5-MHz options Selectable auto PWM/PFM or forced PWM Externally programmable or 16 internal options TPS62902-Q1 0 A–2 A TPS62901-Q1 0 A–1 A TPS62903 0 A–0.3 A

3 V–18 V

–40°C to 125°C Selectable 1-MHz or 2.5-MHz options Selectable auto PWM/PFM or forced PWM Externally programmable or 16 internal options TPS62902 0 A–2 A TPS62901 0 A–1 A TPS62903E 0 A–3 A –55°C to 165°C www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS62903-Q1

6 Pin Configuration and Functions

Figure 6-1. 9-Pin RPJ VQFN Package (Top View, Device Pins Face Down) Table 6-1. Pin Functions Pin Type(1) Description Name Number PG 1 O Open-drain power good output. High = VOUT is ready. Low = VOUT is below nominal regulation. This pin requires a pullup resistor. SW 2 — Switch pin of the converter and is connected to the internal power switches. Connect the inductor between SW and the output capacitor. VOS 3 I Output voltage sense pin. Connect directly to the positive pin of the output capacitor. GND 4 — Ground pin. This pin must be connected directly to the common ground plane. EN 5 I Enable input pin. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected. VIN 6 I Power supply input pin. Ensure the input capacitor is connected as close as possible between the VIN and GND pins. MODE/ S-CONF 7 I Device mode selection (auto PFM/PWM or forced PWM operation) and SmartConfig™ pin. Connect high, low, or to a resistor to configure the device according to Table 8-1. Do not leave this pin unconnected. SS/TR 8 I Soft start and tracking pin. An external capacitor connected from this pin to GND defines the rise time for the internal reference voltage. The pin can also be used as an input for tracking and sequencing. The pin can be left floating for the fastest ramp-up time. FB/VSET 9 I Depends on device configuration (see Section 8.3.1.)

FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage according to Table 8-2. (1) O = output, I = input TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage(2) VIN, EN, PG, MODE/S-CONF –0.3 19.5 V Voltage(2) SW (3) –0.3 VIN + 0.3 V Voltage(2) SW (AC, less than 10 ns)(3) –3.0 23 V Voltage(2) FB/VSET, SS/TR, VOS –0.3 6 V TJ Junction temperature –55 165 °C Tstg Storage temperature –65 165 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to network ground terminal. (3) While switching

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002 HBM ESD Classification Level 2, all pins(1) ±2000 V V(ESD) Electrostatic discharge Charged device model (CDM), per AEC-Q100-011 CDM ESD Classification level C4B All pins ±500 V Corner pins (3, 4, 7, and 9) ±750 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VI Input voltage range 3.0 18 V VO Output voltage range 0.4 5.5 V CI Effective input capacitance 3 10 µF CO Effective output capacitance (2.5-MHz selection)(1) 10 22 100 (1) µF CO Effective output capacitance (1-MHz selection)(1) 10 22 100 (1) µF L Output inductance(2) 1 2.2 4.7(3) µH IOUT Output current 0 3 A ISINK_PG Sink current at the PG pin 1 mA TJ Junction temperature (4) –40 165 °C (1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the capacitor. (2) Nominal inductance value (3) Larger values of inductance can be used to reduce the ripple current, but they can have a negative impact on efficiency and the overall transient response. (4) Operating lifetime is derated at junction temperatures greater than 165°C. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS62903-Q1

7.4 Thermal Information

THERMAL METRIC(1) SOT583 (8) UNIT JEDEC PCB TPS6290xEVM-xxx RθJA Junction-to-ambient thermal resistance 97.2 73.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.4 N/A °C/W RθJB Junction-to-board thermal resistance 25 N/A °C/W ΨJT Junction-to-top characterization parameter 2.7 4.3 °C/W ΨJB Junction-to-board characterization parameter 24.7 28 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VI = 3 V to 18 V, TJ = –40°C to +165°C, typical values at VI = 12 V and TA = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Operating quiescent current (power save mode) IOUT = 0 mA, device not switching 4 µA IQ;PWM Operating quiescent current (PWM mode) VIN = 12 V, VOUT = 1.2 V; IOUT = 0 mA, device switching 8 mA ISD Shutdown current into the VIN pin EN = 0 V, TJ = –40°C to 150°C 0.27 3.5 µA VUVLO Undervoltage lockout VIN rising, TJ = –40°C to 150°C 2.85 2.925 3.0 V Undervoltage lockout VIN falling 2.7 2.775 2.85 V VUVLO Undervoltage lockout hysteresis 130 mV CONTROL AND INTERFACE ILKG EN input leakage current EN = 5 V 10 310 nA VIH;MODE High-level input voltage at the MODE/S-CONF pin 1.0 V VIL;MODE Low-level input voltage at the MODE/S-CONF pin 0.15 V TSD Thermal shutdown threshold TJ rising 168 175 185 Thermal shutdown threshold TJ falling 12.5 VIH High-level input voltage at the EN pin 0.97 1.0 1.03 V VIL Low-level input voltage at the EN pin 0.820 0.850 0.880 V VPG Power-good threshold VFB rising, referenced to VFB nominal 93.5% 96% 99% VFB falling, referenced to VFB nominal 88.5% 92% 96% VPG_HYS Power-good threshold hysteresis 1.5% 3.5% 6% VPG,OL Low-level output voltage at the PG pin ISINK = 1 mA 0.4 V IPG,LKG Input leakage current into the PG pin VPG = 5 V 25 550 nA tPG,DLY Power-good delay time VFB rising and falling 32 µs RSET VSET resistor tolerance –4% +4% CSET Maximum capacitance connected to the VSET pin 30 pF POWER SWITCHES ILKG;SW Leakage current into the SW pin EN = 0 V, VSW = VOS = 5.5 V 2 7 µA RDS;ON High-side FET on resistance VIN > 4 V, ISW = 500 mA 62 111 mΩ Low-side FET on resistance VIN > 4 V, ISW = 500 mA 22 41 ILIM High-side FET current limit 4 4.6 5.5 A Low-side FET current limit 4.0 4.4 5.0 A ILIM;SINK Low-side FET sink current limit 1.3 1.7 2.5 A TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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VI = 3 V to 18 V, TJ = –40°C to +165°C, typical values at VI = 12 V and TA = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSW Switching frequency 2.5-MHz selection 2.5 MHz TON(MIN) Minimum on time 30 ns fSW Switching frequency 1.0-MHz selection 1.0 MHz OUTPUT VO_Reg1 Output voltage regulation VSET configuration selected, TJ = 25°C –0.9% +0.9% VO_Reg4 Output voltage regulation VSET configuration selected –1.5% +1.5% VFB Feedback regulation voltage Adjustable configuration selected 0.6 V VFB_Reg1 Feedback regulation voltage FB option selected. TJ = 25°C –0.6% +0.6% VFB_Reg4 Feedback regulation voltage FB option selected –1.25% +1.25% IFB Input leakage current into the FB pin Adjustable configuration, VFB = 0.6 V 1 70 nA Tdelay Start-up delay time IO = 0 mA, time from EN = HIGH until start switching, adjustable configuration selected 600 1400 µs Start-up delay time IO = 0 mA, time from EN = HIGH until start switching, VSET configuration selected. The typical value is based on the first option of the VSET configuration. 650 1850 µs TSS Soft-start time IO = 0 mA after Tdelay, from first switching pulse until target VO , CSS = Open 150 200 µs ISS SS/TR source current 2.3 2.5 2.7 µA VFB/VSS/TR Tracking gain, adjustable configuration 0.75 VFB/VSS/TR Tracking gain tolerance –8 +8 mV RDISCH Active discharge resistance Discharge = ON option selected, EN = LOW 7.5 25 Ω www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS62903-Q1

8 Detailed Description

8.1 Overview

The TPS62903-Q1 synchronous switched mode power converters are based on DCS-Control (Direct Control with Seamless Transition into power save mode). DCS-Control is an advanced regulation topology that combines the advantages of hysteretic, voltage mode, and current mode control. This control loop takes information about output voltage changes and feeds the information directly to a fast comparator stage. DCS- Control sets the switching frequency, which is constant for steady-state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.

8.2 Functional Block Diagram

±Ref 1.0V Power Control Power Save Mode Forced PWM 100% Mode HS Limit LS Limit Direct Control TON timer VI VO VFB VO VREF DCS-ControlTM Device Control & Logic Smart-Enable Ref-System UVLO Start-up Handling Smart-CONFIGTM PG-Control Thermal Shutdown Device Control Resistor-to-Digital MODE Detection Internal/External Divider Resistor-to-Digital Gate Driver MODE /S-CONF FB /VSET VO VFB VI TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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8.3 Feature Description

8.3.1 Mode Selection and Device Configuration MODE/S-CONF

With MODE/S-CONF (SmartConfig), this device features an input with two functions. This pin can be used to customize the device behavior in two ways:

Select the device mode (FPWM or auto PFM or PWM with AEE operation) traditionally with a HIGH-level or LOW-level.
Select the device configuration (switching frequency, internal or external feedback, output discharge, and PFM/PWM mode) by connecting a single resistor to the MODE/S-CONF pin. The device interprets this pin during the start-up sequence after the internal OTP readout and before the device starts switching in soft start. If the device reads a HIGH-level or LOW-level, dynamic mode change is active and PFM or PWM mode can be changed during operation. If the device reads a resistor value, there is no further interpretation during operation and device mode or other configurations cannot be changed afterward. Note The MODE/S-CONF pin must not be left floating. Connect the pin high, low, or to a resistor to configure the device according to Table 8-1. EN & UVLO VOUT Precise Enable detection OTP Readout S-CONF Readout VSET Readout Softstart PG -> High Switching Operation No interpretation of MODE/S-CONF or VSET Resistor-to-Digitial readout & interpretation MODE-Pin toggling detection Figure 8-1. Interpretation of S-CONF and VSET Flow www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS62903-Q1

Table 8-1. SmartConfig Setting Table # Level Or Resistor Value [Ω] (1) FB/VSET Pin FSW (MHz) Output Discharge Mode (Auto Or Forced PWM) Dynamic Mode Change Setting Options by Level 1 GND External FB 2.5(1) yes Auto PFM/PWM with AEE Active 2 HIGH (> VIH_MODE) External FB 2.5 yes Forced PWM Setting Options by Resistor 3 7.15 k External FB 2.5(1) no Auto PFM/PWM with AEE Not active 4 8.87 k External FB 2.5 no Forced PWM 5 11.0 k External FB 1 yes Auto PFM/PWM 6 13.7 k External FB 1 yes Forced PWM 7 16.9 k External FB 1 no Auto PFM/PWM 8 21.0 k External FB 1 no Forced PWM 9 26.1 k VSET 2.5(1) yes Auto PFM/PWM with AEE 10 32.4 k VSET 2.5 yes Forced PWM 11 40.2 k VSET 2.5(1) no Auto PFM/PWM with AEE 12 49.9 k VSET 2.5 no Forced PWM 13 61.9 k VSET 1 yes Auto PFM/PWM 14 76.8 k VSET 1 yes Forced PWM 15 95.3 k VSET 1 no Auto PFM/PWM 16 118 k VSET 1 no Forced PWM (1) E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C

8.3.2 Adjustable VO Operation (External Voltage Divider)

The TPS62903-Q1 can be programmed by the MODE/S-CONF pin to either classical configuration where the FB/VSET pin is used as the feedback pin, sensing V O through an external resistive divider. The TPS62903-Q1 can also be programmed to 16 different fixed output voltages. These are set through an external resistor between the FB/VSET pin and GND. In this configuration, VO is directly sensed at the VOS pin of the device. If the device is configured to operate in classical adjustable V O operation, the FB/VSET pin is used as the feedback pin and needs to sense V O through an external divider network. Figure 8-2 shows the typical schematic for this configuration. VIN 3V t17V EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x-Q1 L1 VOUT 0.6V t5.5V GNDR3C3 F F Figure 8-2. Adjustable VO Operation Schematic TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, V O is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by an external resistor connected between the VSET pin and GND. Figure 8-3 shows the typical schematic for this configuration. VIN 3V t17V EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x-Q L1 VOUT 0.4V t5.5V GNDR3C3 F F Figure 8-3. Selectable VO Operation Schematic Table 8-2. VSET Selection Table # Level Or Resistor Value [Ω] (1) Target VO [V] 1 GND 1.2 2 4.64 k 0.4 3 5.76 k 0.6 4 7.15 k 0.8 5 8.87 k 1.0 6 11.0 k 1.1 7 13.7 k 1.3 8 16.9 k 1.35 9 21.0 k 1.8 10 26.1 k 1.9 11 40.2 k 2.5 12 61.9 k 3.8 13 76.8 k 5.0 14 95.3 k 1.25 15 118.0 k 5.5 16 249.00 k or larger/Open 3.3 (1) E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C

8.3.4 Soft Start and Tracking (SS/TR)

With the SS/TR pin, the user can adjust the soft-start behavior and track an external voltage. See Section 9.2.2.6 for operation details. The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush current and makes sure there is a controlled output voltage rise time. The soft-start circuitry also prevents unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a delay, then the internal reference, and hence V O, rises with a slope controlled by an external capacitor connected to the SS/TR pin. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS62903-Q1

Leaving the SS/TR pin unconnected provides the fastest start-up, limited internally (the pin must not be pulled LOW externally). If the device is set to shut down (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down to make sure there is a proper low level. Returning from those states causes a new start-up sequence as set by the SS/TR connection. A voltage supplied to SS/TR can be used to track another system voltage rail. The output voltage follows this voltage up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current.

8.3.5 Smart Enable with Precise Threshold

The voltage applied at the enable pin of the TPS62903-Q1 is compared to a fixed threshold rising voltage. This allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a power-up delay. The precise enable input allows the user to program the undervoltage lockout by adding a resistor divider to the input of the EN pin. The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS62903-Q1 starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side and low-side MOSFETs are turned off and the entire internal control circuitry is switched off. An internal resistor pulls the EN pin to GND when the device is disabled and avoids the pin to be floating (once the device is enabled, the pulldown is removed). This prevents an uncontrolled start-up of the device in case the EN pin cannot be driven to a low level safely. With EN low, the device is in shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit disconnects the pulldown resistor on the EN pin once the internal control logic and the reference have been powered up. With EN set to a low level, the device enters shutdown mode and the pulldown resistor is activated again.

8.3.6 Power Good (PG)

The TPS62903-Q1 has a built-in power-good (PG) feature to indicate whether the output voltage has reached its target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level. PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. V IN must remain present for the PG pin to stay low. If the power-good output is not used, it is recommended to tie to GND or leave it open. Table 8-3. Power Good Indicator Functional Table Logic Signals PG Status VIN EN Pin Thermal Shutdown VOUT VIN > UVLO HIGH No VOUT on target High Impedance VOUT < target LOW Yes × LOW LOW × × LOW

1.8 V< VIN < UVLO × × × LOW

VIN < 1.8 V × × × Undefined Note For prebiased V OUT conditions (during start up) of 60% or more of the programmed output voltage, a minimum 250- μs external soft start (C SS > 0.75 nF) is required. If the 250- μs soft start minimum is not ensured and V OUT is prebiased above 60% of the programmed output voltage during start-up, PG can be seen asserted "early" before V OUT reaches the PG rising threshold, a glitch on PG can be observed, or both. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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8.3.7 Output Discharge Function

The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage when the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge feature is only active once the TPS62903-Q1 has been enabled at least once since the supply voltage was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V.

8.3.8 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input voltage trips below the threshold for a falling supply voltage.

8.3.9 Current Limit And Short Circuit Protection

The TPS62903-Q1 is protected against overload and short circuit events. If the inductor current exceeds the high-side FET current limit (I LIMH), the high-side switch is turned off and the low-side switch is turned on to ramp down the inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side FET current limit threshold. Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit is given as Equation 1: PD L LIMHtyppeak tL VII /c180/c43/c61) ( (1) where

ILIMH is the static high-side FET current limit as specified in the Electrical Characteristics.
L is the effective inductance at the peak current.
VL is the voltage across the inductor (VIN–VOUT).
tPD is the internal propagation delay of typically 50 ns. The current limit can exceed static values, especially if the input voltage is high and very small inductance is used. The dynamic high-side switch peak current can be calculated as follows: n sL V O U TV I NII L I M Ht y pp e a k 5 0)( /c180/c45/c43/c61 (2) The TPS62903-Q1 also includes a low-side negative current limit (ILIM:SINK) to protect against excessive negative currents that can occur in forced PMW mode under heavy to light load transient conditions. If the negative current in the low-side switch exceeds the I LIM:SINK threshold, the low-side switch is disabled. Both the low-side and high-side switches remain off until an internal timer re-enables the high-side switch based on the selected PWM switching frequency. CAUTION It is recommended that the inductor be sized such that the inductor ripple current, ΔIL (see Section 8.4.3), does not exceed 2.6 A to avoid the potential for continuous operation of the negative current limit with no output load (IO = 0 A).

8.3.10 High Temperature Specifications

The TPS62903-Q1 is capable of high operating junction temperatures up to 165°C. The AEC-Q100 Grade-1 maximum ambient temperature requirement (T A_max = 125°C) combined with power dissipation on integrated chips often results in device operating temperatures well above 125 °C. Additionally, although Grade 1 with extended temperature does not exist as a standard by itself, the 165°C maximum operating junction temperature www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS62903-Q1

allows for the TPS62903-Q1 to be used in applications with ambient temperatures upwards of 150°C that require less device power dissipation. Note For more information on the different thermal metrics for semiconductor integrated circuits (ICs) including the relationship between the operating junction (T J) and ambient (T A) temperatures of a device, refer to the Semiconductor and IC Package Thermal Metrics application report. The TPS62903-Q1 is designed to sustain these high temperatures while maintaining performance and reliability, which is accomplished by compliant electrical specifications up to T J = 165°C. In addition, extra reliability testing has been performed that exceeds the AEC-Q100 Grade 1 requirements. The TPS62903-Q1 passes the temperature profile displayed in Table 8-4. Table 8-4. Power On Hours (POH) Profile Junction Temperature (°C)(1) Hours % –40°C to 0°C 720 6 0°C to 50°C 2400 20 50°C to 100°C 7800 65 100°C to 150°C 840 7 150°C to 155°C 120 1 155°C to 165°C 120 1 (1) Due to the variety of voltage and current levels used across different applications, the operating temperature ranges are provided as junction temperature instead of ambient temperature. Table 8-4 shows an automotive profile of time and temperature for the TPS62903-Q1 converter application specified with 12,000 POH. Power-On Hours (POH) reliability for the TPS62903-Q1 is a function of power dissipation, temperature, and time. Increased usage at higher loads or temperatures results in a reduction in the total POH.

8.3.11 Thermal Shutdown

The junction temperature, T J, of the device is monitored by an internal temperature sensor. If T J rises and exceeds the thermal shutdown threshold, T SD, the device shuts down. Both the high-side and low-side power FETs are turned off and PG goes low. When T J decreases below the hysteresis, the converter resumes normal operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A shutdown or restart is only triggered during a switching cycle. See Section 8.4.2. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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8.4 Device Functional Modes

8.4.1 Forced Pulse Width Modulation (FPWM) Operation

The TPS62903-Q1 has two operating modes: forced PWM mode discussed in this section and PWM and PFM as discussed in Section 8.4.2. With the MODE/S-CONF pin configured for FPWM mode, the TPS62903-Q1 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of either 2.5 MHz or 1.0 MHz. The frequency variation in PWM is controlled and depends on V IN, VOUT, and the inductance. The on time in forced PWM mode is given by Equation 3: 1OUT IN sw VTON V f u (3) For very small output voltages, a minimum on time of approximately 30 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high.

8.4.2 Power Save Mode Operation (Auto PFM and PWM)

When the MODE/S-CONF pin is configured for power save mode (auto PFM and PWM). The device operates in PWM mode as long the output current is higher than half of the ripple current of the inductor. To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to discontinuous conduction mode (DCM). PSM occurs if the output current becomes smaller than half of the ripple current of the inductor. Power save mode is entered seamlessly when the load current decreases, which makes sure there is a high efficiency in light load operation. The device remains in power save mode as long as the inductor current is discontinuous. In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency. The transition in and out of power save mode is seamless in both directions. In addition to adjusting the switching, the TPS62903-Q1 adjusts the on time (TON) in power save mode, depending on the input voltage and the output voltage to maintain highest efficiency using the AEE function when 2.5 MHz is selected as described in Section 8.4.3. In power save mode, the TON time can be estimated using Equation 3 for 1 MHz and Equation 7 for 2.5 MHz. For very small output voltages, an absolute minimum on time of approximately 30 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the typical peak inductor current in power save mode is approximated by Equation 4: /c40 /c41 T O NL V O U TV I NI L P S M p e a k /c180/c45/c61)( (4) The output voltage ripple in power save mode is given by Equation 5: /c247 /c248 /c246/c231 /c232 /c230 /c43/c45/c180 /c180/c61/c68 VOUTVOUTVINC VINLV 11 200 (5) where

L is the effective inductance.
C is the output effective capacitance. Note When V IN decreases to typically 15% above V OUT, the TPS62903-Q1 does not enter power save mode, regardless of the load current. The device maintains output regulation in PWM mode. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS62903-Q1

8.4.3 AEE (Automatic Efficiency Enhancement)

When the MODE/S-CONF pin is configured for AEE mode, the TPS62903-Q1 provides the highest efficiency over the entire input voltage and output voltage range by automatically adjusting the switching frequency of the converter. This adjustment is achieved by setting the predictive off time of the converter. The efficiency of a switched mode converter is determined by the power losses during the conversion. The efficiency decreases if VOUT decreases, VIN increases as shown in Equation 6, or both. To keep the efficiency high over the entire duty cycle range (VOUT / VIN ratio), the switching frequency is adjusted while maintaining the ripple current. 2( ) 10 IN OUT sw OUT IN V V F MHz V V u u (6) The AEE function in the TPS62903-Q1 adjusts the on time (TON) in power save mode, depending on the input voltage and the output voltage to maintain highest efficiency. The on time in steady-state operation can be estimated as using Equation 7: /c91 /c93nsVOUTVIN VINTON /c45/c180/c61 100 (7) Equation 8 shows the relation among the inductor ripple current, switching frequency, and duty cycle. 1 ( )1( ) ( ) OUT IN L OUT OUT SW SW V VDI V V L f L f ' u u u u (8) Efficiency increases by decreasing switching losses and preserving high efficiency for varying duty cycles, while the ripple current amplitude remains low enough to deliver the full output current without reaching current limit. The AEE feature provides an efficiency enhancement for various duty cycles, especially for lower V OUT values where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates for the very small duty cycles of high V IN to low V OUT conversion, which limits the control range in other topologies. 8.4.4 100% Duty-Cycle Operation The duty cycle of the buck converter operating in PWM mode is given as D = V OUT / V IN. The duty cycle increases as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time of typically 80 ns is reached, the TPS62903-Q1 scales down its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output voltage is below the internal set point, allowing the conversion of small input to output voltage differences (for example, getting longest operation time of battery-powered applications). In 100% duty cycle mode, the low-side FET is switched off. The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as: spacing /c40 /c41 LonDS RRIOUTVOUTVIN /c43/c43/c61 ) ((min) (9) where

IOUT is the output current.
RDS(on) is the on-state resistance of the high-side FET.
RL is the DC resistance of the inductor used. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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8.4.5 Starting into a Prebiased Load

The TPS62903-Q1 is capable of starting into a prebiased output. The device only starts switching when the internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased to a higher voltage than the nominal value, the TPS62903-Q1 does not start switching unless the voltage at the feedback pin drops to the target. See the note in Section 8.3.6 regarding the soft-start requirement during prebiased conditions. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS62903-Q1

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPS62903-Q1 devices are highly efficient, small, and highly flexible synchronous step-down DC/DC converters that are easy to use. A wide input voltage range of 3 V to 18 V supports a wide variety of inputs like 12-V supply rails, single-cell or multi-cell Li-Ion, and 5-V or 3.3-V rails.

9.2 Typical Application with Adjustable Output Voltage

0.6V t5.5V GNDR3C3 F F Figure 9-1. Typical Application Circuit

9.2.1 Design Requirements

Table 9-1. List of Components Reference Description Manufacturer IC 18 V, 3-A step-down converter TPS62903-Q1 series; Texas Instruments L 1-µH inductor XGL4020-102; Coilcraft CIN 10 µF, 25 V, Ceramic, X8R CGA6P1X8R1E106K250AE, TDK COUT 22 µF, 16 V, Ceramic, X8L CGA6P1X8L1C226M250AC, TDK R1 Depending on VOUT; see Section 9.2.2.2. AEC-Q200 qualified, Standard 1% metal film R2 Depending on VOUT; see Section 9.2.2.2. AEC-Q200 qualified, Standard 1% metal film R3 Depending on device setting, see Section 8.3.1. AEC-Q200 qualified, Standard 1% metal film

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

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Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Programming the Output Voltage

The output voltage of the TPS62903-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to 5.5 V using a resistor divider from V OUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the output voltage is set by the selection of the resistor divider from Equation 10. It is recommended to choose resistor values that allow a current of at least 2 μA, meaning the value of R2 must not exceed 400 k Ω. Lower resistor values are recommended for highest accuracy and most robust design. /c247 /c248 /c246/c231 /c232 /c230 /c45/c61 /c180 121 VFB VOUTRR (10) With typical VFB = 0.6 V: Table 9-2. Setting the Output Voltage Nominal Output Voltage R1 R2 Exact Output Voltage 0.75 V 24.9 kΩ 100 kΩ 0.749 V 1.2 V 100 kΩ 100 kΩ 1.2 V 1.5 V 150 kΩ 100 kΩ 1.5 V 1.8 V 200 kΩ 100 kΩ 1.8 V 2.0 V 49.9 kΩ 21.5 kΩ 1.992 V 2.5 V 100 kΩ 31.6 kΩ 2.498 V 3.0 V 100 kΩ 24.9 kΩ 3.009 V 3.3 V 113 kΩ 24.9 kΩ 3.322 V 5.0V 182 kΩ 24.9 kΩ 4.985 V

9.2.2.3 External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the control loop of the device. The TPS62903-Q1 is optimized to work within a range of external components. The LC output filters inductance and capacitance have to be considered together, creating a double pole responsible for the corner frequency of the converter (see Section 9.2.2.7). Table 9-3 can be used to simplify the output filter component selection. The values in Table 9-3 are nominal values. The effective capacitance was considered to vary by +20% and –50%. Table 9-3. Recommended LC Output Filter Combinations 4.7 µF 10 µF 22 µF 47 µF 100 µF 200 µF 1.5 µH √ √ √ √(3) 3.3 µH √ √ √ √ (1) This LC combination is the standard value and recommended for most applications with 2.5-MHz switching frequency. (2) This LC combination is the standard value and recommended for most applications with 1-MHz switching frequency. (3) Output capacitance needs to have a ESR of ≥ 10 mΩ for stable operation, see Section 9.3.2. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS62903-Q1

9.2.2.4 Inductor Selection

The TPS62903-Q1 is designed for a nominal 1-µH inductor. Larger values can be used to achieve a lower inductor current ripple, but they can have a negative impact on efficiency and transient response. Smaller values than 1 µH cause a larger inductor current ripple, which causes larger negative inductor current in forced PWM mode at low or no output current. Therefore, they are not recommended at large voltages across the inductor as it is the case for high input voltages and low output voltages. Low-output current in forced PWM mode causes a larger negative inductor current peak, which can exceed the negative current limit. At low or no output current and small inductor values, the output voltage cannot be regulated any more. More detailed information on further LC combinations can be found in the Optimizing the TPS62130/40/50/60 Output Filter application report. The inductor selection is affected by several factors like inductor ripple current, output ripple voltage, PWM-to- PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). Equation 11 calculates the maximum inductor current. (max) (max)(max) L OUTL III /c68/c43/c61 (11) (max) (max) (min)

1 OUT

V VI V L f § · ¨ ¸ ¨ ¸ ' u ¨ ¸ u ¨ ¸ © ¹ (12) where

IL(max) is the maximum inductor current.
ΔIL(max) is the maximum peak-to-peak inductor ripple current.
L(min) is the minimum effective inductor value.
fsw is the actual PWM switching frequency.
VOUT is the output voltage.
VIN(max) is the maximum expected output voltage. Calculating the maximum inductor current using the actual operating conditions gives the needed minimum saturation current of the inductor. It is recommended to add a margin of about 20%. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and size as well. The following inductors have been used with the TPS62903-Q1 and are recommended for use: Table 9-4. List of Inductors Type Inductance [µH] Current A Dimensions [L × B × H] mm Manufacturer (1) ISAT at 30% drop The inductor value also determines the load current at which power save mode is entered: LPSMload II /c68/c612 (13)

9.2.2.5 Capacitor Selection

9.2.2.5.1 Output Capacitor

The recommended value for the output capacitor is 22 µF. The architecture of the TPS62903-Q1 allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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capacitance variation with temperature, it is recommended to use X8R dielectric. Using a higher value has advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode (see the Optimizing the TPS62130/40/50/60 Output Filter application report). In power save mode, the output voltage ripple depends on the following:

Output capacitance
ESR
ESL
Peak inductor current . Using ceramic capacitors provides small ESR, ESL, and low ripple. The output capacitor needs to be as close as possible to the device. For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to be observed.

9.2.2.5.2 Input Capacitor

For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and should be placed between VIN and GND as close as possible to those pins. Table 9-5. List of Capacitors Type (1) Nominal Capacitance [µF] Voltage Rating [V] Size Manufacturer CGA6P1X8R1E106K250AE 10 25 1210 TDK CGA6P1X8L1C226M250AC 22 16 1210 TDK (1) Lower of IRMS at 40°C rise or ISAT at 30% drop

9.2.2.5.3 Soft-Start Capacitor

A capacitor connected between SS/TR pin and GND allows a user-programmable start-up slope of the output voltage. SS/TR to VREF ISS Figure 9-2. Soft-Start Operation Simplified Schematic An internal constant current source is provided to charge the external capacitance. The capacitor required for a given soft-start ramp time is given by: SS SS SS REF IC T V u (14) where

CSS is the capacitance required at the SS/TR pin.
TSS is the desired soft-start ramp time.
ISS is the SS/TR source current, see the Electrical Characteristics.
VREF is the feedback regulation voltage divided by tracking gain (VFB / 0.75); see the Electrical Characteristics. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS62903-Q1

The fastest achievable typical ramp time is 150 µs, even if the external C ss capacitance is lower than 680 pF or the pin is open.

9.2.2.6 Tracking Function

If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the Electrical Characteristics. SS/TR to VREF ISS Figure 9-3. Tracking Operation Simplified Schematic /0.75FB SS TRV V u (15) When the SS/TR pin voltage is above 0.8 V, the internal voltage is clamped and the device goes to normal regulation. This action works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside the recommended operating conditions. For decreasing the SS/TR pin voltage in PFM mode, the device does not sink current from the output. The resulting decrease of the output voltage can therefore be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin, which is 6 V. The SS/TR pin is internally connected with a resistor to GND when EN = 0. If the input voltage drops below undervoltage lockout, the output voltage will go to zero, independent of the tracking voltage. Figure 9-4 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function. See Section 9.3.3 in the systems examples. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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TPS6290x 1µH VOUT1 GND F EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x 1µH VOUT2 GND F CSS 10uF VIN=12V 10uF Device 1 Device 2 Figure 9-4. Schematic for Ratiometric and Simultaneous Start-Up The resistive divider of R7 and R8 can be used to change the ramp rate of VOUT2 to be faster, slower, or the same as VOUT1. A sequential start-up is achieved by connecting the PG pin of VOUT of device 1 to the EN pin of device 2. PG requires a pullup resistor. Ratiometric start-up sequence happens if both supplies are sharing the same soft-start capacitor. Equation 14 gives the soft-start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing circuits are found in the Sequencing and Tracking With the TPS621-Family and TPS821-Family application report. Note If the voltage at the FB pin is below its typical value of 0.6 V, the output voltage accuracy can have a wider tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the tracking function, especially for high resistive external voltage dividers on the SS/TR pin.

9.2.2.7 Output Filter and Loop Stability

The devices of the TPS62903-Q1 family are internally compensated to be stable with L-C filter combinations corresponding to a corner frequency to be calculated with Equation 16: www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS62903-Q1

/c215 /c61 /c1122 (16) Proven nominal values for inductance and ceramic capacitance are given in Section 9.2.2.3 and are recommended for use. Different values can work, but care has to be taken on the loop stability, which is affected. More information including a detailed LC stability matrix can be found in the Optimizing the TPS62130/40/50/60 Output Filter application report. The TPS62903-Q1 devices include an internal 3-pF feedforward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per Equation 17 and Equation 18: 2 3 zerof R pFS u u (17) 1 2 1 1 1 2 3 polef pF R RS (18) Though the TPS62903-Q1 devices are stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in power save mode, improved transient response, or both. An external feedforward capacitor can also be added. A more detailed discussion on the optimization for stability versus transient response can be found in the Optimizing Transient Response of Internally Compensated DC-DC Converters and Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family application reports.

9.3 System Examples

9.3.1 LED Power Supply

The TPS62903-Q1 can be used as a power supply for power LEDs. The FB pin can be easily set to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid excessive power loss. Since this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an external resistor per Equation 19. This drop, proportional to the LED current, is used to regulate the output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62903-Q1. Figure 9-5 shows an application circuit, tested with analog dimming. VIN 3V t 17V EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x L1 VOUT GNDR3R4 F F Figure 9-5. Single Power LED Supply The resistor at SS/TR defines the FB voltage. It is set to 304 mV by R SS/TR = R4 = 162 k Ω using Equation 19. This cuts the losses on R4 to half from the nominal 0.6 V of feedback voltage while it still provides good accuracy. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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/0.75 2.5FB SS TRV uA R u u (19) The device now supplies a constant current set by resistor R2 from FB/VSET to GND. The minimum input voltage has to be rated according the forward voltage needed by the LED used. More information is available in the Step-Down LED Driver With Dimming With the TPS621-Family and TPS821-Family application report.

9.3.2 Powering Multiple Loads

In applications where the TPS62903-Q1 is used to power multiple load circuits, the total capacitance on the output can be very large. In order to properly regulate the output voltage, there needs to be an appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output voltage ripple sufficiently high on the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are several load circuits with their associated input capacitor on a PCB, these loads are typically distributed across the board. This adds enough trace resistance (R trace) to keep a large enough AC signal on the VOS pin for proper regulation. The minimum total trace resistance on the distributed load is 10 m Ω. The total capacitance n × CIN in the use case below was 32 × 47 μF of ceramic X7R capacitors. VIN 3V t 17V EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x L1 VOUT 0.6V t 5.5V GNDR3C3 F F Load1Rtrace CIN Load2Rtrace CIN LoadnRtrace CIN Figure 9-6. Multiple Loads Note Figure 9-6 shows an external feedback configuration, but the internal (VSET) configuration can also be used.

9.3.3 Voltage Tracking

Device 2 follows the voltage applied to the SS/TR pin. A ramp on SS/TR to 0.8 V ramps the output voltage according to the 0.6-V reference on VFB. Tracking the 3.8 V of device 1 requires a resistor divider on SS/TR of device 2 to output 0.8 V when the output voltage divider of device 1 is 0.6 V. The output current of 2.5 µA from the SS/TR pin causes an offset voltage on the resistor divider formed by R7 and R8. The equivalent resistance of R7 // R8 must therefore be kept below 15 kΩ. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS62903-Q1

TPS6290x 1µH VOUT1 GND F EN SS/TR VIN MODE/ S-CONF SW PG VOS FB/ VSET TPS6290x 1µH VOUT2 GND F CSS 10uF VIN=12V 10uF Device 1 Device 2 Figure 9-7. Tracking Example Figure 9-8. Tracking

9.3.4 Inverting Buck-Boost (IBB)

The need to generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 18-V input voltage range of the TPS62903-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the output voltage is inverted or negative with respect to ground. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the components are connected the same as with a traditional buck converter, thme output voltage terminals are reversed. See Figure 9-9. The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can be applied to the TPS62903-Q1 in a typical buck configuration. This is because the ground pin of the IC is connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not VIN to ground. Thus, the input voltage range of the TPS62903-Q1 in an IBB configuration becomes 3 V to 18 V + VOUT, where VOUT is a negative value. The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the output voltage for a TPS62903-Q1 in an IBB configuration can be set between –0.4 V and –5.5 V. The maximum output current for the TPS62903-Q1 in an IBB topology is normally lower than a traditional buck configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current capability. When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage rail, and in turn, the electrical characteristics of the TPS62903-Q1 device are referenced to this rail. During power up, as there is no charge in the output capacitor and the IC GND pin (and V OUT) are effectively 0 V, thus parameters such as the V IN UVLO and EN thresholds are the same as in a typical buck configuration. However, after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally continues to operate below what can appear to be the normal UVLO or EN falling thresholds relative to the system ground. Take care if the user is using the dynamic mode change feature on the MODE pin of the TPS62903-Q1 or driving the EN pin from an upstream microcontroller as the high and low thresholds are relative to the negative rail and not the system ground. More information on using a DCS regulator in an IBB configuration can be found in the Description Compensating the Current Mode Boost Control Loop, Using the TPS6215x in an Inverting Buck-Boost Topology, and Using the TPS629210 in an Inverting Buck-Boost Topology application notes. VIN EN VIN MODE/ S-CONF SW PG VOS FB/VSET

10 F 22 F

1.0 µH VOUT -0.6V to -5.5V GND TPS629xx SS/TR Css Figure 9-9. IBB Example with Adjustable Feedback Note Figure 9-9 shows an external feedback configuration, but the internal (VSET) configuration can also be used.

10 Power Supply Recommendations

The power supply to the TPS62903-Q1 needs to have a current rating according to the supply voltage, output voltage, and output current of the TPS62903-Q1. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS62903-Q1

11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS62903-Q1 demands careful attention to make sure the device works correctly and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. See Figure 11-1 for the recommended layout of the TPS62903-Q1, which is designed for common external ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin of TPS62903-Q1. Also, connect the VOS pin in the shortest way to VOUT at the output capacitor. Provide low inductive and resistive paths for loops with high di/dt. Therefore paths, conducting the switched load current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for traces with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an alternating current must outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (for example, SW). As they carry information about the output voltage, they must be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1 and R2, must be kept close to the IC and connected directly to those pins and the system ground plane. The same applies to the VSET resistor if VSET is used to scale the output voltage. The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat through the PCB. In case any of the digital inputs EN and MODE/S-CONF need to be tied to the input supply voltage at V IN, the connection must be made directly at the input capacitor as indicated in the schematics. The recommended layout is implemented on the EVM and shown in the TPS6290x-Q1 Step-Down Converter Evaluation Module user's guide.

11.2 Layout Example

Figure 11-1. Layout TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

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11.2.1 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipation limits of a given component. The basic approaches for enhancing thermal performance are:

Improving the power dissipation capability of the PCB design, for example, increasing copper thickness, thermal vias, number of layers
Introducing airflow in the system For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports. The TPS62903-Q1 is designed for a maximum operating junction temperature (T J) of 165°C. Therefore, the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To get an improved thermal behavior, it is recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance. If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation. The device is qualified for long term qualification with 165°C junction temperature. For more details about the derating and life time of the HotRod™ package, see the Derating and Lifetime Calculations for FCOL Packages HotRod and FC-SOT application note. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS62903-Q1

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS62903-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, Derating and Lifetime Calculations for FCOL Packages HotRod and FC-SOT application note
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs application report
Texas Instruments, TPS6290x-Q1 Step-Down Converter Evaluation Module user's guide
Texas Instruments, Using the TPS629210 in an Inverting Buck-Boost Topology application report
Texas Instruments, Description Compensating the Current Mode Boost Control Loop application report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

SmartConfig™, HotRod™, and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS62903-Q1

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS62903-Q1

www.ti.com PACKAGE OUTLINE C 2X 1.5 8X 0.5 6X 0.775 0.575 13X 0.3 0.2 0.575 0.375 2.1 1.9 2.3 2.1 2X 1 1.05 0.95 0.080.05 0.00 (0.2) TYP

0.1 MIN

(0.05) VQFN-HR - 1 mm max heightRYT0009A PLASTIC SMALL OUTLINE - NO LEAD 4226765/A 04/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.

0.1 C A B

0.05 PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM SYMM TYPICAL SCALE 6.000 SECTION A-A A B TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS62903-Q1

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

(0.825) (0.65) 2X (2.55) 8X (0.5) 2X (1.5) 13X (0.25) 4X (0.4) (R0.05) TYP 2X (1) (0.875) (1.525) VQFN-HR - 1 mm max heightRYT0009A PLASTIC SMALL OUTLINE - NO LEAD 4226765/A 04/2021 NOTES: (continued) 3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE: 30X SYMM SYMM METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS www.ti.com TPS62903-Q1 SLVSG65 – MAY 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS62903-Q1

www.ti.com EXAMPLE STENCIL DESIGN 2X (0.4) 13X (0.25) (2.55) (0.875) (0.825) (0.5) 2X (1.5) (R0.05) TYP (0.65) 2X (1) (1.525) VQFN-HR - 1 mm max heightRYT0009A PLASTIC SMALL OUTLINE - NO LEAD 4226765/A 04/2021 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 30X SYMM SYMM TPS62903-Q1 SLVSG65 – MAY 2022 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS62903-Q1

www.ti.com 15-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS62903QRYTRQ1 ACTIVE VQFN-HR RYT 9 3000 TBD Call TI Call TI -40 to 165 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS62903-Q1 : Addendum-Page 1

www.ti.com 15-May-2022

Catalog : TPS62903 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

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