PPS37100Z91DDYYRQ1

TPS37100-Q1 TI | Alldatasheet

Document overview

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Technical content

TPS37100-Q1, TPS37102-Q1 Automotive 105V, 5μA, Window, Overvoltage, or Undervoltage Supervisor with Integrated Buffer for Supply Voltage Measurements

1 Features

• AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature TA
• ASIL D Functional Safety-Compliant (Targeted for TPS37102-Q1) – Documentation to aid ISO 26262 system design – Systematic capability up to ASIL D targeted – Hardware capability up to ASIL D targeted
• Functional Safety-Capable (TPS37100-Q1) – Documentation available to aid functional safety system design
• Wide supply voltage range: 3V to 105V
• Low quiescent current: 5μA
• High threshold accuracy: 1.1% (maximum)
• -95V reverse polarity protection on SENSE
• 5μs fast UV/OV monitor for 24V/48V systems
• Integrated buffer (AOUT) for supply voltage measurement with enable pin
• Fixed and programmable release time delay
• Fixed and programmable sense time delay
• Open-drain, active-low output: OUT A and OUT B
• BIST and Latch available for TPS37102-Q1

2 Applications

• Battery management unit
• DC/DC converter system
• 2-wheeler and 3-wheeler traction drive
• Low-voltage battery system
• Traction inverter

3 Description

The TPS37100-Q1 and TPS37102-Q1 are 105V input voltage supervisors with low quiescent current (5uA), fast detection time, and an integrated buffer for supply voltage measurements. This family of devices can be connected directly to a 24V / 48V / 72V battery or voltage rail for continuous monitoring of over (OV) or under (UV) voltage conditions. Wide hysteresis voltage options are available to ignore false output deassertions that are be caused by battery voltage transients. The TPS37100-Q1 and TPS37102-Q1 include two outputs (OUT A and OUT B) that are used as separate OV and UV fault monitors enabling system to take different action based on the fault that occurs. Additionally, the AOUT pin provides a scaled down SENSE pin voltage output and is intended to be sampled by ADC for supply voltage measurements. The user can choose the scaling factor desired based on the orderable part selected. The TPS37102-Q1 comes with BIST which is implemented at start-up to verify device health as well as an optional latching feature on OUT A to help the system bring into a safe state when critical faults occurs.

Package Information

PART NUMBER PACKAGE (1) PACKAGE SIZE(3) TPS37100-Q1 SOT-23 (14) (DYY) 4.1mm × 1.9mm TPS37102-Q1 (2) SOT-23 (14) (DYY) 4.1mm × 1.9mm (1) For package details, see the mechanical drawing addendum at the end of the data sheet. (2) PRODUCT PREVIEW (3) The package size (length × width) is a nominal value and includes pins, where applicable. TPS37100-Q1 VDD GND SENSE CTR CTS OUT B AOUT ADC VPULLUP GPIO, EN, ect... OUT A AEN GPIO VPULLUP VDD 3.3V DC/DC 3.3V 48V Rail Typical Application Circuit T e m p e r a t u r e (  C ) Supply Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 0 Typical IDD vs Temperature (VDD = 48V) TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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4 Device Comparison

Figure 4-1 shows some of the device naming nomenclature of the TPS37100-Q1 and TPS37102-Q1. Not all device namings follow this nomenclature table. For a detailed breakdown of every device part number by features, thresholds, and analog out scale see Table 4-1 for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. Table 4-1. Device Threshold Table ORDERABLE PART NAME Feature OV / UV SETTINGS OUT A / OUT B SETTINGS TIME DELAY ANALOG OUT SCALE PPS37100Z91DDYYRQ1 Analog Out VITN: 800mV (ADJ) HYST: 1% OUT A: VITN OUT B: VITN CTS: Disabled CTR: Enabled 0.75 TPS37100W41DDYYRQ1 Analog Out VITP: 832mV (ADJ) VITN: 768mV (ADJ) HYST: 1% OUT A: VITP OUT B: VITN CTS: Disabled CTR: Enabled 0.75 TPS37100JI1GDYYRQ1 Analog Out VITP: 56V VITN: 36V HYST: 1% OUT A: VITP & VITN OUT B: VITP & VITN CTS: Disabled CTR: Enabled 24 1. For listed percentage denotes hysteresis tolerance, see Section 6.5 for more information 2. VITN or VITP threshold with ADJ denotes an adjustable voltage threshold set by an external resistor divider, see Section 7.3.2.1 for more information on how to set the threshold. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS37100-Q1 TPS37102-Q1

TPS3710 X X X X X DYY R Q1

FEATURES

0: AOUT 2: AOUT, BIST UNDERVOLTAGE THRESHOLD Z: 800mV Adjustable A: 18V B: 20V C: 22V D: 24V E: 26V F: 28V G: 30V H: 32V I: 34V J: 36V K: 38V L: 40V M: 42V N: 44V O: 46V P: 48V Q: 50V R: 52V S: 54V T: 56V U: 58V V: 60V X: 62V Y: 64V 0: 66V 1: 68V 2: 70V 3: 72V 4: 74V 5: 76V 6: 78V 7: 80V 8 82V 9: UV not included, OV only W: Adjustable window centered around 800mV with 1% hysteresis. OVERVOLTAGE THRESHOLD Z: 800mV Adjustable A: 40V B: 42V C: 44V D: 46V E: 48V F: 50V G: 52V H: 54V I: 56V J: 58V K: 60V L: 62V M: 64V N: 66V O: 68V P: 70V Q: 72V R: 74V S: 76V T: 78V U: 80V V: 82V X: 84V Y: 86V 0: 88V 1: 90V 2: 92V 3: 94V 4: 96V 5: 98V 6: 100V 7: 102V 8 104V 9: OV not included, UV only * For Adjustable window options, 3 to 9 represent the window size. HYSTERESIS 1: 1% 5: 5% 0: 10% PACKAGE DYY: SOT23-14 REEL R: Large reel Rating Q1: Automotive OUT A / OUT B Settings + TIME DELAY + AOUT SCALE A: CTS: Disabled CTR: Enabled AOUT Scale: 24 OUT A/B: Standard B: CTS: Disabled CTR: Enabled AOUT Scale: 30 OUT A/B: Standard C: CTS: Disabled CTR: Enabled AOUT Scale: 40 OUT A/B: Standard D: CTS: Disabled CTR: Enabled AOUT Scale: 0.75 OUT A/B: Standard E: CTS: Disabled CTR: Enabled AOUT Scale: 0.75 OUT A/B: Combined F: CTS: Disabled CTR: Enabled AOUT Scale: 30 OUT A/B: Combined G: CTS: Disabled CTR: Enabled AOUT Scale: 24 OUT A/B: Combined H: CTS: Enabled CTR: Enabled AOUT Scale: 0.75 OUT A/B: Standard I: CTS: Enabled CTR: Enabled AOUT Scale: 24 OUT A/B: Standard J: CTS: Enabled CTR: Enabled AOUT Scale: 30 OUT A/B: Standard K: CTS: Enabled CTR: Enabled AOUT Scale: 40 OUT A/B: Standard L: CTS: Disabled CTR: Enabled AOUT Scale: 0.75 OUT A/B: Standard Latch: Enabled M: CTS: Enabled CTR: Enabled AOUT Scale: 0.75 OUT A/B: Standard Latch: Enabled Figure 4-1. Device Naming Convention 1. Refer to Table 4-1 for a decoding table by part number. 2. Adjustable OV or UV only options threshold is 800mV. 3. Adjustable Window option thresholds are centered around 800mV. a. Example: TPS37100W41xDYYRQ1 is a ±4% adjustable window device. i.Overvoltage threshold: 800mV × (1 + 0.04) = 832mV (1) ii.Undervoltage threshold: 800mV × (1 − 0.04) = 768mV (2) 4. OUT A/B standard is available for OV only, UV only, and window. OUT A/B Combined is only available for window. Refer to Section 7.3.3. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. DYY Package, 14-Pin SOT-23, TPS37100-Q1 (Top View) 1VDD 2NC 3SENSE 4NC 5OUT A 6NC 7OUT B 14 NC CTS CTR BIST_EN AOUT GND BIST Figure 5-2. DYY Package, 14-Pin SOT-23, TPS37102-Q1 (Top View) PRODUCT PREVIEW Table 5-1. Pin Functions PIN TPS37100-Q1 TPS37102-Q1 I/O DESCRIPTION NAME NO. NO. VDD 1 1 I Input Supply Voltage: Supply voltage pin. For noisy systems, bypass with a 0.1µF capacitor to GND. SENSE 3 3 I Sense Voltage: Connect this pin to the supply rail that must be monitored. See Section 7.3.2 for more details. Sensing Topology: Overvoltage (OV) or Undervoltage (UV) or Window (OV + UV) OUT A 5 5 O Output A: OUT A asserts varies on configuration as denoted by in Section 4. See Section 7.3.2 for more details on overvoltage and undervoltage behavior. The active low open-drain output requires an external pullup resistor. See Section 7.3.3 for more details on open-drain output. Output topology: Open-Drain Active-Low OUT B 7 7 O Output B: OUT B asserts varies on configuration as denoted by in Section 4. See Section 7.3.2 for more details on overvoltage and undervoltage behavior. The active low open-drain output requires an external pullup resistor. See Section 7.3.3 for more details on open-drain output. Output topology: Open-Drain Active-Low BIST - 8 O Built-In Self-Test: BIST asserts when a logic high input occurs on the BIST_EN pin, this initiates the internal BIST testing. BIST recovers after tBIST to signify BIST completed successfully. BIST remains asserted for a time period longer than tBIST if there is a failure during BIST. BIST active-low open-drain output requires an external pullup resistor. See Section 7.3.7 for more details. GND 9 9 - Ground. GND pin must be electrically connected to the board ground. AOUT 10 10 O Analog Out: Output of AOUT is a scaled voltage from the SENSE pin. TPS37100-Q1 can enable or disable Analog Out with AEN Pin. TPS37102-Q1 cannot enable or disable Analog Out and it is in default configuration as denoted in Table 4-1. A 0.1µF is required at AOUT for output stability. See Section 7.3.6 for more details. AEN 11 - I Analog Out Enable: Enables or disables the AOUT pin. A logic high input enables the AOUT. A logic low disables AOUT. AEN pin has an internal 100kΩ pulldown resistor. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS37100-Q1 TPS37102-Q1

Table 5-1. Pin Functions (continued) PIN TPS37100-Q1 TPS37102-Q1 I/O DESCRIPTION NAME NO. NO. BIST_EN - 11 I Built-in Self-test Enable: A rising edge input must occur on the BIST_EN to initate BIST. For variants with latch enabled in the configuration as denoted by in Section 4, BIST_EN enables or disables a latch on OUT A. See Section 7.3.7 for more details. CTR 12 12 - Release Time Delay: User-programmable release time delay for CTR enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.4 for more details. CTS 13 13 - Sense Time Delay: User-programmable sense time delay for CTS enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay when CTS is enabled. See Section 7.3.5 for more details. NC 2, 4, 6, 8, 14 2, 4, 6, 14 - NC stands for “No Connect.” The pins are to be left floating. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted (1) MIN MAX UNIT Voltage VDD, VSENSE(ADJ), VOUT A –0.3 105 V Voltage VSENSE(Fixed) –95 105 V Voltage VAEN, VCTS, VCTR, VOUT B, VAOUT, VBIST, VBIST_EN –0.3 6 V Current IOUT A, IOUT B, I BIST 10 mA Output Short-current (2) IAOUT Continuous µA Temperature Operating junction temperature, TJ –40 150 °C Temperature Operating ambient temperature, TA –40 125 °C Temperature Storage, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Short-circuit to ground.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD 3 105 V Voltage VSENSE, VOUT A 0 105 V Voltage VAEN, VOUT B, VAOUT, V BIST , VBIST_EN 0 5.5 V Current IOUT A, IOUT B, I BIST 0 ±5 mA Current IAOUT 0 ±20 µA TJ Junction temperature (free air temperature) –40 125 °C

6.4 Thermal Information

(1) TPS3710x-Q1 UNITDYY 14-PIN RθJA Junction-to-ambient thermal resistance 120.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 54.2 °C/W RθJB Junction-to-board thermal resistance 50.1 °C/W ψJT Junction-to-top characterization parameter 2.7 °C/W ψJB Junction-to-board characterization parameter 49.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS37100-Q1 TPS37102-Q1

6.5 Electrical Characteristics

At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR = CTS = open, output OUT A and OUT B pull-up resistor with RPU = 10kΩ and VPU = 5.5V. The operating free-air temperature range TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16V. VIT refers to VITN or VITP. AOUT CLoad = 100nF and AOUT VOUT = 2.5V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD VDD Supply Voltage 3 105 V UVLO (1) Undervoltage Lockout VDD Falling below VDD (MIN) 2.6 V UVLO(HYS) (1) Undervoltage Lockout Hysteresis VDD Rising above VDD (MIN) 400 mV VPOR Power on Reset Voltage (2) OUT_A VOL(MAX) = 300mV IOUT A(Sink) = 15µA 1.4 V VPOR Power on Reset Voltage (2) OUT_B VOL(MAX) = 300mV IOUT B (Sink) = 15µA 1.4 V IDD Supply current into VDD pin VDD (MIN) ≤ VDD ≤ VDD (MAX) Analog out = disabled 5 13 µA IDD Supply current into VDD pin VDD (MIN) ≤ VDD ≤ VDD (MAX) Analog out = enabled IAOUT = 0µA 9 18 µA SENSE (Input) ISENSE Input current VIT = 800mV 300 nA ISENSE Input current VIT = 18V to 105V 1.5 8 µA VITN Input Threshold Negative (VITN) VITN = 18V to 105V -1.1 1.1 % VITN = 800mV -0.8 0.8 % VITP Input Threshold Positive (VITP) VITP = 18V to 105V -1.1 1.1 % VITP = 800mV -0.8 0.8 % VHYS Hysteresis Accuracy (3) VIT = 18V to 105V VHYS Range = 1% 1 1.5 % VHYS Hysteresis Accuracy (3) VIT = 800mV VHYS Range = 1% 1 1.8 % VHYS Hysteresis Accuracy (3) VIT = 18V to 105V VHYS Range = 5% 4.5 5 6 % VHYS Hysteresis Accuracy (3) VIT = 800mV VHYS Range = 5% 4.5 5 6 % VHYS Hysteresis Accuracy (3) VIT = 18V to 105V VHYS Range = 10% 9 10 11 % VHYS Hysteresis Accuracy (3) VIT = 800mV VHYS Range = 10% 9 10 11 % OUT A and OUT B (Output) Ilkg(OUT A) Open-Drain leakage VOUT A = 5.5V VITN < VSENSE < VITP 900 nA VOUT A = 105V VITN < VSENSE < VITP 900 nA VOL(OUT A) Low level output voltage 3V ≤ VDD ≤ 105V IOUT A = 2.7mA 350 mV Ilkg(OUT B) Open-Drain leakage VOUT B = 5.5V VITN < VSENSE < VITP 300 nA VOL(OUT B) Low level output voltage 3V ≤ VDD ≤ 105V IOUT B = 5mA 300 mV Capacitor Timing (CTS, CTR) RCTR Internal resistance (CTR) 2960 3700 4440 Kohm RCTS Internal resistance (CTS) 2960 3700 4440 Kohm TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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6.5 Electrical Characteristics (continued)

At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR = CTS = open, output OUT A and OUT B pull-up resistor with RPU = 10kΩ and VPU = 5.5V. The operating free-air temperature range TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16V. VIT refers to VITN or VITP. AOUT CLoad = 100nF and AOUT VOUT = 2.5V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Out IOUT Output buffer current, sink & source -20 +20 µA ISC Short circuit current. 450 µA Slew Rate Slew Rate for current 50 mA/ms VIL_EN 500 mV VIH_EN 1300 mV VAOUT(Min) AOUT Range 0.35 V VAOUT(Max) AOUT Range VDD - VDO < 5V VDD-VDO V VAOUT(Max) AOUT Range VDD - VDO ≥ 5V 5 V VDO Voltage dropout IAOUT = 0µA 0.41 V VDO Voltage dropout IAOUT = 20µA 0.41 V Accuracy 25℃ IAOUT = 0µA, TA = 25℃ Analog Out Scale = 0.75 -0.3 0.3 % Accuracy over Temp IAOUT = 0µA 3V > VAOUT ≥ 0.5V -1 1 % Accuracy over Temp IAOUT = 0µA 0.5V ≥ VAOUT -2 2 % Line Regulation VDD = 3V to 105V -0.1 0.1 % Load Regulation (source) IAOUT = 0µA to 20µA 0.03 %/uA Load Regulation (sink) IAOUT = 0µA to -20µA 0.03 %/uA COUT Output buffer capacitor for stability ESR = 5mΩ to 20mΩ 0.07 0.1 0.13 µF Response time 90% of SENSE input to 0.7% accuracy of VAOUT 2 ms Turn-on (EN) Time IAOUT = 0µA, 1.5 ms Ilkg(BIST_OD) Open-Drain leakage VBIST = 5.5V VITN < VSENSE < VITP 300 nA VBIST_OL Low level output voltage 3V ≤ VDD ≤ 105V IBIST (Sink) = 5mA 300 mV VBIST_EN BIST_EN pin logic low input 500 mV VBIST_EN BIST_EN pin logic high input 1300 mV (1) When VDD voltage falls below UVLO, OUT A and OUT B are asserted until VPOR. VDD slew rate ≤ 1V/µs (2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD slew rate ≤ 1V/µs (3) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS37100-Q1 TPS37102-Q1

6.6 Switching Characteristics

At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR = CTS = open, output OUT A and OUT B pull-up resistor with RPU = 10kΩ and VPU = 5.5V. The operating free-air temperature range TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16V. VIT refers to VITN or VITP. AOUT CLoad = 100nF and AOUT VOUT = 2.5V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Common switching parameters tCTR(OUT A) Release time delay (CTR)(1) VIT = 18V to 100V, CCTR = Open 20% Overdrive from Hysteresis 500 µs tCTR(OUT A) Release time delay (CTR)(1) VIT = 800mV, CCTR = Open 20% Overdrive from Hysteresis 500 µs tCTR(OUT B) Release time delay (CTR)(1) VIT = 18V to 100V, CCTR = Open 20% Overdrive from Hysteresis 500 µs tCTR(OUT B) Release time delay (CTR)(1) VIT = 800mV, CCTR = Open 20% Overdrive from Hysteresis 500 µs tCTS Sense time delay (2) (4) VITP = 800mV, CTS = Disabled 20% Overdrive from VIT 3 µs VITN = 800mV, CTS = Disabled 20% Overdrive from VIT 5 µs VITP = 18V to 100V, CTS = Disabled 20% Overdrive from VIT 6 10 µs VITN = 18V to 100V, CTS = Disabled 20% Overdrive from VIT 6 10 µs VIT = 800mV, CCTS = Open (5) 20% Overdrive from VIT 75 100 µs VIT = 18V to 100V, CCTS = Open (5) 20% Overdrive from VIT 75 120 µs tSD Startup Delay (3) CCTR = Open 1 ms tBIST Test time for BIST 2.5 ms (1) CTR Release detect time delay: Overvoltage active-LOW output is measure from VITP - HYS to VOH Undervoltage active-LOW output is measure from VITN + HYS to VOH (2) CTS Sense detect time delay: Active-low output is measure from VIT to VOL (or VPullup) (3) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state. (4) This parameter is established by design and/or characterization and is not tested in production. (5) CCTS = Open assumes there is less than 20pF of parasitic capacitance on the pin.

6.7 Timing Requirements

At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR = CTS = open, output OUT A and OUT B pull-up resistor with RPU = 10kΩ and VPU = 5.5V. The operating free-air temperature range TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16V. VIT refers to VITN or VITP. AOUT CLoad = 100nF and AOUT VOUT = 2.5V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Common timing parameters tGI_SNS Sense Glitch(1) 10% overdrive, Fixed threshold, CTS = Disabled 1.2 µs tGI_SNS Sense Glitch(1) 10% overdrive, Fixed threshold, CTS = Enabled, CTS = 20pF 65 µs (1) Overdrive % = [(VSENSE/ VIT) - 1] × 100% (3) VIT refers to either VITN or VITP TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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6.8 Timing Diagrams

tSD + tCTR(OUT B) VPOR UVLO(MIN) VDD(MIN) VDD SENSE VITN (UV) + VHYS VITN (UV) OUT B (Window variants) tCTS tCTR (OUT B) Undefinedt < tCTS Undefined tSD + tCTR(OUT A) tCTS tCTR (OUT A) Undefinedt < tCTS OUT A (UV only variants) A. OUT A and OUT B pins are connected via external pull-up resistors to pullup voltages. B. Be advised that Figure 6-1 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time. Figure 6-1. SENSE Undervoltage (UV) Timing Diagram www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS37100-Q1 TPS37102-Q1

tCTR(OUT A) VPOR UVLO VDD(MIN) VDD SENSE VITP - VHYS VITP OUT A (Window variants) tCTS tCTR (OUT A) Undefinedt < tCTS Undefined tSD + tCTR(OUT B) tCTS tCTR (OUT B) Undefinedt < tCTS OUT B (OV only variants) A. OUT A and OUT B pins are connected via external pull-up resistors to pullup voltages. B. Be advised that Figure 6-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time. Figure 6-2. SENSE Overvoltage (OV) Timing Diagram TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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6.9 Typical Characteristics

Typical characteristics show the typical performance of the TPS3710x-Q1 devices. Test conditions are TA = 25°C, RPU = 10kΩ, CLoad = 10pF, AOUT CLoad = 100nF and AOUT VOUT = 2.5V, unless otherwise noted. VIT refers to VITN or VITP. T e m p e r a t u r e (  C ) Supply Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 0 Figure 6-3. Typical IDD vs Temperature (VDD = 48V) with AOUT Disabled T e m p e r a t u r e (  C ) Supply Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 2 1 5 1 8 Figure 6-4. Typical IDD vs Temperature (VDD = 48V) with AOUT Enabled Figure 6-5. Typical Adjustable VIT Accuracy vs Temperature T e m p e r a t u r e (  C ) VIT Accuracy (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 - 0 . 5 0 . 5 1 Figure 6-6. Typical Fixed VIT Accuracy vs Temperature T e m p e r a t u r e (  C ) VIT Hysteresis (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 0 . 5 1 . 5 Figure 6-7. Typical VIT 1% Hysteresis vs Temperature T e m p e r a t u r e (  C ) VIT Hysteresis (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 4 . 5 5 . 5 6 Figure 6-8. Typical VIT 5% Hysteresis vs Temperature www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS37100-Q1 TPS37102-Q1

7 Detailed Description

7.1 Overview

The TPS3710x-Q1 is a family of high voltage and low quiescent current voltage supervisors with overvoltage and undervoltage threshold voltage, delay timings, Built-In Self-Test ( TPS37102-Q1 only), and AOUT. The TPS3710x-Q1 over and undervoltage thresholds are device specific and are offered in either adjustable thresholds or fixed thresholds. The adjustable threshold option uses an external resistor ladder to make a voltage divider on SENSE pin which uses the internal 800mV threshold to trigger overvoltage and/or undervoltage faults. The benefit of using an adjustable option with external resistors is the faster reaction speed compared to a fixed internal threshold variant. The TPS3710x-Q1 fixed threshold option utilizes an integrated voltage divider to eliminate the need for external resistors and provides a lower total current consumption. VDD, SENSE, and OUT A pins can support 105V continuous operation. SENSE has -95V reverse polarity protection for fixed threshold options only. VDD, SENSE, OUT A, and OUT B pins are voltage level independent of each other. Fixed and programmable sense and release time delay options are available to avoid false assertion and false deassertions. The AOUT pin provides a scaled output voltage from the SENSE for both fixed and adjustable options. The AOUT pin is intended to be sampled with an ADC for supply voltage measurements. The AOUT and supervisor combination simplifies high voltage rail monitoring for low voltage ADCs.

7.2 Functional Block Diagram

BIST BIST_EN TPS37102 Only TPS37100 Only OUT A OUT B Figure 7-1. Fixed Threshold Functional Block Diagram Timing Logic VREF Output Logic SENSE VDD OUT A CTS CTR Buffer AOUT AEN GND OUT B BIST BIST BIST_EN TPS37102 Only TPS37100 Only Figure 7-2. Adjustable Threshold Functional Block Diagram TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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7.3 Feature Description

7.3.1 Input Voltage (VDD)

VDD operating voltage ranges from 3V to 105V. An input supply capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 0.1µF capacitor between the VDD and GND. VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional. VDD voltage is independent of V SENSE, VOUT A, and VOUT B, meaning that VDD can be higher or lower than the other pins.

7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)

When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (V POR), the OUT A, OUT B, and BIST pins are asserted, regardless of the voltage at SENSE pin.

7.3.1.2 Power-On Reset (VDD < VPOR )

When the voltage on VDD is lower than the power-on reset voltage (V POR), the output signal is undefined and is not to be relied upon for proper device function.

7.3.2 SENSE

The SENSE pin connects to the supply rail that is to be monitored. The sense pin on each device is configured to monitor either overvoltage (OV), undervoltage (UV), or window (OV and UV) conditions. TPS3710x-Q1 device offers built-in hysteresis that provides noise immunity and maintains stable operation. Although not required in most cases, designers can use either t CTS or place a 10nF to 100nF bypass capacitor at the SENSE input to reduce sensitivity to transient voltages on the monitored signal. SENSE can be connected directly to VDD pin.

7.3.2.1 Adjustable Voltage Thresholds

Section 7.3.2.1 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. Adjustable voltage threshold variants bypass the internal resistor ladder. For example, consider a 48V rail, V MON, being monitored for undervoltage (UV) only using of the TPS37100Z91DDYYRQ1 variant. The monitored UV threshold, denoted as V MON-, is the desired voltage where the device asserts the reset. For this example V MON- = 40V. To assert an undervoltage reset the voltage at the sense pin, V SENSE, needs to be equal or lower to the input threshold positive, V ITN. For this example variant VSENSE = V ITN = 0.8V. Using R 1 and R 2 the correlation between V MON- and V SENSE can be seen in Equation 4. Assuming R2 = 2kΩ, and R1 can be calculated as R1 = 98kΩ. VSENSE = VMON- × [R2 ÷ (R1 + R2)] (4) The TPS37100Z91DDYYRQ1 comes with variant specific 1% voltage threshold hysteresis. For the reset signal to become deasserted, V MON must go above V ITN + V HYS. For this example variant a 1% voltage threshold hysteresis was selected. Therefore, VMON equals 40.4V when the reset signal becomes deasserted. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS37100-Q1 TPS37102-Q1

Figure 7-3. Adjustable Voltage Threshold with External Resistor Dividers

7.3.2.2 SENSE Hysteresis

TPS3710x-Q1 device offers built-in hysteresis around the UV and OV thresholds to avoid erroneous OUT A and OUT B deassertions. The hysteresis is opposite to the threshold voltage; for overvoltage options the hysteresis is subtracted from the positive threshold (V ITP), for undervoltage options hysteresis is added to the negative threshold (VITN). Figure 7-4 and Figure 7-5 highlight the OUT A and OUT B behavior based on a window variant with standard OUT A/B. VOUT A VSENSE VITP - VHYS VITP Figure 7-4. Hysteresis (Overvoltage Active-Low) VOUT B VSENSE VITN VITN+VHYS Figure 7-5. Hysteresis (Undervoltage Active-Low) Table 7-1. Common Adjustable Threshold Hysteresis Lookup Table TARGET DEVICE HYSTERESIS OPTIONADJUSTABLE THRESHOLD TOPOLOGY RELEASE VOLTAGE (V) 800mV Overvoltage 792mV -1% 800mV Overvoltage 760mV -5% 800mV Overvoltage 720mV -10% 800mV Undervoltage 808mV 1% 800mV Undervoltage 840mV 5% 800mV Undervoltage 880mV 10% Table 7-1 shows a sample of hysteresis for the 800mV adjustable variant of TPS3710x-Q1. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is (V ITN + VHYS) and for the overvoltage (OV) channel is (VITP - VHYS). Undervoltage (UV) VITN = 800mV Voltage Hysteresis (VHYS) = 1% = 8mV Release Voltage = VITN + VHYS = 808mV Overvoltage (OV) VITP = 800mV Voltage Hysteresis (VHYS) = 1% = 8mV Release Voltage = VITP - VHYS = 792mV

7.3.2.3 Reverse Polarity Protection

SENSE has -95V reverse polarity protection for fixed threshold options only. Adjustable threshold option does not have reverse polarity protection.

7.3.3 Output Logic Configurations

TPS3710x-Q1 is a single channel device that has a single input SENSE pin with dual outputs, OUT A and OUT B pins. The OUT A and OUT B pins are available only with open-drain active-low topology.

7.3.3.1 Open-Drain

The open-drain output pins require an external pull-up resistor to hold the voltage high to the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at the correct interface voltage levels. To select the right pull-up resistor, consider system V OH and the Open-Drain Leakage Current (I lkg) provided in the electrical characteristics, high resistors values have a higher voltage drop affecting the output voltage high. The open-drain outputs can be connected as a wired-AND logic with other open-drain signals such as another TPS3710x-Q1 open-drain output pin.

7.3.3.2 Active-Low (OUT A and OUT B)

OUT A and OUT B (active low) remain high voltage (V OH, deasserted) as long as sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. STANDARD: For window (Overvoltage + Undervoltage) standard output variants , to assert the OUT A or OUT B the sense pins needs to meet one of the conditions below:

• For OUT A, the SENSE voltage need to cross the upper boundary (VITP).
• For OUT B, the SENSE voltage needs to cross the lower boundary (VITN). COMBINED: For window (Overvoltage + Undervoltage) combined output variants , to assert the OUT A and OUT B the sense pins needs to meet one of the conditions below:
• The SENSE voltage need to cross the upper boundary (VITP).
• The SENSE voltage needs to cross the lower boundary (VITN). STANDARD: For Undervoltage only variants, to assert the OUT A or OUT B the sense pins needs to meet the condition below:
• For OUT A and OUT B, the SENSE voltage need to cross the lower boundary (VITN). STANDARD: For Overvoltage only variants, to assert the OUT A or OUT B the sense pins needs to meet the condition below:
• For OUT A and OUT B, the SENSE voltage needs to cross the upper boundary (VITP). www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS37100-Q1 TPS37102-Q1

7.3.4 User-Programmable Release Time Delay

TPS3710x-Q1 has adjustable release time delay with external capacitors.

• A capacitor on CTR programs the deassertion release time of the output.
• No capacitor on this pin gives the fastest release time indicated by tCTR in Section 6.6.
• Certain variants use a fixed internal time delay. Check Table 4-1 to verify variant specific timing.

7.3.4.1 Deassertion Time Delay Configuration

Capacitor release time delay (t CTR) occurs when the OUT A and OUT B transitioning from a fault state (V OL) to a non-fault state (V OH). The time delay (t CTR) can be programmed by connecting a capacitor between CTR pin and GND. For situations with a fault on SENSE after OUT A and OUT B recovers, the TPS3710x-Q1 makes sure that the CTR capacitor is fully discharged before starting the recovery sequence. This makes sure that the programmed CTR time is maintained for consecutive faults. The relationship between external capacitor CCTR_EXT (typ) and the time delay tCTR (typ) is given by Equation 5. tCTR (typ) = RCTR (typ) x CCTR_EXT (typ) + tCTR (CTR = open) (5) RCTR (typ) = is in kilo ohms (kΩ) CCTR_EXT (typ) = is given in microfarads (μF) tCTR (typ) = is given in milliseconds (ms) The release delay time varies according to three variables: the external capacitor (C CTR_EXT), CTR pin internal resistance (R CTR) provided in Section 6.5, and the constant (t CTR (CTR = open) ) provided in Section 6.7. The minimum and maximum variance due to the constant is show in Equation 6 and Equation 7: tCTR (min) = RCTR (min) x CCTR_EXT (min) + tCTR (CTR = open) (6) tCTR (max) = RCTR (max) x CCTR_EXT (max) + tCTR (CTR = open) (7) There is no limit to the capacitor on CTR pin. Having a too large of a capacitor value can cause very slow charge up (rise times) due to capacitor leakage and system noise can cause the internal circuit to hold OUT A or OUT B active. * Leakages on the capacitor can affect accuracy of release time delay.

7.3.5 User-Programmable Sense Delay

TPS3710x-Q1 has adjustable sense release time delay with external capacitors.

• A capacitor on CTS programs the sense time delay of the input.
• When TCTS is enabled, no capacitor on this pin gives the fastest sense delay time indicated by tCTS in Section 6.7.
• Certain TPS3710x-Q1 variants comes with an optional fixed internal time delay that disables the CTS pin and offers the fastest detection time (5μs). Check the Section 4 to verify variant specific functionality.

7.3.5.1 Sense Time Delay Configuration

SENSE time delay (t CTS) is the minimum length of time required to count a fault on the SENSE pin as a valid fault and assert OUT A and OUT B. The time delay (t CTS) can be programmed by connecting a capacitor between CTS pin and GND. The relationship between external capacitor CCTS_EXT (typ) and the time delay tCTS (typ) is given by Equation 8. tCTS (typ) = RCTS (typ) x CCTS_EXT (typ) + tCTS (CTS = Open) (8) RCTS (typ) = is in kilo ohms (kΩ) CCTS_EXT (typ) = is given in microfarads (μF) TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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tCTS (typ) = is given in milliseconds (ms) The sense delay varies according to three variables: the external capacitor (C CTS_EXT), CTS pin internal resistance (R CTS) provided in Section 6.5, and the constant ( t CTS (CTS = Open) ) provided in Section 6.5. The minimum and maximum variance due to the constant is show in Equation 9 and Equation 10: tCTS (min) = RCTS (min) x CCTS_EXT (min) + tCTS (CTS = Open) (9) tCTS (max) = RCTS (max) x CCTS_EXT (max) + tCTS (CTS = Open) (10) The recommended maximum sense delay capacitor for the TPS3710x-Q1 is 10 μF as this makes sure there is enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the internal circuit to trip unpredictably. This leads to a variation in time delay where the delay accuracy can be worse in the presence of system noise. * Leakages on the capacitor can affect accuracy of sense time delay.

7.3.6 Analog Out

The TPS3710x-Q1 family contains one buffer for supply voltage measurements. The integrated buffer outputs a voltage on the AOUT pin that is representative on the SENSE pin input voltage. The AOUT pin paired with an ADC can be used to directly measure the voltage on the SENSE pin. The AOUT simplifies the need for an external discrete network of resistors, capacitors, and FETs to measure a high voltage rail with a low voltage ADC. The AOUT voltage is dependent on the analog out scale factor. The analog out scale factor can be found in Table 4-1. AOUT = SENSE / Analog Out Scale (11) For Figure 7-6 the outputs are calculated in Equation 12. AOUT = SENSE / Analog Out Scale = 1.6V / 0.75 = 2.133V (12) The AOUT pin requires a 0.1µF capacitor for stability. Place the stability capacitor as close as possible to the pin. TI recommends to use a stability capacitor on AOUT even if the feature is not in use. The AOUT can also be enabled or disabled using AEN on certain variants. When AEN > 1.3V the AOUT is enabled. When the AEN < 0.5V the AOUT is disabled. The AEN has a 100k Ω pull-down resistor which sets the default behavior as disabled. AOUT is always enabled for variants without AEN pin. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS37100-Q1 TPS37102-Q1

T i m e ( s ) Voltage (V) 0 . 5 1 . 5 2 . 5 A O U T S E N S E Figure 7-6. AOUT following SENSE pin.

7.3.7 Built-in Self-Test

The built-in self-test (BIST) feature is only in TPS37102-Q1 option only. TPS37100-Q1 does not have BIST. The BIST sequence of internal tests verifies the health of the internal signal chain of the device by checking for faults on the internal comparators on the SENSE pin, bandgap voltage, and OUT A and OUT B outputs. The TPS37102-Q1 has a Built-In Self-Test (BIST) feature that runs diagnostics internally in the device to monitor the health of the device. During power-up BIST is initiated automatically after crossing V DD(min). During BIST the BIST pin and OUT A and OUT B output asserts low and deasserts if the BIST test completes successfully indicating no internal faults in the device. The length of the BIST and BIST assertion is specified by tBIST. If BIST is not successful, the BIST pin stays asserted low signifying an internal fault. The OUT A and OUT B output asserts on BIST failure. During BIST, the device is not monitoring the SENSE pin for faults and the OUT A and OUT B is not dependent on the SENSE pin voltage. After a successful power-up sequence, BIST can be initiated any time with a rising edge input (V BIST_EN > 1.3V) on the BIST_EN pin. BIST initiates and the BIST pin asserts only if the SENSE pin is not in a overvoltage or undervoltage fault mode.

7.3.7.1 Latch

The TPS37102-Q1 comes with the optional output reset latching feature for the window (OV & UV) and OV only variants, check the Table 4-1 to verify variant specific latch functionality. When using a variant with latch, latch is enabled when enabled V BIST_EN < 0.5V and latch is disabled when V BIST_EN > 1.3V. The BIST_EN pin has an internal pull-down resistor to GND which enables latch at startup. When latch is enabled and a OV fault occurs, OUT A asserts and stays asserted regardless of voltage on SENSE pin. When V BIST_EN > 1.3V, latch disabled, and SENSE < V ITP + HYST then OUT A deasserts after a delay. This delay is dependent on BIST and CTR timing. While VBIST_EN > 1.3V, the device is in latch disabled mode and OUT A asserts for OV faults but does not latch. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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BIST_EN SENSE VITN VITP - VHYS tCTS VITP VPULLUP GND tBIST_EN tBIST Unmonitored tCTR BIST VBIST-PULLUP GND tBIST_recover Figure 7-7. TPS37102 Latch Disable www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS37100-Q1 TPS37102-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The following sections describe in detail how to properly use this device. As this device has many applications and setups, there are many situations that this data sheet can not characterize in detail and vary from these applications depending on the requirements of the final application

8.2 Typical Application

8.2.1 Design 1: Off-Battery Monitoring

This application is intended for the initial power stage in applications with the 48V batteries. Variation of the battery voltage is common between 40V and 55V. Furthermore, load transients can cause voltage spikes up to 100V. In this design example, we are highlighting the ability for low power, direct off-battery voltage supervision with capabilities to handle 100V transients. Figure 8-1 illustrates an example of how the TPS37100-Q1 is monitoring the battery voltage while being powered by the same rail. TPS37100-Q1 VDD GND SENSE CTR CTS OUT B AOUT ADC VPULLUP GPIO, EN, ect... OUT A AEN GPIO VPULLUP VDD 3.3V DC/DC 3.3V 48V Rail Figure 8-1. TPS37100-Q1 Overvoltage Supervisor with Direct Off-Battery Monitoring

8.2.1.1 Design Requirements

This design requires voltage supervision on a 48V battery voltage rail with possibility of the 48V battery rail rising up as high as 100V. The undervoltage fault occurs when the power supply voltage drops below 40V. PARAMETER DESIGN REQUIREMENT DESIGN RESULT Power Rail Voltage Supervision Monitor 48V power supply for undervoltage condition, trigger a undervoltage fault at 40V. TPS3710x-Q1 provides undervoltage monitoring up to 100V. Maximum Input Power Operate with power supply input up to 100V. The TPS3710x-Q1 VDD, SENSE, OUT A pin can support a VDD of up to 105V. Output logic voltage Open-Drain Output Topology OUT A and OUT B are both open-drain outputs. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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PARAMETER DESIGN REQUIREMENT DESIGN RESULT Maximum system current consumption 1mA max when power supply is at 48V typical TPS3710x-Q1 allows for IQ to remain low with support of up to 100V. The Adjustable variant does require external resistors which increases the power consumption. A fixed threshold variant does not require external resistors which decreases the power consumption. Always on monitor Maximum voltage monitor accuracy of 1.5%. The TPS3710x-Q1 has 0.8% maximum voltage monitor accuracy. Feature ADC monitoring for telemetry The TPS3710x-Q1 has a AOUT pin that can be sampled by an ADC for voltage telemetry.

8.2.1.2 Detailed Design Procedure

The primary advantage of this application is being able to directly monitor a voltage on an automotive battery with the SENSE input. Voltage rail monitoring is done by connecting the SENSE input to a external resistor ladder then to the battery rail. The TPS3710x-Q1 that is being used in this example is an adjustable voltage variant where the monitored threshold voltage has to be set externally. Word of caution, the TVS protection diodes must be chosen such that the transient voltages on the monitored rails do not exceed the absolute max limit listed in Section 6.1. Adjustable threshold variants do not offer reverse polarity protection on the SENSE pin. To use this configuration, the specific voltage threshold variation of the device must be chosen according to the application. In this configuration, the TPS37100Z91DDYYRQ1 is used and has the parameters and features listed in Table 4-1. The 40V undervoltage threshold is set by R1 and R2. Assuming R 2 = 2k Ω, and R 1 can be calculated as R 1 = 98kΩ. The AOUT pin requires a 0.1µF stability capacitor. When operating at 48V the AOUT = 1.6V which pairs well with a 3 or 3.3V ADC of a MCU. OUT A and OUT B can be connected to different loads. Example, OUT A be connected to the enable of a wide VIN DC/DC converter while OUT B can be connected to a MCU GPIO. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS37100-Q1 TPS37102-Q1

8.2.1.3 Application Curves

Figure 8-2. TPS3710x-Q1 waveform

8.3 Power Supply Recommendations

These devices are designed to operate from an input supply with a voltage range between 3V (V POR) to 105V (maximum operation). Good analog design practice recommends placing a minimum 0.1µF ceramic capacitor as near as possible to the VDD pin.

8.3.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. The maximum continuous allowable power dissipation for the device in a given package can be calculated using Equation 13: PD-MAX = ((TJ-MAX – TA) / RθJA) (13) The actual power being dissipated in the device can be represented by Equation 14: PD = VDD × IDD + POUT A +POUT B (14) POUT A and P OUT B are calculated by Equation 15 or Equation 16. VOUT A and V OUT B depend on the assertion status of the outputs. POUT A = VOUT A x IOUT A (15) POUTB = VOUT B x IOUT B (16) Equation 13 and Equation 14 establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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device. These two equations must be used to determine the optimum operating conditions for the device in the application. In applications where lower power dissipation (P D) and/or excellent package thermal resistance (R θJA) is present, the maximum ambient temperature (TA-MAX) can be increased. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (T A-MAX) have to be de-rated. T A-MAX is dependent on the maximum operating junction temperature (T J-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 17: TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (17)

8.4 Layout

8.4.1 Layout Guidelines

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a greater than 0.1µF ceramic capacitor as near as possible to the VDD pin.
• To further improve the noise immunity on the SENSE pins, either use the CTS feature with a 100pF capacitor or place a 10nF to 100nF capacitor on the SENSE pin.
• If a capacitor is used on CTS or CTR, place these components as close as possible to the respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of parasitic capacitance on the pins to less than 20pF as this affects the delay of CTS and CTR.
• To further improve the noise immunity on the SENSE pins, either use the CTS feature with a 100pF capacitor or place a 10nF to 100nF capacitor on the SENSE pin.
• Place the AOUT stability capacitor as close as possible to the pin.
• For the open-drain outputs, place the pull-up resistors on OUT A, OUT B, and BIST as close to the pin as possible.
• When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If high and low voltage traces need to run close by, spacing between traces must be greater than 20mils (0.5mm).
• Do not have high voltage metal pads or traces closer than 20mils (0.5mm) to the low voltage metal pads or traces.

8.4.2 Layout Example

The layout example in Figure 8-3 shows how the TPS37100-Q1 is laid out on a printed circuit board (PCB) with user-defined delays. 3 12 4 11 5 10 141VDD TPS37100-Q1 GND NC NC OUT A Vias used to connect pins for application-specific connections NC NC AOUT AEN GND SENSE NC OUT B VPULLUP Figure 8-3. TPS37100-Q1 Recommended Layout www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS37100-Q1 TPS37102-Q1

Vias used to connect pins for application-specific connections NC BIST AOUT BIST_EN GND SENSE NC OUT B VPULLUP VPULLUP Figure 8-4. TPS37102-Q1 Recommended Layout

8.4.3 Creepage Distance

Per IEC 60664, Creepage is the shortest distance between two conductive parts or as shown in Figure 8-5 the distance between high voltage conductive parts and grounded parts, the floating conductive part is ignored and subtracted from the total distance. a b BA C Figure 8-5. Creepage Distance Figure 8-5 details

• A = Left pins (high voltage)
• B = Central pad (conductive not internally connected, can be left floating or connected to GND)
• C = Right pins (low voltages)
• Creepage distance = a + b TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (September 2024) to Revision A (September 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS37100-Q1 TPS37102-Q1

www.ti.com 6-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PPS37100Z91DDYYRQ1 Active Preproduction SOT-23-THIN (DYY) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 125 PPS37100Z91DDYYRQ1.A Active Preproduction SOT-23-THIN (DYY) | 14 3000 | LARGE T&R - Call TI Call TI -40 to 125 TPS37100W41DDYYRQ1 Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 371W41DQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 6-Nov-2025 OTHER QUALIFIED VERSIONS OF TPS37100-Q1 :

• Catalog : TPS37100 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

0.1 C A B

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

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