PPS35AA38AGADDFRQ1

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TPS35-Q1 Automotive Nano IQ Precision Voltage Supervisor with Precision Watchdog Timer NOVEMBER 2022

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TPS35-Q1 Automotive Nano IQ Precision Voltage Supervisor with Precision Watchdog Timer

1 Features

AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to 125°C ambient operating temperature range
Input voltage range: VDD = 1.04 V to 6.0 V
Fixed threshold voltage (VIT-): 1.05 V to 5.4 V – Threshold voltage available in 50 mV steps – 1.2% Voltage threshold accuracy (maximum) – Built-in hysteresis (VHYS): 5% (Typical)
Ultra low supply current: IDD = 250 nA (typical)
Factory programmed or user-programmable watchdog timeout – ±10% Accurate timer (maximum) – Factory programmed: 1 msec to 100 sec
Factory programmed or user-programmable reset delay – ±10% Accurate timer (maximum) – Factory programmed option: 2 msec to 10 sec
Open-drain, push-pull; active-low outputs
Various programmability options: – Watchdog enable-disable – Watchdog startup delay: no delay to 10 sec – On the fly timer extension: 1X to 256X – Latched output option
MR functionality support

2 Applications

On-board (OBC) and wireless charger
Driver monitoring
Battery Management System (BMS)
Front camera
Surround view system ECU

3 Description

The TPS35-Q1 is an ultra-low power consumption (250 nA typical) device offering a precision voltage supervisor with a programmable watchdog timer. The TPS35-Q1 supports wide threshold levels for undervoltage supervision with 1.2% accuracy across the specified temperature range. The TPS35-Q1 offers a high accuracy watchdog timer with a host of features for a wide variety of applications. The watchdog timer can be factory programmed or user programmed using an external capacitor. The timer value can be changed on-the- fly using a combination of logic pins. The watchdog feature can be enabled or disabled using a dedicated pin or combination of timer extension pins. The device also offers start-up delay options to disable watchdog monitoring for fixed time immediately after host power up or a RESET event . The TPS35-Q1 offers a pinout option with an independent WDO pin. This helps determine the nature of the fault condition. The RESET or WDO delay can be set by factory- programmed default delay settings or programmed by an external capacitor. The device also offers a latched output operation where the output is latched until the supervisor or watchdog fault is cleared. The TPS35-Q1 is available in a small 8-pin SOT23 package. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) TPS35-Q1 DDF (8) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS35-Q1 µC RESET RESET WDO NMI GPIOWDI WD-EN GPIO SET[0:1] GPIO GND GND VDD VDD CWD CRST MR GND TPS35-Q1 offers various pinout options to support different features. Choose suitable pinout based on application needs Supply Typical Application Circuit ADVANCE INFORMATION TPS35-Q1 SLVSGE8 – NOVEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

12.1 Receiving Notification of Documentation Updates..25

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES November 2022 * Initial Release TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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5 Device Comparison

Figure 5-1 shows the device naming nomenclature of the TPS35-Q1. For all possible output types, threshold voltage options, watchdog time options and output assert delay options, see Section 8 for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. TPS35 X X XX X X X XXX X Q1 Pinout Op on A B C D Threshold Voltage 01: 1.05 V 02: 1.10 V ... 87: 5.35 V 88: 5.40 V Package DDF: SOT23-8 Output Topology, Startup Delay A: DL, No Delay B: DL, 200 msec C: DL, 500 msec D: DL, 1 sec E: DL, 5 sec F: DL, 10 sec G: PL, No Delay H: PL, 200 msec I: PL, 500 msec J: PL, 1 sec K: PL, 5 sec L: PL, 10 sec Watchdog Time A: External Capacitor B: 1 msec C: 5 msec D: 10 msec E: 20 msec F: 50 msec G: 100 msec H: 200 msec I: 1 sec J = 1.4 sec K = 1.6 sec L = 10 sec M = 50 sec N = 100 sec Watchdog Time Scaling A: 1, 2, 4 B: 1, 4 , 8 C: 1, 8, 16 D: 1, 16, 32 E: 1, 32, 64 F: 1, 64, 128 G: 1, 128, 256 Output Assert Time A: External Capacitor B: 2 msec C: 10 msec D: 25 msec E: 50 msec F: 100 msec G: 200 msec H: 1 sec I: 10 sec J = Latched output Tape/Reel R: Reel T: Tape Refer ‘Mechanical, Packaging and Orderable Informa on’ sec on for list of released orderable. For any other orderable, contact local TI support. Figure 5-1. Device Naming Nomenclature TPS35-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in Table 5-1. Table 5-1. Pin Compatible Device Families Device Voltage Supervisor Type of Watchdog TPS35-Q1 Yes Timeout TPS36-Q1 Yes Window TPS3435-Q1 No Timeout TPS3436-Q1 No Window www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS35-Q1

6 Pin Configuration and Functions

Figure 6-1. Pin Configuration Option A TPS35-Q1 Top View Not to scale VDD WDI SET1 CWD GND CRST 3 6 SET0 RESET Figure 6-2. Pin Configuration Option B TPS35-Q1 Top View Not to scale VDD WD-EN SET1GND WDI 3 6 SET0 RESET MR Figure 6-3. Pin Configuration Option C TPS35-Q1 Top View Not to scale VDD SET1GND WDI 3 6 SET0 WD-EN RESET WDO Figure 6-4. Pin Configuration Option D TPS35-Q1 Top View Table 6-1. Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See Section 8.3.4 for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog timeout is set by connecting a GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See Section 8.3.3 for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See Section 8.3.4 for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 8.3.2.4 for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 8.3.2.4 for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See Section 8.3.2.2 for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin before the timeout expires in order for RESET / WDO to not assert. See Section 8.3.2 for more details. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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Table 6-1. Pin Functions (continued) PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See Section 8.3.4 for more details. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS35-Q1

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted(1) MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI, MR (2), RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 (3) V RESET (Open Drain), WDO (Open Drain) –0.3 6.5 Current RESET, WDO pin –20 20 mA Temperature (4) Operating ambient temperature, TA –40 125 Temperature (4) Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. (3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller (4) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±4000 V Charged device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.7 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO(Open Drain) 0 6 RESET (Push Pull) , WDO (Push Pull) 0 VDD Current RESET WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ (1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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7.4 Thermal Information

THERMAL METRIC(1) TPS35-Q1 UNITDDF (SOT23-8)

8 PINS

RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS35-Q1

7.5 Electrical Characteristics

At 0.9 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy (1) VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin (2) VDD = 2 V VIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃ 0.25 1 µA 0.25 3.2 VDD = 6 V VIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃ 0.25 1 0.25 3.2 VIL Low level input voltage WD–EN, WDI, SETx, MR (2) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (2) 0.7VDD V RMR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VPOR Power on Reset voltage (3) VOL(max) = 300 mV IOUT(Sink) = 15 µA 900 mV VOL Low level output voltage VDD = 0.7 V, 1.05 V ≤ VIT– ≤ 1.5 V IOUT(Sink) = 15 µA 300 mVVDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 V IOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 V IOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6V TA = –40℃ to 85℃ 10 100 nA VDD = VPULLUP = 6V 10 350 nA RESET / WDO (Push-pull active-low) VPOR Power on Reset voltage (3) VOL(max) = 300 mV IOUT(Sink) = 15 µA 900 mV VOL Low level output voltage VDD = 0.7 V, 1.05 V ≤ VIT– ≤ 1.5 V IOUT(Sink) = 15 µA 300 mVVDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 V IOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 V IOUT(Sink) = 2 mA 300 VOH High level output voltage VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 V IOUT(Source) = 500 µA 0.8VDD VVDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 V IOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 V IOUT(Source) = 2 mA 0.8VDD (1) VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps. (2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. (3) VPOR is the minimum VDD voltage level for a controlled output state TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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7.6 Timing Requirements

At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive(1) 10 µs tMR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame (2) VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation (2) VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting (2) VDD > VIT– 150 µs tWD Watchdog timeout period Orderable Option TPS35xxxxA; CCWD = 0.1µF TBD TBD TBD ms Orderable Option TPS35xxxxB 0.8 1 1.2 Orderable Option TPS35xxxxC 4 5 6 Orderable Option TPS35xxxxD 9 10 11 Orderable Option TPS35xxxxE 18 20 22 Orderable Option TPS35xxxxF 45 50 55 Orderable Option TPS35xxxxG 90 100 110 Orderable Option TPS35xxxxH 180 200 220 Orderable Option TPS35xxxxI 0.9 1 1.1 s Orderable Option TPS35xxxxJ 1.26 1.4 1.54 Orderable Option TPS35xxxxK 1.44 1.6 1.76 Orderable Option TPS35xxxxL 9 10 11 Orderable Option TPS35xxxxM 45 50 55 Orderable Option TPS35xxxxN 90 100 110 (1) Overdrive % = [(VDD/ VIT–) – 1] × 100% (2) Not production tested www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS35-Q1

7.7 Switching Characteristics

At 1.05 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(2) CCRST pin = Open or NC 500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%) (1) 30 50 µs tSD Watchdog startup delay Orderable part number TPS35xA, TPS35xG 0 msOrderable part number TPS35xB, TPS35xH 180 200 220 Orderable part number TPS35xC, TPS35xI 450 500 550 Orderable part number TPS35xD, TPS35xJ 0.9 1 1.1 sOrderable part number TPS35xE, TPS35xK 4.5 5 5.5 Orderable part number TPS35xF, TPS35xL 9 10 11 tD Reset time delay (3) Orderable part number TPS35xxxxxxA; CCRST = 0.1uF (4) TBD TBD µs Orderable part number TPS35xxxxxxB 1.6 2 2.4 ms Orderable part number TPS35xxxxxxC 9 10 11 ms Orderable part number TPS35xxxxxxD 22.5 25 27.5 ms Orderable part number TPS35xxxxxxE 45 50 55 ms Orderable part number TPS35xxxxxxF 90 100 110 ms Orderable part number TPS35xxxxxxG 180 200 220 ms Orderable part number TPS35xxxxxxH 0.9 1 1.1 s Orderable part number TPS35xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s tMR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = VMR_H to VMR_L 100 ns tMR_tD Delay from MR release to reset deassert VDD = 3.3 V, MR = VMR_L to VMR_H tD s (1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS (2) When VDD starts from less than the specified minimum VDD and then exceeds VIT-, reset is release after the startup delay (tSTRT), a capacitor at CT pin will add tD delay to tSTRT time (3) VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%) (4) Refer Section 8.3.4 to understand programmable delay set using external capacitor TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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7.8 Timing Diagrams

Devices with only RESET output, the output will be AND operation of RESET and WDO signals. Figure 7-1. Functional Timing Diagram www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS35-Q1

8 Detailed Description

8.1 Overview

The TPS35-Q1 is a high-accuracy under voltage supervisor with an integrated timeout watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. Relevant failure mode distribution and pin failure mode analysis details are available to compute system level ASIL ratings.

8.2 Functional Block Diagrams

Figure 8-1. Pinout Option A GND Reference GND Capacitance Detection Watchdog Timer Logic RESET Logic Oscillator VDD CRST CWD WDI SET0 SET1 GND RESET Figure 8-2. Pinout Option B TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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Figure 8-3. Pinout Option C GND Reference GND Watchdog Timer Logic RESET and WDO Logic Oscillator VDD WDI SET0 SET1 WD-EN GND RESET WDO Figure 8-4. Pinout Option D

8.3 Feature Description

8.3.1 Voltage Supervisor

The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < V POR, the RESET and WDO outputs will be actively driven when VDD is greater than V POR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for t STRT + t D time after the VDD > V IT+ (VIT- + V HYS). Refer Section 8.3.4 for the t D value computation. For a capacitor based t D delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (V IT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below V IT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS35-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above V IT+. The t D time duration can be programmable using an external capacitor or fixed time options offered by the device. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS35-Q1

The typical timing behavior for a voltage supervisor and the RESET output is showcased in Figure 8-5 diagram. The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the t D time duration has elapsed. VDD WDI ttDttP-HL Ignore ttSDt ttWDt ttDt VPOR VIT+ VIT- ttWDt Ignore ttWDt ttSDt ttSDt Ignore tP-WD WDO RESET tSTRT + tD Devices with only RESET output, the output will be AND operation of RESET and WDO signals. Figure 8-5. Voltage Supervisor Timing Diagram

8.3.2 Timeout Watchdog Timer

The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The timeout watchdog is active when the VDD voltage is higher than the V IT- + V HYS and the RESET is deasserted after the t D time. The watchdog stays active as long as VDD > V IT- and watchdog is enabled. TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by t WD time period. Refer Section 8.3.2.1 section to arrive at the relevant t WD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the t WD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD. Refer Section 8.3.4 to arrive at the relevant tD value needed for appliaction. Figure 8-6 shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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Devices with only RESET output, the RESET output will be asserted when watchdog error occurs. Figure 8-6. Timeout Watchdog Timer Operation 8.3.2.1 tWD Timer The t WD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D . The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS35-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event . The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at t WD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure C CWD is < 200 x C CRST for accurate calibration of capacitance. Equation highlights the relationship between t WD in second and CWD capacitance in farad. The t WD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWD (sec) = 4.95 x 106 x CCWD (F) (1) The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for t WD ≥ 10 msec. For t WD < 10 msec, the accuracy is ±20%. t WD value relevant to application can be identified from the orderable part number. Refer Section 5 section to identify mapping of orderable part number to tWD value. The TPS35-Q1 offers flexibility to change the t WD value on the fly by controlling the logic levels on the SETx pins. Section 8.3.2.4 section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.

8.3.2.2 Watchdog Enable Disable Operation

The TPS35-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below.

Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error interrupt.
Keep watchdog disabled until host boots up. The TPS35-Q1 supports watchdog enable or disable functionality through either WD-EN pin or SET[1:0] = 0b'01 logic combination or by keeping WDI pin in the floating state. For a given pinout only one of these three methods is available for the user to disable watchdog operation. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS35-Q1

For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The Figure 8-7 diagram shows timing behavior with WD-EN pin control. VDD WDI ttWDt ttDt VIT+ Ignore WD-EN ttWDt tWD Ignore WDO RESET Devices with only RESET output, the output will be AND operation of RESET and WDO signals. Figure 8-7. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during A pinout which does not offer WD-EN or SET[1:0] pins uses WDI float pin status to disable the watchdog operation. Users can float the WDI pin during normal operation to disable the watchdog. To enable watchdog, drive the WDI pin and apply a valid edge to trigger the watchdog. It is recommended to drive HIGH and then LOW when exiting the WDI float state. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Note, capacitance value is detected and latched during start-up or after an error event. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or error condition is needed to detect change in capacitance. When watchdog is disabled the ongoing frame will be terminated and WDO will stay deasserted. For a pinout with only RESET output, the RESET may assert if supply supervisor error occurs. When enabled the device will immediately enter tWD frame and start watchdog monitoring operation. 8.3.2.3 tSD Watchdog Start Up Delay The TPS35-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When t SD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer Section 5 section for details to map the part number to tSD time. The t SD frame is complete when the time duration selected for t SD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during t SD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in Section 8.3.2.2 section. Figure 8-8 diagram shows the operation for tSD time frame. VDD WDI Ignore ttSDt ttDt VPOR VIT+ ttWDt ttWDtttSDt Ignore tSTRT + tD WDO RESET Devices with only RESET output, the output will be AND operation of RESET and WDO signals. Figure 8-8. tSD Frame Behavior

8.3.2.4 SET Pin Behavior

The TPS35-Q1 may offer one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the t WD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are

Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base t WD timer value is decided based on the Watchdog Time selector in the Section 5 section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated t WD timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the t WD multiplier value is decided based on the Watchdog Time Scaling selector in the Section 5 section. Table 8-1 table showcases an example of the t WD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec. Table 8-1. tWD Scaling with SET0 Pin Only Watchdog Time Scaling selection tWD SET0 = 0 SET0 = 1 A 10 msec 20 msec B 10 msec 40 msec C 10 msec 80 msec www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS35-Q1

Table 8-1. tWD Scaling with SET0 Pin Only (continued) Watchdog Time Scaling selection tWD SET0 = 0 SET0 = 1 D 10 msec 160 msec E 10 msec 320 msec F 10 msec 640 msec G 10 msec 1280 msec Pinout which offer both SET0 & SET1 pins to the user, the t WD multiplier value is decided based on the Watchdog Time Scaling selector in the Section 5 section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. Table 8-2 table showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. Table 8-2. tWD Scaling with SET0 & SET1 Pins, WD-EN Pin Not Available Watchdog Time Scaling selection tWD A 100 msec Watchdog disable 200 msec 400 msec B 100 msec Watchdog disable 400 msec 800 msec C 100 msec Watchdog disable 800 msec 1600 msec D 100 msec Watchdog disable 1600 msec 3200 msec E 100 msec Watchdog disable 3200 msec 6400 msec F 100 msec Watchdog disable 6400 msec 12800 msec G 100 msec Watchdog disable 12800 msec 25600 msec 1. Example for Watchdog Time setting = 100 msec. Selected pinout option may offer WD-EN pin along with SET[1:0] pins. With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec. Figure 8-9 to Figure 8-11 diagrams show the timing behavior with respect to SETx status changes. WDO WDI ttWDt WD_EN = 1 ttWDt ttWDt ttWD X nt SETx ttWD X nt ttWD X mt ttWD X mt WD multiplier = 1 WD multiplier = n WD multiplier = m Figure 8-9. Watchdog Behavior with SETx Pin Status TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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SET Pin (2 Pins) Operation; WD_EN pin Not available SET[1:0] 00 = WD multiplier = 1 01 = WD Disabled 10 = WD multiplier = n 11 = WD multiplier = m WD time value tWD WD Disabled tWD X mtWD X n SET Pin (2 Pins) Operation; WD_EN available = 1 SET[1:0] 00 or 01 = WD multiplier = 1 10 = WD multiplier = n 11 = WD multiplier = m WD time value tWD tWD X mtWD X n tWD = Fixed based on OPN or programmable using capacitor n,m = Fixed based on timeset multiplier chosen Figure 8-10. Watchdog Operation with 2 SET Pins SET0 0 = WD multiplier = 1 1 = WD multiplier = n 0 = WD multiplier = 1 1 = WD multiplier = n WD time value tWD tWD X n tWD tWD X n tWD = Fixed based on OPN or programmable using capacitor n = Fixed based on timeset multiplier chosen Figure 8-11. Watchdog Operation with 1 SET Pin

8.3.3 Manual RESET

The TPS35-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 k Ω pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time t D is elapsed . Refer Figure 8-12 for more details. MR tP-HL 0.3 x VDD ttSDt ttDt RESET 0.7 x VDD Figure 8-12. MR Pin Response www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS35-Q1

8.3.4 RESET and WDO Output

The TPS35-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer Section 5 section for all available options. Equation 2 describes the relationship between capacitor value and the time tD. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tD (sec) = 4.95 x 106 x CCRST (F) (2) TPS35-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the V IT- + V HYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x V DD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again.

8.4 Device Functional Modes

Table 8-3 summarizes the functional modes of the TPS35-Q1. Table 8-3. Device Functional Modes VDD Watchdog Status WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tpulse (1) < tWD(min) High High Enabled tpulse (1) > tWD(max) Low High (1) Where tpulse is the time between falling edges on WDI. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application requirements.

9.1.1 CRST Delay

The TPS35-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor.

9.1.1.1 Factory-Programmed RESET Delay Timing

Fixed watchdog timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWD.

9.1.1.2 Adjustable Capacitor Timing

The TPS35-Q1 also utilizes a programmable reset delay, using a precision current source to charge an external capacitor upon device startup. By monitoring the voltage on the CRST pin, the TPS35-Q1 can be programmed to have a desired reset delay. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by Equation 3 , where t D is the reset delay time in seconds and C CRST is the capacitance in microfarads. tD (sec) = 4.95 × 106 × CCRST (F) (3) Note that in order to minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. Table 9-1 lists the reset delay time ideal capacitor values for CCRST. Table 9-1. Reset Delay Time for Common Ideal Capacitor Values CCRST RESET DELAY TIME (tD) UNIT MIN (1) TYP MAX (1) 10 nF 44.55 49.5 54.45 ms 100 nF 445.5 495 544.5 ms 1 μF 4455 4950 5445 ms (1) Minimum and maximum values are calculated using ideal capacitors.

9.1.2 CWD Functionality

The TPS35-Q1 features two options for setting the watchdog timer: using a fixed timing and programming the timing through an external capacitor.

9.1.2.1 Factory-Programmed RESET Delay Timing

Fixed watchdog timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWD. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS35-Q1

9.1.2.2 Adjustable Capacitor Timings

Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult Equation 1 for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.

9.2 Typical Applications

9.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer

The TPS35-Q1 features high-accuracy (1.2% maximum) voltage supervising along with on-the-fly adjustable watchdog timing in order to monitor critical processing elements in systems. In this example, the TPS35CD13KAGDDFRQ1 is used to monitor a microcontroller supply voltage and watchdog. VDD GND TPS35-Q1 1.8V MicrocontrollerSET1 VDD CRST GNDCWD SET0 WDI GPIO RESETRESET Figure 9-1. Microcontroller Supply and Watchdog Monitoring Circuit

9.2.1.1 Design Requirements

Table 9-2. Design Parameters PARAMETER DESIRED REQUIREMENT DESIGN RESULT Threshold Voltage Typical threshold voltage of 1.65 V Typical threshold voltage of 1.65 V Watchdog Timeout Period Typical timeout period of 1.6 s Typical timeout period of 1.6 s RESET Delay Typical reset delay of 200 ms Typical reset delay of 200 ms Startup Delay Minimum startup delay of 700 ms Minimum startup delay of 900 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3.2 μA maximum

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Setting the Voltage Threshold

The negative-going threshold voltage, V IT-, is set by the device variant. Equation 4 shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1)/0.05 (4) In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device will be reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using Equation 4, the part number is reduced to TPS35xx13xxxxxxxQ1. Since the hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is 1.73 V. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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9.2.1.2.2 Meeting the Watchdog Timeout Period

The watchdog timeout design requirement can be met either by using a fixed-timeout version of the TPS35- Q1 or by connecting a capacitor between the CWD pin and GND. The typical values can be met with preprogrammed fixed time options, hence a pinout offering fixed time options is selected. Please see the Timing Requirements for a list of fixed timeouts. If using the CWD feature, pinout A or B must be used; please refer to tWD Timer for instructions on how to program the timout period.

9.2.1.2.3 Setting the Reset Delay

The reset delay requirement can be met either by using a fixed-timeout version of the TPS35-Q1 or by connecting a capacitor between the CRST pin and GND. The typical values can be met with preprogrammed fixed time options, hence a pinout offering fixed time options is selected. Please see the Timing Requirements for a list of fixed timeouts. If using the CRST feature, pinout A or B must be used; please refer to the Timing Specifications for instructions on how to program the timout period.

9.2.1.2.4 Setting the Startup Delay and Output Topology

The startup delay and output topology are set by the device variant. Please refer to Device Comparison for the possible options. A minimum startup delay of 700 ms and open-drain output are desired, thus Option D, 1 s typical startup delay and open-drain active-low, is selected.

9.2.1.2.5 Calculating the RESET Pullup Resistor

The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in Figure 9-2 . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that V OL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (V PU), the recommended maximum RESET pin current (I RST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with I RST kept below 2 mA for V DD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep I RST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. RESET VDD RESET CONTROL Figure 9-2. Open-Drain RESET Configuration

10 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.04 V and 6.5 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS35-Q1

11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.

Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin.
If a CCRST capacitor or pullup resistor is used, place these components as close as possible to the CRST pin. If the CRST pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
If a CCWD capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
Place the pullup resistor on the RESET pin as close to the pin as possible.

11.2 Layout Example

Figure 11-1. Typical Layout for the TPS35-Q1 TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. www.ti.com TPS35-Q1 SLVSGE8 – NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS35-Q1

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS35-Q1 SLVSGE8 – NOVEMBER 2022 www.ti.com ADVANCE INFORMATION

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www.ti.com 16-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS35AA38AGADDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX

6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

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