PPS3423DAHGFADRLR

Texas Instruments

TPS3423, TPS3424, Nano-Power, Push-Button Controllers With Configurable Delay to enable Battery Freshness Seal SEPTEMBER 2024

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TPS3423_V01 TI | Alldatasheet

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PDF pages: 27

Technical content

TPS3423, TPS3424, Nano-Power, Push-Button Controllers With Configurable Delay to enable Battery Freshness Seal

1 Features

Operating voltage range: 1V to 6V
Nano supply current: 22nA (typical)
HBM ESD rating on push-button pin: 10kV
Programmable short press and long press duration – TPS3423, TPS3424 fixed timing options:
Short press duration: 50msec to 13 sec
Long press duration: 1sec to 30 sec
Timer accuracy (max): 10 % – TPS3424: user-programmable option (50 msec to 50 sec) through external capacitor
Output configurations: – RESET configurations:
Push-pull / open-drain, active high / low
Latched / non-latched
100msec to 1sec pulse option for non- latched version – INT configurations:
open drain, active low
non-latched (100msec to 1sec pulse duration)
Kill feature: used as feedback from the host to de- assert RESET
Available in pin compatible 8 pin and 6 pin DRL package

2 Applications

Wearables
Gaming consoles
Home theater entertainment
Printers
Health care
Portable electronics
Factory automation & control

3 Description

TPS3423 and TPS3424 are push-button controllers which offer wide range of independent short press and long press functionality. These devices offer up to two outputs per push-button (RESET and INT), which can be used for various use cases including enabling the voltage regulator or circuit breakers, sending an interrupt to micro controller and generating logic. The device generates an interrupt pulse both for short press and long press notifying the micro controller. RESET output changes the state based on the device configuration. By controlling the power tree running off the battery, TPS3423/4 extends battery life and prolongs device shelf life. This feature is also known as battery freshness seal. TPS3423/4 are offered in fixed timing options for short and long press durations. To provide flexibility to the designer, TPS3424 also offers user-programmable short and long press durations through an external capacitor. Kill pin in TPS3424 enables feedback from the microcontroller to asynchronously de-assert RESET. Device Information PART NUMBER PACKAGE (1) PACKAGE SIZE (3) TPS3423 DRL (SOT-5X3) 2.10mm × 1.60mm DRL (SOT-5X3) (2) 1.60mm × 1.20mm TPS3424 DRL (SOT-5X3) 2.10mm × 1.60mm DRL (SOT-5X3) (2) 1.60mm × 1.20mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package (3) The package size (length × width) is a nominal value and includes pins, where applicable VDD PB Kill INTSPT RST LPT GND GND VBAT GND TPS3424 DC/DC EN VOUT VDD µC 10k Push-bu on 10k TPS3424 Typical Application Diagram ADVANCE INFORMATION TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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4 Device Comparison

Figure 4-1 and Figure 4-3 shows the device nomenclature of the TPS3423 and TPS3424, for output / push- button input, short press and long press, interrupt, reset and kill timing options. Figure 4-2 extends nomenclature of TPS3423 to provide 2 different timing option for channels. Refer Section 7 for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options. TPS3423 X X X X X X XXX X RESET Topology, PB Topology A: PH, AL B: PL, AL C: DL, AL D: DH, AL E: PH, AH F: PL, AH G: DL, AH H: DH, AH Short press dura on (PB1, PB2) A: 50 ms B: 100 msec C: 200 msec D: 500 msec E: 800 msec F: 1 sec G: 1.6 sec H: 2 sec I: 4 sec J: 5 sec K: 6 sec L: 8 sec M: 10 sec N: 12 sec O: 13 sec DL – Open Drain ac ve low RESET DH – Open Drain ac ve high RESET PL – Push-pull ac ve low RESET PH – Push-pull ac ve high RESET AH – Ac ve high push-bu on input AL – Ac ve low push-bu on input Package DRL Tape/Reel R: Reel SINT – Interrupt dura on at short press LINT – Interrupt dura on at short press SP – Short press LP – Long press RESET pulse Latching op on , RESET pulse width (RESET1 , RESET2) 1: Latched , NA A: Non-latched (SP: No Reset, LP: RESET at INT), 50 ms B: Non-latched (SP: RESET post INT, LP: RESET at INT), 50 ms C: Non-latched (SP: No Reset, LP: RESET at INT) , 100 ms D: Non-latched (SP: RESET at INT, LP: RESET post INT), 100 ms E: Non-latched (SP: RESET post INT, LP: RESET at INT), 100 ms F: Non-latched (SP: No Reset, LP: RESET at INT) , 500 ms G: Non-latched (SP: No Reset, LP: RESET at INT) , 1 sec H: Non-latched (SP: No Reset, LP: RESET at INT) , 2 sec I: Non-latched (SP: No Reset, LP: RESET at INT) , 5 sec INT dura on (INT1, INT2) A: SINT = 2 msec, LINT = SINT B: SINT = 50 msec, LINT = SINT 1 C: SINT = 50 msec, LINT = SINT 2 D: SINT = 50 msec, LINT = SINT 4 E: SINT = 100 msec, LINT = SINT 2 F: SINT = 100 msec, LINT = SINT 4 G: SINT = 200 msec, LINT = SINT 2 H: SINT = 200 msec, LINT = SINT 4 I: SINT = 500 msec, LINT = SINT 2 Long press dura on (PB1, PB2) A: 1 sec B: 1.6 sec C: 2 sec D: 4 sec E: 5 sec F: 6 sec G: 7 sec H: 8 sec I: 10 sec J: 12 sec K: 14 sec L: 16 sec M:20 sec N: 25 sec O: 30 sec OPN with long press dura on shorter than short press is not supported No of Pins A: 8 Pins B: 6 pins Figure 4-1. Dual Push-Button Nomenclature TPS3423 X X X X X X XXX X RESET Topology, PB Topology Refer Figure 4-1 Short press dura on (PB1, PB2) P: PB1-50ms : PB2- 1 sec Package DRL Tape/Reel R: Reel RESET pulse Latching op on , RESET pulse width (RESET1 , RESET2) Refer Figure 4-1 INT dura on (INT1, INT2) Refer Figure 4-1 Long press dura on (PB1, PB2) P: PB1-1 sec PB2-30 sec Q: PB1- 5 sec PB2-10 sec No of Pins A: 8 pin B: 6 pin Figure 4-2. Dual Push-Button Extended Nomenclature www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

TPS3424 X X X X X X X XXX X Short press dura on A: 50 ms B: 100 msec C: 200 msec D: 500 msec E: 800 msec F: 1 sec G: 1.6 sec H: 2 sec I: 4 sec J: 5 sec K: 6 sec L: 8 sec M: 10 sec N: 12 sec O: 13 sec 1: SPT Cap DL – Open Drain ac ve low RESET DH – Open Drain ac ve high RESET PL – Push-pull ac ve low RESET PH – Push-pull ac ve high RESET AH – Ac ve high push-bu on input AL – Ac ve low push-bu on input Package DRL Tape/Reel R: Reel SINT – Interrupt dura on at short press LINT – Interrupt dura on at short press SP – Short press LP – Long press RESET pulse Latching op on , RESET pulse width 1: Latched , NA A: Non-latched (SP: No Reset, LP: RESET at INT), 50 ms B: Non-latched (SP: RESET post INT, LP: RESET at INT), 50 ms C: Non-latched (SP: No Reset, LP: RESET at INT) , 100 ms D: Non-latched (SP: RESET at INT, LP: RESET post INT), 100 ms E: Non-latched (SP: RESET post INT, LP: RESET at INT), 100 ms F: Non-latched (SP: No Reset, LP: RESET at INT) , 500 ms G: Non-latched (SP: No Reset, LP: RESET at INT) , 1 sec H: Non-latched (SP: No Reset, LP: RESET at INT) , 2 sec I: Non-latched (SP: No Reset, LP: RESET at INT) , 5 sec INT dura on A: SINT = 2 msec, LINT = SINT B: SINT = 50 msec, LINT = SINT 1 C: SINT = 50 msec, LINT = SINT 2 D: SINT = 50 msec, LINT = SINT 4 E: SINT = 100 msec, LINT = SINT 2 F: SINT = 100 msec, LINT = SINT 4 G: SINT = 200 msec, LINT = SINT 2 H: SINT = 200 msec, LINT = SINT 4 I: SINT = 500 msec, LINT = SINT 2 Kill Dura on 1: 50 msec 2: 200 msec 3: 500 msec 4: 1 sec Long press dura on A: 1 sec B: 1.6 sec C: 2 sec D: 4 sec E: 5 sec F: 6 sec G: 7 sec H: 8 sec I: 10 sec J: 12 sec K: 14 sec L: 16 sec M:20 sec N: 25 sec O: 30 sec 1: LPT Cap SPT Cap – Short press dura on is programmed by load capacitor on SPT , leave the SPT pin oa ng for xed short press dura on LPT Cap – Long press dura on is programmed by load capacitor on LPT , leave LPT pin oa ng for long press OPN with long press dura on shorter than short press is not supported RESET Topology, PB Topology A: PH, AL B: PL, AL C: DL, AL D: DH, AL E: PH, AH F: PL, AH G: DL, AH H: DH, AH No of Pins A: 8 Pins B: 6 pins Figure 4-3. Single Push-Button Nomenclature TPS3423/4 belongs to family of devices offering different feature sets as highlighted in Device Information. Device Information PART NUMBER NO. OF PUSH-BUTTONS PUSH-BUTTON TIMING OPTION KILL FEATURE TPS3423 2 Fixed No TPS3424 1 Fixed , programmable with external capacitor Yes TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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5 Pin Configuration and Functions

/RESET1 INT2 PB1 VDD GND RESET2 /RESET2 Figure 5-1. Pin Configuration Option: TPS3423 8-Pin SOT-5X3 Top View PB21 3 4 6PB1 VDD GND RESET1 /RESET1 RESET2 /RESET2 Figure 5-2. Pin Configuration Option TPS3423 6-Pin SOT-5X3 Top View KILL1 3 6 LPT SPT PB VDD GND INT RESET /RESET Figure 5-3. Pin Configuration Option TPS3424 8-Pin SOT-5X3 Top View KILL1 3 4 INT5 6PB VDD GND RESET /RESET Figure 5-4. Pin Configuration Option TPS3424 6-Pin SOT-5X3 Top View www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

Table 5-1. TPS3423 - Pin Functions TPS3423 I/O DESCRIPTIONPIN NAME 8 PIN SOT-5X3 6 PIN SOT-5X3 PB1 1 1 I Push-button input 1, refer Section 7.3.1.1 for additional details. GND 2 2 - Ground connection for IC. VDD 3 3 I Supply connection, connect a 0.1µF capacitor near the pin for best performance. INT2 4 O Interrupt output for push-button input 2, INT2 is open drain active low output which toggles from every short press and long press on push- button input 2 as described in Section 7.3.2.1 INT1 5 O Interrupt output for push-button input 1, INT1 is open drain active low output which toggles from every short press and long press on push- button input 1 as described in Section 7.3.2.1 RESET1/ RESET1 6 4 O RESET output for push-button input 1. The response of RESET to short press and long press is described in Section 7.3.2.2. RESET2/ RESET2 7 5 I RESET output for push-button input 2. The response of RESET to short press and long press is described in Section 7.3.2.2. PB2 8 6 Push-button input 2, refer Section 7.3.1.1 for additional details. TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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Table 5-2. TPS3424 - Pin Functions TPS3424 I/O DESCRIPTIONPIN NAME 8 PIN SOT-5X3 6 PIN SOT-5X3 PB 1 1 I Push-button input, refer Section 7.3.1.1 for additional details. GND 2 2 - Ground connection for IC. VDD 3 3 I Supply connection, connect a 0.1µF capacitor near the pin for best performance. SPT 4 Connect capacitor to program short press time as described in Section 7.3.1.1 for SPT Cap version. LPT 5 O Connect capacitor to program long press time as described in Section 7.3.1.1 for LPT Cap version. RESET/ RESET 6 4 O RESET output for the device. The response of RESET to short press and long press is described in Section 7.3.2.2. INT 7 5 I Interrupt output. INT is open drain active low output which toggles from every short press and long press on push-button input as described in Section 7.3.2.1 KILL 8 6 Kill is feedback from the host. RESET can be de-asserted in the latched version by pulling KILL low. Connect this pin to VDD if not used. Please refer Section 7.3.1.3 for additional details. www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage VDD –0.3 6.5 V VPB (1) –0.3 VDD + 0.3 V VKILL (1) –0.3 VDD + 0.3 V Current IRESET -6 6 mA Temperature(2) Operating free-air temperature, TA -40 125 °C Storage temperature, Tstg -65 150 °C (1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD ratings (Industrial)

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (PB pin only) (1) ±10000 V Charged device model (CDM), per JEDEC specification JESD22-C101 ±750 V (1) AEC Q-100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

6.3 Recommended Operating Conditions

VDD Supply pin voltage 1 6 V VPB Push-button pin input voltage 0 VDD V VKILL KILL pin Voltage 0 VDD V V INT Interrupt pin voltage 0 VDD V VRESET Output pin voltage 0 VDD V IRESET Output pin current 0 5 mA TA Ambient temperature (free-air temperature) -40 125 ℃ CSPT SPT capacitor (1) 125 nF CLPT LPT capacitor 125 nF (1) SPT capacitor value must be less than LPT capacitor TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TPS3423 / TPS3424 UNITDRL (SOT-583) DRL (SOT-563)

8 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance °C/W RθJC(top) Junction-to-case (top) thermal resistance °C/W RθJB Junction-to-board thermal resistance °C/W ΨJT Junction-to-top characterization parameter °C/W ΨJB Junction-to-board characterization parameter °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

At 1 V <VDD <6 V, SPT = LPT = Open, KILL = VDD CRESET = 50 pF, INT = 10K pull up to VDD and over the operating free-air temperature range of - 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER TEST CONDITION MIN TYP MAX UNIT POWER SUPPLY VDD Supply Voltage 1 6 V IDD(Standby) Standby supply current(1) VDD = 3V TA = 25℃ 22 30 nA TA = –40℃ to 85℃ 90 VDD = 6V TA = –40℃ to 85℃ 45 100 VDD = 6V 45 350 Push-button PIN IDD(Active) Supply current when V PB = 0V ( two push- button is pressed)(2) VDD = 3V µA Supply current when V PB = 0V ( one push- button is pressed)(2) Supply current when VPB = VDD ( both-push buttons are pressed)(3) 1.1 VIH(PB / PB) PB Logic high input(2) VDD = 3V 0.8*VDD VIL(PB / PB) PB Logic low Input(2) 0.3*VDD RPB PB pin internal pull-up / pull-down resistance(2) (3) 1000 kΩ INT and RESET VOL(INT) Low level output voltage VDD = 1V, INT = 100µA 200 mV Low level output voltage VDD = 3V, INT = 1mA 300 ILKG(INT) Open drain output leakage current for INT VDD = V Pullup = 6V 100 nA www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

6.5 Electrical Characteristics (continued)

At 1 V <VDD <6 V, SPT = LPT = Open, KILL = VDD CRESET = 50 pF, INT = 10K pull up to VDD and over the operating free-air temperature range of - 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER TEST CONDITION MIN TYP MAX UNIT VOL(RESET) Low level output voltage (Open Drain) VDD = 1V, IRESET = 300µA 200 mV Low level output voltage (Push-Pull)(4) VDD = 1V, IRESET = 300µA 200 Low level output voltage (Open Drain) VDD = 3V, IRESET = 5mA 300 Low level output voltage (Push-Pull)(4) VDD = 3V, IRESET = 5mA 300 VOH(RESET) High level output voltage (Push-Pull)(4) VDD = 1V, IRESET = 200µA 0.7*VDD High level output voltage (Push-Pull)(4) VDD = 3V, IRESET = 5mA 0.7*VDD ILKG (RESET) Open drain output leakage current for (RESET) VDD = V Pullup = 6V 300 nA KILL , SPT , LPT IKILL Kill Input current 25 nA VKILL_L KILL logic low input 0.3*VDD VKILL_H KILL logic high input 0.7*VDD (1) PB pin is floating. (2) PB pin as active low. (3) PB pin as active high. (4) This spec holds true both for active high RESET and active low RESET.

6.6 Timing Requirements

At 1 V <VDD <6 V, SPT = LPT = Open, KILL = VDD, CRESET = 50 pF, INT = 10K pull up to VDD and over the operating free-air temperature range of - 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. Parameter Test Condition MIN TYP MAX UNIT tSP Accuracy Short press duration accuracy for fixed version(1) -10 10 % Short press duration accuracy for adjutable version(1) SPT = 330pF, LPT = 4.7nF -20 20 % tLP Accuracy Long press duration accuracy for fixed version -10 10 % Long press duration accuracy for adjutable version SPT = 330pF, LPT = 4.7nF -20 -20 % tSINT Accuracy Interrupt pulse width accuracy for PB long press -10 10 % tLINT Accuracy Interrupt pulse width accuracy for PB short press -10 10 % tKILL Accuracy PB/KILL debounce accuracy when RESET deaaserts in latched version -10 10 % tRESET Reset pulse duration (non latched) - Accuracy -10 10 % tGI(KILL) Glitch Immunity at KILL pin 250 ns tPD(KILL) KILL falling edge to RESET assert delay 500 ns (1) tSPD should always be less than tLPD. TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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6.7 Timing Diagrams

(Active high , Latched) ttSPt ttLPt ttSINTt Ignore ttSPt ttSINTt ttLINTt Ignore PB input is ignored if it is released and again pressed during - Interrupt pulse PB (Active Low) Figure 6-1. Timing Diagram: Latched RESET VDDMIN VDD INT RESET ttSPt ttSINTt -No Interrupt pulse for second press during INT pulse PB (Active Low) ttSPt Figure 6-2. Timing Diagram: Example of PB Input Ignore www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

(Active Low) VDDMIN VDD INT RESET (Active high, Non-latched: D configuration ) ttSPt ttLPt ttSINTt Ignore ttSPt ttSINTt ttLINTt Ignore ttRESETt PB input is ignored if it is released and again pressed during - Interrupt pulse - Non-latched RESET pulse Figure 6-3. Timing Diagram: Non-Latched RESET VDDMIN VDD INT RESET (Active high, Latched) ttSPt ttSINTt Ignore PB input is ignored if it is released and again pressed during - Interrupt pulse - KILL debounce PB (Active Low) KILL tKILL tGI ttSPt ttSINTt Ignore tPD (KILL) tPD (KILL) tKILL Ignore Ignore Figure 6-4. Timing Diagram: KILL TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TPS3423 & TPS3424 are nano power push-button family which offer wide range of timing option for input (PB, KILL) and output (RESET, INT) pins. This device family is available in two different pinout with 8 and 6 pin DRL package and various output and input configuration as per Device Comparison to support various applications.

7.2 Functional Block Diagrams

INT1* PB1 RESET/INT Logic 2 Push-button Timer Logic 2PB2 RESET2/ RESET2 INT2* VDD VDD 1000 k 1000 k * Available only in 8 pin DRL (SOT5X3) package Figure 7-1. TPS3423 Block Diagram Capacitance Detection Push-button Timer Logic RESET/INT Logic Oscillator VDD SPT* LPT* KILL GND RESET/ RESET INT PB 1000 k VDD * Available only in 8 pin DRL (SOT5X3) package Figure 7-2. TPS3424 Block Diagram www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

7.3 Feature Description

7.3.1 Inputs

This section discusses the inputs of the TPS3423 & TPS3424 devices.

7.3.1.1 Push-Button Input (PB)

Push-button input (PB) for TPS3423 and TPS3424 is available in active low and active high configuration as per Table 7-1 as shown in Figure 7-1 and Figure 7-2. Table 7-1. Push-Button Configuration PUSH-BUTTON CONFIGURATION INTERNAL RESISTOR ORIENTATION PB TRIGGER STATE Active low 1000kΩ , pulled up to VDD Pull the PB pin to GND level Active High 1000kΩ , pulled down to GND Pull the PB pin to VDD level PB pin should be connected to a switch with ON resistance less than 20% of the pull-up / pull-down resistance to provide the correct PB input trigger for the device. A precise timer gets started once PB pin is triggered. The device generates the output corresponding to short press, once PB pin is kept low (for active low PB) or kept high (for active high PB) for more than short press (t SP) duration. The device generates output corresponding to long press if the PB pin is held in the same state for long press (tLP) duration. The timer stops and gets reset when PB pin is released. If PB is released during interrupt pulse (Figure 7-3), non-latched RESET pulse or KILL debounce time then next PB input is ignored as described in Section 6.7. VDDMIN VDD INT ttSPt ttLPt ttSINTt Ignore ttSPt ttSINTt ttLINTt Ignore PB input is ignored if it’s width is less than tsp. PB input is ignored if it is released and again pressed during interrupt pulse. PB (Active Low) <tSP Figure 7-3. Push Button Functionality TPS3423 has two independent push-button pins PB1 and PB2. These pins are factory programmed for short press (tSP) and long press (t LP) duration. TPS3424 has single PB pin. PB pin in TPS3424 is available both in fixed timing and user programmable option (8-pin DRL package) through capacitor connection on SPT and LPT pins. SPT and LPT pins must be floating for fixed timing option of TPS3424. TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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7.3.1.2 Push-Button Timing Programmability

TPS3424x11xxx8DRLR has options to program short press duration (t SP) and long press duration (t LP) with capacitor on SPT pin and LPT pin respectively. Equation 1 shows the relation between the press duration and the capacitance. If the pin is left floating, the device defaults to fixed timer of 50msec. Connecting a capacitor which provides less than 50msec press duration as per, programs to 50msec press duration. Make sure t LP is greater than tSP for proper device operation. t SP or t LP s ec = 0.422 × C nF (1) where

Press duration is tSP for SPT capacitor and tLP for LPT capacitor.
C is the value capacitance connected on SPT or LPT pin.

7.3.1.3 KILL

KILL pin is used as a control input from the host in the latched RESET version. A short press on PB pin asserts the RESET in latched version. The host pulls KILL high if RESET assert for the host has performed all the expected tasks like enabling the whole power tree. The device ignores the KILL input for t SINT + t KILL time, allowing sufficient time for host to monitor the operation. The Host pulls KILL low if RESET assert doesn't perform all expected operations. Push-button de-asserts RESET if KILL is low after debounce period as shown in Figure 6-4. Host can pull KILL low at any time to de-assert RESET without any button press. KILL input is ignored for non-latched RESET configuration. Short kill to VDD is unused. www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

7.3.2 Outputs

This section discusses the outputs of the TPS3423/4 devices.

7.3.2.1 Interrupt (INT)

INT is open drain active low output. This pin generates low pulse for short press and long press as shown in Figure 6-1. Pulse duration for short press t INTS and long press t INTL is factory programmed. Please refer Section 4 section for the available option for the interrupt duration.

7.3.2.2 RESET / RESET

RESET output of the device supports multiple configurations as described in Table 7-2. This device is available in all combination as described in Section 4. Table 7-2. RESET CONFIGURATIONS PARAMETER VALUE Latching option Latched, Non-latched Logic Active High (AH), Active Low (AL) Output configuration Open Drain (OD), Push-Pull (PP) RESET is asserted for short press and de-asserted for long press on PB pin for latched version as shown in Figure 6-1. Pulling KILL pin low also de-asserts the RESET in latched version as described in Figure 6-4. Non-latched RESET helps in achieving complex logic function with push-button. Non-latched RESET version of device supports multiple pattern as described in Section 4. RESET pattern is always different for short press and long press. One of the non-latched RESET pattern is shown in Figure 6-3. TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

Push-button controllers play an important role in any human-machine interface (HMI) design. They decode user inputs from single or multiple button presses, control system power or reset, and perform other essential user interface functions. TPS3423 and TPS3424 devices are designed to extend the shelf life of battery powered applications.

8.2 Typical Applications

8.2.1 Power Button Control with TPS3424

TPS3424 is designed for power button applications which need to put the system in deep sleep mode with very small standby power. TPS3424 controls enable for load switch or DC-DC converter in latched mode of RST pin. An application diagram is shown in Figure 8-1. VDD PB Kill INT SPT RST LPT GND GND TPS3424 ON VIN MCU 10k Push-bu on VOUT GND TPS22991 10k Figure 8-1. TPS3424 Application Diagram

8.2.1.1 Design Requirements

Table 8-1 lists the design requirements for Figure 8-1. Table 8-1. Design Requirements and Results DESIGN REQUIREMENTS DESIGN RESULT Single input PB TON = 100ms tSP= 100ms TOFF = 1sec tSP= 1sec Supply = 3V VDD = 3V MCU IO pin current rating < 500uA INT & KILL pull up = 10kΩ

8.2.1.2 Detailed Design Procedure

Short press on the PB pin triggers the RESET, which enables the load switch TPS22991 and INT signal notifies to MCU. Load switch TPS22991 can be disabled either by a long press on the PB pin as shown Figure 8-2 or through KILL pin as shown in Figure 8-3 and Figure 8-4. www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

8.2.1.3 Application Curve

Figure 8-2. ON and OFF functionality of Push button VDD PB InputPB Input INT RESET Figure 8-3. Asynchronous RESET deassert from HOST through KILL TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

Figure 8-4. RESET deassertion by the HOST at the time of power ON

8.2.2 High Voltage Connection

R R1R2 ATL431/TL431 GND INT2 Figure 8-5. High voltage support with ATL431

8.3 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1V and 6V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1µF capacitor between the VDD pin and the GND pin.

8.4 Layout

8.4.1 Layout Guidelines

Follow these guidelines for laying out the printed circuit board (PCB) that is used for the TPS3423 and TPS3424.

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1µF ceramic capacitor as near as possible to the VDD pin.
Place the external capacitor on close to LPT and SPT pin for TPS3424. www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

Parasitic on LPT and SPT must be less than 50pF when these pins are floating for TPS3424.

8.4.2 Layout Example

Figure 8-6. TPS3423: Layout Example (8-Pin DRL Package) Figure 8-7. TPS3423: Layout Example (8-Pin DRL Package) TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 www.ti.com

Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS3423, TPS3424 SNVSCN9 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS3423 TPS3424 ADVANCE INFORMATION

www.ti.com 6-Nov-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS3423DAHGFADRLR ACTIVE SOT-5X3 DRL 8 4000 TBD Call TI Call TI -40 to 125 Samples PPS3424A11C13ADRLR ACTIVE SOT-5X3 DRL 8 4000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 6-Nov-2024 Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 1.7 1.5 6X 0.5 2X 1.5

0.6 MAX

0.18 0.08 8X 0.4 0.2 0.05 0.00 8X 0.27 0.17 2X 4 -10 2X 0 -10 B 1.3 1.1 A 2.2 2.0 NOTE 3 SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE 4224486/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4.Reference JEDEC Registration MO-293, Variation UDAD 1 8 ID AREA PIN 1 SEATING PLANE 0.05 C SCALE 8.000

0.1 C A B

0.05 SYMM SYMM

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (0.67) 8X (0.3) (1.48) 6X (0.5) (R0.05) TYP 4224486/F 08/2024 SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:30X SYMM 4 5 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 6X (0.5) 8X (0.67) 8X (0.3) (R0.05) TYP SOT-5X3 - 0.6 mm max heightDRL0008A PLASTIC SMALL OUTLINE 4224486/F 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated

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