PPS23730A0RMTT

TPS23730 TI1 | Alldatasheet

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ADVANCE□INFORMATION RCLSA From Ethernet Transformers VDD VSS CLSA From Spare Pairs or Transformers DEN GATE TPS23730 VCC 0.1 F 58V RDEN CDTR CBULK CS RCSDTHR RTN RFRS FRS APD VB CVB 48V Adapter RAPD1 RAPD2 DA CSST SSTRDTR I_in VCC TPH RTPH TPL RTPL PPD CLSB RCLSB BT CVCC DVC DVC2 GAT2 DT COMP RDT VB VB Voltage feedback circuitry TLV431 GND RUV1 RUV2 LINEUV I_STP RI_STP EMPS Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS23730 SLVSER6 –MAY 2020 TPS23730IEEE802.3btType3PoEPDwithHighEfficiencyDC-DCController

1 Features

1• Complete IEEE 802.3bt Type 3 (Class 1-6) PoE PD Solution – EA Gen 2 Logo-Ready (PoE 2 PD Controller) – Robust 100 V, 0.3 Ω (typ) Hotswap MOSFET – Supports Power Levels for up to 60-W Operation – Allocated Power Indicator Outputs - parallel or serial encoding selectable

• Integrated PWM Controller for Flyback or Active Clamp Forward Configuration – Flyback Control with Primary-Side Regulation – Supports CCM Operation – ±1.5% (typ, 5-V Output) Load Regulation (0-100% load range) — with Sync FET – Also supports secondary-side regulation – Soft-Start Control with Advanced Startup and Hiccup Mode Overload Protection – Soft-Stop Shutdown – Adjustable Frequency with Synchronization – Programmable Frequency Dithering for EMI
• Automatic Maintain Power Signature (MPS) – Auto-adjust to PSE Type and Load Current with Auto-stretch
• Primary Adapter Priority Input
• –40°C to 125°C Junction Temperature Range

2 Applications

• Video and VoIP Telephones
• Access Points
• Pass-through System
• Security Cameras
• Redundant Power Feeds or Power Sharing

3 Description

The TPS23730 device combines a Power over Ethernet (PoE) powered device (PD) interface, and a current-mode DC-DC controller optimized for flyback and active clamp forward (ACF) switching regulator designs. In the case of flyback configuration, the use of primary-side regulation (PSR) is supported. The PoE interface supports the IEEE 802.3bt standard for applications needing up to 51 W or less at PD input. Programmable spread spectrum frequency dithering (SSFD) is provided to minimize the size and cost of EMI filter. Advanced Startup with adjustable soft-start helps to use minimal bias capacitor while simplifying converter startup and hiccup design, also ensuring that IEEE 802.3bt startup requirements are met. The soft-stop feature minimizes stress on switching power FETs, allowing FET BOM cost reduction. The PSR feature of the DC-DC controller uses feedback from an auxiliary winding for control of the output voltage, eliminating the need for external shunt regulator and optocoupler. It is optimized for continuous conduction mode (CCM), and can work with secondary side synchronous rectification, resulting in optimum efficiency, regulation accuracy and step load response over multiple outputs. The DC-DC controller features slope compensation and blanking. Typical switching frequency is 250 kHz. The automatic MPS enables applications with low power modes or multiple power feeds. It automatically adjusts its pulsed current amplitude and duration according to PSE Type and system conditions, to maintain power while minimizing consumption. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS23730 VSON (45) 7.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table of Contents

7.5 Electrical Characteristics: DC-DC Controller

13 Mechanical, Packaging, and Orderable

4 Revision History

May 2020 * Advance Information release

ADVANCE□INFORMATION NC VSS VDD SCDIS RTN VCC DEN VSS RTN VBG 21CLSA DTHR FRS GATE GND CP FB SST COMP PSRS CS GAT2 NC APD LINEUV AGND PPD TPL I_STP TPH BT NC EMPS REF TEST NC NC CLSB NC RTN VBNC DT EA_DIS 10NC PAD_G PAD_S TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

5 Device Comparison Table

KEY FEATURES TPS23730 TPS23731 TPS23734 Class Range 1-6 1-4 1-4 ACF Support Yes No Yes SSFD Yes Yes Yes Soft-stop Yes Yes Yes Advanced Startup Yes Yes Yes PSR (Flyback) Yes Yes Yes Auto MPS Yes Yes Yes PPD Yes No No APD Yes Yes Yes PoE allocated power and AUX power indicator(s) TPH/TPL (parallel) or TPL (serial) T2P, APDO T2P, APDO

6 Pin Configuration and Functions

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NO. NAME 1 CS I/O DC-DC controller current sense input. Connect directly to the external power current sense resistor. 2 AGND - AGND is the DC-DC converter analog return. Tie to RTN and GND on the circuit board.

3 DTHR O

Used for spread spectrum frequency dithering. Connect a capacitor (determines the modulating frequency) from DTHR to RTN and a resistor (determines the amount of dithering) from DTHR to FRS. If dithering is not used, short DTHR to VB pin. 4 FRS I This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to RTN to set the frequency. 5 APD I Primary auxiliary power detect input. Raise 1.5 V above RTN to disable pass MOSFET, also turning class off. If not used, connect APD to RTN. 7, 8, 9 RTN - RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller. 11 EMPS I Automatic MPS enable input, referenced to RTN, internally pulled-up to 5V internal rail. Tie to RTN to disable automatic MPS.

12 BT O

Indicates that a PSE applying an IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified. Open-drain, active-low output referenced to RTN. BT state remains unchanged if an auxiliary power adapter is detected via APD or PPD input. BT is also disabled if SCDIS is low. 13 TPH O TPH/TPL binary code indicates the PSE allocated power output. Open-drain, active-low outputs referenced to RTN. The default operation is with parallel binary code. Also, whenever an auxiliary power adapter is detected via the APD input or PPD input, both TPH and TPL pull low. Serial code over TPL can also be enabled by tying SCDIS pin to VSS. In this case, TPH becomes high impedance.

14 TPL O

17 REF O Internal 1.25 V voltage reference. Connect a 49.9kΩ_1% resistor from REF to VSS. 18 SCDIS I TPL serial code disable, referenced to VSS. Leave open to select parallel TPH/TPL configuration. Tie to VSS to select serial code. 19 PPD I Raising VPPD-VSS above 2.5 V enables the hotswap MOSFET, activates TPH and TPL and turn class off. Tie PPD to VSS or float when not used. 20 CLSB O Connect a resistor from CLSB to VSS to program the second classification current. 21 CLSA O Connect a resistor from CLSA to VSS to program the first classification current. 23 VDD — Positive input power rail for PoE interface circuit and source of DC-DC converter start-up current. Bypass with a 0.1 µF to VSS and protect with a TVS. 24 DEN I/O Connect a 25.5-kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin to VSS during powered operation causes the internal hotswap MOSFET to turn off. 27, 28 VSS - Negative power rail derived from the PoE source. 30 TEST O Used internally for test purposes only. Leave open. 31 DT I Connect a resistor from DT to AGND to set the GATE to GAT2 dead time. Tie DT to VB to disable GAT2 operation.

32 I_STP I

This pin sets the SST discharge current during a soft-stop event independently from the setting used during a regular soft-start event. Connect a resistor from this pin to AGND to set the DC/DC soft-stop rate.

33 SST I/O

A capacitor from SST to RTN pin sets the soft-start (ISSC charge current) and the hiccup timer (ISSD discharge current) for the DC-DC converter. Connect a capacitor from this pin to RTN to set the DC/DC startup rate.

34 FB I

Converter error amplifier inverting (feedback) input. If flyback configuration with primary-side regulation, it is typically driven by a voltage divider and capacitor from the auxiliary winding, working with CP pin, FB also being connected to the COMP compensation network. If optocoupler feedback is enabled, tie FB to VB.

35 COMP I/O

Compensation output of the DC-DC convertor error amplifier or control loop input to the PWM. If the internal error amplifier is used, connect the compensation networks from this pin to the FB pin to compensate the converter. If optocoupler feedback is enabled, the optocoupler and its network pulled up to VB directly drives the COMP pin.

36 EA_DIS I

Error Amplifier disable input, referenced to AGND, internally pulled-up to 5V internal rail. Leave EA_DIS open to disable the Error amplifier, to enable optocoupler feedback for example. Connect to AGND otherwise. 37 VB O 5-V bias rail for DC/DC control circuits and the feedback optocoupler (when in use). Connect a 0.1uF capacitor from this pin to AGND to provide bypassing.

ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME

38 LINEUV I LINEUV is used to monitor the bulk capacitor voltage to trigger a soft-stop event when an

undervoltage condition is detected if APD is low. If not used, connect LINEUV to VB pin.

39 PSRS I

PSR Sync enable input, referenced to AGND, internally pulled-up to 5V internal rail. PSRS works with CP pin to support flyback architecture using primary-side regulation. Leave PSRS open if the flyback output stage is configured with synchronous rectification and uses PSR. If diode rectification is used, or for applications not using PSR, connect PSRS to AGND. 40 VBG O 5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF ceramic capacitor to GND pin. 41 GAT2 O Gate drive output for a second DC-DC converter switching MOSFET. 42 VCC I/O DC/DC converter bias voltage. The internal startup current source and converter bias winding output power this pin. Connect a 1µF minimum ceramic capacitor to RTN.

43 GATE O Gate drive output for the main DC-DC converter switching MOSFET

44 CP O CP provides the clamp for the primary-side regulation loop. Connect this pin to the lower end of the bias winding of the flyback transformer. 45 GND - .Power ground used by the flyback power FET gate driver and CP. Connect to RTN. 6, 10, 15, 16, 22, 25, 26, 29 NC - No connect pin. Leave open. 47 PAD_S - The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation. 46 PAD_G - The exposed thermal pad must be connected to RTN. A large fill area is required to assist in heat dissipation.

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) IRTN = 0 for VRTN > 80 V. (3) Do not apply voltage to these pins.

7 Specifications

7.1 Absolute Maximum Ratings

Voltage are with respect to VSS (unless otherwise noted)(1) MIN MAX UNIT Input voltage VDD, DEN, GND, AGND, RTN(2) –0.3 100 VVDD to RTN –0.3 100 APD, FB, CS, EA_DIS, LINEUV, PSRS, EMPS, all to RTN –0.3 6.5 Input voltage PPD, SCDIS(3) -0.3 6.5 V Voltage FRS(3), COMP, VB(3), VBG(3), I_STP(3), DTHR(3), SST(3), DT(3),BT, all to RTN -0.3 6.5 V VCC to RTN -0.3 19 GATE(3), GAT2(3), all to RTN -0.3 VCC+0.3 CP to GND -0.3 60 GND, AGND, all to RTN -0.3 0.3 REF(3), CLSA(3), CLSB(3) -0.3 6.5 TPH, TPL, all to RTN -0.3 19 Sourcing current VB, VBG, VCC Internally limited mACOMP Internally limited REF Internally limited Sourcing current CLSA, CLSB 65 mA Sinking current RTN Internally limited mADEN 1 COMP Internally limited Sinking current TPH, TPL, BT 10 mA Peak sourcing current CP 2 A Peak sinking current CP 0.7 A TJ(max) Maximum junction temperature Internally Limited °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the TPS23730, TPS23730EVM-093 evaluation module (documentation available on the web). These were the test levels, not the failure threshold.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 IEC 61000-4-2 contact discharge(3) ±8000 IEC 61000-4-2 air-gap discharge(3) ±15000

7.3 Recommended Operating Conditions

Voltage with respect to VSS (unless otherwise noted) MIN NOM MAX UNIT Input voltage range VDD, RTN, GND, AGND 0 60 V VCC to RTN 0 16 APD, EA_DIS, LINEUV, PSRS, FB, all to RTN 0 VB CS to RTN 0 2 CP to GND 0 45 Input voltage range PPD 0 5 V

ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Recommended Operating Conditions (continued) Voltage with respect to VSS (unless otherwise noted) MIN NOM MAX UNIT (1) Voltage should not be externally applied to this pin. Voltage range COMP, BT, all to RTN VB V Voltage range TPH, TPL, all to RTN 0 VCC V Sinking current RTN 1.2 A Sinking current TPH, TPL, BT 3 mA Sourcing current VCC 20 mA VB 5 Capacitance VB, VBG(1) 0.08 0.1 1 μF VCC 0.7 1 100 Resistance I_STOP 16.5 499 KΩ Resistance CLSA, CLSB(1) 30 Ω REF(1) 48.9 49.9 50.9 kΩ Synchronization pulse width input (when used) 35 ns TJ Operating junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Thermal metrics are not JEDEC standard values and are based on the TPS23731EVM-095 evaluation board.

7.4 Thermal Information(1)

THERMAL METRIC UNITR__ (VSON)

48 PINS

RθJA (2) Junction-to-ambient thermal resistance 38.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.6 RθJB (2) Junction-to-board thermal resistance 19.3 ψJT (2) Junction-to-top characterization parameter 6.8 ψJB (2) Junction-to-board characterization parameter 19.3 RθJC(bot_POE) Junction-to-case (bottom PAD2 pad) thermal resistance 3.9 RθJC(bot_DCDC) Junction-to-case (bottom PAD1 pad) thermal resistance 9.1 (1) The hysteresis tolerance tracks the rising threshold for a given device.

7.5 Electrical Characteristics: DC-DC Controller Section

Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C. [VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC-DC SUPPLY (VCC) VCUVLO_R Undervoltage lockout VVCC rising 8 8.25 8.5 V VCUVLO_F VVCC falling, VFB = VRTN 5.85 6.1 6.35 V VCUVLO_H Hysteresis(1) 2 2.15 2.3 V IRUN Operating current VVCC = 10 V, VFB = VRTN , CP with 2-kΩ pull up to 30 V 1.5 2 2.4 mA IVC_ST Startup source current VAPD = 2.5V VVDD ≥ 28V, VVCC = 11.7 V 21.5 30 34 mAVVDD = 10.2V, VVCC = 8.6 V 1 6 17.5 VVDD = 10.2V, VVCC = 6.8 V 8 16 32 tST Startup time, CVCC = 1 μF VVDD = 10.2 V, VVCC(0) = 0 V, measure time until VCUVLO_R 0.25 0.7 1.15 ms VVDD = 35 V, VVCC(0) = 0 V, measure time until VCUVLO_R 0.24 0.35 0.48 ms VVC_ST VCC startup voltage Measure VVCC during startup, IVCC = 0 mA 11 12.5 14 V Measure VVCC during startup, IVCC = 21.5 mA 11 12.5 14

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics: DC-DC Controller Section (continued) Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C. [VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVC_SSTP VCC soft-stop voltage VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC = 0 mA 11 12.5 14 V VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC = 21.5 mA 11 12.5 14 VB Voltage VFB = VRTN, 8.5 V ≤ VVCC ≤ 16 V, 0 ≤ IVB ≤ 5 mA 4.75 5.0 5.25 V DC-DC TIMING (FRS) fSW Switching frequency VFB = VRTN, Measure at GATE 223 248 273 kHz DMAX Duty cycle VFB = VRTN, RDT = 24.9 kΩ, Measure at GATE 74.5% 78.5% 82.5% VSYNC Synchronization Input threshold 2 2.2 2.4 V FREQUENCY DITHERING RAMP GENERATOR (DTHR) IDTRCH Charging (sourcing) current 0.5 V < VDTHR < 1.5 V 3 x IFRS µA 47.2 49.6 52.1 µA IDTRDC Discharging (sinking) current 0.5 V < VDTHR < 1.5 V 3 x IFRS µA 47.2 49.6 52.1 µA VDTUT Dithering upper threshnold VDTHR rising until IDTHR > 0 1.41 1.513 1.60 V VDTLT Dithering lower threshold VDTHR falling until IDTHR < 0 0.43 0.487 0.54 V VDTPP Dithering pk-pk amplitude 1.005 1.026 1.046 V ERROR AMPLIFIER (FB, COMP) VREFC Feedback regulation voltage 1.723 1.75 1.777 V IFB_LK FB leakage current (source or sink) VFB = 1.75 V 0.5 μA GBW Small signal unity gain bandwidth 0.9 1.2 MHz AOL Open loop voltage gain 70 80 db VZDC 0% duty-cycle threshold VCOMP falling until GATE switching stops 1.35 1.5 1.65 V ICOMPH COMP source current VFB = VRTN , VCOMP = 3 V 1 mA ICOMPL COMP sink current VFB = VVB , VCOMP = 1.25 V 2.1 6 mA VCOMPH COMP high voltage VFB = VRTN , 15 kΩ from COMP to RTN 4 VB V VCOMPL COMP low voltage VFB = VVB , 15 kΩ from COMP to VB 1.1 V COMP input resistance, error amplifier disabled EA_DIS open 70 100 130 kΩ COMP to CS gain ΔVCS / ΔVCOMP , 0 V < VCS < 0.22 V 0.19 0.2 0.21 V/V SOFT-START, SOFT-STOP (SST, I_STP) ISSC Charge current SST charging, 6.35 V ≤ VVCC ≤ 16 V 7.5 10 12.5 µA ISSD Discharge current SST discharging, 6.35 V ≤ VVCC ≤ 16 V 3 4 5 µA VSFST Soft-start lower threshold 0.15 0.2 0.25 V VSTUOF Startup turn off threshold VSST rising until VCC startup turns off 1.99 2.1 2.21 V VSSOFS Soft-start offset voltage, closed- loop mode VFB = VRTN, VSST rising until start of switching 0.2 0.25 0.3 V Soft-start offset voltage, peak current mode VCOMP = VVB, VSST rising until start of switching, EA_DIS open 0.55 0.6 0.65 V VSSCL Soft-start clamp 2.3 2.6 V ISSD_SP SST discharge current in soft-stop mode RI_STP = 499 kΩ, VLINEUV < VLIUVF 1.5 2 2.5 µA RI_STP = 16.5 kΩ, ,VLINEUV < VLIUVF 52.5 60.6 67.5 VSSTPEND End of soft-stop threshold VFB = VRTN, VLINEUV < VLIUVF 0.15 0.2 0.25 V CURRENT SENSE (CS) VCSMAX Maximum threshold voltage VFB = VRTN, VCS rising 0.227 0.25 0.273 V tOFFD_IL Current limit turn off delay VCS = 0.3 V 25 41 60 ns

ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics: DC-DC Controller Section (continued) Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C. [VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. tOFFD_PW PWM comparator turn off delay VCS = 0.15 V, EA_DIS open, VCOMP = 2 V 25 41 60 ns Blanking delay In addtition to tOFFD_IL and tOFFD_PW 75 95 115 ns VSLOPE Internal slope compensation voltage VFB = VRTN, Peak voltage at maximum duty cycle, referred to CS 51 66 79 mV ISL_EX Peak slope compensation current VFB = VRTN, ICS at maximum duty cycle (ac component) 14 20 26 μA Bias current DC component of CS current -3 -2 -1 μA LINE UNDERVOLTAGE, SOFT-STOP (LINEUV) VLIUVF LINEUV falling threshold voltage VLINEUV falling 2.86 2.918 2.976 V VLIUVH Hysteresis(1) 57 82 107 mV Leakage current VLINEUV = 3 V 1 µA DEAD TIME (DT) tDT1 Dead time RDT = 24.9 kΩ, GAT2 ↑ to GATE ↑ VFB = VRTN , VPSRS = 0 V, EA_DIS open, VCOMP = VVB , CGATE = 1 nF, CGAT2 = 0.5 nF, VVCC = 10 V 40 50 62.5 nstDT2 RDT = 24.9 kΩ, GATE ↓ to GAT2 ↓ 40 50 62.5 tDT1 RDT = 75 kΩ, GAT2 ↑ to GATE ↑ 120 150 188 tDT2 RDT = 75 kΩ, GATE ↓ to GAT2 ↓ 120 150 188 GATE Peak source current VFB = VRTN , VVCC = 10 V, VGATE = 0 V, pulsed measurement 0.3 0.5 0.8 A Peak sink current VFB = VRTN , VVCC = 10 V, VGATE = 10 V, pulsed measurement 0.6 0.85 1.2 A Rise time(2) tprr10-90 , CGATE = 1 nF , VVCC = 10 V 30 ns Fall time(2) tpff90-10 , CGATE = 1 nF , VVCC = 10 V 15 ns GAT2 Peak source current VFB = VRTN , VVCC = 10 V, RDT = 24.9 kΩ, VGAT2 = 0 V, pulsed measurement 0.3 0.5 0.8 A Peak sink current VFB = VRTN , VVCC = 10 V, RDT = 24.9 kΩ, VGAT2 = 10 V, pulsed measurement 0.3 0.43 0.6 A Rise time(2) tprr10-90 , CGAT2 = 0.5 nF , VVCC = 10 V 15 ns Fall time(2) tpff90-10 , CGAT2 = 0.5 nF , VVCC = 10 V 15 ns CLAMPING FET (CP) RDS(ON)CL CP FET on resistance ICP = 100 mA 1.5 3.3 Ω CLAMPING DIODE (CP) VFCP CP Diode forward voltage VPSRS = 0 V, ICP = 15 mA 0.45 0.6 0.85 V CP Leakage current VPSRS = 0 V, VCP = 45 V 20 µA AUXILIARY POWER DETECTION (APD) VAPDEN APD threshold voltage VAPD rising 1.42 1.5 1.58 V VAPDH Hysteresis(1) 0.075 0.095 0.115 V Leakage current VAPD = 5 V 1 µA PPD VPPDEN PPD threshold voltage VVDD > 16 V, VPPD - VVSS rising, PD input UVLO disable 2.34 2.5 2.66 V VPPDH Hysteresis(1) 0.47 0.5 0.53 IPPD PPD sink current VPPD - VVSS = 3 V 2.5 5 7.5 µA THERMAL SHUTDOWN Turnoff temperature 145 155 165 °C Hysteresis(2) 15 °C

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) The hysteresis tolerance tracks the rising threshold for a given device.

7.6 Electrical Characteristics PoE

Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C. VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD DETECTION (DEN) Detection bias current DEN open, VVDD = 10 V, Not in mark, Measure IVDD + IRTN 3.5 6.9 13.9 µA Ilkg DEN leakage current VDEN = VVDD = 60 V, Float RTN, Measure IDEN 0.1 5 µA Detection current Measure IVDD + IDEN + IRTN, VVDD = 1.4 V 54.2 56.5 58.6 μA Measure IVDD + IDEN + IRTN, VVDD = 10 V, Not in mark 391 398 404.8 μA VPD_DIS Hotswap disable threshold DEN falling 3 4 5 V PD CLASSIFICATION (CLSA, CLSB) ICLS Classification A, B signature current RCLSAor RCLSB = 806 Ω

13 V ≤ VDD ≤ 21 V,

2.1 2.5 2.9 mA RCLSAor RCLSB = 130 Ω 9.9 10.6 11.3 mA RCLSAor RCLSB = 69.8 Ω 17.6 18.6 19.4 mA RCLSAor RCLSB = 46.4 Ω 26.5 27.9 29.3 mA RCLSAor RCLSB = 32 Ω 38 39.9 42 mA VCL_ON Classification regulator lower threshold rising VVDD rising, ICLS ↑ 11.4 12.2 13 V VCL_H Classification regulator lower threshold Hysteresis(1) 0.8 1.2 1.6 V VCU_OFF Classification regulator upper threshold VVDD rising, ICLS ↓ 21 22 23 V VCU_H Hysteresis(1) 0.5 0.77 1 V VMSR Mark state reset threshold VVDD falling 3 3.9 5 V Mark state resistance 2-point measurement at 5 V and 10.1 V 6 10 12 kΩ Ilkg Leakage current VVDD = 60 V, VCLS = 0 V, VDEN = VVSS, Measure ICLS 1 μA tLCF_PD Long first class event timing Class 1st event time duration for new MPS 76 81.5 86 ms RTN (PASS DEVICE) ON-resistance 0.3 0.55 Ω ILIM Current limit VRTN = 1.5 V, pulsed measurement 1.5 1.85 2.2 A IIRSH inrush current limit VRTN = 2 V, VVDD: 20 V → 48 V, measure IRTN , pulsed measurement 100 140 180 mA Inrush current limit with nonstandard UVLO VPPD - VVSS > VPPDEN , VRTN = 2 V, VVDD: 0 V →

20 V, measure IRTN , pulsed measurement 100 140 180 mA

Percentage of inrush current. 80% 90% 99% tINR_DEL Inrush delay 80 84 88 ms Foldback voltage threshold VRTN rising 13.5 14.8 16.1 V

ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics PoE (continued) Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C. VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Foldback deglitch time VRTN rising to when current limit changes to inrush current limit. This applies in normal operating condition or during auto MPS mode. 1.5 1.8 2.1 ms Leakage current VVDD = VRTN = 100 V, VDEN = VVSS 70 μA PSE TYPE INDICATION (TPL, TPH, BT) VTPL Output low voltage ITPL = 1 mA, after 2- or 3-event classification, startup has completed, VRTN = 0 V 0.27 0.5 V VTPH Output low voltage ITPH = 1 mA, after 4-event classification, startup has completed, VRTN = 0 V 0.27 0.5 V VBT Output low voltage IBT = 2 mA, after IEEE802.3bt classification, startup has completed, VRTN = 0 V 0.27 0.5 V fTPL TPL frequency VSCDIS = 0 V, VAPD-RTN = 5 V, after startup has completed. 550 625 700 Hz TPL duty cycle in PoE operation VSCDIS = 0 V, after 4-event classification, after startup has completed 24% 25% 26% TPL duty cycle in nonstandard PoE operation VSCDIS = 0 V, after startup has completed 49% 50% 51% TPL duty cycle in auxiliary supply operation VSCDIS = 0 V, VAPD-RTN = 5 V, after startup has completed. 74% 75% 76% Leakage current VTPL-RTN or VTPH-RTN = 10 V or VBT-RTN = 5 V, VRTN = 0 V 1 µA SCDIS pullup current VVDD ≥ VUVLO_R or VAPD-RTN = 5 V 14 20 25 µA PD INPUT SUPPLY (VDD) VUVLO_R Undervoltage lockout threshold VVDD rising 35.8 37.6 39.5 V VUVLO_F Undervoltage lockout threshold VVDD falling 30.5 32 33.6 V VUVLO_H Undervoltage lockout threshold Hysteresis (1) 5.7 6.0 6.3 V IVDD_ON Operating current 40 V ≤ VVDD ≤ 60 V, Startup completed, VVCC =

10 V, Measure IVDD

650 900 µA IVDD_OFF Off-state current RTN, GND and VCC open, VVDD = 30 V, Measure IVDD 700 µA MPS IMPSL MPS total VSS current for Type 1-2 PSE EMPS open, inrush delay has completed, 0 mA ≤ IRTN ≤ 10 mA, measure IVSS 10 12.5 15 mA IMPSH MPS total VSS current for Type 3-4 PSE EMPS open, inrush delay has completed, 0 mA ≤ IRTN ≤ 16 mA, measure IVSS 16.5 19 21.5 mA MPS pulsed mode duty cycle for Type 1-2 PSE MPS pulsed current duty-cycle EMPS open 26.2% 26.6% 26.9% tMPSL MPS pulsed current ON time EMPS open 76 81.5 87 ms MPS pulsed current OFF time EMPS open 225 240 ms

Positive currents are into pins unless otherwise noted. Typical values are at 25°C. VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted. (2) These parameters are provided for reference only. Figure 2. GATE and GAT2 Timing and Phasing

7.7 Typical Characteristics

To be furnished at Production-data release.

ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TPS23730 device is a 45-pin integrated circuit that contains all of the features needed to implement a single interface IEEE 802.3bt Type 3 Class 1-6 and IEEE802.3at powered device (PD), combined with a current-mode DC-DC controller optimized for flyback and active clamp forward switching regulator design. The DC-DC controller of the TPS23730 features two complementary gate drivers with programmable dead time. This simplifies the design of active-clamp forward converters or optimized gate drive for highly-efficient flyback topologies. The second gate driver may be disabled if desired for self-driven synchronous flyback or for single MOSFET topologies. Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during startup. DC-DC converter features include startup function and current mode control operation. The TPS23730 device integrates a low 0.3-Ω internal switch to minimize heat dissipation and maximize power utilization. A number of input voltage Oring options or input voltage ranges are also supported by use of APD and PPD inputs. The TPS23730 device contains several protection features such as thermal shutdown, current limit foldback, and a robust 100-V internal return switch.

ADVANCE□INFORMATION EA_DIS vb VDD VCC Regulator VB Reference QD CLK CLRB+ t Blanking Control RTN CS E/A t Vrefc (1.75V) FB VCSMAX (0.25 V) t 0.3 V GATE 80k 20k 3.3k Converter off from PD COMP SST A disch Current Ramp Timing DT uvlo A A (pk) PSRS RTN

0.25 Vchrg

t Vdd GAT2 LINEUV 3V & 2.9V vb Regulator VBG EAD EAD I_STP S_stop/start ctl RTN Soft Stop Discharge t 12.2V & 11V 22V & 21.2V 37.6V & 32V S R Q Inrush limit threshold Current limit threshold VSS RTN APD VSS DEN 800 s 1.25V REG. Detection Comp. 1.5V &1.4V Hotswap MOSFET Class Comp. APD Comp. 14.8V & 1V UVLO Comp. OTSD IRTN sense,1 if < 90% of inrush and current limit Signals referenced to VSS unless otherwise noted Class Comp. Inrush latch RTN 1.8ms IRTN sense High if over temperature RTN Converter OFF Inrush timing CLSA State Eng. Mark Comp Out VSS TPH, TPL /BT RTN Class Comp Out CLSBMark R Mark Comp.3.9V Vdd sect PPD 2.5V &2V PPD Comp. State eng control apdout, PPD 1.25V Bias Oscillator REF apdout FoldB SCDIS vb 2V & 1.7V Automatic MPS Control Vdd mpcl apdout EMPS Av PWM COMP ILIMIT COMP mpcl TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

precedence over any numerical values used in the following sections.

8.3.1 CLSA, CLSB Classification

disables the classification signatures. on the first two cycles and Class 0 or 1 signature is presented on the third cycle. Table 1. Class Resistor Selection

8.3.2 DEN Detection and Enable

5%. TI recommends a resistor of 25.5 kΩ ± 1% for RDEN. simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.

8.3.3 APD Auxiliary Power Detect

• Internal pass MOSFET is turned off
• Classification current is disabled
• The LINEUV input is disabled
• Maintain Power Signature (MPS) pulsed mode is disabled

(1) If APD or PPD is high, both TPH and TPL outputs become low.

• TPH and TPL outputs are turned on (low state) if SCDIS is open
• TPL duty-cycle becomes 75% if SCDIS level is low This also gives adapter source priority over the PoE. A resistor divider (RAPD1–RAPD2 in Figure 19) provides system-level ESD protection for the APD pin, discharges leakage from the blocking diode (DA in Figure 19) and provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at excessively low voltages. If not used, connect APD to RTN.

8.3.4 PPD Power Detect

The PPD pin has a 5-µA internal pulldown current.

8.3.5 Internal Pass MOSFET

plane) for the DC-DC controller and converter primary to maintain signal integrity. capacitance is fully charged and the inrush period has been completed.

8.3.6 TPH, TPL and BT PSE Type Indicators

IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified. allocated power. In this case, TPH becomes high impedance. Table 2. TPH, TPL and Allocated Power Truth Table, with APD and PPD Low, SCDIS Open

Table 2. TPH, TPL and Allocated Power Truth Table, with APD and PPD Low, SCDIS Open (continued) (2) If PoE++ PSE, the BT output is also high. (1) If APD or PPD is high, TPL output becomes low with 75% duty-cycle. Table 3. TPL Duty-Cycle and Allocated Power Truth Table, with APD and PPD Low, SCDIS Low

• DC-DC controller is back to soft-start mode
• DC-DC controller transitions to soft-stop mode
• DC-DC controller shuts off due to reasons including VVCC falling below VCUVLO_F, or the PoE hotswap is in inrush limit while APD is low
• The device enters thermal shutdown Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the internal logic state of these signals is remembered such that these outputs will be activated accordingly after the soft- start has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold. The TPH, TPL and BT pins can be left unconnected if not used.

8.3.7 DC-DC Controller Features

source with control are provided. optocoupler feedback (ACF and flyback). optocoupler output directly drives the COMP pin which serves as a current-demand control to the PWM. current in the switching MOSFET.

period, while operational power must come from a converter (bias winding) output. power loss of external resistors. slope compensation. This makes it easier to design the current limit to a fixed value. the soft-start generator, and forces the VCC control into an undervoltage state.

8.3.7.1 VCC, VB, VBG and Advanced PWM Startup

auxiliary winding on the flyback transformer, to sustain normal operation after startup. has ramped up its output voltage and VSST has exceed approximately 2.1 V (VSTUOF), as shown in Figure 3. typically 1 μF in most applications. startup current source is turned back on, initiating a new PWM startup cycle. Figure 3. Advanced Startup Note that the startup current source is also turned on while in soft-stop mode.

8.3.7.2 CS, Current Slope Compensation and blanking

immediately follows, the CS pin is pulled to AGND through an internal pulldown resistor. is on. The IPK specification does not include the approximately 2-μA fixed current that flows out of the CS pin. designed that run at duty cycles well below this for a narrower, 36-V to 57-V range. unitless (for example, DMAX = 0.78). Figure 4. Additional Slope Compensation traces such as the gate drive signal and the CP signal.

8.3.7.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback

comparator which determines the switching MOSFET peak current. approximately (VZDC + 5 × (VCSMAX + VSLOPE)). The AC gain from COMP to the PWM comparator is typically 0.2. resulting in significantly lower noise sensitivity. current range can be achieved. configurations are possible.

8.3.7.4 FRS Frequency Setting and Synchronization

terminates. A short pulse is preferred to avoid reducing the potential ON-time. Figure 5. Synchronization

ADVANCE□INFORMATION CSS (nF) = ISSC :JA; x tSS (ms) (2 F 0.25) RDTR (3) =0.513 × RFRS (3) %DTHR CDTR =

3 RFRS (3)W

2.052 × fm (Hz) TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

8.3.7.5 DTHR and Frequency Dithering for Spread Spectrum Applications

The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions. Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 and IEEE 802.3bt sections 145.3 and 145.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data transmission. A technique referred to as frequency dithering can also be used to provide additional EMI measurement reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider bandwidth, thus lowering peak measurements. Fully programmable frequency dithering is a built-in feature of the TPS23730. The oscillator frequency can be dithered by connecting a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor, CDTR (Figure 19), is selected to define the modulation frequency fm. This capacitor is being continuously charged and discharged between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink equivalent to ~3x the current through FRS pin. CDTR value is defined according to: (3) fm should always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission measurement. Typically, fm should be set to around 11 kHz to account for component variations. The resistor RDTR is used to determine ∆f, which is the amount of dithering, and its value is determined according to: (4) For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of ±33 kHz.

8.3.7.6 SST and Soft-Start of the Switcher

Converters require a soft-start to prevent output overshoot on startup. In PoE applications, the PD also needs soft-start to limit its input current at turn on below the limit allocated by the power source equipment (PSE). For flyback applications using primary-side control, the TPS23730 provides closed loop controlled soft-start, which applies a slowly rising ramp voltage to a second control input of the error amplifier. The lower of the reference input and soft-start ramp controls the error amplifier, allowing the output voltage to rise in a smooth monotonic fashion. In all other applications where secondary-side regulation is used, the TPS23730 provides a current-loop soft- start, which controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The lower of COMP-derived current demand and soft-start ramp controls the PWM comparator. Note that in this case there is usually a (slower) secondary-side soft-start implemented with the typical TL431 or TLV431 error amplifier to complement the action of the primary-side soft-start. The soft-start period of the TPS23730 is adjustable with a capacitor between SST and RTN. During soft-start, CSST (Figure 19) is being charged from less than 0.2 V to 2.45 V by a ~10µA current source. Once VSST has exceeded approximately 2.1 V (VSTUOF), the VCC startup is also turned off. The actual control range of the primary-side closed-loop soft-start capacitor voltage is between 0.25V and 2V nominally. Therefore, the soft-start capacitor value must be based on this control range and the required soft- start period (tSS) according to: (5)

The actual control range of the current-loop soft-start capacitor voltage is between 0.6V and 1.2V nominally. soft-start to complete. For more details regarding the secondary-side soft start, refer to Application Information.

8.3.7.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher

down to approximately 50 mV at beginning of soft-stop.

8.3.8 Switching FET Driver - GATE, GTA2, DT

when the converter is disabled. synchronous rectifiers. Connecting DT to VB also disables GAT2 in a high-impedance condition. Figure 2. Both MOSFETs should be off between GAT2 going high to GATE going high, and GATE going low to programmed dead time is maintained until the switching stops completely.

8.3.9 EMPS and Automatic MPS

VSS pin with an amplitude adjusted such that its net current reaches a level high enough to maintain power. ILOAD is the DC current going into the RTN pin.

Figure 6. Auto MPS period of approximately 5 ms.

8.3.10 VDD Supply Voltage

its UVLO threshold, the TPS23730 returns to inrush phase.

8.3.11 RTN, AGND, GND

is internally connected to RTN pin.

8.3.12 VSS

8.3.13 Exposed Thermal pads - PAD_G and PAD_S

8.4 Device Functional Modes

8.4.1 PoE Overview

reduce standby power consumption and enhanced classification. change and must always be referenced when making design decisions.

classification. The PSE may then power the PD if it has adequate capacity. Type 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification. Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. the PSE to the idle state. Figure 7 shows the operational states as a function of PD input voltage. Figure 7. Operational States standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. two revisions of the standard.

Table 4. Comparison of Operational Limits

13 W 37 V – 57 V N/A

1. Must interpret respectively Type 2, 3 or 4 hardware classification.
2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, as

well as to Type 3 PD with Class level 4 or higher.

1. If Type 3 Class 5-6 or Type 4 single interface PD, it must present hardware Class in the range of 0 to 3

during the third and any subsequent classification events.

1. Must implement DLL negotiation.
2. Must draw less than 400 mA from 50 ms until 80 ms after the PSE applies operation voltage (power up), if

Type 2 or 3, single interface PD. This covers the PSE inrush period, which is 75 ms maximum.

1. Must draw less than 800 mA total and 600 mA per pairset from 50 ms until 80 ms after the PSE applies

operation voltage (power up), if Type 4 (Class 7-8) single interface PD.

1. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.
2. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received
3. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission
4. Must not draw more than 51 W if it has not received at least 5 classification events or received permission
5. Must meet various operating and transient templates.
6. Optionally monitor for the presence or absence of an adapter.

adapter is plugged in and operational.

8.4.2 Threshold Voltages

states as shown in Figure 7. Figure 8 relates the parameters in Electrical Characteristics PoE to the PoE states. hardware class state machine.

Figure 8. Threshold Voltages

8.4.3 PoE Start-Up Sequence

guard against misdetection of a device when plugged in during the detection sequence. full voltage. In Figure 11, the converter soft-start is also delayed until the end of inrush period.

Figure 9. PoE Start-Up Sequence

8.4.4 Detection

detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS. resistance is partially cancelled by the effective resistance of the TPS23730 during detection.

8.4.5 Hardware Classification

requested, in which case there is power demotion.

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6 Type 3 PD presents Class 4 in hardware during the first two class events and it presents Class 0 or 1, respectively, for all subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during the first two class events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSE will treat a Class 4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSE will treat a Class 5 to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PD that receives a 2- event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receives a 5-event class, understands that the PSE has agreed to allocate the PD requested power. In the case where there is power demotion, the PD may choose to not start, or to start while not drawing more power than initially allocated, and request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD to indicate that it is underpowered if this occurs. Startup of a high-power PD at lower power than requested implicitly requires some form of powering down sections of the application circuits. The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 1 limit; however, the average power requirement always applies. The TPS23730 implements one- to four-event classification. RCLSA and RCLSB resistor values define the class of the PD. DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by the TPS23730. The TPS23730 disables classification above VCU_OFF to avoid excessive power dissipation. CLSA/B voltage is turned off during PD thermal limiting or when APD or DEN is active. The CLSA and CLSB outputs are inherently current-limited, but should not be shorted to VSS for long periods of time. Figure 10 shows how classification works for the TPS23730. Transition from state-to-state occurs when comparator thresholds are crossed (see Figure 7 and Figure 8). These comparators have hysteresis, which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with increasing voltage from left to right. A 2- to 4-event classification follows the (heavy lined) path towards the bottom, ending up with a latched TPL/TPH decode along the lower branch that is highlighted. Once the valid path to the PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew.

Figure 10. Up to Four-Event Class Internal States

8.4.6 Maintain Power Signature (MPS)

MPS may remove power from the PD. amplitude requirement for Class 5-8 PDs have also increased to 16 mA at the PSE end of the ethernet cable.

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated If the current through the RTN-to-VSS path is very low, the TPS23730 automatically generates the MPS pulsed current through the VSS pin, with an amplitude adjusted such that its net current reaches a level high enough to maintain PSE power. The TPS23730 is also able to determine if the PSE is of Type 1-2 or Type 3-4, automatically adjusting the pulsed current amplitude, duration and duty-cycle, while minimizing power consumption. Note that the IEEE802.3bt requirement for the PD is applicable at the PSE end of the cable. That means that depending the cable length and other parameters including the bulk capacitance, a longer pulse duration may be required to ensure a valid MPS. For that purpose, the TPS23730 provides auto-stretch capability which is used to cancel the impact of such system conditions on the effective pulsed current duration. See Figure 6. When APD is pulled high or when DEN is pulled to VSS (forcing the hotswap switch off), the DC MPS will not be met. A PSE that monitors the DC MPS will remove power from the PD when this occurs.

8.4.7 Advanced Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CBULK, CVCC, CVB and CVBG while the PD is unpowered. Thus VVDD-RTN will be a small voltage until just after full voltage is applied to the PD, as seen in Figure 9. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, approximately 37.6 V) with RTN high, the TPS23730 enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 11 for an example. Converter switching is disabled while CBULK charges and VRTN falls from VVDD to nearly VVSS; however, the converter start-up circuit is allowed to charge CVCC (the VB regulator also powers the internal converter circuits as VVCC rises). Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1.85 A). Additionally, once the inrush period duration has also exceeded approximately 84 ms (end of inrush phase), the converter switching is allowed to start, once VVCC also goes above its UVLO (approximately 8.25 V). Continuing the start-up sequence shown in Figure 11, once VVCC goes above its UVLO , the soft-start (SST) capacitor is first discharged with controlled current (ISSD) below nominally 0.2 V (VSFST) if the discharge was not already completed, then it is gradually recharged until it reaches ~0.25 V (VSSOFS in closed-loop mode) at which point the converter switching is enabled, following the closed loop controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain VVCC during the converter soft-start without requiring any significant CVCC capacitance, in 48 V input applications. At the end of the soft-start period, more specifically when SST voltage has exceeded ~2 V (VSTUOF), the startup current source is turned off. VVCC falls as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises to support VVCC before it falls to VCUVLO_F (~6.1 V), a successful start-up occurs. Figure 11 shows a small droop in VVCC while the output voltage rises smoothly and a successful start-up occurs. Figure 12 also illustrates similar scenario if optocoupler feedback is used instead of PSR. In this case, the converter switching is enabled when VSST exceeds approximately 0.6 V (VSSOFS in peak current mode).

Figure 11. Power Up and Start - Flyback with PSR

Figure 13. Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter Also, when a VCC fall occurs, the TPS23730 can differentiate between an overload and a light load condition.

Figure 14. Startup Operation if VCC Undervoltage is caused by Light Load Condition of Diode-rectified

8.4.8 Line Undervoltage Protection and Converter Operation

during next power up, due to precharged clamp capacitor, the soft-start could cause transformer saturation. apply to both ACF and flyback (at power down or next soft-start) configurations.

optimum switching MOSFETs protection. See Figure 15. Figure 15. Soft-Stop Operation ms, before the converter is allowed to restart.

8.4.9 PD Self-Protection

over 4 pairs. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2012. The PD section has the following self-protection functions.

• Hotswap switch current limit
• Hotswap switch foldback
• Hotswap thermal protection The internal hotswap MOSFET of the TPS23730 is protected against output faults and input voltage steps with a current limit and deglitched foldback. High stress conditions include converter output shorts, shorts from VDD to RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a result. If VRTN rises above approximately 14.8 V for longer than approximately 1.8 ms, the current limit reverts to the inrush limit, and turns the converter off, although there is no minimum inrush delay period (84 ms) applicable in this case. The 1.8-ms deglitch feature prevents momentary transients from causing a PD reset,

Figure 16. Response to PSE Step Voltage restarts in inrush phase when exiting from a PD overtemperature event. converter topologies that can deliver power in both directions.

• VAPD above VAPDEN (approximately 1.5 V)
• VDEN ≤ VPD_DIS when VVDD-VSS is in the operational range
• PD over temperature
• VVDD-VSS < PoE UVLO (approximately 32 V).

8.4.10 Thermal Shutdown - DC-DC Controller

GATE/GAT2 drivers, and forces the VCC control into an under-voltage state.

8.4.11 Adapter ORing

Adapter ORing Solutions using the TPS23753, (SLVA306). Figure 17. ORing Configurations Figure 18. Low-Voltage Option 1 ORing

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the combinations. However, the TPS23730 device offers several built-in features that simplify some combinations. Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE (option 1) presents the problem that either source may have the higher voltage. A blocking switch would be required to assure that one source dominates. A second example is combining a 12-V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example is use of a 24-V adapter with ORing option 1. The PD hotswap would have to handle two times the current, and have 1/4 the resistance (be 4 times larger) to dissipate equal power. The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD momentarily loses power until the PSE completes its start-up cycle. The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET, and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven from the secondary side of the converter. Another option 3 alternative which does not require DEN optocoupler is achievable by ensuring that the auxiliary voltage is always higher then the converter output; in this case, the PSE power can then be maintained by use of the auto MPS function of the TPS23730. The TPS23730 also supports the use of an option 1 adapter, for example 24-V, by use of the PPD input. See Figure 18. The IEEE standards require that the PI conductors be electrically isolated from ground and all other system potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter. Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option 3.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

an active clamp forward converter.

9.2 Typical Application

Figure 19. Basic TPS23730 Implementation

9.2.1 Design Requirements

high power density flyback topologies such as primary side regulation synchronous or non-synchronous flyback. designed for the design parameters in Table 5. Table 5. Design Parameters

9.2.1.1 Detailed Design Procedure

9.2.1.1.1 Input Bridges and Schottky Diodes

about 30%. These are often used to maximize the efficiency when FET bridge architectures are not used. Schottky diode leakage current and different input bridge architectures can impact the detection signature. the simplest solution. Adjusting RDEN slightly may also help meet the requirement. A general recommendation for the input rectifiers are 2 A, 100-V rated discrete or bridge schottky diodes. higher overall system efficiency.

9.2.1.1.2 Input TVS Protection

ratings. Outdoor transient levels or special applications require additional protection. would be a good initial selection between RTN (cathode) and VSS (annode).

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9.2.1.1.3 Input Bypass Capacitor

The IEEE 802.3bt standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF. Typically a 0.1-μF, 100-V, 10% ceramic capacitor is used.

9.2.1.1.4 Detection Resistor, RDEN

The IEEE 802.3bt standard specifies a detection signature resistance, RDEN from 23.7 kΩ to 26.3 kΩ, or 25 kΩ ± 5%. Choose an RDEN of 25.5 kΩ.

9.2.1.1.5 Classification Resistor, RCLSA and RCLSB

Connect a resistor from CLSA and CLSB to VSS to program the classification current according to the IEEE 802.3bt standard. The class power assigned should correspond to the maximum average power drawn by the PD during operation. Select RCLSx according to Table 1. For a high-power design, choose Class 6 where RCLSA = 32 Ω and RCLSB = 130 Ω.

9.2.1.1.6 Dead Time Resistor, RDT

Program the dead time with a resistor connected from DT to RTN. The required dead-time period depends on the specific topology and parasitics. The easiest technique to obtain the optimum timing resistor is to build the supply. A good initial value is 100 ns. Then the dead time can be tuned to achieve the best efficiency after considering all corners of operation (load, input voltage, and temperature). 1. Choose RDT as follows assuming a tDT of 100 ns: b. Choose RDT = 49.9 kΩ

9.2.1.1.7 APD Pin Divider Network, RAPD1, RAPD2

The APD pin can be used to disable the TPS23730 device internal hotswap MOSFET giving the adapter source priority over the PoE source. An example calculation is provided, see SLVA306.

9.2.1.1.8 PPD Pin Divider Network, RPPD1, RPPD2

For this design example, passive PoE is not required so PPD is pulled down to VSS. However, the PPD pin can be used to override the internal hotswap MOSFET UVLO (VUVLO_R and VUVLO_H) when using low voltage adapters connected between VDD and VSS. The PPD pin has an internal 5-μA pulldown current source. As an example, consider the choice of RPPD1 and RPPD2, for a 24-V adapter. 1. Select the start-up voltage, VADPTR-ON approximately 75% of nominal for a 24-V adapter. Assuming that the adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage. 2. Choose VADPTR-ON = 24 V × 0.75 = 18 V. 3. Choose RPPD2 = 3.01 kΩ. 4. IRPPD1 = IRPPD2 + 5 µA so RPPD1 can be calculated using KCL. Choose 18.7 kΩ

9.2.1.1.9 Setting Frequency (RFRS) and Synchronization

The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. As an example: 1. Optimal switching frequency (fSW) for isolated PoE applications is 250 kHz. 2. Compute RFRS per Equation 2 3. Select 60.4 kΩ.

ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated The TPS23730 device may be synchronized to an external clock to eliminate beat frequencies from a sampled system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 5. RFRS should be chosen so that the maximum free-running frequency is just below the desired synchronization frequency. The synchronization pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates. The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and rise and fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

9.2.1.1.10 Bias Supply Requirements and CVCC

Advanced startup in the TPS23730 allows for relatively low capacitance on the bias circuit. It is recommended to use a 1uF 10% 25V ceramic capacitor on CVCC.

9.2.1.1.11 TPH, TPL, and BT Interface

The TPH, TPL, and BT pins are active low, open-drain outputs which give an indication about the PSE allocated power along with its Type. Optocouplers can interface these pins to circuitry on the secondary side of the converter. A high-gain optocoupler and a high-impedance (for example, CMOS) receiver are recommended. Please refer to the TPS23730EVM-093 as an example circuit. Below is an example design calculation. 1. Let VCC = 12 V, VOUT = 5 V, RTPx-OUT = 10 kΩ, VTPx-OUT (low) = 400 mV maximum a. ITPx-OUT = 0.46mA 2. The optocoupler CTR will be needed to determine RTpx. A device with a minimum CTR of 300% at 5-mA LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation of CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE curve on the optocoupler data sheet. a. The approximate forward voltage of the optocoupler diode is 1.1 V from the data sheet. b. ITPx-MIN = 1mA and RTPx = 10.6 kΩ 3. Select 10.7 kΩ resistor

9.2.1.1.12 Secondary Soft Start

Converters require a soft start on the voltage error amplifier to prevent output overshoot on start-up. Figure 20 shows a common implementation of a secondary-side soft start that works with the typical TLV431 error amplifier. The soft-start components consist of DSS, RSS, and CSS. They serve to control the output rate-of-rise by pulling VCOMP down as CSS charges through ROB, the optocoupler, and DSS. This has the added advantage that the TLV431 output and CIZ are preset to the proper value as the output voltage reaches the regulated value, preventing voltage overshoot due to the error amplifier recovery. The secondary-side error amplifier will not become active until there is sufficient voltage on the secondary. The TPS23730 provides an adjustable primary- side soft start, which persists long enough for secondary side voltage-loop soft start to take over. The primary- side current-loop soft start controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The PWM is controlled by the lower of the soft-start ramp or the COMP-derived current demand. The actual output voltage rise time is usually much shorter than the internal soft-start period. Initially the primary soft-start ramp limits the maximum current demand as a function of time. Either the current limit, secondary-side soft start, or output regulation assume control of the PWM before the primary soft-start period is over. Since the VCC startup source stays on longer after converter's output voltage is ramped up (VCC startup turns off only when 2.1V is reached on the SS pin), a large bias winding hold up capacitor is not necessary like in some traditional PWM controllers. Instead, this allows for a small 1 µF ceramic capacitor to be used on VCC.

Figure 20. Error Amplifier Soft Start

9.2.1.1.13 Frequency Dithering for Conducted Emissions Control

Dithering for Spread Spectrum Applications. These equations yield CDTR = 2.2 nF and RDTR = 235 kΩ where a 237 kΩ standard resistor can be used.

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10 Power Supply Recommendations

The TPS23730 converter must be designed such that the input voltage of the converter is capable of operating within the IEEE 802.3 protocol at the recommended input voltage as shown inTable 4 and the minimum operating voltage of the adapter if applicable.

11 Layout

11.1 Layout Guidelines

The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set of recommendations include:

• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-μF capacitor, and TPS23730.
• All leads should be as short as possible with wide power traces and paired signal and return.
• There should not be any crossovers of signals from one part of the flow to another.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
• The TPS23730 should be located over split, local ground planes referenced to VSS for the PoE input and to RTN for the switched output.
• Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay copper fills should be used in the power path.
• It is recommended having at least 8 vias (PAD_G) and 5 vias on (PAD_S) connecting the exposed thermal pad through a top layer plane (2 oz. copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal dissipation.

11.2 Layout Example

A detailed PCB layout can be found in the user’s guide of the TPS23730EVM-093 which show the top and bottom layer and assemblies as a reference for optimum parts placement.

11.3 EMI Containment

• Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
• Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface).
• Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground floods).
• Use 4 layer PCB if economically feasible (for better grounding).
• Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
• Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.
• Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).
• Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
• Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line).
• Possible use of common-mode inductors.
• Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
• End-product enclosure considerations (shielding).

11.4 Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations assume that the TPS23730 is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS23730 device to experience an OTSD event if it is excessively heated by a nearby device.

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11.5 ESD

ESD requirements for a unit that incorporates the TPS23730 have a much broader scope and operational implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design testing that only validates the ruggedness of the TPS23730.

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™ at (Clause 33)
• Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement, International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03
• Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306
• Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V. Comiskey, TI, SLUA469
• TPS23730EVM-093: Evaluation Module for TPS23730

12.2 Support Resource

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

13.1 Pack Material Addendum

13.1.1 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant

ADVANCE□INFORMATION TAPE AND REEL BOX DIMENSIONS Width (mm) W L H TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTPS237300RMTT VQFN RMT 45 250 210 185 35 TPS23730RMTR VQFN RMT 45 3000 210 185 35 TPS23730RMTT VQFN RMT 45 250 210 185 35

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225180/A 08/2019 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLATPACK-NO LEAD RMT0045A A 0.08 C

0.1 C A B

0.05 C B PKG PKG PIN 1 INDEX AREA 5.1 4.9 7.1 6.9

1 MAX

0.05 0.00 SEATING PLANE C (0.1) TYP 5.2 3.6 39X 0.4 45X 0.25 0.15 45X 0.5 0.3 2.9±0.1 2.15±0.1 2.1±0.1 3.7±0.1 1.3751 1.4 0.6 1.4 0.2 0.6 1.4 14 22 3645 PIN 1 ID (OPTIONAL) ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225180/A 08/2019 www.ti.com VQFN - 1 mm max heightRMT0045A PLASTIC QUAD FLATPACK-NO LEAD PKG PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X SOLDER MASK DEFINED SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK

0.05 MIN

(PREFERRED) EXPOSED METAL SOLDER MASK OPENING METAL

0.05 MAX

(3.7) (2.9) (2.1) (2.15) (3.6) (4.8) (6.8) (5.2) (0.6) 39X (0.4) (1.4) (1.4) (0.2) (0.595) (1.4) (2.205) (0.55) (1.375) (2.2) (1.2) (0.625) (1.6) 45X (0.2) 45X (0.6) 14 22 3645 (R0.05) TYP (Ø0.2) VIA TYP ADVANCE□INFORMATION TPS23730 SLVSER6 –MAY 2020 www.ti.com Product Folder Links: TPS23730 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225180/A 08/2019 www.ti.com VQFN - 1 mm max heightRMT0045A PLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PAD 46: 76%; PAD 47: 78% SCALE: 12X PKG PKG 4X (1.27) 6X (0.94) (3.6) (4.8) (6.8) (5.2) (0.6) 39X (0.4) (1.4) (1.4) (0.2) (0.83) (1.97) (0.795) (1.955) (0.735) (1.25) 45X (0.2) 45X (0.6) 14 22 3645 (R0.05) TYP METAL TYP 4X (0.96) 6X (1.05) ADVANCE□INFORMATION TPS23730 www.ti.com SLVSER6 –MAY 2020 Product Folder Links: TPS23730 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com 20-May-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PPS23730A0RMTT ACTIVE VQFN RMT 45 250 TBD Call TI Call TI -40 to 125 TPS23730RMTR PREVIEW VQFN RMT 45 250 TBD Call TI Call TI -40 to 125 TPS23730RMTT PREVIEW VQFN RMT 45 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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